U2786B DECT PLL / TX IC Description The U2786B is an RF IC for low-power DECT transmit applications. The IC includes a complete PLL with 1-GHz prescaler, on-chip frequency doubler, biasing for off-chip VCO, an integrated TX filter and a modulationcompensation circuit for advanced closed-loop modulation concept. Electrostatic sensitive device. Observe precautions for handling. Features 1-GHz PLL, frequency doubler, TX data filter (13.824-MHz/ 27.648-MHz reference clock) Switchable charge-pump current for enhanced switching time Supply-voltage range: 2.7 V to 4.7 V 1 operational amplifier for active loop filter Low current consumption Advanced closed-loop modulation (with 13.824-MHz/ 27.648-MHz reference clock) and open loop modulation supported Few external components No mechanical tuning necessary Block Diagram GND_D PU TX_DATA 28 OLE 27 DAC 26 25 Control logic RF_IN VCO_BIAS n.c. GND_RF_IN 24 23 22 20 19 18 17 OP_N 16 PC f DAC 21 PU_MIN OP_OUT OP_P GND_OP 15 OP :n PD MCC RC FD f f :n GF 2f 3-wire bus 1 CP 2 3 DATA CLOCK - + 4 5 REF_CLK ENABLE 6 I_CP_SW LD 8 7 9 FD_OUT1 GND_FD_OUT 10 11 VS FD_OUT2 12 13 GND_CP GF_DATA 14 CP VS_CP 14224 Figure 1. Block diagram Ordering Information Extended Type Number Package Remarks U2786B-MFS SSO28 Tube U2786B-MFSG3 SSO28 Taped and reeled Rev. A2, 18-Aug-00 1 (17) Preliminary Information U2786B Pin Description CLOCK 1 28 TX_DATA DATA 2 27 PU ENABLE 3 26 OLE REF_CLK 4 25 GND_D LD 5 24 DAC I_CP_SW 6 23 RF_IN 22 GND_RF_IN GND_FD_OUT 7 U2786B FD_OUT1 8 21 VCO_BIAS FD_OUT2 9 20 n.c. VS 10 19 PU_MIN 11 18 GND_OP GND_CP 12 17 OP_OUT GF_DATA VS_CP 13 16 OP_P CP 14 15 OP_N Figure 2. Pinning AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Pin Symbol Function 1 CLOCK 3-wire bus: Clock input 2 DATA 3-wire bus: Data input Configuration VS 1,2 and 3 3 ENABLE 3-wire bus: Enable input 2 (17) Ref 5k (10k) 5k (10k) Rev. A2, 18-Aug-00 Preliminary Information U2786B Pin Description (continued) AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAAAAAAAAA AAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Pin Symbol 4 REF_CLK Function Configuration Reference frequency input VS 10k 10k 4 5 LD Lock detect output VS 5 100 6 I_CP_SW VS Charge-pump current switch 6 Ref 5k (10k) 7 5k (10k) GND_FD_OUT Frequency-doubler buffer ground 8 FD_OUT1 Frequency-doubler buffer output 1 9 FD_OUT2 Frequency-doubler buffer output 2 VS 8,9 7 10 VS Supply voltage Rev. A2, 18-Aug-00 3 (17) Preliminary Information U2786B Pin Description (continued) AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Pin Symbol 11 GF_DATA Function Configuration VS Modulation output (Gaussian filtered data signal) 11 12 GND_CP 13 VS_CP 14 CP Charge-pump ground Charge-pump supply voltage Charge-pump output 13 14 12 15 OP_N Operational-amplifier inverting input 16 OP_P Operational-amplifier non-inverting input VS 15 16 18 OP_OUT Operational-amplifier output VS AB-Control 17 17 18 18 GND_OP Operational-amplifier ground 19 PU_MIN 3-wire bus: Data-hold enable in powerdown mode 4 (17) Rev. A2, 18-Aug-00 Preliminary Information U2786B Pin Description (continued) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Pin Symbol 20 n.c. 21 VCO_BIAS Function Configuration Not connected VCO bias voltage output VS 1k 21 22 GND_RF_IN 23 RF_IN RF input ground RF input from VCO to doubler and PLL VS 1.5k 1.5k 23 22 24 DAC DAC for VCO pretune VS 24 10k 25 GND_D 26 OLE Digital ground Open-loop enable input VS Ref 26 Rev. A2, 18-Aug-00 5k (10k) 5k (10k) 5 (17) Preliminary Information U2786B Pin Description (continued) AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Pin Symbol 27 PU Function Configuration Power-up input (active high) 10k 20k 10k 10k 25k 25k 140k 27 28 TX_DATA Digital TX data input to Gaussian filter and modulation compensation circuit VS 28 Ref 5k (10k) 5k (10k) Functional Blocks CP FD OP MCC PD VCO Charge pump Frequency doubler Amplifier for loop filter Modulation-compensation circuit Phase detector Voltage-controlled oscillator DAC GF LF PC RC DA converter for pretuning of VCO Gaussian filter for transmit data Loop filter Programmable counter = MC (main counter) + SC (swallow counter) Reference counter Absolute Maximum Ratings All voltages refer to GND (Pins 7, 12, 18, 22 and 25). Parameter Symbol Supply voltage Pins 10 and 13 VS Logic input voltage Pins 1, 2, 3, 6, 26, 27 and 28 VIN Junction temperature Tjmax Storage temperature Tstor Min. - 0.3 -40 Max. Unit 5.0 V 5.0 V 150 C 150 C Thermal Resistance Parameter Junction ambient Symbol Value Unit RthJA 130 K/W 6 (17) Rev. A2, 18-Aug-00 Preliminary Information U2786B Operating Range Parameter Supply voltage Symbol Min. Typ. Max. Unit VS 2.7 3.0 4.7 V Tamb -25 +25 +85 C Typ. Max. Unit IS,OFF 1 10 A RX (OLE = `1') IS 6 mA TX (OLE = `0') IS 11.5 mA TX, MCC on IS 13.2 mA TX, MCC, GF on IS 12.8 mA TX, MCC, GF, OP on IS 15 mA TX, MCC, GF, OP, FD on IS 25.8 mA VVS_CP = 3 V, PLL in lock condition Pin 14 ICP 1 A Pins 10 and 13 Ambient temperature Electrical Characteristics Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25C Parameter Test Conditions / Pins Power supply Standby y current Supply current CP Symbol Min. Pin 10 VPU = low level = `0' Frequency doubler fRF_IN = 900 MHz (Pin 23) Pins 8 and 9 (differential) Output power PRF_IN= -10 dBm Zload = 50 (differential) Pins 8 and 9 PFD_OUT - 10 Harmonic suppression Subharmonic suppression -5 -3 dBm 2nd + 3rd; PRF_IN= -10 dBm Pins 8 and 9 HS - 20 dBc PRF_IN= -10 dBm Pins 8 and 9 SHS - 20 dBc fRF_IN 800 1000 MHz VRF_IN 20 200 mVRMS PLL Input frequency Input voltage Pin 23 fRF_IN = 800 to 1000 MHz AC-coupled sinewave, Pin 23 Scaling factor prescaler SPSC 32/33 Scaling factor main counter SMC 31/32/33/34 Scaling factor swallow counter SSC 0 31 External reference input frequency AC-coupled sinewave Pin4 fREF_CLK 5 28 MHz External reference input voltage AC-coupled sinewave Pin4 VREF_CLK 50 250 mVRMS Scaling factor reference counter Pin4 SRC Rev. A2, 18-Aug-00 12/16/24/32 7 (17) Preliminary Information U2786B Electrical Characteristics (continued) Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25C Parameter Test Conditions / Pins Charge pump active when RX, TX Output current Current scaling factor Symbol Min. Typ. Max. Unit Pin 14 VI_CP_SW = `0' VCP =VVS_CP / 2 ICP_1 1 mA VI_CP_SW = `1' VCP = VVS_CP / 2 ICP_5 5 mA See bus protocol D0...D2 ICP = CPCS x ICP_TYP CPCS Leakage current 60 130 % IL 100 pA PGBW 10 MHz 80 degree Operational amplifier Power-gain bandwidth Excess phase Pin 17 Rload = 1 k, Cload = 15 pF Pin 17 Voffs 1 mV Open-loop gain Pin 17 g 70 dB Output voltage range Pin 17 Vout 0.3 VS - 0.3 V Vin 0.3 VS - 0.3 V Input offset voltage Common-mode input voltage Pins 15 and 16 Pins 15 and 16 Modulation-compensation circuit @ max. DSV 64, MCC only for fREF_CLK = 13.824MHz or 27.648 MHz Oversampling fREF_CLK= 13.824 MHz or 27.648 MHz Integration counter Current scaling factor See bus protocol E3...E5 OVS 6 MAC - 511 511 MCCS 60 130 % Gaussian transmit filter (Gaussian shape BxT = 0.5) fREF_CLK has to be chosen ! Tx data filter clock fREF_CLK = 13.824 MHz, TX, 12 taps in filter fTXFCLK 6.912 MHz fREF_CLK = 27.648 MHz, TX, 12 taps in filter fTXFCLK 6.912 MHz Maximum output current Polarity see bus protocol D13 Pin 11 |IGF_DATA| 8.5 A Current scaling factor See bus protocol D6...D8 IGF_DATA = GFCS x IGF_TYP Pin 11 GFCS VCO biasing 130 % Pin 21 Bias voltage g Standby, PU = `0' Temperature coefficient 60 VVCO 1.5 VVCO 0 TC - 3.3 8 (17) V 10 mV mV/K Rev. A2, 18-Aug-00 Preliminary Information U2786B Electrical Characteristics (continued) Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25C Parameter Test Conditions / Pins Symbol Min. DAC for VCO PRETUNE 3-bit programming, see BUS protocol D3....D5 Typ. Max. Unit Pin 24 DAC low level Iload = 1 A VDAC_min DAC step level Nonlinear (see D3...D5) VDAC_step DAC high level Iload = 1 A VDAC_max 2.25 V RDAC_out 10 k Output impedance 0.3 V V Lock-detect output Lock-detect output, test-mode output locked = `1', unlocked = `0' test modes see bus protocol E0....E2 Pin 5 LD Leakage current VOH = 4.5 V Pin5 IL 5 A Saturation voltage IOL = 0.5 mA Pin 5 VSL 0.4 V Pin 1 fclock 3-wire bus Clock 1.152 MHz Logic input levels (CLOCK, DATA, ENABLE, I_CP_SW, OLE, GF_DATA) Pins 1, 2, 3, 6, 26 and 28 High input level =`1' ViH Low input level =`0' ViL High input current =`1' IiH Low input current =`0' 1.5 V 0.5 V -5 5 A IiL -5 5 A 2.0 Standby control Power up High input level PU = `1' Pin 27 VPU Low input level PU = `0' Pin 27 VPU,OFF DATA hold enable High input level PU_MIN = `1' Pin 19 VPU_MIN Low input level PU_MIN = `0' Pin 19 VPU_MIN PU = `1' VPU = 3 V VPU = 4.5 V Pin 27 PU = `0', PU_MIN = `1' VPU_MIN = 3 V Pin 19 IPU_MIN,ON Standby Low input current PU = `0' , PU_MIN = `0' Pin 27 VPU = 0 V VPU_MIN = 0.5 V Pin 19 IPU,OFF IPU_MIN,OFF Settling time: VS = 0 active operation Switched from VS = 0 to VS = 3 V tsoa < 10 s Settling time: standby active operation Switched from standby to PU = `1' tssa < 10 s Settling time: active operation standby Switched from PU = `1' to standby tsas <2 s Power up High input current Standby High input current IPU Rev. A2, 18-Aug-00 V 0.7 2.0 100 220 V V 125 300 0.7 V 150 420 A A A 21 0.1 1 A A 9 (17) Preliminary Information U2786B PLL Principle RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD(SMC32 + SSC) fVCO fPD CP Phase frequency detector PD Frequency doubler FD VCO fOUT FD_OUT DAC fPD = 864 kHz Controlled phase shifting Reference counter RC REF_CLK 10.368MHz* 13.824MHz 20.736MHz* 27.648MHz** GF_DATA Modulation compensation MMC 6.912MHz SRC 12 16 24 32 * MCC and GF not possible **Reference counter not possible PLL reference Frequency REF_CLK Gaussian filter GF 1.152 Mbit/s TX_DATA Baseband controller Figure 3. PLL principle 10 (17) Rev. A2, 18-Aug-00 Preliminary Information U2786B The following table shows the LO frequencies for RX and TX for the DECT band plus additional channels for an optional DECT band extension. Intermediate frequencies of 110.592 and 112.32 MHz are supported. Table 1 LO frequencies Mode TX fIF/MHz RX 110,592 , 112,32 , Channel C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 fANT/MHz 1897,344 1895,616 1893,888 1892,16 1890,432 1888,704 1886,976 1885,248 1883,52 1881,792 1897,344 1895,616 1893,888 1892,16 1890,432 1888,704 1886,976 1885,248 1883,52 1881,792 1897,344 1895,616 1893,888 1892,16 1890,432 1888,704 1886,976 1885,248 1883,52 1881,792 fLO/MHz 948,672 947,808 946,944 946,08 945,216 944,352 943,488 942,624 941,76 940,896 893,376 892,512 891,648 890,784 889,92 889,056 888,192 887,328 886,464 885,6 892,512 891,648 890,784 889,92 889,056 888,192 887,328 886,464 885,6 884,736 2fLO/MHz 1897,344 1895,616 1893,888 1892,16 1890,432 1888,704 1886,976 1885,248 1883,52 1881,792 1786,752 1785,024 1783,296 1781,568 1779,84 1778,112 1776,384 1774,656 1772,928 1771,2 1785,024 1783,296 1781,568 1779,84 1778,112 1776,384 1774,656 1772,928 1771,2 1769,472 SMC 34 34 34 34 34 34 34 34 34 34 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 SSC 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 1 0 fANT/MHz 1714,176 1824,768 1826,496 1933,632 2044,224 2045,952 fLO/MHz 857,088 857,088 857,088 966,816 966,816 966,816 2fLO/MHz 1714,176 1714,176 1714,176 1933,632 1933,632 1933,632 SMC 31 31 31 34 34 34 SSC 0 0 0 31 31 31 Table 2 Limits Mode RX RX fIF/MHz TX 110,592 112,32 TX 110,592 112,32 fmin fmax Rev. A2, 18-Aug-00 11 (17) Preliminary Information U2786B Formula fANT C1 - fANT C2 = 1,728MHz for TX fLO = fANT / 2 for RX fLO = (fANT - fIF) / 2 SMC = integer (fLO / 0,864 MHz / 32) SSC = MOD ((fLO / 0,864 MHz) / 32) Control Signals Standard Settings I_CP_SW Input for switching charge-pump current by factor 5 0 LD Output, which is active after PLL is locked and testmode output (according to programmed testmode) OLE Enable input for open-loop modulation DAC DAC for VCO band switch PU Hardware power up / standby of complete PLL / TX - IC 1 PU_MIN Data-hold enable of 3-wire bus in power-down mode 1 0 Serial Programming Bus Reference and programmable counters can be programmed by the 3-wire bus (CLOCK, DATA and ENABLE). Beside this information additional control bits as phase detector polarity and scaling of charge-pump currents as well as internal currents for Gaussian lowpass filter and modulation compensation circuit can be transferred. made how many pulses have arrived during ENABLElow condition. The bus then returns to a low current standby mode until the ENABLE signal changes to low again. After setting ENABLE signal to low condition, the data status is transferred bit by bit on the rising edge of the CLOCK signal into the shift register, starting with the MSB-bit. After ENABLE returning to high condition the programmed information is loaded into the addressed latches, according to the addressbit condition (last bit). Additional leading bits are ignored and there is no check In powerdown mode of complete PLL/TX-IC (PU is set to 0) there are two possible states of the 3-wire bus. During standby of the PLL the information in the registers of the PLL is maintained. 3. PU_MIN = 1: the informations in the registers of 3-wire bus are maintained 4. PU_MIN = 0: the informations in the registers of 3-wire bus are lost MSB LSB Data bits D22 D21 D20 D19 RC 0 D18 D17 D16 D15 SC 1 0 1 1 D14 D13 MC 1 1 0 D12 D11 Phase 0 0 1 0 Address bit D10 D9 GF MCC 1 1 D8 D7 D6 D5 GFCS 1 D4 D3 D2 DAC 0 0 1 0 D1 D0 CPCS 0 1 0 1 0 Data bits Standard bit setting: Word 1 Word 2 E7 E6 FD OP 1 1 12 (17) E5 E4 E3 0 E2 E1 E0 TEST 0 1 Address bit MCCS 1 A0 0 0 A0 0 0 0 Rev. A2, 18-Aug-00 Preliminary Information U2786B PLL Settings RC (Reference Counter) MC (Main Counter) D22 D21 SRC D15 D14 SMC 0 0 32 0 0 31 0 1 12 0 1 32 1 0 16 1 0 33 1 1 24 1 1 34 SC (Swallow Counter) D20 D19 D18 D17 D16 SSC * 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 ... * 1 1 1 1 0 30 1 1 1 1 1 31 SSC = [D16] x 20 + [D17] x 21 + ... [D20] x 24 SPGD = 32 x SMC + SSC Phase Settings Current Saving Power up/down Settings Phase of GFDATA D10 GF (Gaussian Filter) D13 GFDATA 0 OFF (RX) 0 Source 1 ON (TX) 1 Sink E7 FD (Frequency Doubler) 0 OFF 1 ON Phase of MCC Internal Connection D12 MCC Data 0 Inverted 1 Normal Phase of CP (Charge Pump) D9 MCC (Modulation Compensation Circuit) 0 OFF (RX or OLE = `1') 1 ON (TX) D11 fR > fP fR < fP fR = fP 0 ISink ISource High imp E6 OP (OpAmp) 1 ISource ISink High imp 0 OFF 1 ON Rev. A2, 18-Aug-00 13 (17) Preliminary Information U2786B Current Gain Settings GFCS (Gaussian Filtered Current Settings) MCCS (Modulation Compensation Settings) D8 D7 D6 GFCS E5 E4 E3 MCCS 0 0 0 60% 0 0 0 60% 0 0 1 70% 0 0 1 70% 0 1 0 80% 0 1 0 80% 0 1 1 90% 0 1 1 90% 1 0 0 100% 1 0 0 100% 1 0 1 110% 1 0 1 110% 1 1 0 120% 1 1 0 120% 1 1 1 130% 1 1 1 130% Pretune DAC Voltage Settings CPCS (Charge-Pump Current Settings) Pretune DAC Voltage D2 D1 D0 CPCS D5 D4 D3 DAC / V 0 0 0 60% 0 0 0 0.33 0 0 1 70% 0 0 1 0.43 0 1 0 80% 0 1 0 0.60 0 1 1 90% 0 1 1 0.79 1 0 0 100% 1 0 0 1.02 1 0 1 110% 1 0 1 1.38 1 1 0 120% 1 1 0 1.73 1 1 1 130% 1 1 1 2.24 Test Mode Settings Test Output Pin (Lock Detect) D11 E2 E1 E0 x 0 0 0 Lock detect mode Signal at Lock Detect and PLL Mode CP Mode Active 0 0 0 1 RC out and CP active Active 1 0 1 0 PC out and CP active (phase changed) Active x 0 1 1 MCCTEST (RC out divided by 2048 or 4096) x 1 0 0 CP tristate only High impedance 0 1 0 1 RC out and CP high impedance High impedance 1 1 1 0 PC out and CP high impedance High impedance x 1 1 1 GFTEST (RC out divided by 4 or 8) High impedance Active 3-Wire Bus Protocol Pulse Diagram MSB LSB ENABLE DATA CLOCK Figure 4. Pulse diagram 14 (17) Rev. A2, 18-Aug-00 Preliminary Information U2786B 3-Wire Bus Protocol Timing Diagram DATA CLOCK ENABLE TL TS TC TH TEC TED TT Figure 5. Timing diagram Description Symbol Min. Value Unit Set time DATA to CLOCK TS 434 ns Hold time DATA to CLOCK TH 0 ns CLOCK pulse width TC 434 ns Set time ENABLE to CLOCK TL 217 ns Hold time ENABLE to CLOCK TEC 0 ns Hold time ENABLE to DATA TED 0 ns TT 868 ns Time between two protocols Typical Application Circuit PU_MIN PU_MIN VCO OLE PU TX_DATA LOOP-FILTER LF PRETUNE RFIN VS/2 VCO_BIAS n.c. OP_OUT OP_P OP_N U2786B CP CLOCK DATA ENABLE REF_CLK LD I_CP_SW MOD VS FD_OUT1 FD_OUT2 VS_CP 14226 Figure 6. Application circuit Rev. A2, 18-Aug-00 15 (17) Preliminary Information U2786B Package Information Package SSO28 Dimensions in mm 5.7 5.3 4.5 4.3 9.10 9.01 1.30 0.15 0.15 0.05 0.25 0.65 6.6 6.3 8.45 28 15 technical drawings according to DIN specifications 13018 1 14 16 (17) Rev. A2, 18-Aug-00 Preliminary Information U2786B Ozone Depleting Substances Policy Statement It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 5. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423 Rev. A2, 18-Aug-00 17 (17) Preliminary Information