ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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GENERAL DESCRIPTION
The AK4116 is a low power S/PDIF AES/EBU receiver supporting resolution up to 24-bit. The integrated
channel status decoder supports both consumer and professional modes. The AK4116 can automatically
detect a Non-PCM bit stream. Combining the AK4116 with a multi-channel codec such as AKM’s
AK4527B or AK4529 can create a complete AC-3 system. Mode settings can be controlled via
microprocessor serial interface. The small 20pin QFN package saves board space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
Low jitter Analog PLL
PLL Lock Range : 32kHz to 48kHz
Clock Source: PLL or X'tal
Auxiliary digit al input
Detection Functions
- Non-PCM Bit Stream Detection
- DTS-CD Bit Stream Detec tion
- Sampling Frequency Detection (32kHz, 44.1kHz, 48kHz)
- Unlock & Parity Error Detection
- Validity Flag Detection
Up to 24bi t Audio Data Format
Audio I/F: Left justified, Right justified (16bit, 18bit, 20bit, 24bit), I2S
40-bit Channel Status Buffer
Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream
Q-subcode Buffer for CD bit stream
4-wire Serial µP I/F
Master Clock Output: 256fs
Operating Voltage: 2.7 to 3.6V
Power Supply Current: 7mA (PLL mode)
2mA (X’tal mode)
Small Package: 20pin QFN
Ta: -40 to 85°C
Low Power 48kHz Digital Audio Receive
r
AK4116
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Block Diagram
Clock
Recovery Clock
Generator
DAIF
Decoder
AC-3/MPEG
Detect µP I/F
Audio
I/F
X'tal
Oscillator
PDN
INT0
LRCK
BICK
SDTO
DAUX
XTOXTIRAVDDAVSS
CDTI
CDTO
CCLK
CSN
DVDD
DVSS
MCKO
Error &
Detect
STATUS
INT1
Q-subcode
buffer
RX0
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Ordering Guide
AK4116VN -40 ~ +85 °C 20pin QFN (0.5mm pitch)
Pin Layout
RX0
AVDD
1
DVDD
20
2
DVSS 3
X
TI 4
X
TO 5
R
19
A
VSS18
17
16
LRCK 6
BICK 7
SDTO 8
DAU
X
9
MCKO 10
15
14
13
12
11
INT1
CSN
CCLK
CDTI
CDTO
Top View
PDN
INT0
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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PIN/FUNCTION
No. Pin Name I/O Function
1 RX0 I Receiver Chan nel 0 (Interna l Biased P in)
2 DVDD - Digital Power Supply Pin
3 DVSS - Digital Ground Pin
4 XTI I X'tal Input Pin
5 XTO O X'tal Output Pin
6 LRCK O Out put Channel Clock Pin
7 BICK O Audio Serial Data Clock Pin
8 SDTO O Audio Serial Data Output Pin
9 DAUX I Auxiliary Audio Data Input Pin
10 MCKO O Master Clock O utpu t Pin
11 CDTO O Control Data Output Pin
12 CDTI I Control Data Input Pin
13 CCLK I Control Data Clock Pin
14 CSN I Chip Select Pin
15 INT1 O Interrupt 1 Pin
16 INT0 O Interrupt 0 Pin
17 PDN I Power-Down & Reset Pin
When “L”, the AK4116 is powered-down and reset, and all output pins go to
“L” and the control registers a re reset to default state.
18 AVSS - Analog Ground Pin
19 R - External Resistor Pin
12k-5% ~ 13k+5% resistor to AVSS externally.
20 AVDD - Analog P ower Supply Pin
Note 1: All input pins except internal biased pins should not be left floating.
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 2)
Parameter Symbol min max Units
Power Supplies: Analog
Digital
|AVSS-DVSS| (Note 3)
AVDD
DVDD
GND
-0.3
-0.3 4.6
4.6
0.3
V
V
V
Input Current (Any pins except supplies) IIN - ±10 mA
Input Voltage (Except RX0, RX1 pins)
(RX0, RX1 pins) VIN1
VIN2 -0.3
-0.3 DVDD+0.3
AVDD+0.3 V
V
Ambient Temper ature (P ow er applied) Ta -40 85 °C
Storage Tempera ture Tstg - 65 150 °C
Note 2. All voltages with respect to ground.
Note 3. AVSS and DVSS must be connec ted to the same grou nd.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDE D OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 2)
Parameter Symbol min typ max Units
Power Supplies: Analog
Digital AVDD
DVDD 2.7
2.7 3.3
3.3 3.6
AVDD V
V
Note 2. All voltages with respect to ground.
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.7~3.6V)
Parameter Symbol min typ max Units
Input Resistance Zin - 10 - k
Input Voltage VTH 350 mVpp
Input Sample Frequency fs 32 - 48 kHz
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.7~3.6V; unless otherwise specified)
Parameter Symbol min typ max Units
Power Supply Current
Normal operation (PDN= “H”) (Note 4)
CM1-0= 00 (Note 5)
CM1-0= 01 (Note 6)
Power down (PDN = “L”) (Note 7)
7
2
10
14
-
100
mA
mA
µA
High-Level Input Voltage
Low-Level Input Voltage VIH
VIL 70%DVDD
DVSS-0.3 -
- DVDD+0.3
30%DVDD V
V
High-Level Output Voltage (Iout=-400µA)
Low-Level Output Voltage (Iout=400µA) VOH
VOL DVDD-0.4
- -
- -
0.4 V
V
Input Leakage Current Iin - - ± 10 µA
Note 4. AVDD=DVDD=3.3V.
Note 5. fs=48kHz, X 'tal=2 4.5 76MH z, CL=20pF. AVDD=5mA (typ), DVDD=9mA (typ).
Note 6. fs=48kHz, X 'tal=2 4.576 MH z. The external load current is not include d.
Note 7. RX inputs are open and all digital input pins are held at DVDD or DVSS.
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.7~3.6V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Crystal Resonator Frequenc y fXTAL 11.2896 24.576 MHz
External Clock Frequenc y
Duty Cycle fECLK
dECLK 2.048
40
50 24.576
60 MHz
%
MCKO Output Fr eque ncy
Duty Cycle (Note 8) fMCK
dMCK 1.024
40
50 24.576
60 MHz
%
PLL Clock Recover Frequen cy (RX0) fpll 32 - 48 KHz
LRCK Timing
Frequency PLL mode
X’tal mode
External Clock m ode
Duty Cycle
fs
fs
fs
dLCK
32
44.1
8
45
48
48
48
55
kHz
kHz
kHz
%
Audio Interface Timing
BICK F r equen c y
BICK D uty
BICK ” to LRCK
BICK ” to SDTO
DAUX Hold Time
DAUX Setup Time
fBCK
dBCK
tMBLR
tBSD
tDXH
tDXS
-20
20
20
64fs
50
20
15
Hz
%
ns
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN” to CCLK “
CCLK “” to CSN “
CDTO Delay
CSN” to CDTO Hi-Z
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
50
50
150
50
50
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN Pulse Width
tPW
150
ns
Note 8. Except the external c lock input.
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Timing Diagram 1/fECLK
tECLKL
VIH
tECLKH
XTI VIL
dECLK = tECLKH x fECLK x 100
= tECLKL x fECLK x 100
1/fMCK
50%DVDDMCKO
tMCKLtMCKH dMCK = tMCKH x fMCK x 100
= tMCKL x fMCK x 100
1/fs
LRCK VIH
VIL
tLRLtLRH dLCK = tLRH x fs x 100
= tLRL x fs x 100
Figure 1. Clock Timing
LRCK
BICK
SDTO
tBSD
tMBLR
50%DVDD
50%DVDD
50%DVDD
DAUX
tDXHtDXS
VIH
VIL
Figure 2. Serial Interface Timing
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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tCCKL
CSN
CCLK
tCDS
CDTI
tCDH
tCSS
C0 A4
tCCKH
CDTO Hi-Z
R/W
C1
VIH
VIL
VIH
VIL
VIH
VIL
tCCK
Figure 3. WRITE/READ Command Input Timing
tCSW
CSN
CCLK
CDTI D2 D0
tCSH
CDTO Hi-Z
D1D3
VIH
VIL
VIH
VIL
VIH
VIL
Figure 4. WRI TE D ata Inpu t Timing
CSN
CCLK
tDCD
CDTO D7 D6
CDTI A1 A0
D5
Hi-Z 50%DVDD
VIH
VIL
VIH
VIL
VIH
VIL
Figure 5. READ Data Output Timing 1
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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CSN
CCLK
tCCZ
CDTO D2 D1
CDTI
D0
D3
tCSW
tCSH
50%DVDD
VIH
VIL
VIH
VIL
VIH
VIL
Figure 6. READ Data Input Timing 2
tPW
PDN VIL
Figure 7. Power Down & Reset Timing
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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OPERATION OVERVIEW
Non-PCM (AC- 3, MPEG, etc.) and DTS-C D Bitstream Detection
The AK4116 has a Non-PCM steam auto-detection function. When the 32-bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC60958 Interface” is detected, the NPCM bit goes to “1”. The 96-bit sync code consists of
0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM to “1”. Once the
NPCM is set to “1”, it will remain “1” until 4096 frames pass through the chip without an additional sync pattern being
detected (Timing diagram: Figure 26 and Figure 27). When those preambles are detected, the burst preambles Pc (burst
information: Table 8) and Pd (length code: Table 9) that follow those sync codes are stored to registers. The AK4116 also
has a DTS-CD bitstream auto-detect ion funct ion. When AK 4116 detects DTS-CD bitstream s, the DTSCD bit goes to “1”.
If the next sync code does not occur within 4096 frames, the DTSCD bit goes to “0” until either the AK4116 detects the
stream again. OR’ed value of the NPCM and DTSCD bits are output to the AUTO bit. The AK4116 detects 14bit sync
word of a DTS- CD bitstearm, while it does not detect 16bit sync word (0x7FFE8001).
Clock Recovery
The on-chip, low jitter PLL has a wide lock range of 32kHz to 48kHz and a lock time of less than 20ms. The AK4116 has
a sampling frequency detect function (32kHz, 44.1kHz and 48kHz) that uses either clock comparison against the X’tal
oscillator or the channel sta tus informatio n. The PLL loses lock when the received sync inte rval is incorr ect.
Clock Operation Mode
The AK4116 has two sources for MCKO and SDTO.
1) MCKO and SDTO source is recovered by PLL from RX input.
2) MCKO source is X’tal or External clock. SDTO source is DAUX input.
The CM1-0 bits select the clock operation mode (Table 1). In Mode 2, the clock source is switched from PLL to X'tal
when the PLL loses lock. In Mode3, even though the clock source is fixed to X'tal, the PLL is also operating. This allows
the monitoring of recovered data such as C bits. For Mode2 and 3, it is recommended that the X’tal frequency and PLL
recovery frequency be se t differently.
Mode CM1 CM0 UNLCK PLL X'tal Clock source SDTO
0 0 0 - ON ON(Note) PLL RX Default
1 0 1 - OFF ON X'tal DAUX
0 ON ON PLL RX
2 1 0 1 ON ON X'tal DAUX
3 1 1 - ON ON X'tal DAUX
ON: Oscillation (Power-up) , OFF : STOP (Power-down)
Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off.
Table 1. Clock Operation Mode select
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Master Cloc k Output
The AK4116 has a master clock output pin, MCKO. In PLL mode, PLL lock range is up to 48kHz and the MCKO
frequency is fixed to 256fs.
In the X’tal mode, XCKS1-0 bits select the ratio of the X’tal frequency t o fs (sampling frequency). The DIV bit selects
the ratio (x1 or x1/2) of the MCKO freque ncy to the X tal frequency (Table 2).
fs [kHz]
MCKO EXTCLK [MHz] X’tal [MHz]
XCKS1 XCKS0 X’tal
or
EXT DIV=0 DIV=1 2.048 4.096 8.192 11.2896 12.288 24.576
0 0 128fs 128fs 64fs 16 32 N/A N/A N/A N/A
0 1 256fs 256fs 128fs 8 16 32 44.1 48 N/A Default
1 0 512fs 512fs 256fs N/A 8 16 N/A N/A 48
1 1 1024fs 1024fs 512fs N/A N/A 8 N/A N/A N/A
Table 2. Master Clock Frequency Select
(X’tal mode: Clock operation mode 1, 2( UNLCK=1), 3)
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Clock Source
The follow ing circuits are available to fee d a clock into the XTI pin of AK4116.
1) X’ tal mode
The X’ ta l with proper value s hould be co nne cted be tw een X TI and XTO pins.
XTI
XTO
A
K4116
Figure 8. X’tal mode (EXCK= “0”)
Note: External capacitance depends on the crystal oscillator (Typ.10-40pF).
2) External clock mode
EXCK bit shoul d be set to “1” and the proper frequency clock input into the XTI pin. X T O pin should be left open.
XTI
XTO
A
K4116
External Clock
Figure 9. External clock mode (EXCK = “1”)
3) OFF mode
CM1-0 bits should be set to “00” and XTL1-0 bits to “11” respectively. XTI and XTO pins should be left open. The
XTI pin can also be connected to ground externally.
XTI
XTO
A
K4116
Figure 10. OFF mode (CM1-0 = “00”, XTL1- 0= “ 11”)
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Sampling Frequency and Pre-emphasis Dete ction
The AK4116 has two methods for detec ting the sample frequency:
1) Clock comparison betwee n rec overe d clock and the X’tal oscillator
FS3-0 bits indicate the detected RX input frequency referred to X’tal frequency. XTL1-0 bits select the reference
X’tal frequency (Table 3).
2) Sampling frequency in formation on cha nnel status
When XTL1-0= “11”, FS3-0 bits indicate the decoded sampling freq uency information from channel status.
XTL1 XTL0 X’tal Frequency
0 0 11.2896MHz Default
0 1 12.288MHz
1 0 24.576MHz
1 1 (Use channel status)
Table 3. Reference X’tal frequency
Except XTL1-0= “11” XTL1-0= “11”
Register output fs Consumer
mode
(Note 2) Pr ofessional mode
FS3 FS2 FS1 FS0
Clock compariso n
(Note 1) Byte3
Bit3,2,1,0 Byte0
Bit7,6 Byte4
Bit6,5,4,3
0 0 0 0 44.1kHz 44.1kHz ± 3% 0 0 0 0 0 1 0 0 0 0
0 0 0 1 Reserved Reserved 0 0 0 1 (Others)
0 0 1 0 48kHz 48kHz ± 3% 0 0 1 0 1 0 0 0 0 0
0 0 1 1 32kHz 32kHz ± 3% 0 0 1 1 1 1 0 0 0 0
1 0 0 0 Reserved Reserved ( 1 0 0 0 ) 0 0 1 0 1 0
1 0 1 0 Reserved Reserved ( 1 0 1 0 ) 0 0 0 0 1 0
1 1 0 0 Reserved Reserved ( 1 1 0 0 ) 0 0 1 0 1 1
1 1 1 0 Reserved Reserved ( 1 1 1 0 ) 0 0 0 0 1 1
Note 1: At least ±3% range is identified as the value in the Table 4. In case of an intermediate frequency of these two,
FS3-0 bits indicate the nearer value. When the frequency is much larger than 48kHz or much smaller than
32kHz, FS3-0 bits indicate any values except 32kH z, 44.1kHz and 48kHz.
Note 2: In cons umer mode, Byte3 Bit3-0 are copie d to FS3-0.
Table 4. Sam pling frequency information
The pre-emphasis information is detected and reported on the PEM bit. This information is extracted from channel 1 by
default (CS12=0). It can be switched to channel 2 by changing the CS 12 bit in the control register.
Consumer mode P rofessional mode
PEM Pre-emphasis Byte 0
Bits 3-5 Byte 0
Bits 2-4
0 OFF 0X100 110
1 ON 0X100 110
Table 5. Pre-emphasis inform ation
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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System Reset and Power-D own
The AK4116 has a full power-down mode for all circuits that is activated by the PDN pin, and a partial power-down
mode activated by the PWN bit. The RSTN bit initializes the internal registers and timing. The AK4116 should be reset
once at power-up by bringing PDN pin = “L”.
PDN Pi n:
All analog and digital circuits are placed in power-down and reset modes by bringing PDN= “L”. All the registers
are initial ized and cloc ks are stopped. Read/write operations to the registers are disabled.
RSTN Bit (Address 00H; D0):
All the registers except RSTN, PWN, XTL1-0 and EXCK are initialized by bringing RSTN bit = “0”. The internal
timings are also initialized. When RSTN bit= “0”, clocks are output, but SDTO is “L”. All register writes except
RSTN, PWN, XTL1-0 and EXCK are disabled. Reading from the registers is enabled.
PWN Bit (Address 00H; D1):
Clock recovery mode is initialized by bringing PWN bit = “0”. Clocks from the PLL are stopped while the X’tal
clocks continue to be output. Unlike the PDN pin operation described above, internal registers and mode settings
are not initialized. Read/write operations to the registers a re enabled.
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Biphase signal inpu t circuit
RX
AK4116
0.1uF
75
Coax 75
Figure 11. Consumer Input Circuit (Coaxial Input)
Note: When using a coaxial input, if the coupling level to this input from the next RX input
line pattern exceeds 50mV, incorrect operation may occur. This can be reduced or
prevented by adding a dec oupling capacitor.
RX
AK4116
470
O/E
Op tic a l Re c e iv e r
Optical
Fiber
3.3V 3.3V
Figure 12. Consumer Input Cir cuit (Optica l Inpu t; Using 3.3V Optical Receiver)
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Q-subcode buffers
The AK4116 has a Q-subcode buffer for CD application. The AK4116 takes Q-subcode into registers under the following
conditions:
1) The sync word (S0,S1) is consis ts of leas t 16 “0”s.
2) The start bit is “1”.
3) Those 7bits Q-W follow s to the start bit.
4) The distance between two sta rt bits is 8-16 bits.
The QINT bit in the control register goes “1” when the new Q-subcode diff ers from old one, and goes “0” when QINT bit
is read.
1 2 3 4 5 6 7 8 *
S0 0 0 0 0 0 0 0 0 0…
S1 0 0 0 0 0 0 0 0 0…
S2 1 Q2 R2 S2 T2 U2 V2 W2 0…
S3 1 Q3 R3 S3 T3 U3 V3 W3 0…
: : : : : : : : : :
S97 1 Q97 R97 S97 T97 U97 V97 W97 0…
S0 0 0 0 0 0 0 0 0 0…
S1 0 0 0 0 0 0 0 0 0…
S2 1 Q2 R2 S2 T2 U2 V2 W2 0…
S3 1 Q3 R3 S3 T3 U3 V3 W3 0…
: : : : : : : : : :
(*) number of "0" : min=0; max=8.
Figure 13. Configuration of U-bit(CD)
Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
CTRL ADRS TRACK NUMBER INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49
MINUTE SECOND FRAME
Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73
ZERO ABSOLUTE MINUTE ABSOLUTE SECOND
Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97
ABSOLUTE FRAME CRC
G(x)=x
16+x12+x5+1
Figure 14. Q-subcode
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
11H Q-subcode Address / Control Q9 Q8 · · · · · · · · · · · · Q3 Q2
12H Q-subcode Track Q17 Q16 · · · · · · · · · · · · Q11 Q10
13H Q-subcode Index · · · · · · · · · · · · · · · · · · · · · · · ·
14H Q-subcode Minute · · · · · · · · · · · · · · · · · · · · · · · ·
15H Q-subcode Second · · · · · · · · · · · · · · · · · · · · · · · ·
16H Q-subcode Frame · · · · · · · · · · · · · · · · · · · · · · · ·
17H Q-subcode Zero · · · · · · · · · · · · · · · · · · · · · · · ·
18H Q-subcode ABS Minute · · · · · · · · · · · · · · · · · · · · · · · ·
19H Q-subcode ABS Second · · · · · · · · · · · · · · · · · · · · · · · ·
1AH Q-subcode ABS Frame Q81 Q80 · · · · · · · · · · · · Q75 Q74
Figure 15. Q-subco de register map
Q
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Interrupt Handling
There are eight events which cause the INT1-0 pins to go “H”.
1. UNLCK: PLL unlock state detect
“1” when the PLL loses lock. The AK4116 loses lock when the distance between two preambles is
not correct or when those preambles a r e not correct.
2. PAR: Parity error or biphase coding error detection
“1” when parity error or biphase coding error is detected, updated every sub-frame cycle. Reading
this register resets it.
3. AUTO: Non-PCM or DTS-CD Bit S tream detect ion
The OR function of NPCM and DTSCD bit s is output to the AUTO bit.
4. V: Validity flag detection
“1” when validity flag is detected. Updated every sub-fram e cycle.
5. AUDION: Non-audio detection
“1” when the “AUDIO” bit in recovered channel status indicates “1” . Updated ever y block cycle.
6. STC: Sampling frequency or pre-emphasis information change detection
“1” when FS3-0 or PEM bit changes. Reading this re gister resets it.
7. QINT: U bit (Q-subcode) sync flag
“1” when the Q-subcode differs from old one, and stays “1” until this register is read. Updated
every sync code cycle for Q-subcode . Read ing this regis ter resets it.
8. CINT: Channel status sync flag
“1” when received C bits differ from old ones, and stays “1” until this register is read. Updated
every block cycle. Reading this register resets it.
INT1-0 pins o utput an OR’ed signal based on the above eight interrupt events. When masked, the in terrupt event does not
affect the operation of the INT1-0 pins (the masks do not affect the resisters (UNLCK, PAR, etc.) themselves). Once
INT0 pin goes to “H”, it maintains “H” for 1024 cycles (this value can be changed by the EFH1-0 bits) after all events
not masked by mask bits are cleared. INT1 pin immediately goes to “ L when those events are cleared.
UNLCK, AUTO, V and AUDION bits indicate th e interrupt status events above in real time. Once PAR, STC, QINT or
CINT bit goes to “1 ”, it stays “1” un til t he regis ter i s read . INT pin h olds “H” for o ne sub-f rame, t hen goes to “L” in t his
case.
When the AK4116 loses lock, the channel status bits are initialized. In this initial state, INT0 outputs the OR’ed signal
between UNLCK and PAR bits. INT1 outputs the OR’ed signal to AUTO, V and AUDION. INT1-0 pins are “L” when
the PLL is OFF (Clock Operation Mode 1).
Event
UNLCK PAR Others SDTO Pin
1 x x “L”
0 1 x Previous Data
0 0 x Output
Table 6. Interrupt handling
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Interrupt
(UNLCK, PAR,..)
INT1 pin
SDTO
(UNLCK)
MCK O,BICK,LRCK
(UNLCK)
Previous Data
Register (PAR,STC,
CINT,QINT) Hold ”1
Command READ 05H
MCK O,BICK,LRCK
(except UNLCK)
(fs: around 20kHz)
SDTO
(PAR error)
Hold Time = 0
Reset
(Interrupt)
SDTO
(others)
Normal Operation
INT0 pin Hold Time (max: 4096/fs)
Register
(others)
Fr ee R un
Figure 16. INT1-0 pin timing
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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INT0/1 pin ="H"
No
Yes
Yes
Initialize
PDN pin ="L" to "H"
Read 05H
Mute DAC output
Read 05H
No
(Each Error Handling)
Read 05H
(Resets registers)
INT0/1 pin ="H"
Release
Muting
Figure 17. Interrupt Handl ing S eque nce Exa m ple 1
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
- 20 -
INT1 pin ="H"
No
Yes
Initialize
PDN pin ="L" to "H"
Read 05H
Read 05H
and
Detect QSUB= “1”
No
(Read Q-buffer)
New data
is valid
INT 1 pin ="L"
QCRC = “0”
Yes
Yes
New data
is invalid
No
Figure 18. Interrupt Handling Sequence Example (for Q/CINT)
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Audio Serial Interfa ce Fo rmat
The DIF2-0 bits can select six serial data formats as shown in Table 7. In all formats, the serial data is MSB-first, 2’s
compliment format. The SDTO is clocked out on the falling edge of BICK and the DAUX is latched on the rising edge of
BICK. BICK outputs 64fs clock. Wh en the SDTO format is equal or less than 20 bits (Mode 0-2), LSBs in the sub-frame
are truncated. In Modes 3- 7, the last fo ur LSBs are auxiliary data (see Figure 19).
When a Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, the AK4116 continues to output the
last normal sub-frame data from SDTO repeatedly until the error is removed. When an Unlock Error occurs, the AK4116
outputs “0” from SDTO. When using the DAUX pin, the data is transformed and output from SDTO. The DAUX pin is
used in Clock Operation Modes 1, 3 and in the unlock state of Mode 2. The input data format to DAUX should be
left-justified except in Mode 5. In Mode 5, both the input data format of DAUX and the output data format of SDTO are
I2S.
0 3 4 7 8 11 12 27 28 29 30 31
preamble Aux.
LSB MSB
VUC P
su b-frame of IEC60958
023
AK4116 Audio Data (MSB First)
LSBM SB
Figure 19. Bit configuration
Mode DIF2 DIF1 DIF0 DAUX SDTO LRCK
0 0 0 0 24bit, Left justified 16bit, Right ju stified H/L
1 0 0 1 24bit, Left justified 18bit, Right ju stified H/L
2 0 1 0 24bit, Left justified 20bit, Right ju stified H/L
3 0 1 1 24bit, Left justified 24bit, Right ju stified H/L
4 1 0 0 24bit, Left justified 24bit, Left justified H/L Default
5 1 0 1 24bit, I2S 24bit, I2S L/H
6 1 1 0
7 1 1 1 Reserved
Table 7. Audio data format
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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LRCK
BICK
(64fs)
SDTO
0 1 2 31 0 1
15:MSB, 0:LSB
Lch Data Rch Data
15 1716 1531 0 1 2 1716
01 0 1
15 141415
Figure 20. Mode 0 Timing
LRCK
BICK
(64fs)
SDTO
0 1 2 31 0 1
23:MSB, 0:LSB
Lch Data Rch Data
9 1110 931 0 1 2 1110
01 0 1
12
21 202021
12
22 23 2223
Figure 21. Mode 3 Timing
LRCK
BICK
(64fs)
SDTO
0 1 2 31 0 1
23:MSB, 0:LSB
Lch Data Rch Data
21 2322 2131 0 1 2 2322
23 222
24
1 001
24
21 22 23 32 23 22
Figure 22. Mode 4 Timing
LRCK
BICK
(64fs)
SDTO
0 1 2 31 0 1
23:MSB, 0:LSB
Lch Data Rch Data
2322 2131 0 1 2 2322
23 22
24
10
24
32 23
25
2 0121 22 23
25
Figure 23. Mode 5 Timing
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Serial Control Interface
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, C1-0 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition
of CSN. The maximum speed of CCLK is 5MH z. PDN= “L” resets the registers to their default values.
CDTI
CCLK
CSN
C1
012345678 9 10 11 12 13 14 15
D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3
CDTO Hi-Z
WRITE
CDTI C1 D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3
CDTO Hi-Z
READ
D4D5D6D7 D0D1D2D3 Hi-Z
C1,C0: Chip Address (Fixed to “00”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 24. 4-wire Serial Control I/F Timing
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Power Down Control 0 0 0 EXCK XTL1 XTL0 PWN RSTN
01H Clock Control 1 0 1 DIV XCKS1 XCKS0 CM1 CM0
02H Input/Output Control 0 0 CS12 EFH1 EFH0 DIF2 DIF1 DIF0
03H INT0 MASK MULK0 MPAR0 MAUT0 MV0 MAUD0 MSTC0 MCIT0 MQIT0
04H INT1 MASK MULK1 MPAR1 MAUT1 MV1 MAUD1 MSTC1 MCIT1 MQIT1
05H Receiver status 0 UNLCK PAR AUTO V AUDION STC CINT QINT
06H Receiver status 1 0 DTSCD NPCM PEM FS3 FS2 FS1 FS0
07H Receiver status 2 0 0 0 0 0 0
CCRC QCRC
08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8
0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16
0BH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24
0CH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32
0DH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
0EH Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
0FH Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
10H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8
11H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2
12H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10
13H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18
14H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26
15H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34
16H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42
17H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50
18H Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58
19H Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66
1AH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74
Note: When PDN pin goes to “L”, the registers are initial iz ed to their defa ult va lue s.
When RSTN bit goes to “0”, the internal timing is reset and all registers except RSTN, PWN, XTL1-0 and EXCK
bits are initial ized to their default values.
All data can be written to the registers even if PWN bit is “0”.
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
- 25 -
Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Power Down Control 0 0 0 EXCK XTL1 XTL0 PWN RSTN
R/W RD RD RD R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 1 1
RSTN: Timing Reset & Regis ter Initialize
0: Reset & Initialize (except RSTN , PWN, XTL1-0 and EXCK bits)
1: Normal Operation (Default)
PWN: Power-Down for Clock Recove ry Part
0: Power Down
1: Normal Operation (Default)
XTL1-0: Refer ence X’tal Frequency Select (Table 3; Default: 00)
EXCK: External Clock Mode Select
0: X’tal mode (Default)
1: External clo ck mode (Feedback resistor of X’tal oscillator circuit is o pen.)
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Clock Control 1 0 1 DIV XCKS1 XCKS0 CM1 CM0
R/W RD RD RD R/W R/W R/W R/W R/W
Default 1 0 1 0 0 1 0 0
CM1-0: Master Cloc k O peratio n Mo de Se lect (Table 1; Default: 00)
XCKS1-0: Master Cl oc k F reque nc y Se lect at X’tal Mode (Table 2; Default: 01)
DIV: Master Clock Outp ut Select at X’tal Mode
0: Same frequency a s X’tal (Default)
1: Half frequency of X’tal
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Format Control 0 0 CS12 EFH1 EFH0 DIF2 DIF1 DIF0
R/W RD RD R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 1 1 0 0
DIF2-0: Audio Data Format Control (Table 7; Default: 100)
EFH1-0: INT0 Pin Hold Count Select
00: 512 LRCK 01: 1024 LRCK (Default)
10: 2048 LRCK 11: 4096 LRCK
CS12: Channe l Status Select
0: Channel 1 (Default)
1: Channel 2
This bit selects whi ch channel status i s used to derive C-bit bu ffers, AUDION, PEM, FS3-0, Pc, Pd
and CRC.
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
- 27 -
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H INT0 MASK MULK0 MPAR0 MAUT0 MV0 MAUD0 MSTC0 MCIT0 MQIT0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 1 1 1 1 1 1
MQIT0: Mask Enable for QINT bit
MCIT0: Mask Enable for CINT bit
MSTC0: Mask Enable for STC bit
MAUD0: Mask Enable for AUDION bit
MV0: Mask Enable for V bit
MAUT0: Mask Enable for AUTO bit
MPAR0: Mask Enable for PAR bit
MULK0: Mask Enable for UNLOCK bit
0: Mask disable
1: Mask enable
The factor which mask bit is set to 0” affects INT0 pin operation.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
04H INT0 MASK MULK1 MPAR1 MAUT1 MV1 MAUD1 MSTC1 MCIT1 MQIT1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 0 0 0 1 1 1
MQIT1: Mask Enable for QINT bit
MCIT1: Mask Enable for CINT bit
MSTC1: Mask Enable for STC bit
MAUD1: Mask Enable for AUDION bit
MV1: Mask Enable for V bit
MAUT1: Mask Enable for AUTO bit
MPAR1: Mask Enable for PAR bit
MULK1: Mask Enable for UNLOCK bit
0: Mask disable
1: Mask enable
The factor whose mask bit is set to “0” affect s INT1 pin operation.
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
05H Receiver status 0 UNLCK PAR AUTO V AUDION STC CINT QINT
R/W RD RD RD RD RD RD RD RD
Default 0 0 0 0 0 0 0 0
QINT: Q-subcode Buf fer Interrupt
0: No change 1: Changed
This bit goes to “1” when Q-subcode stored in register add resses 11H to 1AH is updated.
CINT: Channel Sta tus Buffer Interrupt
0: No change 1: Changed
This bit goes to “1” when C-bit stored in register addresses 08H to 0CH changes.
STC: Sam pling F re quenc y or Pre- em phasis Infor ma tio n Change De tect ion
0: No detect 1: Detect
This bit goes to “1” when either the FS3-0 or PEM bit changes.
AUDION: Audio Bit Output
0: Audio 1: Non Audio
This bit is made by encoding channe l status bits.
V: Validity Bit
0: Valid 1: Invalid
AUTO: Non-PCM or DTS-CD Bit Steam Auto Detection
0: No detect 1: Detect
This bit outputs the OR’ed value of NP CM and DTS CD bits.
PAR: Parity Error or Biphase Error Status
0:No Error 1:Error
This bit goes to “1” if a parity error or biph ase error is detected in the sub-frame.
UNLCK: PLL Lock Status
0: Lock 1: Unlock
QINT, CINT, STC and PAR bits are initialized when 05H is read.
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
06H Receiver status 1 0 DTSCD NPCM PEM FS 3 FS2 FS1 FS0
R/W RD RD RD RD RD RD RD RD
Default 0 0 0 0 0 0 0 1
FS3-0: Sampling Fr e quency D etectio n (Table 4)
PEM: Pre-emphasis Detect
0: OFF 1: ON
This bit is made by encoding the channel status bits.
NPCM: Non-PCM Bit Stream Auto Detection
0: No detect 1: Detect
DTSCD: DTS-CD Bit Stream Auto Detect
0: No detect 1: Detect
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
07H Receiver status 2 0 0 0 0 0 0 CCRC QCRC
R/W RD RD RD RD RD RD RD RD
Default 0 0 0 0 0 0 0 0
QCRC: Cyclic Redundancy Check for Q-subcode
0: No Error 1: Error
CCRC: Cyclic Redundancy Check for Channel Status
0: No Error 1: Error
This bit is enabled only in professional mode and only for the channel se lected by the CS12 bit.
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8
0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16
0BH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24
0CH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32
R/W RD
Default Not initialized
CR39-0: Receiver Cha nne l Status Byte 4-0
All 40 bits are updated at the same time every block (192 frames) cycle.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0DH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
0EH Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
0FH Burst Preamble Pd Byte 0 PD7 P D 6 P D 5 PD4 PD3 PD2 PD1 PD 0
10H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD1 1 PD10 PD9 PD8
R/W RD
Default Not initialized
PC15-0: Burst Preamble Pc Byte 0 and 1
PD15-0: Burst P reamble Pd Byte 0 an d 1
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
11H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2
12H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10
13H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18
14H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26
15H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34
16H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42
17H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50
18H Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58
19H Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66
1AH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74
R/W RD
Default Not initialized
Q2-81: Q-subc ode (Figure 14 a nd Figure 15)
All 80 bits are updated at the same time every sync code cycle for Q-subcode.
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Burst Preambles in non-PCM Bitstreams
0
16 bits of bitstream
34 781112 27 28 29 30 31
preamble Aux. LSB MSB V U C P
sub-frame of IEC60958
015
Pa Pb Pc Pd Burst_payload stuffing
repetition time of the burst
Figure 25. Data structure in IEC609 58
Preamble word Length of field Contents Value
Pa 16 bits sync word 1 0xF872
Pb 16 bits sync word 2 0x4E1F
Pc 16 bits Burst info see Table 9
Pd 16 bits Length code numbers of bits
Table 8. Burst preamble words
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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Bits of Pc value contents repetition time of burst
in IEC958 frames
0-4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
data type
NULL data
Dolby AC- 3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 witho ut extension
MPEG-2 data with extensi on
MPEG-2 AAC ADTS
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
5, 6 0 reserved, shall be set to “0”
7 0
1 error -flag i ndicating a valid burst_payload
error-flag indicating that the burst_payload may contain
errors
8-12 data type dependent info
13-15 0 bit stream number, shall be set to “0”
Table 9. Fields of burst info Pc
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
- 33 -
Non-PCM Bitstream timing
1) When Non-PCM preamble does not ar rive within 4096 frames,
Pa Pc1Pd1
Pb Pa Pc2Pd2
Pb Pa Pc3Pd3
Pb
“0” Pc1Pc2
“0” Pd1Pd2Pd3
Pc3
PDN pin
Bit stream
A
UTO bi
t
Pc Register
Pd Registe
Repetition time >4096 frames
Figure 26. Timing example 1
2) When Non-PCM bitstream stops (when MULK0=0),
Pa Pc1Pd1
Pb Stop Pa PcnPdn
Pb
Pc0Pc1
Pd0Pd1Pdn
Pcn
INT 0 pin
Bit stream
A
UTO bi
t
Pc Register
Pd Registe
r
INT 0 hold tim e
2~3 Syncs (B,M or W)
<20 mS (L ock time)
<Rep etition time
Figure 27. Timing example 2
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
- 34 -
SYSTEM DESIGN
Figure 28 is a system connection diagram. An evaluation board is available which demonstrates application circuits, the
optimum layout, power supply arrangements and measurement results.
10u
+
3.3V Supply
0.1u 10u
+
12k
S/PDIF (see Figure 11-13)
AD/DA
Micro-
controller
C
0.1u
3.3V Supply
C
(see Figure 8-10)
DS
P
AVD
D
1
9
18
1
7
16
R
AVS
S
LRC K
6
7
8
9
10
DAU
X
BICK
SDT
O
MCK
O
PD
N
INT
0
20
1
2
3
4
5 11
15
14
13
12
RX0
DVDD
DVSS
XTI
XTO
INT1
CS
N
CCL
K
CDTI
CDT
O
AK4116
Figure 28. Typical Connection Diagram
Notes:
(1) “C” depends on the X’tal. (Typ.10-40pF)
(2) AVSS and DVSS must be connected the same ground plane.
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
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PACKAGE
20pin QFN (Unit: mm)
4.20 ± 0.10
4.20 ± 0.10
0.22 ± 0.05
4.00 ± 0.05
4.00 ± 0.05
0.50
0.05 M
0.05
1.00
SAB
1.00
C0.7
0.22 ± 0.05
45.0° 45.0°
3 - 0.69 ± 0.11
0.35 ± 0.11
0.50
B
A
3 - C0.2
0.60 ± 0.10 S
+ 0.03
- 0.05
0.22
S
0.02TYP
0.005MIN 0.04MAX
0.90 ± 0.05
Note: The black parts of ba ck package should be ope n.
Material & Lead finish
Package m olding comp ound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
- 36 -
MARKING
4116
X
XXX
1
XXXX : Date code identifier (4 digits)
Revision History
Date (YY/MM/DD) Revision Reason Page Contents
02/05/27 00 First Edition
03/04/14 01 Error Correct 1 General Description:
“Mode settings can be controlled via
microprocessor serial interface or via dedicated
pin.” “Mode settings can be controlled via
microprocessor serial interface.
21
Audio Serial Interface Format:
“The DIF2-0 pins can select...” Æ“ The DIF2-0
bits can select...”
04/04/19 02 Error Correct 16 Figure 15. Q-subcode register map
Addr = 16H 1FH Æ 11H 1AH
32
Table 9. Fields of burst info Pc
Value 7: reserved Æ MPEG2 AAC ADTS;
repetition time of b urs t: 102 4
Value 14: reserved Æ ATRAC; repetition time
of burst: 512
Value 15: reserved Æ ATRAC2/3; repetition
time of burst: 1024
Value 27: (Reserved for MPEG-4 AAC data)
Æ reserved
Value 28: MPEG-2 A A C data Æ reserved
05/08/24 03 Error Correct 3 Order ing Guide : AK4116VF Æ AK41 16VN
ASAHI KASEI [AK411 6]
MS0156-E-03 2005/08
- 37 -
IMPORTANT NOTICE
These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authoriz ed distributor conc erning their current s tatus.
AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information c ontained herein.
Any export of t hese products, or devices or systems containing them, may require a n export license
or other official approval under the law and regulations of the country of export pertaining to
customs and tariffs, curren cy exchange, or st rategic materials.
AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to funct ion or perform may reasonably be expected to result in loss of life or in signif icant
injury or damage to perso n or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditi ons, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such not ification.