KAI-11002 IMAGE SENSOR 4008 (H) X 2672 (V) INTERLINE CCD IMAGE SENSOR JUNE 22, 2012 DEVICE PERFORMANCE SPECIFICATION REVISION 1.0 PS-0012 KAI-11002 Image Sensor TABLE OF CONTENTS Summary Specification ......................................................................................................................................................................................... 5 Description .................................................................................................................................................................................................... 5 Features ......................................................................................................................................................................................................... 5 Applications .................................................................................................................................................................................................. 5 Ordering Information ............................................................................................................................................................................................ 6 Device Description ................................................................................................................................................................................................. 7 Architecture .................................................................................................................................................................................................. 7 Pixel................................................................................................................................................................................................................. 8 Vertical to Horizontal Transfer ................................................................................................................................................................ 9 Horizontal Register to Floating Diffusion .......................................................................................................................................... 10 Horizontal Register Split......................................................................................................................................................................... 11 Single Output Operation .................................................................................................................................................................... 11 Dual Output Operation ....................................................................................................................................................................... 11 Output ......................................................................................................................................................................................................... 12 Pin Description and Physical Orientation ........................................................................................................................................... 13 Imaging Performance .......................................................................................................................................................................................... 14 Imaging Performance Operational Conditions ................................................................................................................................. 14 Specifications............................................................................................................................................................................................. 14 All Configurations ................................................................................................................................................................................ 14 KAI-11002-ABA Configuration .......................................................................................................................................................... 15 KAI-11002-CBA Configuration........................................................................................................................................................... 15 Typical Performance Curves ............................................................................................................................................................................ 16 Quantum Efficiency.................................................................................................................................................................................. 16 Monochrome with Microlens ............................................................................................................................................................. 16 Monochrome without Microlens ...................................................................................................................................................... 16 Color with Microlens ............................................................................................................................................................................ 17 Color without Microlens ..................................................................................................................................................................... 17 Angular Quantum Efficiency .................................................................................................................................................................. 18 Monochrome with Microlens ............................................................................................................................................................. 18 Color with Microlens ............................................................................................................................................................................ 18 Power - Estimated .................................................................................................................................................................................... 19 Frame Rates - Continuous Mode .......................................................................................................................................................... 19 Defect Definitions ................................................................................................................................................................................................ 20 Defect Map ................................................................................................................................................................................................. 20 Test Definitions ..................................................................................................................................................................................................... 21 Test Regions of Interest ......................................................................................................................................................................... 21 OverClocking ............................................................................................................................................................................................. 21 Tests ............................................................................................................................................................................................................. 22 Dark Field Defect Test ........................................................................................................................................................................ 22 Bright Field Defect Test ...................................................................................................................................................................... 22 Operation .................................................................................................................................................................................................................. 23 Maximum Ratings ..................................................................................................................................................................................... 23 Maximum Voltage Ratings Between Pins .......................................................................................................................................... 23 DC Bias Operating Conditions ............................................................................................................................................................... 23 Power Up Sequence ............................................................................................................................................................................. 24 AC Operating Conditions ........................................................................................................................................................................ 24 Clock Levels ........................................................................................................................................................................................... 24 Clock Line Capacitances ...................................................................................................................................................................... 24 www.truesenseimaging.com Revision 1.0 PS-0012 Pg 2 KAI-11002 Image Sensor Timing Requirements .............................................................................................................................................................................. 25 Main Timing - Continuous Mode .......................................................................................................................................................... 25 Frame Timing - Continuous Mode ....................................................................................................................................................... 26 Frame Timing without Binning .......................................................................................................................................................... 26 Frame Timing for Vertical Binning by 2 .......................................................................................................................................... 26 Frame Timing Edge Alignment .......................................................................................................................................................... 27 Line Timing - Continuous Mode............................................................................................................................................................ 28 Line Timing Single Output.................................................................................................................................................................. 28 Line Timing Dual Output - Left Output .......................................................................................................................................... 28 Line Timing Dual Output - Right Output ....................................................................................................................................... 29 Line Timing Vertical Binning by 2 ..................................................................................................................................................... 29 Line Timing Detail................................................................................................................................................................................. 30 Line Timing Binning by 2 Detail ........................................................................................................................................................ 30 Line Timing Edge Alignment .............................................................................................................................................................. 31 Pixel Timing - Continuous Mode .......................................................................................................................................................... 32 Pixel Timing Detail ............................................................................................................................................................................... 32 Fast Line Dump Timing ............................................................................................................................................................................ 33 Electronic Shutter..................................................................................................................................................................................... 34 Electronic Shutter Line Timing .......................................................................................................................................................... 34 Electronic Shutter - Integration Time Definition ......................................................................................................................... 34 Electronic Shutter Description .......................................................................................................................................................... 35 Storage and Handling .......................................................................................................................................................................................... 36 Storage Conditions................................................................................................................................................................................... 36 ESD ............................................................................................................................................................................................................... 36 Cover Glass Care and Cleanliness ......................................................................................................................................................... 36 Environmental Exposure ........................................................................................................................................................................ 36 Soldering Recommendations ................................................................................................................................................................ 36 Mechanical Information ..................................................................................................................................................................................... 37 Package ....................................................................................................................................................................................................... 37 Die to Package Alignment ...................................................................................................................................................................... 38 Glass ............................................................................................................................................................................................................. 39 Glass Transmission ................................................................................................................................................................................... 40 Quality Assurance and Reliability .................................................................................................................................................................. 41 Quality and Reliability ............................................................................................................................................................................. 41 Replacement .............................................................................................................................................................................................. 41 Liability of the Supplier ........................................................................................................................................................................... 41 Liability of the Customer ........................................................................................................................................................................ 41 Test Data Retention ................................................................................................................................................................................. 41 Mechanical.................................................................................................................................................................................................. 41 Life Support Applications Policy .................................................................................................................................................................... 41 Revision Changes................................................................................................................................................................................................... 42 MTD/PS-0938 ............................................................................................................................................................................................. 42 PS-0012 ....................................................................................................................................................................................................... 42 www.truesenseimaging.com Revision 1.0 PS-0012 Pg 3 KAI-11002 Image Sensor TABLE OF FIGURES Figure 1: Block Diagram ................................................................................................................................................................................ 7 Figure 2: Pixel Architecture .......................................................................................................................................................................... 8 Figure 3: Vertical to Horizontal Transfer Architecture ......................................................................................................................... 9 Figure 4: Horizontal Register to Floating Diffusion Architecture ....................................................................................................10 Figure 5: Horizontal Register .....................................................................................................................................................................11 Figure 6: Output Architecture ...................................................................................................................................................................12 Figure 7: Pin Description .............................................................................................................................................................................13 Figure 8: Monochrome with Microlens Quantum Efficiency..............................................................................................................16 Figure 9: Monochrome without Microlens Quantum Efficiency .......................................................................................................16 Figure 10: Color with Microlens Quantum Efficiency Using AR Glass .............................................................................................17 Figure 11: Color without Microlens Quantum Efficiency Using AR Glass .......................................................................................17 Figure 12: Monochrome with Microlens Angular Quantum Efficiency ...........................................................................................18 Figure 13: Color with Microlens Angular Quantum Efficiency ..........................................................................................................18 Figure 14: Power ...........................................................................................................................................................................................19 Figure 15: Frame Rates ................................................................................................................................................................................19 Figure 16: Overclock Regions of Interest ...............................................................................................................................................21 Figure 17: Main Timing - Continuous Mode............................................................................................................................................25 Figure 18: Framing Timing without Binning ...........................................................................................................................................26 Figure 19: Frame Timing for Vertical Binning by 2 ...............................................................................................................................26 Figure 20: Frame Timing Edge Alignment ..............................................................................................................................................27 Figure 21: Line Timing Single Output ......................................................................................................................................................28 Figure 22: Line Timing Dual Output - Left Output...............................................................................................................................28 Figure 23: Line Timing Dual Output - Right Output ............................................................................................................................29 Figure 24: Line Timing Vertical Binning by 2 ..........................................................................................................................................29 Figure 25: Line Timing Detail .....................................................................................................................................................................30 Figure 26: Line Timing by 2 Detail ............................................................................................................................................................30 Figure 27: Line Timing Edge Alignment ..................................................................................................................................................31 Figure 28: Pixel Timing ................................................................................................................................................................................32 Figure 29: Pixel Timing Detail ....................................................................................................................................................................32 Figure 30: Fast Line Dump Timing ............................................................................................................................................................33 Figure 31: Electronic Shutter Line Timing ..............................................................................................................................................34 Figure 32: Integration Time Definition ....................................................................................................................................................34 Figure 33: Package Drawing .......................................................................................................................................................................37 Figure 34: Die to Package Alignment ......................................................................................................................................................38 Figure 35: Glass Drawing.............................................................................................................................................................................39 Figure 36: Glass Transmission ....................................................................................................................................................................40 www.truesenseimaging.com Revision 1.0 PS-0012 Pg 4 KAI-11002 Image Sensor Summary Specification KAI-11002 Image Sensor DESCRIPTION The KAI-11002 Image Sensor is a high-performance 11million pixel sensor designed for professional digital still camera applications. The 9.0 m square pixels with microlenses provide high sensitivity and the large full well capacity results in high dynamic range. The two highspeed outputs and binning capabilities allow for 1-3 frames per second (fps) video rate for the progressively scanned images. The vertical overflow drain structure provides antiblooming protection and enables electronic shuttering for precise exposure control. Other features include low dark current, negligible lag and low smear. FEATURES High resolution Parameter Value Architecture Interline CCD; Progressive Scan Total Number of Pixels 4072 (H) x 2720 (V) = 11.1M Number of Effective Pixels 4033 (H) x 2688 (V) = 10.8M Number of Active Pixels 4008 (H) x 2672 (V) = 10.7M Number of Outputs 1 or 2 High sensitivity High dynamic range Pixel Size 9.0 m (H) x 9.0 m (V) Low noise architecture Imager Size 43.3mm (diagonal) High frame rate Chip Size 37.25mm (H) x 25.70mm (V) Aspect Ratio 3:2 Binning capability for higher frame rate Saturation Signal 60,000 electrons Electronic shutter Quantum Efficiency KAI-11002-ABA KAI-11002-CBA (RGB) 50% 34%, 37%, 42% Output Sensitivity 13 V/e Total Noise 30 electrons Dark Current < 50 mV/s Dark Current Doubling Temperature 7 C Dynamic Range 66 dB Charge Transfer Efficiency > 0.99999 Blooming Suppression > 1000X Smear < -80 dB Image Lag < 10 electrons Maximum Data Rate 28 MHz Package 40-pin, CerDIP, 0.070" pin spacing APPLICATIONS Industrial Inspection Aerial Photography Cover Glass AR Coated All parameters above are specified at T = 40 C www.truesenseimaging.com Revision 1.0 PS-0012 Pg 5 KAI-11002 Image Sensor Ordering Information Catalog Number Product Name 4H0745 KAI-11002-AAA-CR-B1 Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Grade 1 4H0746 KAI-11002-AAA-CR-B2 Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Grade 2 4H0747 KAI-11002-AAA-CR-AE Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Engineering Sample 4H0805 KAI-11002-ABA-CD-BX Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Special Grade 4H0735 KAI-11002-ABA-CD-B0 Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Grade 0 4H0736 KAI-11002-ABA-CD-B1 Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Grade 1 4H0737 KAI-11002-ABA-CD-B2 Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Grade 2 4H0738 KAI-11002-ABA-CD-AE Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Engineering Sample 4H0742 KAI-11002-ABA-CR-B1 Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Grade 1 4H0743 KAI-11002-ABA-CR-B2 Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Grade 2 4H0744 KAI-11002-ABA-CR-AE Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Engineering Sample 4H0732 KAI-11002-CAA-CD-B1 Color (Bayer RGB), No Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Grade 1 4H0733 KAI-11002-CAA-CD-B2 Color (Bayer RGB), No Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Grade 2 4H0734 KAI-11002-CAA-CD-AE Color (Bayer RGB), No Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Engineering Sample 4H0739 KAI-11002-CBA-CD-B1 Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Grade 1 4H0740 KAI-11002-CBA-CD-B2 Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Grade 2 4H0741 KAI-11002-CBA-CD-AE Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Engineering Sample 4H0178 KEK-4H0178-KAI-11000/11002-12-30 Description Evaluation Board (Complete Kit) Marking Code KAI-11002-AAA S/N KAI-11002-ABA S/N KAI-11002-CAA S/N KAI-11002-CBA S/N n/a See Application Note Product Naming Convention for a full description of the naming convention used for Truesense Imaging image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.truesenseimaging.com. Please address all inquiries and purchase orders to: Truesense Imaging, Inc. 1964 Lake Avenue Rochester, New York 14615 Phone: (585) 784-5500 E-mail: info@truesenseimaging.com Truesense Imaging reserves the right to change any information contained herein without notice. All information furnished by Truesense Imaging is believed to be accurate. www.truesenseimaging.com Revision 1.0 PS-0012 Pg 6 KAI-11002 Image Sensor Device Description ARCHITECTURE 16 Dark Rows G R Pixel 1,1 B G G R B G G R 8 Buffer Rows 17 Dark Rows Fast Line Dump Video L Single or Dual Output 4 Dummy Pixels 4008 (H) x 2672 (V) Active Pixels 19 Dark Columns B G G R 13 Buffer Columns 12 Buffer Columns 4 Dummy Pixels 20 Dark Columns 8 Buffer Rows B G 4 20 12 4 20 12 Video R 4008 2004 2004 13 19 4 13 19 4 Figure 1: Block Diagram There are 17 light shielded rows followed 2688 photoactive rows and finally 16 more light shielded rows. The first 8 and the last 8 photoactive rows are buffer rows giving a total of 2672 lines of image data. In the single output mode all pixels are clocked out of the Video L output in the lower left corner of the sensor. The first 4 empty pixels of each line do not receive charge from the vertical shift register. The next 20 pixels receive charge from the left light shielded edge followed by 4033 photosensitive pixels and finally 19 more light shielded pixels from the right edge of the sensor. The first 12 and last 13 photosensitive pixels are buffer pixels giving a total of 4008 pixels of image data. In the dual output mode the clocking of the right half of the horizontal CCD is reversed. The left half of the image is clocked out Video L and the right half of the image is clocked out Video R. For the Video L each row consists of 4 empty pixels followed by 20 light shielded pixels followed by 2016 photosensitive pixels. For the Video R each row consists of 4 empty pixels followed by 19 light shielded pixels followed by 2017 photosensitive pixels. When reconstructing the image, data from Video R will have to be reversed in a line buffer and appended to the Video L data. The dark rows are not entirely dark and so should not be used for a dark reference level. Use the dark columns on the left or right side of the image sensor as a dark reference. Of the dark columns, the first and last dark columns should not be used for determining the zero signal level. Some light does leak into the first and last dark columns. www.truesenseimaging.com Revision 1.0 PS-0012 Pg 7 KAI-11002 Image Sensor PIXEL Top View Cross Section Down Through VCCD Direction of Charge Transfer V1 V1 V2 V1 9.0 m Photodiode Transfer Gate n- V2 n- Direction of Charge Transfer nn p Well (GND) 9.0 m n Substrate True Two Phase Burried Channel VCCD Lightshield over VCCD not shown Cross Section Through Photodiode and VCCD Phase 2 at Transfer Gate Cross Section Through Photodiode and VCCD Phase 1 Photo diode p p+ n Light Shield p n p Light Shield Transfer Gate V1 p V2 p+ n p n p p p n Substrate n Substrate p Cross Section Showing Lenslet Drawings not scale Lenslet Red Color Filter Light Shield VCCD Light Shield VCCD Photodiode Figure 2: Pixel Architecture An electronic representation of an image is formed when incident photons falling on the sensor plane create electronhole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. www.truesenseimaging.com Revision 1.0 PS-0012 Pg 8 KAI-11002 Image Sensor VERTICAL TO HORIZONTAL TRANSFER Direction of Vertical Charge Transfer Top View V1 Photo diode Transfer Gate V2 V1 Fast Line Dump V2 Lightshield not shown H H2 1 S B H 2 B H1S Direction of Horizontal Charge Transfer Figure 3: Vertical to Horizontal Transfer Architecture When the V1 and V2 timing inputs are pulsed, charge in every pixel of the VCCD is shifted one row towards the HCCD. The last row next to the HCCD is shifted into the HCCD. When the VCCD is shifted, the timing signals to the HCCD must be stopped. H1 must be stopped in the high state and H2 must be stopped in the low state. The HCCD clocking may begin THD s after the falling edge of the V1 and V2 pulse. Charge is transferred from the last vertical CCD phase into the H1S horizontal CCD phase. Refer to Figure 25 for an example of timing that accomplishes the vertical to horizontal transfer of charge. If the fast line dump is held at the high level (FDH) during a vertical to horizontal transfer, then the entire line is removed and not transferred into the horizontal register. www.truesenseimaging.com Revision 1.0 PS-0012 Pg 9 KAI-11002 Image Sensor HORIZONTAL REGISTER TO FLOATING DIFFUSION RD R n+ n OG H1 H2S H2B n- n+ H1S n- H1B H2S n- n (burried channel) Floating Diffusion p (GND) n (SUB) Figure 4: Horizontal Register to Floating Diffusion Architecture The HCCD has a total of 4080 pixels. The 4072 vertical shift registers (columns) are shifted into the center 4072 pixels of the HCCD. There are 4 pixels at both ends of the HCCD, which receive no charge from a vertical shift register. The first 4 clock cycles of the HCCD will be empty pixels (containing no electrons). The next 20 clock cycles will contain only electrons generated by dark current in the VCCD and photodiodes. The next 4033 clock cycles will contain photoelectrons (image data). Finally, the last 19 clock cycles will contain only electrons generated by dark current in the VCCD and photodiodes. Of the 20 dark columns at the start of the line and the 19 dark columns at the end of the line, the first and last dark columns should not be used for determining the zero signal level. Some light does leak into the first and last dark columns. Only use the center 18 columns of the 20 column dark reference at the start of the line. Only use the center 17 columns of the 19 column dark reference at the end of the line. When the HCCD is shifting valid image data, the timing inputs to the electronic shutter (SUB), VCCD (V1, V2), and fast line dump (FD) should be not be pulsed. This prevents unwanted noise from being introduced. The HCCD is a type of charge coupled device known as a pseudo-two phase CCD. This type of CCD has the ability to shift charge in two directions. This allows the entire image to be shifted out to the video L output, or to the video R output (left/right image reversal). The HCCD is split into two equal halves of 2040 pixels each. When operating the sensor in single output mode the two halves of the HCCD are shifted in the same direction. When operating the sensor in dual output mode the two halves of the HCCD are shifted in opposite directions. The direction of charge transfer in each half is controlled by the H1BL, H2BL, H1BR, and H2BR timing inputs. www.truesenseimaging.com Revision 1.0 PS-0012 Pg 10 KAI-11002 Image Sensor HORIZONTAL REGISTER SPLIT H1 H2 H2 H1 H1BL H2SL H2BL H1SL H1 H1BL H2 H2 H1 H1 H2 H2SL H1BR H1SR H2BR H2SR Pixel 2040 Pixel 2041 Single Output H1 H2 H2 H1 H1BL H2SL H2BL H1SL H1 H1BL H2 H1 H1 H2 H2 H2SL H1BR H1SR H2BR H2SR Pixel 2040 Pixel 2041 Dual Output Figure 5: Horizontal Register Single Output Operation When operating the sensor in single output mode all pixels of the image sensor will be shifted out the Video L output (pin 2). To conserve power and lower heat generation the output amplifier for Video R may be turned off by connecting VDDR (pin 18) and VOUTR (pin 19) to GND (zero volts). The H1 timing from the timing diagrams should be applied to H1SL, H1BL, H1SR, H2BR, and the H2 timing should be applied to H2SL, H2BL, H2SR, and H1BR. In other words, the clock driver generating the H1 timing should be connected to pins 8, 9, 13, and 11. The clock driver generating the H2 timing should be connected to pins 7, 10, 14, and 12. The horizontal CCD should be clocked for 4 empty pixels plus 20 light shielded pixels plus 4032 photoactive pixels plus 20 light shielded pixels for a total of 4076 pixels. H1BINL and H1BINR use the H1 timing, but should be generated from a separate clock driver for optimal performance. Dual Output Operation In dual output mode the connections to the H1BR and H2BR pins are swapped from the single output mode to change the direction of charge transfer of the right side horizontal shift register. In dual output mode both VDDL and VDDR (pins 3, 18) should be connected to 15 V. The H1 timing from the timing diagrams should be applied to H1SL, H1BL, H1SR, H1BR, and the H2 timing should be applied to H2SL, H2BL, H2SR, and H2BR. The clock driver generating the H1 timing should be connected to pins 8, 9, 13, and 12. The clock driver generating the H2 timing should be connected to pins 7, 10, 14, and 11. The horizontal CCD should be clocked for 4 empty pixels plus 20 light shielded pixels plus 2016 photoactive pixels for a total of 2040 pixels. If the camera is to have the option of dual or single output mode, the clock driver signals sent to H1BR and H2BR may be swapped by using a relay. Another alternative is to have two extra clock drivers for H1BR and H2BR and invert the signals in the timing logic generator. If two extra clock drivers are used, care must be taken to ensure the rising and falling edges of the H1BR and H2BR clocks occur at the same time (within 3ns) as the other HCCD clocks. www.truesenseimaging.com Revision 1.0 PS-0012 Pg 11 KAI-11002 Image Sensor OUTPUT H1B H1S HCCD Charge Transfer H2B H2S 31 K H1BIN VDD OG R RD Floating Diffusion VOUT Source Follower #1 Source Follower #2 Source Follower #3 Figure 6: Output Architecture Charge packets contained in the horizontal register are dumped pixel by pixel onto the floating diffusion (fd) output node whose potential varies linearly with the quantity of charge in each packet. The amount of potential charge is determined by the expression Vfd=Q/Cfd. A three-stage source-follower amplifier is used to buffer this signal voltage off chip with slightly less than unity gain. The translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of microvolts per electron (V/e ). After the signal has been sampled off chip, the reset clock (R) removes the charge from the floating diffusion and resets its potential to the reset drain voltage (RD). www.truesenseimaging.com Revision 1.0 PS-0012 Pg 12 KAI-11002 Image Sensor OGR 29 28 27 12 13 14 15 16 17 18 19 20 GND V2 21 V1 FD VRDR GND ESD GND GND GND 26 25 24 23 22 34 33 32 31 30 H1BR GND GND GND SUB GND 39 38 37 36 35 V2 FD 40 V1 OGL VRDL PIN DESCRIPTION AND PHYSICAL ORIENTATION GND H2SL RR H1BINL VOUTR GND 10 11 VDDR VDDL 9 GND VOUTL 8 H1BINR 7 H2SR 6 H1SR 5 H2BL 4 H2BR 3 H1BL 2 H1SL 1 RL Pixel 1,1 Figure 7: Pin Description Pin Name Description Pin Name Description 1 RL Reset Gate, Left 40 OGL Output Gate, Left 2 VOUTL Video Output, Left 39 FD Fast Line Dump Gate 3 VDDL Vdd, Left 38 RDL Reset Drain, Left 4 GND Ground 37 V1 Vertical Clock, Phase 1 5 H1BINL H1 Last Phase, Left 36 V2 Vertical Clock, Phase 2 6 GND Ground 35 GND Ground 7 H2SL H2 Storage, Left 34 SUB Substrate 8 H1SL H1 Storage, Left 33 GND Ground 9 H1BL H1 Barrier, Left 32 GND Ground 10 H2BL H2 Barrier, Left 31 GND Ground 11 H2BR H2 Barrier, Right 30 GND Ground 12 H1BR H1 Barrier, Right 29 GND Ground 13 H1SR H1 Storage, Right 28 GND Ground 14 H2SR H2 Storage, Right 27 ESD ESD Protection 15 GND Ground 26 GND Ground 16 H1BINR H1 Last Phase, Right 25 V1 Vertical Clock, Phase 1 17 GND Ground 24 V2 Vertical Clock, Phase 2 18 VDDR Vdd, Right 23 RDR Reset Drain, Right 19 VOUTR Video Output, Right 22 FD Fast Line Dump Gate 20 RR Reset Gate, Right 21 OGR Output Gate, Right The pins are on a 0.070" spacing www.truesenseimaging.com Revision 1.0 PS-0012 Pg 13 KAI-11002 Image Sensor Imaging Performance IMAGING PERFORMANCE OPERATIONAL CONDITIONS Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions. Description Condition Notes Frame Time 1732 msec 1 Horizontal Clock Frequency 10 MHz Light Source Continuous red, green and blue illumination centered at 450, 530 and 650 nm Operation Nominal operating voltages and timing Notes: 1. 2. 3. 2,3 Electronic shutter is not used. Integration time equals frame time. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP-8115. For monochrome sensor, only green LED used. SPECIFICATIONS All Configurations Units Sample Plan 2 % Design 2, 3 n/a 10 % Design 2, 3 n/a 1 % Design 2, 3 139 ke- Design 90 91 ke- Die PNe 58 60 ke- Die Horizontal CCD Charge Transfer Efficiency HCTE 0.99999 n/a Design Vertical CCD Charge Transfer Efficiency VCTE 0.99999 n/a Design Photodiode Dark Current Ipd n/a 800 e/p/s Die 27, 40 Photodiode Dark Current Ipd n/a 0.15 nA/cm2 Die 27, 40 Vertical CCD Dark Current Ivd n/a 3800 e/p/s Die 27, 40 Die 27, 40 Description Symbol Min. Nom. Maximum Photoresponse Nonlinearity NL n/a Maximum Gain Difference Between Outputs G Max. Signal Error due to Nonlinearity Dif. NL Horizontal CCD Charge Capacity HNe Vertical CCD Charge Capacity VNe Photodiode Charge Capacity Max. Vertical CCD Dark Current Ivd n/a 0.5 nA/cm Image Lag Lag n/a <10 50 e- Antiblooming Factor Xab 100 300 n/a Vertical Smear Smr n/a -85 -75 Total Noise ne-T Dynamic Range DR Output Amplifier DC Offset Vodc Output Amplifier Bandwidth F-3db Output Amplifier Impedance ROUT Output Amplifier Sensitivity V/N www.truesenseimaging.com 4 Notes Design Design dB Design 30 e-rms Design 4 66 dB Design 5 14 V Die MHz Die 200 Ohms Die V/e- Design 9 106 100 2 Temperature Tested At (C) 150 13 6 Revision 1.0 PS-0012 Pg 14 KAI-11002 Image Sensor KAI-11002-ABA Configuration Symbol Min. Nom. Max. Units Sample Plan Peak Quantum Efficiency QEmax 45 50 n/a % Design Peak Quantum Efficiency Wavelength QE n/a 500 n/a nm Min. Nom. Max. Units Sample Plan QEmax 34 37 42 n/a n/a n/a % Design QE 630 550 470 n/a n/a n/a nm Design Description Temperature Tested At (C) Notes Temperature Tested At (C) Notes KAI-11002-CBA Configuration Description Symbol Peak Quantum Efficiency Red Green Blue Peak Quantum Efficiency Wavelength Red Green Blue n/a: not applicable Notes: 1. 2. 3. 4. 5. 6. Per color. Value is over the range of 10% to 90% of photodiode saturation. Value is for the sensor operated without binning Includes system electronics noise, dark pattern noise and dark current shot noise at 30 MHz. Uses 20LOG(PNe/ ne-T) Last stage only, Cload=10pF. Then f-3db = (1 / (2*Rout*Cload)) www.truesenseimaging.com Revision 1.0 PS-0012 Pg 15 KAI-11002 Image Sensor Typical Performance Curves QUANTUM EFFICIENCY Monochrome with Microlens 0.60 Absolute Quantum Efficiency 0.50 0.40 0.30 0.20 0.10 0.00 300 400 500 600 700 800 900 1000 Wavelength (nm ) Figure 8: Monochrome with Microlens Quantum Efficiency Monochrome without Microlens 0.20 Absolute Quantum Efficiency 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 400 500 600 700 800 900 1000 Wavelength (nm ) Figure 9: Monochrome without Microlens Quantum Efficiency www.truesenseimaging.com Revision 1.0 PS-0012 Pg 16 KAI-11002 Image Sensor Color with Microlens 0.45 Absolute Quantum Efficiency 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 400 500 600 700 800 900 1000 Wavelength (nm) Red Green Blue Figure 10: Color with Microlens Quantum Efficiency Using AR Glass Color without Microlens 0.18 Absolute Quantum Efficiency 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 400 500 600 700 800 900 1000 Wavelength (nm ) Red Green Blue Figure 11: Color without Microlens Quantum Efficiency Using AR Glass www.truesenseimaging.com Revision 1.0 PS-0012 Pg 17 KAI-11002 Image Sensor ANGULAR QUANTUM EFFICIENCY For the curves marked "Horizontal", the incident light angle is varied in a plane parallel to the HCCD. For the curves marked "Vertical", the incident light angle is varied in a plane parallel to the VCCD. Monochrome with Microlens 100% 90% Vertical Relative Quantum Efficiency (%) 80% 70% 60% 50% Horizontal 40% 30% 20% 10% 0% 0 5 10 15 20 25 30 Angle (degress) Figure 12: Monochrome with Microlens Angular Quantum Efficiency Color with Microlens 100% Red 90% Blue 80% Relative Quantum Efficiency Vertical Green Vertical 70% 60% 50% 40% Horizontal 30% 20% 10% 0% -25 -20 -15 -10 -5 0 5 10 15 20 25 Angle (degress) Figure 13: Color with Microlens Angular Quantum Efficiency www.truesenseimaging.com Revision 1.0 PS-0012 Pg 18 KAI-11002 Image Sensor POWER - ESTIMATED Right Output Disabled 500 450 400 Power (mW) 350 300 250 200 150 100 50 0 0 5 10 15 20 25 30 Horizontal Clock Frequency (MHz) Output Pow er One Output(mW) Horizonatl Pow er (mW) Vertical Pow er One Output(mW) Total Pow er One Output (mW) Figure 14: Power FRAME RATES - CONTINUOUS MODE 5 4.5 Dual output Frame Rate (fps) 4 3.5 3 Single output 2.5 2 1.5 1 0.5 0 0 5 10 15 20 25 30 Pixel Clock (MHz) Figure 15: Frame Rates www.truesenseimaging.com Revision 1.0 PS-0012 Pg 19 KAI-11002 Image Sensor Defect Definitions Class X Monochrome with microlens only Class 0 Monochrome with microlens only Class 2 Monochrome Only Definition Major dark field defective pixel Defect 239 mV Major bright field defective pixel Defect 15% Minor dark field defective pixel Defect 123 mV 1000 1000 1000 2000 2000 1,2 Cluster defect A group of 2 to "N" contiguous major defective pixels, but no more than "W" adjacent defects horizontally 0 1 N=10 W=3 20 N=10 W=3 20 N=10 W=3 20 N=12 W=5 1,2 Column defect A group of more than 10 contiguous major defective pixels along a single column 0 0 0 10 2 1,2 Notes: 1. 2. Class 1 Class 2 Color Only Description Notes 1,2 100 100 100 200 200 1,2 There will be at least two non-defective pixels separating any two major defective pixels. Tested at 27 C and 40 C. Class X sensors are offered strictly "as available". Truesense Imaging cannot guarantee delivery dates. Please call for availability. DEFECT MAP The defect map supplied with each sensor is based upon testing at an ambient (27 C) temperature. Minor point defects are not included in the defect map. All defective pixels are reference to pixel 1,1 in the defect maps. www.truesenseimaging.com Revision 1.0 PS-0012 Pg 20 KAI-11002 Image Sensor Test Definitions TEST REGIONS OF INTEREST Active Area ROI: Pixel (1, 1) to Pixel (4008, 2672) Center 100 by 100 ROI: Pixel (1954, 1336) to Pixel (2053, 1435) Only the active pixels are used for performance and defect tests. OVERCLOCKING The test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. See Figure 16 for a pictorial representation of the regions. H Horizontal Overclock Pixel 1,1 V Vertical Overclock Figure 16: Overclock Regions of Interest www.truesenseimaging.com Revision 1.0 PS-0012 Pg 21 KAI-11002 Image Sensor TESTS Dark Field Defect Test This test is performed under dark field conditions. The sensor is partitioned into 384 sub regions of interest, each of which is 167 by 167 pixels in size. In each region of interest, the median value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the "Defect Definitions" section. Bright Field Defect Test This test is performed with the imager illuminated to a level such that the output is at approximately 40,000 electrons. Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 60,000 electrons. The average signal level of all active pixels is found. The bright and dark thresholds are set as: Dark defect threshold = Active Area Signal * threshold Bright defect threshold = Active Area Signal * threshold The sensor is then partitioned into 384 sub regions of interest, each of which is 167 by 167 pixels in size. In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. Example for major bright field defective pixels: Average value of all active pixels is found to be 520 mV (40,000 electrons). Dark defect threshold: 520mV * 15% = 78 mV Bright defect threshold: 520mV * 15% = 78 mV Region of interest #1 selected. This region of interest is pixels 1,1 to pixels 167,167. o Median of this region of interest is found to be 520 mV. o Any pixel in this region of interest that is (520+78 mV) 598 mV in intensity will be marked defective. o Any pixel in this region of interest that is (520-78 mV) 442 mV in intensity will be marked defective. All remaining 384 sub regions of interest are analyzed for defective pixels in the same manner. www.truesenseimaging.com Revision 1.0 PS-0012 Pg 22 KAI-11002 Image Sensor Operation MAXIMUM RATINGS Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or the condition is exceeded, the device will be degraded and may be damaged. Description Symbol Minimum Maximum Units Notes Operating Temperature TOP -50 70 C 1 Humidity RH 5 90 % 2 Output Bias Current Iout 0.0 -40 mA 3 10 pF Off-chip Load Notes: 1. 2. 3. CL Noise performance will degrade at higher temperatures. T=25 C. Excessive humidity will degrade MTTF. Total for both outputs. Current is -20 mA for each output. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). Operation at these values will reduce MTTF. MAXIMUM VOLTAGE RATINGS BETWEEN PINS Description RL, RR, H1BINL, H1BINR, H2SL, H1SL, H1BL, H2BL, H2BR, H1BR, H1SR, H2SR, OGL, OGR to ESD Pin to Pin with ESD Protection VDDL, VDDR to GND Notes: 1. Minimum Maximum Units 0 17 V -17 17 V 0 25 V Notes 1 Pins with ESD protection are: RL, RR, H1BINL, H1BINR, H2SL, H1SL, H1BL, H2BL, H2BR, H1BR, H1SR, H2SR, OGL, and OGR. DC BIAS OPERATING CONDITIONS Units Maximum DC Current (mA) -2.5 -2.0 V 1 A 11.5 12.0 V 1 A 15.5 V 2 mA 0.0 0.0 V TBD 17.0 V 1, 5 -8.0 -7.0 V 2 -5 -10 mA 3 Symbol Output Gate OG -3.0 Reset Drain RD 10.5 Output Amplifier Supply VDD 14.5 15.0 Ground GND 0.0 Substrate SUB 8.0 ESD Protection ESD -9.0 Output Bias Current Iout Notes: 1. 2. 3. 4. 5. Minimum Maximum Description Nominal Notes 4 The operating of the substrate voltage, Vab, will be marked on the shipping container for each device. The value of Vab is set such that the photodiode charge capacity is 60,000 electrons. VESD must be at least 1 V more negative than H1L and H2L during sensor operation AND during camera power turn on. An output load sink must be applied to Vout to activate output amplifier. The maximum DC current is for one output unloaded. This is the maximum current that the first two stages of one output amplifier will draw. This value is with Vout disconnected. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions www.truesenseimaging.com Revision 1.0 PS-0012 Pg 23 KAI-11002 Image Sensor Power Up Sequence 1. Substrate 2. ESD Protection 3. All other biases and clocks. AC OPERATING CONDITIONS Clock Levels Description Vertical CCD Clock High Vertical CCD Clocks Midlevel Symbol Minimum Nominal Maximum Units V2H 7.5 8.0 8.5 V V1M, V2M -0.2 0.0 0.2 V Vertical CCD Clocks Low V1L, V2L -9.5 -9.0 -8.5 V Horizontal CCD Clocks Amplitude H1H, H2H 5.8 6.0 6.2 V Horizontal CCD Clocks Low H1L, H2L -4.2 -4.0 -3.8 V Reset Clock High RH 1.3 1.5 1.7 V Reset Clock Low RL -3.7 -3.5 -3.3 V Vshutter 39 40 48 V Fast Dump High FDH 4.5 5.0 5.5 V Fast Dump Low FDL -9.5 -9.0 -8.5 V Electronic Shutter Voltage Notes: 1. 2. Notes 2 1 FDL can use the same supply as Vertical CCD Clocks Low if desired. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions Clock Line Capacitances Clocks Capacitance Units Notes V1 to GND 108 nF 1 V2 to GND 118 nF 1 V1 to V2 56 nF H1S to GND 27 pF 2 H2S to GND 27 pF 2 H1B to GND 13 pF 2 H2B to GND 4 pF 2 H1S to H2B and H2S 13 pF 2 H1B to H2B and H2S 13 pF 2 H2S to H1B and H1S 13 pF 2 H2B to H1B and H1S 13 pF 2 H1BIN to GND 20 pF 2 R to GND 10 pF FD to GND 20 pF Notes: 1. 2. Gate capacitance to GND is voltage dependent. Value is for nominal VCCD clock voltages. For nominal HCCD clock voltages, these values are for half of the imager (H1SL, H1BL, H2SL, H2BL and H1BINL or H1SR, H1BR, H2SR, H2BR and H1BINR). www.truesenseimaging.com Revision 1.0 PS-0012 Pg 24 KAI-11002 Image Sensor TIMING REQUIREMENTS Description Symbol Minimum Nominal Maximum Units THD 3.0 3.5 10.0 s VCCD Transfer time TVCCD 3.0 3.5 20.0 s Photodiode Transfer time TV3rd 8.0 10.0 15.0 s VCCD Pedestal time T3P 100.0 120.0 200.0 s VCCD Delay T3D 15.0 20.0 80.0 s Reset Pulse time TR 2.5 5.0 Shutter Pulse time TS 3.0 4.0 10.0 s Shutter Pulse delay TSD 1.0 1.5 10.0 s 200 ns 1.0 s HCCD Delay HCCD Clock Period TH 33 VCCD rise/fall time TVR 0.0 Fast Dump Gate delay TFD 0.5 Vertical Clock Edge Alignment TVE 0.0 0.1 Notes ns s 100 ns MAIN TIMING - CONTINUOUS MODE Vertical Frame Timing Line Timing Repeat for 2721 Lines Figure 17: Main Timing - Continuous Mode www.truesenseimaging.com Revision 1.0 PS-0012 Pg 25 KAI-11002 Image Sensor FRAME TIMING - CONTINUOUS MODE Frame Timing without Binning V1M V1 V1L V1H TL TV3rd TL V2M V2 T3P 2720 V2L T3D Line 2721 Line 1 H1H, H1BINH H1, H1BIN H1L, H1BINL H2H H2 H2L Figure 18: Framing Timing without Binning Frame Timing for Vertical Binning by 2 V1 TL TV3rd TL 3 x TVCCD V2 T3P Line 1360 T3D Line 1361 Line 1 H1, H1BIN H2 Figure 19: Frame Timing for Vertical Binning by 2 www.truesenseimaging.com Revision 1.0 PS-0012 Pg 26 KAI-11002 Image Sensor Frame Timing Edge Alignment V1M V1 V1L V2H V2M V2 TVE V2L Figure 20: Frame Timing Edge Alignment www.truesenseimaging.com Revision 1.0 PS-0012 Pg 27 KAI-11002 Image Sensor LINE TIMING - CONTINUOUS MODE Line Timing Single Output TL V1 V2 TVCCD THD H1, H1BIN H2 4073 4074 4075 4076 4053 4054 4055 4056 4057 4058 23 24 25 26 27 28 pixel count 1 2 3 4 5 6 R Figure 21: Line Timing Single Output Line Timing Dual Output - Left Output TL V1 V2 TVCCD THD H1, H1BIN H2 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 23 24 25 26 27 28 pixel count 1 2 3 4 5 6 R Figure 22: Line Timing Dual Output - Left Output www.truesenseimaging.com Revision 1.0 PS-0012 Pg 28 KAI-11002 Image Sensor Line Timing Dual Output - Right Output TL V1 TVCCD V2 THD H1, H1BIN H2 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 23 24 25 26 27 28 pixel count 1 2 3 4 5 6 R Figure 23: Line Timing Dual Output - Right Output Line Timing Vertical Binning by 2 TL V1 V2 TVCCD THD H1, H1BIN H2 4073 4074 4075 4076 4053 4054 4055 4056 4057 4058 23 24 25 26 27 28 pixel count 1 2 3 4 5 R Figure 24: Line Timing Vertical Binning by 2 www.truesenseimaging.com Revision 1.0 PS-0012 Pg 29 KAI-11002 Image Sensor Line Timing Detail V1 TVCCD V2 TH THD H1, H1BIN H2 R Figure 25: Line Timing Detail Line Timing Binning by 2 Detail V1 TVCCD V2 TH THD H1, H1BIN H2 R Figure 26: Line Timing by 2 Detail www.truesenseimaging.com Revision 1.0 PS-0012 Pg 30 KAI-11002 Image Sensor Line Timing Edge Alignment TVCCD V1 V2 TVE TVE Figure 27: Line Timing Edge Alignment www.truesenseimaging.com Revision 1.0 PS-0012 Pg 31 KAI-11002 Image Sensor PIXEL TIMING - CONTINUOUS MODE V1 V2 H1, H1BIN H2 Pixel Count 1 2 3 4 5 23 24 25 26 R Vout Dummy Pixels Light Shielded Pixels Photosensitive Pixels Figure 28: Pixel Timing Pixel Timing Detail tR RH R RL H1H, H1BINH H1, H1BIN H1L, H1BINL H2H H2 H2L VOUT Figure 29: Pixel Timing Detail www.truesenseimaging.com Revision 1.0 PS-0012 Pg 32 KAI-11002 Image Sensor FAST LINE DUMP TIMING FD V1 V2 TFD TVCCD TFD TVCCD H1 H2 Figure 30: Fast Line Dump Timing www.truesenseimaging.com Revision 1.0 PS-0012 Pg 33 KAI-11002 Image Sensor ELECTRONIC SHUTTER Electronic Shutter Line Timing V1 V2 TVCCD THD VShutter TS VSUB TSD H1 H2 R Figure 31: Electronic Shutter Line Timing Electronic Shutter - Integration Time Definition V2 Integration Time VShutter VSUB Figure 32: Integration Time Definition www.truesenseimaging.com Revision 1.0 PS-0012 Pg 34 KAI-11002 Image Sensor Electronic Shutter Description The voltage on the substrate (SUB) determines the charge capacity of the photodiodes. When SUB is 8 volts the photodiodes will be at their maximum charge capacity. Increasing VSUB above 8 volts decreases the charge capacity of the photodiodes until 40 volts when the photodiodes have a charge capacity of zero electrons. Therefore, a short pulse on SUB, with a peak amplitude greater than 40 volts, empties all photodiodes and provides the electronic shuttering action. It may appear the optimal substrate voltage setting is 8 volts to obtain the maximum charge capacity and dynamic range. While setting VSUB to 8 volts will provide the maximum dynamic range, it will also provide the minimum antiblooming protection. - The KAI-11002 VCCD has a charge capacity of 90,000 electrons (90 ke ). If the SUB voltage is set such that the photodiode holds more than 90 ke , then when the charge is transferred from a full photodiode to VCCD, the VCCD will overflow. This overflow condition manifests itself in the image by making bright spots appear elongated in the vertical direction. The size increase of a bright spot is called blooming when the spot doubles in size. The blooming can be eliminated by increasing the voltage on SUB to lower the charge capacity of the photodiode. This ensures the VCCD charge capacity is greater than the photodiode capacity. There are cases where an extremely bright spot will still cause blooming in the VCCD. Normally, when the photodiode is full, any additional electrons generated by photons will spill out of the photodiode. The excess electrons are drained harmlessly out to the substrate. There is a maximum rate at which the electrons can be drained to the substrate. If that maximum rate is exceeded, (for example, by a very bright light source) then it is possible for the total amount of charge in the photodiode to exceed the VCCD capacity. This results in blooming. The amount of antiblooming protection also decreases when the integration time is decreased. There is a compromise between photodiode dynamic range (controlled by VSUB) and the amount of antiblooming protection. A low VSUB voltage provides the maximum dynamic range and minimum (or no) antiblooming protection. A high VSUB voltage provides lower dynamic range and maximum antiblooming protection. The optimal setting of VSUB is written on the container in which each KAI-11002 is shipped. The given VSUB voltage for each sensor is selected to provide antiblooming protection for bright spots at least 100 times saturation, while maintaining at least 60 ke- of dynamic range. The electronic shutter provides a method of precisely controlling the image exposure time without any mechanical components. If an integration time of TINT is desired, then the substrate voltage of the sensor is pulsed to at least 40 volts TINT seconds before the photodiode to VCCD transfer pulse on V2. Use of the electronic shutter does not have to wait until the previously acquired image has been completely read out of the VCCD. The figure below shows the DC bias (SUB) and AC clock (Vshutter) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. Vshutter SUB GND www.truesenseimaging.com GND Revision 1.0 PS-0012 Pg 35 KAI-11002 Image Sensor Storage and Handling ENVIRONMENTAL EXPOSURE STORAGE CONDITIONS Description Symbol Minimum Maximum Units Notes Storage Temperature TST -20 80 C 1 Humidity RH 5 90 % 2 Notes: 1. 2. Long-term exposure toward the maximum temperature will accelerate color filter degradation. T=25 C. Excessive humidity will degrade MTTF ESD 1. This device contains limited protection against Electrostatic Discharge (ESD). ESD events may cause irreparable damage to a CCD image sensor either immediately or well after the ESD event occurred. Failure to protect the sensor from electrostatic discharge may affect device performance and reliability. 2. Devices should be handled in accordance with strict ESD procedures for Class 0 (<250V per JESD22 Human Body Model test), or Class A (<200V JESD22 Machine Model test) devices. Devices are shipped in static-safe containers and should only be handled at static-safe workstations. 3. See Application Note Image Sensor Handling Best Practices for proper handling and grounding procedures. This application note also contains workplace recommendations to minimize electrostatic discharge. 4. Store devices in containers made of electroconductive materials. COVER GLASS CARE AND CLEANLINESS 1. The cover glass is highly susceptible to particles and other contamination. Perform all assembly operations in a clean environment. 2. Touching the cover glass must be avoided. 1. Extremely bright light can potentially harm CCD image sensors. Do not expose to strong sunlight for long periods of time, as the color filters and/or microlenses may become discolored. In addition, long time exposures to a static high contrast scene should be avoided. Localized changes in response may occur from color filter/microlens aging. For Interline devices, refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible lighting Conditions. 2. Exposure to temperatures exceeding maximum specified levels should be avoided for storage and operation, as device performance and reliability may be affected. 3. Avoid sudden temperature changes. 4. Exposure to excessive humidity may affect device characteristics and may alter device performance and reliability, and therefore should be avoided. 5. Avoid storage of the product in the presence of dust or corrosive agents or gases, as deterioration of lead solderability may occur. It is advised that the solderability of the device leads be assessed after an extended period of storage, over one year. SOLDERING RECOMMENDATIONS 1. The soldering iron tip temperature is not to exceed 370 C. Higher temperatures may alter device performance and reliability. 2. Flow soldering method is not recommended. Solder dipping can cause damage to the glass and harm the imaging capability of the device. Recommended method is by partial heating using a grounded 30W soldering iron. Heat each pin for less than 2 seconds duration. 3. Improper cleaning of the cover glass may damage these devices. Refer to Application Note Image Sensor Handling Best Practices. www.truesenseimaging.com Revision 1.0 PS-0012 Pg 36 KAI-11002 Image Sensor Mechanical Information PACKAGE NOTES: 1. SEE ORDERING INFORMATION FOR MARKING CODE 2. COVER GLASS IS MANUALLY PLACED AND VISUALLY ALIGNED OVER DIE - LOCATION ACCURACY IS NOT GUARANTEED. Figure 33: Package Drawing . www.truesenseimaging.com Revision 1.0 PS-0012 Pg 37 KAI-11002 Image Sensor DIE TO PACKAGE ALIGNMENT Figure 34: Die to Package Alignment www.truesenseimaging.com Revision 1.0 PS-0012 Pg 38 KAI-11002 Image Sensor GLASS Coat Both Sides 0.020R [0.50] (Typ. 8 plcs.) Chamfer 0.020" [0.50] Ref. AR coat area (Typ. 4 plcs.) Epoxy: NC0-150 HB Thk. 0.002" - 0.005" Chamfer 0.008" [0.20] 8 plcs.) (Typ. NOTES: 1. Multi-Layer Anti-Reflective Coating on 2 sides: Double Sided Reflectance: Range (nm) 420 - 450 nm < 2% 450 - 630 nm < 1% 630 - 680 nm < 2% 2. Dust, Scratch specification - 20 microns max. 3. Substrate - Schott D263T eco or Equivalent 4. Epoxy: NCO-150HB Thickness: 0.002" - 0.005" Figure 35: Glass Drawing www.truesenseimaging.com Revision 1.0 PS-0012 Pg 39 KAI-11002 Image Sensor GLASS TRANSMISSION 100 90 80 Transmission (%) 70 60 50 40 30 20 10 0 200 300 400 500 600 700 800 900 Wavelength (nm ) Figure 36: Glass Transmission www.truesenseimaging.com Revision 1.0 PS-0012 Pg 40 KAI-11002 Image Sensor Quality Assurance and Reliability QUALITY AND RELIABILITY All image sensors conform to the specifications stated in this document. This is accomplished through a combination of statistical process control and visual inspection and electrical testing at key points of the manufacturing process, using industry standard methods. Information concerning the quality assurance and reliability testing procedures and results are available from Truesense Imaging upon request. For further information refer to Application Note Quality and Reliability. REPLACEMENT All devices are warranted against failure in accordance with the Terms of Sale. Devices that fail due to mechanical and electrical damage caused by the customer will not be replaced. LIABILITY OF THE SUPPLIER A reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer. Product liability is limited to the cost of the defective item, as defined in the Terms of Sale. LIABILITY OF THE CUSTOMER Damage from mishandling (scratches or breakage), electrostatic discharge (ESD), or other electrical misuse of the device beyond the stated operating or storage limits, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. TEST DATA RETENTION Image sensors shall have an identifying number traceable to a test data file. Test data shall be kept for a period of 2 years after date of delivery. MECHANICAL The device assembly drawing is provided as a reference. Truesense Imaging reserves the right to change any information contained herein without notice. All information furnished by Truesense Imaging is believed to be accurate. Life Support Applications Policy Truesense Imaging image sensors are not authorized for and should not be used within Life Support Systems without the specific written consent of Truesense Imaging, Inc. www.truesenseimaging.com Revision 1.0 PS-0012 Pg 41 KAI-11002 Image Sensor Revision Changes MTD/PS-0938 Revision Number Description of Changes 1.0 Initial formal release 2.0 Reformatted Ordering Information, Storage and Handling, and Quality Assurance and Reliability pages 3.0 Added the note "Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions" to the following sections o DC Bias Operating Conditions o AC Operating Conditions o Storage and Handling Added figure in Electronic Shutter Description section showing relationship between ground and the substrate DC bias and the electronic shutter pulse Changed cover glass material to D263T eco or equivalent PS-0012 Revision Number 1.0 Description of Changes Initial release with new document number, updated branding and document template Updated Storage and Handling and Quality Assurance and Reliability sections Reorganized structure for consistency with other Interline Transfer CCD documents www.truesenseimaging.com (c)Truesense Imaging Inc., 2012. TRUESENSE is a registered trademark of Truesense Imaging, Inc. Revision 1.0 PS-0012 Pg 42