THS4511
VIN
R =75
SW
VSignal
VS-
VCM =2.5V
RO
RO
-
+
V =5V
S+
175 W
175 W
75 W
130 W
130 W
348 W
348 W
VOD
VideoSource
THS4511
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SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
WIDEBAND, LOW-NOISE, LOW-DISTORTION,
FULLY-DIFFERENTIAL AMPLIFIER
Check for Samples: THS4511
1FEATURES DESCRIPTION
2• Fully-Differential Architecture The THS4511 is a wideband, fully-differential
operational amplifier designed for single-supply 5-V
• Common-Mode Input Range Includes data-acquisition systems. It has very low noise at
the Negative Rail 2 nV/√Hz, and extremely low harmonic distortion of
• Unity-Gain Stable –72 dBc HD2and –87 dBc HD3at 70 MHz with 2 VPP,
• Bandwidth: 1.6 GHz (Gain = 0 dB) G = 0 dB, and 200-Ωload. Slew rate is very high at
4900 Vµs and with settling time of 3.3 ns to 1% (2 V
• Slew Rate: 4900 V/µs step) it is ideal for pulsed applications. It is designed
• 1% Settling Time: 3.3 ns for minimum gain of 0 dB.
• HD2: –72 dBc at 70 MHz To allow for dc coupling to analog-to-digital
• HD3: –87 dBc at 70 MHz converters (ADCs), its unique output common-mode
• OIP2: 76 dBm at 70 MHz control circuit maintains the output common-mode
voltage within 5-mV offset (typical) from the set
• OIP3: 42 dBm at 70 MHz voltage, when set within ±0.5 V of midsupply. The
• Input Voltage Noise: 2 nV/√Hz (f > 10 MHz) common-mode set point is set to midsupply by
• Noise Figure: 21.8 dB (50-ΩSystem, G = 6 dB) internal circuitry, which may be over-driven from an
external source.
• Output Common-Mode Control
• 5-V Power-Supply Current: 39.2 mA The THS4511 is a high-performance amplifier that
has been optimized for use in 5-V single-supply data
• Power-Down Capability: 0.65 mA acquisition systems. The output has been optimized
for best performance with its common-mode voltages
APPLICATIONS set to midsupply, and the input has been optimized
• 5-V Data-Acquisition Systems for performance over a wide range of common-mode
• High Linearity ADC Amplifiers input voltages. High performance at a low
• Wireless Communication power-supply voltage enables single-supply 5-V
data-acquisition systems while minimizing component
• Medical Imaging count.
• Test and Measurement The THS4511 is offered in a quad, 16-pin leadless
RELATED PRODUCTS QFN package (RGT), and is characterized for
operation over the full industrial temperature range
COMMON-MODE RANGE OF from –40°C to +85°C.
DEVICE MIN. GAIN INPUT(1)
THS4508 6 dB –0.3 V to 2.3 V Video Buffer, Single-Ended to Differential
THS4509 6 dB 0.75 V to 4.25 V
THS4511 0 dB –0.3 V to 2.3 V
THS4513 0 dB 0.75 V to 4.25 V
1. Assumes a 5-V single-ended power supply.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
THS4511
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted. UNIT
VSS Supply VS– to VS+ 5.5 V
voltage
VIInput voltage ±VS
VID Differential input voltage 4 V
IOOutput current 200 mA
Continuous power dissipation See Dissipation Ratings Table
TJMaximum junction temperature(2) +150°C
TJMaximum junction temperature, continuous operation, long term reliability(3) +125°C
TAOperating free-air temperature range –40°C to +85°C
TSTG Storage temperature range –65°C to +150°C
HBM 2000 V
ESD ratings CDM 1500 V
MM 100 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(3) The maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device. The THS4511 incorporates a (QFN) exposed thermal pad on the underside
of the chip. This acts as a heatsink and must be connected to a thermally-dissipative plane for proper power dissipation. Failure to do so
may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief
SLMA002 and SLMA004 for more information about using the QFN thermally-enhanced package.
DISSIPATION RATINGS TABLE POWER RATING
PACKAGE(1) θJC θJA TA≤+25°C TA= +85°C
RGT (16) 2.4°C/W 39.5°C/W 2.3 W 225 mW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
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1315 1416
8
67
5
1
3
2
4
12
10
11
9
NC
VIN-
VOUT+
CM
PD
VIN+
VOUT-
CM
VS-
VS+
THS4511
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SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
DEVICE INFORMATION
RGT PACKAGE
16-PIN LEADLESS QFN
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
(RGT PACKAGE) DESCRIPTION
NO. NAME
1 NC No internal connection
2 VIN– Inverting amplifier input
3 VOUT+ Noninverting amplifier output
4, 9 CM Common-mode voltage input
5-8 VS+ Positive amplifier power supply input
10 VOUT– Inverted amplifier output
11 VIN+ Noninverting amplifier input
12 PD Power-down; PD = logic low puts part into low power mode, PD = logic high or open for normal operation
13-16 VS– Negative amplifier power-supply input
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SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: VS+ – VS– = 5 V
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, T = +25°C single-ended input, differential output, input referenced to ground, and output referenced to midsupply.
THS4511 TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS LEVEL(1)
AC PERFORMANCE (see Figure 38)
G = 0 dB, VO= 100 mVPP 1.6
Small-Signal Bandwidth GHz
G = 6 dB, VO= 100 mVPP 1.4
Gain-Bandwidth Product 2 GHz
G = 0 dB, VO= 2 VPP 160
Bandwidth for 0.1-dB flatness MHz
G = 6 dB, VO= 2 VPP 620
Large-Signal Bandwidth G = 10 dB, VO= 2 VPP 1.35 GHz
Slew Rate (Differential) 4900 V/µs
Rise Time VO= 2-V Step 0.5 ns
Fall Time 0.5 ns
Settling Time to 1% 3.3 ns
Settling Time to 0.1% 16 ns
f = 10 MHz –117
f = 50 MHz –80
2nd Order Harmonic Distortion f = 100 MHz –64 dBc
f = 10 MHz –106 C
f = 50 MHz –92
3rd Order Harmonic Distortion f = 100 MHz –80
fC= 70 MHz –78
2nd Order Intermodulation Distortion fC= 140 MHz –56
200-kHz tone spacing, dBc
RL= 100 ΩfC= 70 MHz –88
3rd Order Intermodulation Distortion fC= 140 MHz –71.4
fC= 70 MHz 76.3
2nd Order Output Intercept Point fC= 140 MHz 53.4
200-kHz tone spacing, dBm
RL= 100 ΩfC= 70 MHz 42
3rd Order Output Intercept Point fC= 140 MHz 34
fC= 70 MHz 12.2
1-dB Compression Point(2) dBm
fC= 140 MHz 10.8
Noise Figure 50-Ωsystem, 10 MHz 21.8 dB
Input Voltage Noise f > 10 MHz 2 nV/√Hz
Input Current Noise f > 10 MHz 1.5 pA/√Hz
DC PERFORMANCE
Open-Loop Voltage Gain (AOL) 63 dB C
TA= +25°C 1 4
Input Offset Voltage mV A
TA= –40°C to +85°C 1 5
Average Offset Voltage Drift 2.3 µV/°C B
TA= +25°C 1.75 8 15.5
Input Bias Current µA A
TA= –40°C to +85°C 8 18.5
Average Bias Current Drift 20 nA/°C B
TA= +25°C 0.5 3.6
Input Offset Current µA A
TA= –40°C to +85°C 0.5 7
Average Offset Current Drift 7 nA/°C B
(1) Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(2) The 1-dB compression point is measured at the load with 50-Ωdouble termination. Add 3 dB to refer to amplifier output.
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SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
ELECTRICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, T = +25°C single-ended input, differential output, input referenced to ground, and output referenced to midsupply.
THS4511 TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS LEVEL(1)
INPUT
Common-Mode Input Range High 2.3 V
Common-Mode Input Range Low –0.3 B
Common-Mode Rejection Ratio 90 dB
Differential Input Impedance 18.2 || 1.62 MΩ|| pF C
Common-Mode Input Impedance 4.0 || 1.73
OUTPUT
TA= +25°C 3.7 3.8
Maximum Output Voltage High TA= –40°C to 3.6 3.8 V
+85°C
Each output with 100 ΩA
to midsupply TA= +25°C 1.2 1.3
Minimum Output Voltage Low TA= –40°C to 1.2 1.4
+85°C
TA= +25°C 4.8 5.2
Differential Output Voltage Swing V A
TA= –40°C to +85°C 4.4 5.2
Differential Output Current Drive RL= 10 Ω96 mA C
Output Balance Error VO= 100 mV, f = 1 MHz –52 dB C
Closed-Loop Output Impedance f = 1 MHz 0.3 ΩC
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-Signal Bandwidth 250 MHz
Slew Rate 110 V/μs
Gain 1 V/V
Output Common-Mode Offset from CM Input 1.25 V < CM < 3.5 V 5 mV C
CM Input Bias Current 1.25 V < CM < 3.5 V ±40 μA
CM Input Voltage Range 1.25 to 3.75 V
CM Input Impedance 32 || 1.5 kΩ|| pF
CM Default Voltage CM pins floating 2.5 V
POWER SUPPLY
Specified Operating Voltage 3.75(3) 5 5.25 V C
TA= +25°C 39.2 42.5
Maximum Quiescent Current TA= –40°C to +85°C 39.2 43.5 mA A
TA= +25°C 35.9 39.2
Minimum Quiescent Current TA= –40°C to +85°C 35 39.2
Power-Supply Rejection (±PSRR) To differential output 90 dB C
POWER-DOWN Referenced to VS–
Enable Voltage Threshold Device assured on above 2.1 V > 2.1 V C
Disable Voltage Threshold Device assured off below 0.7 V < 0.7
TA= +25°C 0.65 0.9
Power-Down Quiescent Current mA A
TA= –40°C to +85°C 0.65 1
Input Bias Current PD = VS– 100 μA
Input Impedance 50 || 2 kΩ|| pF C
Turn-On Time Delay Measured to output on 55 ns
Turn-Off Time Delay Measured to output off 10 µs
(3) See the Application Information section of this data sheet for device operation with full supply voltages less than 5 V.
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 5
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SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
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TYPICAL CHARACTERISTICS
G = 0 dB, VOD = 100 mVPP Figure 1
Small-Signal Frequency
Response G = 6 dB, VOD = 100 mVPP Figure 2
G = 0 dB, VOD = 2 VPP Figure 3
Large-Signal Frequency
Response G = 6 dB, VOD = 2 VPP Figure 4
HD2, G = 0 dB, VOD = 2 VPP vs Frequency Figure 5
HD3, G = 0 dB, VOD = 2 VPP vs Frequency Figure 6
HD2, G = 6 dB, VOD = 2 VPP vs Frequency Figure 7
HD3, G = 6 dB, VOD = 2 VPP vs Frequency Figure 8
Harmonic
Distortion HD2, G = 0 dB vs Output Voltage Figure 9
HD3, G = 0 dB vs Output Voltage Figure 10
HD2, G = 0 dB vs CM Output Voltage Figure 11
HD3, G = 0 dB vs CM Output Voltage Figure 12
IMD2, G = 0 dB vs Frequency Figure 13
Intermodulation
Distortion IMD3, G = 0 dB vs Frequency Figure 14
OIP2vs Frequency Figure 15
Output Intercept Point OIP3vs Frequency Figure 16
S-Parameters vs Frequency Figure 17
Transition Rate vs Output Voltage Figure 18
Transient Response Figure 19
Settling Time Figure 20
Rejection Ratio vs Frequency Figure 21
Output Impedance vs Frequency Figure 22
Overdrive Recovery Figure 23
Differential Output Voltage Load Resistance Figure 24
Turn-Off Time Figure 25
Turn-On Time Figure 26
Input Offset Voltage vs Input Common-Mode Voltage Figure 27
Open-Loop Gain and Phase vs Frequency Figure 28
Input-Referred Noise vs Frequency Figure 29
Noise Figure vs Frequency Figure 30
Quiescent Current vs Supply Voltage Figure 31
Output Balance Error vs Frequency Figure 32
CM Input Impedance vs Frequency Figure 33
CM Small-Signal Frequency Response Figure 34
CM Input Bias Current vs CM Input Voltage Figure 35
Differential Output Offset Voltage vs CM Input Voltage Figure 36
Output Common-Mode Offset vs CM Input Voltage Figure 37
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10 100 1000 10000
f− Frequency −MHz
SignalGain − dB
RL=1kΩ
RL=500 Ω
RL=200 Ω
RL=100 Ω
VO=100mVPP
G=6dB
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RL=1kΩ
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VO=100mVPP
RL=200 Ω
RL=100 Ω
G=0dB
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SignalGain − dB
RL=1kΩ
RL=500 Ω
RL=100 Ω
VO=2VPP
RL=200 Ω
G=0dB
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10 100 1000 10000
f− Frequency −MHz
SignalGain − dB
VO=2VPP
RL=1kΩ
RL=500 Ω
RL=200 Ω
RL=100 Ω
G=6dB
THS4511
www.ti.com
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, single-ended input, input referenced to ground, and output referenced to midrail.
SMALL-SIGNAL FREQUENCY RESPONSE SMALL-SIGNAL FREQUENCY RESPONSE
Figure 1. Figure 2.
LARGE-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE
Figure 3. Figure 4.
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 7
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f − Frequency − MHz
VO=2VPP
RL=1kΩ
RL=500 Ω
=100 Ω
RL=200 Ω
2ndOrderHarmonicDistortion − dBc
G=0dB
RL
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1 10 100 1000
f − Frequency − MHz
VO=2VPP
3rdOrderHarmonicDistortion − dBc
RL=1kΩ
RL=500 Ω
RL=100 Ω
RL=200 Ω
G=0dB
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1 10 100 1000
f − Frequency − MHz
G=6dB
RF=348 Ω
RG=165 Ω
VO=2VPP
RL=1kΩ
RL=500 Ω
RL=100 Ω
RL=200 Ω
2ndOrderHarmonicDistortion − dBc
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f − Frequency − MHz
3rdOrderHarmonicDistortion − dBc
RL=1k Ω
RL=500 Ω
RL=100 Ω
L=200 Ω
G=6dB
RF=348 Ω
RG=165 Ω
VO=2VPP
THS4511
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, single-ended input, input referenced to ground, and output referenced to midrail.
HD2vs FREQUENCY HD3vs FREQUENCY
Figure 5. Figure 6.
HD2vs FREQUENCY HD3vs FREQUENCY
Figure 7. Figure 8.
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0 1 2 3 4 5
f=150MHz
f=100MHz
f=64MHz
f=32MHz
f=8MHz
f=16MHz
VO− OutputVoltage − VPP
2ndOrderHarmonicDistortion − dBc
VOD =2VPP
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f=64MHz
f=32MHz
f=8MHz
f=16MHz
VO− OutputVoltage− VPP
VOD =2VPP
3rdOrderHarmonicDistortion − dBc
−140
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−1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1
f=150MHz
f=100MHz
f=64MHz
f=8MHz
3rdOrderHarmonicDistortion − dBc
f=1MHz
f=4MHz
V − Common-ModeOutputV
CM oltage − V
f=32MHz
−140
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0
−1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1
f=150MHz
f=100MHz
f=64MHz
f=32MHz
f=1MHz
f=8MHz f=4MHz
2ndOrderHarmonicDistortion − dBc
V − Common-ModeOutputVoltage V−
CM
THS4511
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SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, single-ended input, input referenced to ground, and output referenced to midrail.
HD2vs OUTPUT VOLTAGE HD3vs OUTPUT VOLTAGE
Figure 9. Figure 10.
HD2vs CM OUTPUT VOLTAGE HD3vs CM OUTPUT VOLTAGE
Figure 11. Figure 12.
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0 50 100 150 200
f − Frequency − MHz
VOD =2VPP Envelope
200kHz ToneSpacing
RL=1kΩ
RL=100 Ω
RL=200 Ω
IMD2− IntermodulationDistortion − dBc
IMD3− IntermodulationDistortion − dBc
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RL=1kΩ
RL=200 Ω
RL=100 Ω
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f − Frequency − MHz
RL=100 Ω
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OIP2− OutputInterceptPoint − dBm
25
30
35
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45
50
0 50 100 150 200
f − Frequency − MHz
RL=100 Ω
VOD =2VPP Envelope
200kHz ToneSpacing
OIP3− OutputInterceptPoint − dBm
THS4511
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, single-ended input, input referenced to ground, and output referenced to midrail.
IMD2vs FREQUENCY IMD3vs FREQUENCY
Figure 13. Figure 14.
OIP2vs FREQUENCY OIP3vs FREQUENCY
Figure 15. Figure 16.
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S22
S11
S12
S−Parameter − dB
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1000
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3000
4000
5000
6000
0 0.5 1 1.5 2 2.5 3
SR − TransitionRate − V/ms
VOD OutputV− oltage − V PP
R Ω
20%-80%
L=200
Falling
Rising
1
1.5
2
2.5
3
3.5
4
t − Time − 500ps/div
VOD =2VPP
VOD − DifferentialOutputV
oltage − V
THS4511
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SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, single-ended input, input referenced to ground, and output referenced to midrail.
S-PARAMETERS vs FREQUENCY TRANSITION RATE vs OUTPUT VOLTAGE
Figure 17. Figure 18.
TRANSIENT RESPONSE SETTLING TIME
Figure 19. Figure 20.
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Rejection Ratio −dB
PSRR+
CMRR
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10
100
0.1 1 10 100 1000
f − Frequency− MHz
− Output Impedance −ZoΩ
−4
−2
0
2
4
t − Time − 100ns/div
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
V − InputV
Ioltage − V
Input
Output
V − DifferentialOutputV
Ooltage − V
0
1
2
3
4
5
6
7
10 100 1000
R -LoadResistance-k
LW
V -DifferentialOutputVoltageSwing-V
OD
THS4511
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, single-ended input, input referenced to ground, and output referenced to midrail.
REJECTION RATIOS vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY
Figure 21. Figure 22.
DIFFERENTIAL OUTPUT VOLTAGE
OVERDRIVE RECOVERY vs LOAD RESISTANCE
Figure 23. Figure 24.
12 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4511
00
12
2.2 4.4
0.2 0.4
1.2 2.4
2.4 4.8
0.4 0.8
1.4 2.8
2.6 5.2
3.2 6.4
1.6 3.2
2.8 5.6
0.6 1.2
1.8 3.6
0.8 1.6
24
36
V -OutputVoltage-V
O
PowerdownInput-V
Output
PDInput
t-Time-(2.5 s/div)m
0
-0.2 0
1
2
2.2
4.4
0.2
0.4
1.2
2.4
2.4
4.8
0.4
0.8
1.4
2.8
2.6
5.2
6.4
1.6
3.2
2.8
5.6
0.6
1.2
1.8
3.6
0.8
1.6
2
4
3
6
V -OutputVoltage-V
O
PowerdownInput-V
Output
PDInput
t-Time-(2.5 s/div)m
-0.5 0 1 1.5 22.5 3
1
0
0.5
2
6
3
7
8
4
9
5
10
V-InputOffsetVoltage-mV
OS
V -Commom-ModeInputVoltage-V
IC
0
10
20
30
40
50
60
70
80
100 10K 1M 100M 10G
f-Frequency-Hz
Open-loopGain-dB
-230
-190
-150
-110
-70
-30
10
50
90
Phase-Degrees
PHASE
GAIN
THS4511
www.ti.com
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, single-ended input, input referenced to ground, and output referenced to midrail.
TURN-OFF TIME TURN-ON TIME
Figure 25. Figure 26.
INPUT OFFSET VOLTAGE OPEN-LOOP GAIN AND PHASE
vs INPUT COMMON-MODE VOLTAGE vs FREQUENCY
Figure 27. Figure 28.
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): THS4511
0
1
10
100
1000
10 100 1k 10k 100k 1M 10M
f-Frequency-Hz
V -VoltageNoise-V/rt(Hz)
I -CurrentNoise-pA/rt(Hz)
n
n
InputVoltageNoise
InputCurrentNoise
20
21
22
23
24
25
0 20 40 60 80 100 120 140 160 180 200
f-Frequency-MHz
NF-NoiseFigure-dB
50- System
G=6dB
W
-60
-55
-50
-45
-40
-35
-30
-25
-20
100k 1M 10M 100M 10G
f-Frequency-Hz
BalanceError-dB
V =500mV
OD PP
3.75 454.25 5.254.754.5
28
34
30
36
40
42
32
38
44
I -QuiescentCurrent-mA
Q
V -SupplyVoltage-V
S
T =25 C
A
o
T =-40 C
A
o
T =85 C
A
o
THS4511
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, single-ended input, input referenced to ground, and output referenced to midrail.
INPUT-REFERRED NOISE vs FREQUENCY NOISE FIGURE vs FREQUENCY
Figure 29. Figure 30.
QUIESCENT CURRENT vs SUPPLY VOLTAGE OUTPUT BALANCE ERROR vs FREQUENCY
Figure 31. Figure 32.
14 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4511
CMInputImpedance − kW
f − Frequency − Hz
0.01
0.1
1
10
100
100k 1M 10M 100M 1G
-4
-3
-2
-1
0
1
2
100k 1M 10M 100M 10G
f-Frequency-Hz
V -Gain-dB
OCM
DifferentialOutputOffsetVoltage-mV
0
-1
0.5 2.5
13
0
2
1
3
4
5
1.5 3.5 4.5
2 4 5
V -Common-ModeInputVoltage-V
IC
Common-ModeInput-BiasCurrent- Am
0
-300 0.5 2.51 3
-200
0
-100
100
200
1.5 3.5 4.52 4 5
V -Common-ModeInputVoltage-V
IC
THS4511
www.ti.com
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, single-ended input, input referenced to ground, and output referenced to midrail.
CM INPUT IMPEDANCE vs FREQUENCY CM SMALL-SIGNAL FREQUENCY RESPONSE
Figure 33. Figure 34.
CM INPUT BIAS CURRENT DIFFERENTIAL OUTPUT OFFSET VOLTAGE
vs CM INPUT VOLTAGE vs CM INPUT VOLTAGE
Figure 35. Figure 36.
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): THS4511
V-Common-ModeOutputOffsetVoltage-mV
OC
0
-50
20
0.5 2.5
13
-40
30
-20
50
-30
40
-10
0
10
1.5 3.5 4.5
2 4 5
V -Common-ModeInputVoltage-V
IC
THS4511
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO= 2 VPP, RF= 349 Ω, RL= 200 Ω
differential, single-ended input, input referenced to ground, and output referenced to midrail.
OUTPUT COMMON-MODE OFFSET
vs CM INPUT VOLTAGE
Figure 37.
16 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4511
OutputMeasured
HereWithHigh
Impedance
DifferentialProbe
THS4511
CM
VIN RF
RF
RG
RG
RIT
RIT
From
50 W
Source 5V
49.9 W
49.9 W100 W
0.22 Fm
49.9 W0.22 Fm
Open
THS4511
CM
From
50 W
Source
VIN
0.22 Fm
49.9 W
VOUT
Open
To50 W
Test
Equipment
RG
RIT
RG
RIT
RF
5V
RO
ROROT
0.22 Fm
1:1
RF
THS4511
www.ti.com
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
TEST CIRCUITS
The THS4511 is tested with the following test circuits
built on the evaluation module (EVM). For simplicity,
the power-supply decoupling is not shown—see
Layout in the Application Information section for
recommendations. Depending on the test conditions,
component values are changed per the following
tables, or as otherwise noted. The signal generators
used are ac-coupled 50-Ωsources, and a 0.22-µF
capacitor and 49.9-Ωresistor to ground are inserted
across RIT on the alternate input to balance the Figure 38. Frequency Response Test Circuit
circuit.
Distortion and 1-dB Compression
Table 1. Gain Component Values The circuit shown in Figure 39 is used to measure
GAIN RFRGRIT harmonic distortion, intermodulation distortion, and
0 dB 348 Ω340 Ω56.2 Ω1-db compression point of the amplifier.
6 dB 348 Ω165 Ω61.9 ΩA signal generator is used as the signal source and
Note the gain setting includes 50-Ωsource the output is measured with a spectrum analyzer. The
impedance. Components are chosen to achieve output impedance of the signal generator is 50 Ω. RIT
gain and 50-Ωinput termination. and RGare chosen to impedance-match to 50 Ω, and
to maintain the proper gain. To balance the amplifier,
Table 2. Load Component Values a 0.22-µF capacitor and 49.9-Ωresistor to ground are
inserted across RIT on the alternate input.
RLROROT ATTEN.
100 Ω25 ΩOpen 6 dB A low-pass filter is inserted in series with the input to
reduce harmonics generated at the signal source.
200 Ω86.6 Ω69.8 Ω16.8 dB The level of the fundamental is measured, then a
499 Ω237 Ω56.2 Ω25.5 dB high-pass filter is inserted at the output to reduce the
1 kΩ487 Ω52.3 Ω31.8 dB fundamental so that it does not generate distortion in
the input of the spectrum analyzer.
Note the total load includes 50-Ωtermination by
the test equipment. Components are chosen to The transformer used in the output to convert the
achieve load and 50-Ωline termination through a signal from differential to single ended is an
1:1 transformer. ADT1-1WT. It limits the frequency response of the
circuit so that measurements cannot be made below
Due to the voltage divider on the output formed by approximately 1 MHz.
the load component values, the amplifier output is
attenuated. The column Atten in Table 2 shows the
attenuation expected from the resistor divider. When
using a transformer at the output as shown in
Figure 39, the signal will see slightly more loss, and
these numbers will be approximate.
Frequency Response
The circuit shown in Figure 38 is used to measure the
frequency response of the circuit.
A network analyzer is used as the signal source and
as the measurement device. The output impedance Figure 39. Distortion Test Circuit
of the network analyzer is 50 Ω. RIT and RGare
chosen to impedance match to 50 Ω, and to maintain The 1-dB compression point is measured with a
the proper gain. To balance the amplifier, a 0.22-µF spectrum analyzer with 50-Ωdouble termination or
capacitor and 49.9-Ωresistor to ground are inserted 100-Ωtermination as shown in Table 2. The input
across RIT on the alternate input. power is increased until the output is 1 dB lower than
expected. The number reported in the table data is
The output is probed using a high-impedance the power delivered to the spectrum analyzer input.
differential probe across the 100-Ωresistor. The gain Add 3 dB to refer to the amplifier output.
is referred to the amplifier output by adding back the
6-dB loss due to the voltage divider on the output.
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): THS4511
5V
CM
VIN From
source
49.9 W
0.22 Fm
RF
RF
RG
RG
RIT
RIT
VOUT+
V
OUT–
To
50-W
Test
Equipment
RCMT
RCM
THS4511
50-W
49.9 W
0.22 Fm
49.9 W
49.9 W
THS4511
CM
VIN RF
RF
RG
RG
RIT
RIT
From
50-W
Source
0.22 Fm
49.9 W
VOUT+
Open
To50-W
Test
Equipment
5V
0.22 Fm
VOUT-
49.9 W
49.9 W
From
50 W
Source THS4511
CM
VIN
CMRR
PSRR+
PSRR-
VS+
VS-
5V
100 W
100 W
69.8 W
348 W
348 W
49.9 W
49.9 W
Open
0.22 Fm
100 W
Output
Measured
Here
WithHigh
Impedance
Differential
Probe
THS4511
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
S-Parameter, Slew Rate, Transient Response,
Settling Time, Output Impedance, Overdrive,
Output Voltage, and Turn-On/Off Time
The circuit shown in Figure 40 is used to measure
s-parameters, slew rate, transient response, settling
time, output impedance, overdrive recovery, output
voltage swing, and turn-on/turn-off times of the
amplifier. For output impedance, the signal is injected
at VOUT with VIN left open and the drop across the
49.9-Ωresistor is used to calculate the impedance
seen looking into the amplifier output. Figure 41. CM Input Test Circuit
Because S21 is measured single-ended at the load
with 50-Ωdouble termination, add 12 dB to refer to CMRR and PSRR
the amplifier output as a differential signal. The circuit shown in Figure 42 is used to measure the
CMRR and PSRR of VS+ and VS–. The input is
switched appropriately to match the test being
performed.
Figure 40. S-Parameter, SR, Transient Response,
Settling Time, ZO, Overdrive Recovery, VOUT
Swing, and Turn-On/Off Test Circuit Figure 42. CMRR and PSRR Test Circuit
CM Input
The circuit shown in Figure 41 is used to measure the
frequency response and input impedance of the CM
input. Frequency response is measured single-ended
at VOUT+ or VOUT– with the input injected at VIN, RCM =
0Ω, and RCMT = 49.9 Ω. The input impedance is
measured with RCM = 49.9 Ωwith RCMT = open, and
calculated by measuring the voltage drop across RCM
to determine the input current.
18 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4511
5V
Single-Ended
Input
RF
RF
RG
RGTHS4511
Differential
Output
VOUT+
VOUT–
+
–
–
+
RF
VOUT+
VOUT–
5V
V
IN–
RF
RG
RG
VIN+
THS4511
Differential
Input
Differential
Output
+–
–+
÷
÷
ø
ö
ç
ç
è
æ
+
´+
÷
÷
ø
ö
ç
ç
è
æ
+
´= -+
FG
F
IN
FG
G
OUT
IC RR
R
V
RR
R
V
V
THS4511
www.ti.com
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
APPLICATION INFORMATION
APPLICATIONS
The following circuits show application information for
the THS4511. For simplicity, power-supply
decoupling capacitors are not shown in these
diagrams. For more detail on the use and operation
of fully-differential operational amplifiers refer to
application report Fully-Differential Amplifiers
(SLOA054).
Differential Input to Differential Output Amplifier
The THS4511 is a fully-differential operational
amplifier, and can be used to amplify differential input
signals to differential output signals. A basic block Figure 44. Single-Ended Input to Differential
diagram of the circuit is shown in Figure 43 (CM input Output Amplifier
not shown). The gain of the circuit is set by RF
divided by RG.Input Common-Mode Voltage Range
The input common-model voltage of a fully-differential
operational amplifier is the voltage at the (+) and (–)
input pins of the operational amplifier.
It is important to not violate the input common-mode
voltage range (VICR) of the operational amplifier.
Assuming the operational amplifier is in linear
operation the voltage across the input pins is only a
few millivolts at most. So finding the voltage at one
input pin determines the input common-mode voltage
of the operational amplifier.
Treating the negative input as a summing node, the
voltage is given by Equation 1:
Figure 43. Differential Input to Differential Output (1)
Amplifier To determine the VICR of the operational amplifier, the
voltage at the negative input is evaluated at the
Depending on the source and load, input and output extremes of VOUT+.
termination can be accomplished by adding RIT and
RO.As the gain of the operational amplifier increases, the
input common-mode voltage becomes closer and
Single-Ended Input to Differential Output closer to the input common-mode voltage of the
Amplifier source.
The THS4511 can be used to amplify and convert
single-ended input signals to differential output
signals. A basic block diagram of the circuit is shown
in Figure 44 (CM input not shown). The gain of the
circuit is again set by RFdivided by RG.
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): THS4511
V =3.75Vto5V
S+
CM
VSignal
VS–
RF
RF
RG
RG
RIT
RIT
RO
ROVOUT+
VOUT-
THS4511
RS
VCM
RPD
RPD
RS
( )
W
--
=-+
k50
VVV2
ISSCM
EXT
I
R
S
V
F
R
P D
R
1
6.1
2
6.11
1
-
ú
ú
ú
ú
û
ù
ê
ê
ê
ê
ë
é
-
+
=
VS+
CM
VS–
50kW
tointernal
CMcircuit
IEXT
50kW
THS4511
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
Setting the Output Common-Mode Voltage operational amplifier. Note RSand RIT are added to
the alternate input from the signal input to balance
The output common-mode voltage is set by the the amplifier. One resistor that is equal to the
voltage at the CM pin(s). The internal common-mode combined value RI= RG+ RS|| RIT can be placed at
control circuit maintains the output common-mode the alternate input.
voltage within 5-mV offset (typical) from the set
voltage, when set within 0.5 V of midsupply. If left
unconnected, the common-mode set point is set to
midsupply by internal circuitry, which may be
overdriven from an external source. Figure 45 is
representative of the CM input. The internal CM
circuit has about 700 MHz of –3-dB bandwidth, which
is required for best performance, but it is intended to
be a dc-bias input pin. Bypass capacitors are
recommended on this pin to reduce noise at the
output. The external current required to overdrive the
internal resistor divider is given by Equation 2:
Figure 46. THS4511 DC-Coupled Single-Source
Supply Range From 3.75 V to 5 V With RPD Used
(2) To Set VIC
where VCM is the voltage applied to the CM pin, and
VS+ ranges from 3.75 V to 5 V, and VS– is 0 V Note that in Figure 46, the source is referenced to
(ground). ground, as is the input termination resistor RIT. The
proper value of resistance to add can be calculated
from Equation 3:
(3)
where RI= RG+ RS|| RIT.
VS+ is the power-supply voltage, RFis the feedback
Figure 45. CM Input Circuit resistance, RGis the gain-setting resistance, RSis the
signal source resistance, and RIT is the termination
resistance.
Device Operation with Single Power Supplies
Less than 5 V Table 3 is a modification of Table 1 to add the proper
values with RPD assuming VS+ = 3.75 V, a dc-coupled
The THS4511 is optimized to work in systems using 50-Ωsource impedance, and setting the output
5-V single supplies, and the characterization data common-mode voltage to midsupply.
presented in this data sheet were taken with 5-V
single-supply inputs. For ac-coupled systems or Table 3. RPD Values for Various Gains,
dc-coupled systems operating with supplies less than VS+ = 3.75 V, DC-coupled Signal Source
5 V and greater than 3.75 V, the amplifier input
common-mode range is maximized by adding GAIN RFRGRIT RPD
pull-down resistors at the device inputs. The 0 dB 348 Ω340 Ω56.2 Ω422 Ω
pull-down resistors provide additional loading at the 6 dB 348 Ω169 Ω64.9 Ω86.6 Ω
input, and lower the common-mode voltage that is fed
back into the device input through resistor RF.
Figure 46 shows the circuit configuration for this
mode of operation where RPD is added to the
dc-coupled circuit to avoid violating the VICR of the
20 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4511
THS4511
VIN
R =75
SW
VSignal
VS-
VCM =2.5V
RO
RO
-
+
V =5V
S+
175 W
175 W
75 W
130 W
130 W
348 W
348 W
VOD
VideoSource
CM
VSignal
VS-
RF
RF
RG
RG
RIT
RIT
RPD
RPD
RO
RO
VOUT+
VOUT-
THS4511
R
C
C
S
RS
V =3.75Vto5V
S+
-0.4
-0.2
0
0.2
0.4
0.6
0.8
0 5 10 15 20
t-Time- sm
Voltage-V
-1
-0.5
0
0.5
1
1.5
0 5 10 15 20
t-Time- sm
V V
OD -VideoBufferOutput-
THS4511
www.ti.com
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
If the signal originates from an ac-coupled 50-Ω
source (see Figure 47), the equivalent dc-source
resistance is an open circuit and RI= RG+ RIT.
Table 4 is a modification of Table 1 to add the proper
values with RPD assuming VS+ = 3.75 V, an
ac-coupled 50-Ωsource impedance, and setting the
output common-mode voltage to midsupply.
Table 4. RPD Values for Various Gains,
VS+ = 3.75 V, AC-Coupled Signal Source
GAIN RFRGRIT RPD
0 dB 348 Ω340 Ω56.2 Ω390 ΩFigure 48. Single-Supply Video Buffer, Gain = 2
6 dB 348 Ω169 Ω64.9 Ω80.6 Ω
Figure 47. THS4511 AC-Coupled Single-Source
Supply Range From 3.75 V to 5 V With RPD Used
To Set VIC
Figure 49. Y' Signal with 3-Level Sync and Video
Video Buffer Signal
Figure 48 shows a possible application of the
THS4508 as a dc-coupled video buffer with a gain of
2. Figure 49 shows a plot of the Y' signal originating
from an HDTV 720p video system. The input signal
includes a 3-level sync (minimum level at –0.3 V) and
the portion of a video signal with maximum amplitude
of 0.7 V. Although the buffer draws its power from a
5-V single-ended power supply, internal level shifters
allow the buffer to support input signals which are as
much as –0.3 V below ground. This allows maximum
design flexibility while maintaining a minimum parts
count. Figure 50 shows the differential output of the
buffer. Note that the dc-coupled amplifier can
introduce a dc offset on a signal applied at its input.
Figure 50. Video Buffer Differential Output Signal
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): THS4511
.2 7 pF
0.1 Fm
14-bit,
105 MSPS
AIN+
AIN– VBG
ADS5424
5V
THS4511
CM
348 W
348 W
340 W
340
56.2 W
56.2 W
VIN
From
50-
source
W
225 W
225 W
49.9 W
49.9 W
0.22 Fm0.1 Fm
2.7pF
0.1 Fm
AIN +
AIN - CM
ADS5500
5V
THS4511
CM
348 W
348 W
340 W
340 W
56.2 W
56.2 W
49.9 W
VIN
From
50-
source
W
100 W
14-bit,
125MSPS
100 W
0.22 Fm
0.22 Fm
0.22 Fm
THS4511
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
THS4511 and ADS5500 Combined Performance THS4511 and ADS5424 Combined Performance
The THS4511 is designed to be a high-performance Figure 52 shows the THS4511 driving the ADS5424
drive amplifier for high-performance data converters ADC.
like the ADS5500 14-bit 125-MSPS ADC. Figure 51 As before, the THS4511 amplifier provides 0 dB of
shows a circuit combining the two devices. The gain, converts the single-ended input to differential,
THS4511 amplifier circuit provides 0 dB of gain, and and sets the proper input common-mode voltage to
converts the single-ended input signal to a differential the ADS5424. Input termination and circuit testing is
output signal. The default common-mode output of the same as described above for the THS4511 and
the THS4511 (2.5 V) is not compatible with the ADS5500 circuit.
required common-mode input of the ADS5500
(1.55 V), so dc-blocking capacitors are added (0.22 The 225-Ωresistors and 2.7-pF capacitor between
µF). Note that a biasing circuit (not shown in the THS4511 outputs and ADS5424 inputs (along
Figure 51) is needed to provide the required with the input capacitance of the ADC) limit the
common-mode, dc-input for the ADS5500. The 100-Ωbandwidth of the signal to about 100 MHz (–3 dB).
resistors and 2.7-pF capacitor between the THS4511 When the THS4511 is operated from a single power
outputs and ADS5500 inputs along with the input supply with VS+ =5VandVS– = ground, the 2.5-V
capacitance of the ADS5500 limit the bandwidth of output common-mode voltage is compatible with the
the signal to 115 MHz (–3 dB). For testing, a signal recommended value of the ADS5424 input
generator is used for the signal source. The common-mode voltage (2.4 V).
generator is an ac-coupled 50-Ωsource. A band-pass
filter is inserted in series with the input to reduce
harmonics and noise from the signal source. Input
termination is accomplished via the 69.8-Ωresistor
and 0.22-µF capacitor to ground in conjunction with
the input impedance of the amplifier circuit. A 0.22-µF
capacitor and 49.9-Ωresistor is inserted to ground
across the 69.8-Ωresistor and 0.22-µF capacitor on
the alternate input to balance the circuit. Gain is a
function of the source impedance, termination, and
348-Ωfeedback resistor. See Table 1 for component
values to set proper 50-Ωtermination for other
common gains. Figure 52. THS4511 and ADS5424 Circuit
Figure 51. THS4511 and ADS5500 Circuit
22 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4511
DIE
Side View (a)
DIE
End View (b) Bottom View (c)
THS4511
www.ti.com
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
Layout Recommendations as a thermal pad on the underside of the package
(see Figure 53c). Because this thermal pad has direct
It is recommended to follow the layout of the external thermal contact with the die, excellent thermal
components near the amplifier, ground plane performance can be achieved by providing a good
construction, and power routing of the EVM as thermal path away from the thermal pad.
closely as possible. General guidelines are: Note that the THS4511 has no electrical connection
1. Signal routing should be direct and as short as between the PowerPAD and circuitry on the die.
possible into and out of the operational amplifier Connecting the PowerPAD to any potential voltage
circuit. between VS+ and VS– is acceptable. It is most
2. The feedback path should be short and direct; important that it be connected for maximum heat
avoid vias. dissipation.
3. Ground or power planes should be removed from The PowerPAD package allows both assembly and
directly under the amplifier input and output pins. thermal management in one manufacturing operation.
4. An output resistor is recommended on each
output, as near to the output pin as possible. During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also
5. Two 10-µF and two 0.1-µF power-supply be soldered to a copper area underneath the
decoupling capacitors should be placed as near package. Through the use of thermal paths within this
to the power-supply pins as possible. copper area, heat can be conducted away from the
6. Two 0.1-µF capacitors should be placed between package into either a ground plane or other heat
the CM input pins and ground. This configuration dissipating device.
limits noise coupled into the pins. One each
should be placed to ground near pin 4 and pin 9. The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
7. It is recommended to split the ground pane on surface-mount with the heretofore awkward
layer 2 (L2) as shown below and to use a solid mechanical methods of heatsinking.
ground on layer 3 (L3). A single-point connection
should be used between each split section on L2
and L3.
8. A single-point connection to ground on L2 is
recommended for the input termination resistors
R1 and R2. This configuration should be applied
to the input gain resistors if termination is not
used.
9. The recommended printed circuit board (PCB)
footprint for the THS4511 is shown in Figure 54.Figure 53. Views of Thermally-Enhanced Package
PowerPAD™ DESIGN CONSIDERATIONS
The THS4511 is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe on which the
die is mounted (see Figure 53a and Figure 53b). This
arrangement results in the lead frame being exposed
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): THS4511
0.144 0.0195
0.144
0.010
vias
Pin 1
Top View
0.012
0.030
0.0705
0.015
0.0095
0.049
0.032
0.0245
THS4511
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
PowerPAD PCB LAYOUT useful for slowing the heat transfer during
CONSIDERATIONS soldering operations. This resistance makes the
soldering of vias that have plane connections
Although there are many ways to properly heatsink easier. In this application, however, low thermal
the PowerPAD package, the following steps illustrate resistance is desired for the most efficient heat
the recommended approach. transfer. Therefore, the holes under the IC
PowerPAD package should make the connection
to the internal ground plane, with a complete
connection around the entire circumference of the
plated-through hole.
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This configuration prevents
solder from being pulled away from the thermal
pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This process results
in a part that is properly installed.
The next consideration is the package constraints.
Figure 54. PowerPAD PCB Etch and Via Pattern The two sources of heat within an amplifier are
quiescent power and output power. The designer
1. Prepare the PCB with a top side etch pattern as should never forget about the quiescent heat
shown in Figure 54. There should be etch for the generated within the device, especially multi-amplifier
leads as well as etch for the thermal pad. devices. Because these devices have linear output
2. Place five holes in the area of the thermal pad. stages (Class AB), most of the heat dissipation is at
The holes should be 13 mils (0.013 in, 0.33 mm) low output voltages with high output currents.
in diameter. Keep them small so that solder The other key factor when dealing with power
wicking through the holes is not a problem during dissipation is how the devices are mounted on the
reflow. PCB. The PowerPAD devices are extremely useful
3. Additional vias may be placed anywhere along for heat dissipation. But the device should always be
the thermal plane outside of the thermal pad soldered to a copper plane to fully use the heat
area. They help dissipate the heat generated by dissipation properties of the PowerPAD. The SOIC
the IC. These additional vias may be larger than package, on the other hand, is highly dependent on
the 13-mil diameter vias directly under the how it is mounted on the PCB. As more trace and
thermal pad. They can be larger because they copper area is placed around the device, θJA
are not in the thermal pad area to be soldered, so decreases and the heat dissipation capability
that wicking is not a problem. increases. For a single package, the sum of the RMS
4. Connect all holes to the internal ground plane. output currents and voltages should be used to
choose the proper package.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
24 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4511
49.9 W
-
+
J1
R12 C15
0.22 Fm
R1
56.2 W
R3
340 W
R4
340 W
R2
56.2 W
J2
TP2
C14
0.1 FmC11
0.1 Fm
TP1
U1 11
2
12
4
Vocm
9
TP3
R6
348 W
1315
14 16
PwrPad 10
VO-
VO+
3
75
86
VCC
348 W
VCC
R5
PD
J5
GND VS+
J6
C3
10 Fm10 Fm
C5
0.1 Fm0.1 Fm
C12 C13
J8
J3
T1
16
5
4
R9
open
R7
86.6 W
R8
86.6 W
R10
open
XFMR_ADT1-1WT
3
R11
69.8W
J7
C8
open
C7
open
C1
open
C2
open
VCC
THS4511
www.ti.com
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
THS4511 EVM
Figure 55 is the THS4511 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown in Figure 56, and
Table 5 is the bill of materials for the EVM as supplied from TI.
Figure 55. THS4511 EVAL1 EVM Schematic
Figure 56. THS4511 EVAL1 EVM Layer 1 Through 4
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): THS4511
THS4511
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
www.ti.com
Table 5. THS4511RGT EVM Bill of Materials
SMD REFERENCE PCB MANUFACTURER
ITEM DESCRIPTION SIZE DESIGNATOR QTY PART NUMBER(1)
1 CAP, 10.0 µF, Ceramic, X5R, 6.3V 0805 C3, C5 2 (AVX) 08056D106KAT2A
2 CAP, 0.1 µF, Ceramic, X5R, 10V 0402 C11-C14 4 (AVX) 0402ZD104KAT2A
3 CAP, 0.22 µF, Ceramic, X5R, 6.3V 0402 C15 1 (AVX) 04026D224KAT2A
4 OPEN 0402 C1, C2, C7-C10 6
5 OPEN 0402 R9, R10 2
6 Resistor, 49.9 Ω, 1/16W, 1% 0402 R12 1 (KOA) RK73H1ETTP49R9F
7 Resistor, 56.2 Ω, 1/16W, 1% 0402 R1, R2 (KOA) RK73H1ETTP56R2F
8 Resistor, 69.8 Ω, 1/16W, 1% 0402 R11 3 (KOA) RK73H1ETTP69R8F
9 Resistor, 86.6 Ω, 1/16W, 1% 0402 R7, R8 2 (KOA) RK73H1ETTP86R6F
10 Resistor, 340 Ω, 1/16W, 1% 0402 R3, R4 2 (KOA) RK73H1ETTP3400F
11 Resistor, 348 Ω, 1/16W, 1% 0402 R5, R6 2 (KOA) RK73H1ETTP3480F
12 Resistor, 0 Ω, 5% 0805 C4, C6 2 (KOA) RK73Z2ATTD
13 Transformer, RF T1 1 (MINI-CIRCUITS) ADT1-1WT
Jack, banana receptance, 0.25" diameter 2
14 J5, J6 (HH SMITH) 101
hole
15 OPEN J1, J7, J8 3
16 Connector, edge, SMA PCB Jack J2, J3 2 (JOHNSON) 142-0701-801
17 Test point, Red TP1, TP2, TP3 3 (KEYSTONE) 5000
18 IC, THS4511 U1 1 (TI) THS4511RGT
19 Standoff, 4-40 HEX, 0.625" length 4 (KEYSTONE) 1808
20 SCREW, PHILLIPS, 4-40, 0.250" 4 SHR-0440-016-SN
21 Printed circuit board 1 (TI) EDGE# 6475513
(1) The manufacturer's part numbers were used for test purposes only.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input and output voltage ranges as specified in the table provided
below.
INPUT RANGE, VS+ TO VS– 3.0 V TO 6.0 V
Input Range, VI3.0 V to 6.0 V NOT TO EXCEED VS+ or VS–
Output Range, VO3.0 V to 6.0 V NOT TO EXCEED VS+ or VS–
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the product data sheet or EVM user's guide (if user's guide is
available) prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than +30°C. The EVM is
designed to operate properly with certain components above +50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
26 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4511
THS4511
www.ti.com
SLOS471E –SEPTEMBER 2005–REVISED NOVEMBER 2009
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2007) to Revision E Page
• Updated document format to match current standards ........................................................................................................ 1
• Deleted title and conditions of Typical Conditions table of graphs ....................................................................................... 6
• Added title and conditions to Typical Characteristics plots ................................................................................................... 7
• Changed item 9 in the Layout Recommendations section ................................................................................................. 23
• Added PowerPAD Design Considerations section ............................................................................................................. 23
• Added PowerPAD PCB Layout Considerations section ..................................................................................................... 24
• Moved Figure 54 and associated paragraph to PowerPAD PCB Layout Considerations section ..................................... 24
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): THS4511
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
THS4511RGTT ACTIVE VQFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 4511
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4511 :
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
•Space: THS4511-SP
NOTE: Qualified Version Definitions:
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4511RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4511RGTT VQFN RGT 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2017
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
16X 0.30
0.18
1.45 0.1
16X 0.5
0.3
1 MAX
(0.2) TYP
0.05
0.00
12X 0.5
4X
1.5
A3.1
2.9 B
3.1
2.9
VQFN - 1 mm max heightRGT0016A
PLASTIC QUAD FLATPACK - NO LEAD
4219032/A 02/2017
PIN 1 INDEX AREA
0.08
SEATING PLANE
1
49
12
58
16 13
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
SYMM
SYMM
17
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220
SCALE 3.600
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
16X (0.24)
16X (0.6)
( 0.2) TYP
VIA
12X (0.5)
(2.8)
(2.8)
(0.475)
TYP
( 1.45)
(R0.05)
ALL PAD CORNERS (0.475) TYP
VQFN - 1 mm max heightRGT0016A
PLASTIC QUAD FLATPACK - NO LEAD
4219032/A 02/2017
SYMM
1
4
58
9
12
13
16
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
17
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
16X (0.6)
16X (0.24)
12X (0.5)
(2.8)
(2.8)
( 1.34)
(R0.05) TYP
VQFN - 1 mm max heightRGT0016A
PLASTIC QUAD FLATPACK - NO LEAD
4219032/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
ALL AROUND
METAL
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
SYMM
1
4
58
9
12
13
16
17
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