INTEGRATED CIRCUITS DATA SHEET TDA8769 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling Objective specification Supersedes data of 2003 Apr 07 2003 Dec 09 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling CONTENTS 12 PACKAGE OUTLINE 13 SOLDERING 13.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 14 DATA SHEET STATUS 8 LIMITING VALUES 15 DEFINITIONS 9 THERMAL CHARACTERISTICS 16 DISCLAIMERS 10 CHARACTERISTICS 11 APPLICATION INFORMATION 11.1 11.2 11.3 11.4 11.5 11.5.1 11.5.1.1 11.5.1.2 11.5.2 11.5.2.1 11.5.2.2 11.5.2.3 11.5.2.4 11.5.2.5 11.5.2.6 Output coding and control signals TDA8769 in 3G radio receivers Application diagrams Demonstration board Definitions Static parameters Integral non-linearity (INL) Differential non-linearity (DNL) Dynamic parameters Signal-to-noise and distortion (SINAD) Effective number of bits (ENOB) Total harmonic distortion (THD) Signal-to-noise ratio (SNR) Spurious free dynamic range (SFDR) Intermodulation distortion (IMD2 and IMD3) 2003 Dec 09 13.2 13.3 13.4 13.5 2 TDA8769 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling 1 TDA8769 * Advanced Frequency Modulation (FM) radio FEATURES * 12-bit resolution * Imaging (camera scanner and medical) * Optimized for both Nyquist and high IF sampling * Cable modem or set top box * High-speed sampling rate up to 105 MHz * Radar and satellite hub systems. * Maximum analog input frequency of 330 MHz (see Application section) 3 * Only 2 clock cycles latency The TDA8769 is a BiCMOS 12-bit Analog-to-Digital Converter (ADC) optimized for GSM/EDGE, W-CDMA and CDMA2000 radio transceivers, high data rate radios and other applications such as advanced FM radio and professional imaging. Its main innovation is the RF sampling, based on a high-speed clock of up to 105 Msps combined with high input frequencies of up to 250 MHz. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 105 MHz. * 5 V power supplies and 3.3 V output power supply * Binary or two's-complement CMOS outputs * Programmable Complete Conversion Signal (CCS) CMOS output * In-range CMOS compatible output * CMOS compatible static digital inputs * LVTTL and LVCMOS compatible digital outputs The TDA8769 analog performances have been proven in various multi-carrier 3G radio receivers, providing the best-in-class Adjacent Channel Selectivity (ACS) up to 80 dB. * Differential clock input PECL; sine wave and TTL compatible * Integrated track-and-hold amplifier * Differential analog input Moreover the TDA8769 offers the lowest clock cycle latency, which enables competitive and optimized feedback loops in controlled systems. * External amplitude range control * Full-scale controllable from 1.5 to 1.9 V (p-p) * Voltage controlled regulator included All static digital inputs (TH, CEN, OTC, DEL0 and DEL1) are CMOS compatible and all outputs are LVTTL and LVCMOS compatible. A sine wave clock input signal can also be used. * Temperature range from -40 to +85 C. 2 GENERAL DESCRIPTION APPLICATIONS * Cellular infrastructure (2.5G, 3G, etc.) 4 * Base stations and "Zero-IF" or direct IF sampling subsystems Tbf. QUICK REFERENCE DATA * Wireless and wired broadband communications * Wireless Local Loop (WLL) * Local Multipoint Distribution Service (LMDS) 5 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8769HW/6 TDA8769HW/8 HTQFP48 DESCRIPTION plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1.0 mm; heatsink TDA8769HW/10 2003 Dec 09 VERSION SOT545-2 SAMPLING FREQUENCY (MHz) 60 80 105 3 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling 6 TDA8769 BLOCK DIAGRAM 16 FSREF VCCA1 DEL0 DEL1 CLK CLKN handbook, full pagewidth 13 15 39 38 VCCA3 2 VCCA4 3 VCCD1 VCCD2 44 40 17 VREF REFERENCE TDA8769 VREF 36 CLOCK DRIVER 11 19 AMP INN IN TH CMADC n.c. TRACK LATCH 47 46 42 & 23 to 34 12 35 ADC LATCH HOLD 1 22 CMADC REFERENCE 5 48 20 CEN 4 43 41 18 AGND1 AGND3 AGND4 DGND1 DGND2 PINNING PIN TYPE(1) CMADC 1 O regulator output common mode ADC output VCCA1 2 P analog supply voltage 1 (5.0 V) VCCA3 3 P analog supply voltage 3 (5.0 V) AGND3 4 G analog ground 3 DEC 5 I/O n.c. 6 - not connected n.c. 7 - not connected n.c. 8 - not connected n.c. 9 - not connected n.c. 10 - not connected VREF 11 I reference voltage input n.c. 12 - not connected FSREF 13 O reference output n.c. 14 - not connected DEL1 15 I complete conversion sampling delay input 1 DEL0 16 I complete conversion sampling delay input 0 VCCD2 17 P digital supply voltage 2 (5.0 V) 2003 Dec 09 VCCO IR 6 to 10, 12, 14, 21, 45 Fig.1 Block diagram. SYMBOL OTC D0 to D11 POWER MANAGEMENT DEC 7 CCS DESCRIPTION decoupling node 4 37 OGND MBL884 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling PIN TYPE(1) DGND2 18 G digital ground 2 OTC 19 I control input two's complement output (active HIGH) CEN 20 I chip enable input (CMOS level; active LOW) n.c. 21 - not connected IR 22 O in-range output D11 23 O data output bit 11 (MSB) D10 24 O data output bit 10 D9 25 O data output bit 9 D8 26 O data output bit 8 D7 27 O data output bit 7 D6 28 O data output bit 6 D5 29 O data output bit 5 D4 30 O data output bit 4 D3 31 O data output bit 3 D2 32 O data output bit 2 D1 33 O data output bit 1 D0 34 O data output bit 0 (LSB) SYMBOL DESCRIPTION VCCO 35 P supply voltage of data output (3.3 V) CCS 36 O complete conversion signal output OGND 37 G ground of data output CLKN 38 I complementary clock input CLK 39 I clock input VCCD1 40 P digital supply voltage 1 (5.0 V) DGND1 41 G digital ground 1 TH 42 I track-and-hold enable input (CMOS level; active HIGH) AGND4 43 G analog ground 4 VCCA4 44 P analog supply voltage 4 (5.0 V) n.c. 45 - not connected IN 46 I analog input voltage INN 47 I complementary analog input voltage AGND1 48 G analog ground 1 AGND5 exposed die pad G analog ground 5 Note 1. P = power supply, G = ground, I = input and O = output. 2003 Dec 09 5 TDA8769 Philips Semiconductors Objective specification TDA8769 37 OGND 38 CLKN 39 CLK 40 VCCD1 41 DGND1 42 TH 43 AGND4 44 VCCA4 45 n.c. 46 IN handbook, full pagewidth 47 INN 48 AGND1 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling CMADC 1 36 CCS VCCA1 2 35 VCCO VCCA3 3 34 D0 AGND3 4 33 D1 DEC 5 32 D2 n.c. 6 31 D3 TDA8769HW n.c. 7 30 D4 n.c. 8 29 D5 n.c. 9 28 D6 n.c. 10 27 D7 exposed die pad D10 24 D11 23 IR 22 n.c. 21 CEN 20 OTC 19 DGND2 18 VCCD2 17 DEL0 16 25 D9 DEL1 15 n.c. 12 n.c. 14 26 D8 FSREF 13 VREF 11 MBL885 Fig.2 Pin configuration. 8 LIMITING VALUES Tbf. 9 THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth(j-a) thermal resistance from junction to ambient in free air; (tbf) 25 K/W Rth(c-a) thermal resistance from case to ambient in free air; (tbf) (tbf) K/W 2003 Dec 09 6 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling TDA8769 10 CHARACTERISTICS VCCA = 4.75 to 5.25 V; VCCD = 4.75 to 5.25 V; VCCO = 2.7 to 3.6 V; AGND connected to DGND; Tamb = -40 to +85 C; VIN(p-p) - VINN(p-p) = 1.9 V - 0.5 dBFS; VVREF = VCCA3 - 1.75 V; Vi(CM ) = VCCA3 - 1.6 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.0 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. SYMBOL PARAMETER CONDITIONS TEST(1) MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 2.7 3.0 3.6 V ICCA analog supply current - 109 (tbf) mA ICCD digital supply current - 48 (tbf) mA ICCO output supply current fCLK = 80 Msps; fi = 21.4 MHz - 17.5 (tbf) mA Ptot total power dissipation fCLK = 60 Msps; fi = 21.4 MHz - 825 (tbf) mW fCLK = 80 Msps; fi = 21.4 MHz - 840 (tbf) mW fCLK = 105 Msps; fi = 21.4 MHz - 855 (tbf) mW PECL mode 3.19 - 3.52 V TTL mode DGND - 0.8 V PECL mode 3.83 - 4.12 V TTL mode Clock inputs: pins CLK and CLKN; note 2 INPUTS VIL VIH IIL IIH LOW-level input voltage referenced to DGND; VCCD = 5 V HIGH-level input referenced to DGND; voltage VCCD = 5 V LOW-level input current 2.0 - VCCD V VCLK or VCLKN = 3.52 V (tbf) - - A VCLK or VCLKN = 0.80 V (tbf) - - mA - - (tbf) A - - (tbf) mA VCLK = VCLK - VCLKN; AC mode; DC voltage level = 2.5 V (tbf) 1.5 (tbf) V HIGH-level input VCLK or VCLKN = 3.83 V current VCLK or VCLKN = 2.00 V VCLK differential AC input voltage for switching Ri input resistance fCLK = 105 Msps - (tbf) - M Ci input capacitance fCLK = 105 Msps - (tbf) - pF 2003 Dec 09 7 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling SYMBOL PARAMETER CONDITIONS TEST(1) TDA8769 MIN. TYP. MAX. UNIT TIMING - - 9 Msps maximum clock frequency TDA8769HW/6 60 - - MHz/ Msps maximum clock frequency TDA8769HW/8 80 - - MHz/ Msps maximum clock frequency TDA8769HW/10 105 - - MHz/ Msps fclk(min) minimum clock frequency fclk(max) VTH = VCCD tCLKH clock HIGH pulse width fi = 21.4 MHz (tbf) - - ns tCLKL clock LOW pulse fi = 21.4 MHz width (tbf) - - ns Analog inputs: pins IN and INN IIL LOW-level input current VVREF = VCCA3 - 1.75 V; VTH = HIGH - 10 - A IIH HIGH-level input VVREF = VCCA3 - 1.75 V; current VTH = HIGH - 10 - A Ri input resistance D - 8.4 - M Ci input capacitance D - 250 500 fF Vi(CM) common mode input voltage D VCCA3 - 1.2 VCCA3 - 1.6 VCCA3 - 1.7 V VIN = VINN; output code = 2047 Digital inputs: pins OTC, SH, DEL1, DEL0 and CEN VIL LOW-level input voltage DGND - 0.3VCCD V VIH HIGH-level input voltage 0.7VCCD - VCCD V IIL LOW-level input current (tbf) - IIH HIGH-level input VIH = 0.7VCCD current - - (tbf) A VIL = 0.3VCCD A Voltage controlled regulator output: pin CMADC Vo(CM) common mode output voltage - VCCA3 - 1.6 - V IL(CM) load current - 1 2 mA 2003 Dec 09 8 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling SYMBOL PARAMETER CONDITIONS TEST(1) TDA8769 MIN. TYP. MAX. UNIT Reference voltage input: pin VREF; note 3 Vref(FS) full-scale fixed voltage fi = 25 MHz; fCLK = 105 Msps - VCCA3 - 1.75 - V Vi(p-p) input voltage (peak-to-peak value) Vi = VIN - VINN; VVREF = VCCA3 - 1.75 V; Vi(CM) = VCCA3 - 1.6 V - 1.9 - V Iref input current - 0.3 10 A Full-scale voltage controlled regulator output: pin FSREF Vo(FS) 1.9 V full-scale output voltage - VCCA3 - 1.75 - V IL(FS) load current - 1 2 mA Digital outputs: pins D11 to D0 and IR OUTPUT LEVELS VOL LOW-level output voltage IOL = 2 mA DGND - DGND + 0.5 V VOH HIGH-level output voltage IOH = -0.4 mA VCCO - 0.5 - VCCO V IOZ output current in 3-state output level between 0.5 V and VCCO -20 - +20 A TIMING; see Fig. 3 td(s) sampling delay CL = 10 pF; note 4 - (tbf) (tbf) ns th(o) output hold time CL = 10 pF (tbf) 3.7 - ns td(o) output delay CL = 10 pF - 4.6 (tbf) ns 3-STATE OUTPUT DELAY tdZH enable to HIGH state - 2.8 - ns tdZL enable to LOW state - 7.5 - ns tdHZ disable from HIGH state - 7.2 - ns tdLZ disable from LOW state - 2.9 - ns DEL0 = LOW; DEL1 = HIGH - 0 - ns DEL0 = HIGH; DEL1 = LOW - 1.2 - ns DEL0 = HIGH; DEL1 = HIGH - 2.2 - ns Timing complete conversion signal: pin CCS td(CCS) complete conversion signal delay 2003 Dec 09 CL = 10 pF; see Table 4 and Fig 4 9 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling SYMBOL PARAMETER CONDITIONS TEST(1) TDA8769 MIN. TYP. MAX. UNIT Analog signal processing (50% clock duty factor) INL integral non-linearity fCLK = 20 Msps; fi = 400 kHz - 1.7 (tbf) LSB DNL differential non-linearity fCLK = 20 Msps; fi = 400 kHz; no missing code guaranteed - 0.4 (tbf) LSB Eoffset offset error VCCA = VCCD = 5 V; VCCO = 3.0 V; Tamb = 25 C; output code = 2047 - -5 - mV EG gain error VCCA = VCCD = 5 V; amplitude VCCO = 3.0 V; Tamb = 25 C (spread from device to device) (tbf) - (tbf) %FS B analog bandwidth fCLK = 105 Msps; -3 dB; full-scale input; note 5 - 330 - MHz THD total harmonic distortion TDA8769HW/6 B = Nyquist; note 6 - -74 - dBc total harmonic distortion TDA8769HW8 B = Nyquist; note 6 fi = 21.4 MHz - -74 - dBc fi = 50 MHz - -68 - dBc total harmonic distortion TDA8769HW/10 B = Nyquist; note 6 fi = 21.4 MHz - -67 - dBc fi = 78 MHz - -63 - dBc Nth(rms) thermal noise (RMS value) shorted input; VTH = VCCD; fclk = 105 Msps - (tbf) - LSB SNR signal-to-noise ratio TDA8769HW/6 fi = 21.4 MHz; note 7 - 66 - dBc signal-to-noise ratio TDA8769HW/8 fi = 21.4 MHz; note 7 - 66 - dBc B = Nyquist - 66 - dBc B = 5 MHz - 72.4 - dBc - 64 - dBc B = Nyquist - 62 - dBc B = 5 MHz - 72 - dBc signal-to-noise ratio TDA8769HW/10 2003 Dec 09 D fi = 21.4 MHz B = Nyquist B = Nyquist fi = 50 MHz; note 7 fi = 21.4 MHz; note 7 B = Nyquist fi = 78 MHz; note 7 10 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling SYMBOL SFDR PARAMETER spurious free dynamic range TDA8769HW/6 fi = 21.4 MHz spurious free dynamic range TDA8769HW/8 fi = 21.4 MHz TEST(1) TYP. MAX. UNIT 77 - dBc - 77 - dBc B = Nyquist - 70 - dBc B = 5 MHz - 80.8 - dBc - 68 - dBc B = Nyquist - 67 - dBc B = 5 MHz - 84 - dBc effective number fi = 21.4 MHz; note 8 of bits B = Nyquist TDA8769HW/6 - 10.6 - bit effective number fi = 21.4 MHz; note 8 of bits B = Nyquist TDA8769HW/8 fi = 50 MHz; note 8 - 10.6 - bit B = Nyquist - 10.3 - bit B = 5 MHz - 11.7 - bit - 10 - bit B = Nyquist - 9.6 - bit B = 5 MHz - 11.8 - bit - (tbf) - dBFS - 82 - dBFS - (tbf) - B = Nyquist B = Nyquist fi = 50 MHz fi = 21.4 MHz B = Nyquist fi = 78 MHz effective number fi = 21.4 MHz; note 8 of bits B = Nyquist TDA8769HW/10 fi = 78 MHz; note 8 IM2 second order intermodulation distortion fi1 = 15 MHz and fi2 = 18 MHz; note 10 IM3 third order intermodulation distortion fi1 = 15 MHz and fi2 = 18 MHz; note 10 bit error rate fi = 25 MHz; VIN = 16LSB at code 2047; fclk = 105 Msps BER MIN. - spurious free dynamic range TDA8769HW/10 ENOB CONDITIONS TDA8769 fclk= 80 Msps fclk= 80 Msps Notes 1. Explanation tests: a) D = guaranteed by design b) C = guaranteed by characterization c) I = industrially tested for 100%. 2003 Dec 09 11 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling TDA8769 2. The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation: a) PECL mode 1: (DC level varies proportionally with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC level varies proportionally with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC level varies proportionally with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has to be connected to the ground. 3. The ADC input range can be adjusted with an external reference connected to pin VREF. This voltage has to be referenced to VCCA. 4. Output data acquisition: the output data is available after the maximum delay of td(s). 5. The -3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. 6. The total harmonic distortion is obtained with the addition of the first five harmonics. 7. The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency. 8. The effective number of bits, or ENOB, are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to signal-to-noise and distortion, or SINAD, is given by SINAD = ENOB x 6.02 + 1.76 dB. 9. Intermodulation measured relative to either tone with analog input frequencies of (tbf) and (tbf) MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale input to the converter (-6 dB below full-scale for each input signal). 10. IM2 is the ratio of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product. IM3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. 2003 Dec 09 12 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling handbook, full pagewidth CKP TDA8769 n 50% td(o) data n-1 D0 to D11 data n VCCO - 0.5 V data n+1 0.5 V th(o) tds(i) VI sample n sample n+1 sample n+2 sample n+3 sample n+4 MDB034 Fig.3 Output timing diagram. handbook, full pagewidth D0 to D11 td(CCS) CCS MBL874 Fig.4 Complete conversion signal timing diagram. 2003 Dec 09 13 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling TDA8769 11 APPLICATION INFORMATION 11.1 Output coding and control signals Table 1 Output coding with differential inputs (typical values to AGND); VIN(p-p) - VINN(p-p) = 1.9 V - 0.5 dBFS; VVREF = VCCA3 - 1.75 V CODE VIN(p-p) VINN(p-p) IR BINARY OUTPUTS (D11 TO D0) TWO'S COMPLEMENT OUTPUTS (D11 TO D0) Underflow <2.925 >3.875 0 000000000000 100000000000 0 2.925 3.875 1 000000000000 100000000000 1 - - 000000000001 100000000001 : 2047 : : : : : 3.4 3.4 011111111111 111111111111 : : : : 4094 - - 111111111110 011111111110 4095 3.875 2.925 111111111111 011111111111 Overflow >3.875 <2.925 111111111111 011111111111 Table 2 0 Mode selection CONTROL INPUT TWO'S COMPLEMENT OUTPUT (OTC) CHIP ENABLE NOT (CEN) 0 0 binary; active 1 0 two's complement; active don't care 1 high impedance Table 3 OUTPUT DATA (D0 TO D11 AND IR) Track-and-hold selection CONTROL INPUT TRACK-AND-HOLD (TH) Table 4 11.2 MODE 1 active 0 inactive; tracking Complete conversion signal selection DEL1 DEL0 OUTPUT SIGNAL 0 0 inactive 0 1 active (for timing values, see Chapter 10) 1 0 1 1 TDA8769 in 3G radio receivers TDA8769 has been proven in many 3G receivers with various operating conditions regarding input frequency, signal input frequency bandwidth and sampling frequency. TDA8769 provides a maximum analog input frequency of 250 MHz. It allows a significant cost reduction of the RF front-end, from two mixers to only one, even in multicarrier architecture. Table 5 shows possible applications with the TDA8769 in High IF sampling mode. 2003 Dec 09 14 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling Table 5 TDA8769 Examples of possible fi, fclk and fi bandwidth combinations supported fi (MHz) fclk (MHz) fi BW (MHz) SNR (dB) SFDR (dBc) 250 9.60 0.20 66.5 79.9 243.95 9.60 0.20 62.6 68.5 243.95 19.20 0.20 68.4 77.2 243.95 52.00 0.20 65.7 80.0 190 40.00 1.25 72.0 80.0 106 76.80 5.00 70.8 83.6 86 76.80 5.00 72.2 87.1 80 61.44 10.00 (tbf) (tbf) 70 40.00 5.00 70 70 69.99 58.98 1.25 (tbf) (tbf) 27 51.2 3.5 (tbf) (tbf) 10.8 32.5 0.30 84.3 83.0 For a dual carrier W_CDMA receiver, the most important parameters are the sensitivity and Adjacent Channel Selectivity (ACS). In W-CDMA, it can be far below the noise floor, is defined by the Sensitivity to Noise Ratio (SENR). Its value is negative due to the gain processing. The Adjacent Channel Power Ratio (ACPR) is the difference between the peak and noise floor. It represents the ratio of the adjacent channel power and the average power of the channel. The ACS is defined by the sum of SENR and ACPR. Figure 5 illustrates the relation between these parameters. On a typical application with the TDA8769 device, the ACS obtained is 80 dB with an ACPR of 70 dB and a SENR of 10 dB. Moreover, the Noise Figure (NF) of the TDA8769 is 31.5 dB. handbook, full pagewidth interfering channel wanted channel ACS ACPR noise floor SENR NF sensitivity thermal noise MBL875 Fig.5 Adjacent channel selectivity and analog-to-digital converter sensitivity. 2003 Dec 09 15 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling 11.3 TDA8769 Application diagrams TDA8769 TDA8769 CLK CLKN 270 270 CLK CLKN Q TTL TTL D 50 MDB036 Q MDB035 Fig.6 TTL to PECL translator application. 2003 Dec 09 Fig.7 TTL single-ended clock application. 16 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling tbf Fig.8 Application diagram. 2003 Dec 09 17 TDA8769 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling Demonstration board TR1 T1_6T_KK81 IN 4 R1 100 DGND 5 6 VCCA DGND ON R3 100 TH S1 1K2 1 VCCA AGND AGND AGND R2 50 VCCD1 AGND R125680 J2 DGND CLK 48 S2 EXT P1 5 k CMADC 1K2 VCCA1 AGND VCCA3 AGND VCCA AGND3 AGND DEC n.c. n.c. C4 100 nF n.c. n.c. n.c. AGND VREF TB2 VCCA 47 46 44 43 42 41 40 CLKN OGND CLK VCCD1 DGND1 TH VCCA4 45 39 DGND 37 38 DGND 36 1 2 35 3 34 33 4 IC1 5 6 32 31 TDA8769HW 7 30 8 29 9 28 27 10 26 11 25 12 CCS VCCO VCCO D0 PCN12A_44P_2.54DS J1 D1 D2 B1 D3 B2 D4 B3 D5 B4 D6 CSS D7 D0 D8 EXT P2 1 k 1K2 DGND R4 2.4 k VCCD2 ON S4 AGND 19 20 21 22 23 D11 18 B9 B10 B11 AGND B12 DGND B13 DGND B14 VCCD2 VCCD2 ON S8 DEL1 B6 B8 24 D10 17 IR 16 n.c. S3 15 CEN FSREF 100 nF R5 1.2 k 14 OTC 13 DGND2 VCCA B5 B7 D9 C5 VCCD2 VCCA n.c. AGND n.c. VCCA IN C14 330 nF AGND4 CMADC DEL0 AGND VCCD1 DEL1 220 nF 50 3 TB1 2 AGND1 R125680 J1 C1 INN handbook, full pagewidth n.c. 11.4 TDA8769 B15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B16 B17 DEL0 B18 DGND DGND B19 VCCD2 S6 1K2 ON VCCD2 S7 1K2 OFF OTC IC4 2 CEN DGND DGND C12 10 nF C3 100 nF C2 330 nF 5 3 VCC GND AGND DGND DGND 2 VCCO DGND VCCD1 (40) FL3 470D_0D0_S C17 10 nF C15 100 nF C13 330 nF A20 A21 A22 IR D3 LS6T670 3 AGND B22 1 C19 10 nF AGND B21 R10 150 4 C18 10 nF B20 TRIG R9 50 4 74AHC1GUO4GW DGND R11 150 VCCA (44) (2/3) FL1 470D_0D0_S R125680 J3 VCCO DGND DGND DGND VCCD2 (17) FL2 470D_0D0_S C20 10 nF C6 100 nF C11 330 nF TM2 DGND TM3 FL4 HF70A08S AGND DGND DGND D1 BYD17G 12 V J5 MSTBA2.5_20_5D8 GND J5 IN 1 20 V 2 C7 22 F MC7805D2T 1 IC2 2 3 VCCO (35) TM1 OUT 16 V GND C8 4.7 F R6 750 IN C9 470 nF LM317D2T 3 IC3 1 2 TP1 OUT R8 240 R7 330 DGND ADJ C10 1F C16 10 nF DGND DGND DGND DGND D2 PWR LGT679_C0 DGND DGND DGND Fig.9 Demonstration board schematic. 2003 Dec 09 18 MBL876 Philips Semiconductors Objective specification TDA8769 C1 J2 J1 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling TM2 R1 P2 S3 IC4 C12 J3 TM3 R9 C11 D3 R10 C10 TP1 R11 C8 D2 R5 IC3 C16 J4 S4 S5 C20 C5 FL2 R7 R8 C9 C7 1 FL4 S6 S7 C2 C3 IC1 R6 D1 TB2 C5 R4 C17 C18 C19 J5 1 2 FL1 C4 TM1 C15 R2 P1 R3 C14 S1 S2 TR1 IC2 FL3 1TB1 C13 MBL878 MBL877 Fig.10 Component placement, top view. 2003 Dec 09 Fig.11 Component placement, bottom view. 19 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling MBL879 MBL880 Fig.12 Printed-circuit board tracks, layout 1. Fig.13 Printed-circuit board tracks, layout 2. MBL881 Fig.14 Printed-circuit board tracks, layout 3. 2003 Dec 09 TDA8769 20 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling 11.5 where: Definitions 11.5.1 11.5.1.1 TDA8769 i = 0 to 2n - 2 STATIC PARAMETERS Integral non-linearity (INL) Vin = input voltage for code i INL is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of code i is obtained from the following equation: S = slope of the ideal straight line. V in ( i ) - V in ( ideal ) INL ( i ) = ---------------------------------------------S Figure 15 shows the spectrum of a single tone full-scale input sine wave with frequency ft, conforming to coherent sampling and digitized by the ADC under test. Coherent f M sampling means that ----t = ----- , where M is the number of fs N 11.5.2 where: i = code value cycles, N the number of samples and both M and N being a relative prime. Vin = input voltage for code i S = slope of the ideal straight line (code width). 11.5.1.2 DYNAMIC PARAMETERS Remark: The parameter Pnoise used in the following equations includes the power of the random noise, non-linearities, sampling time errors and quantization noise. Differential non-linearity (DNL) DNL is the deviation in code width from the value of one LSB. The DNL of code i is obtained from the following equation: V in ( i + 1 ) - V in ( i ) DNL ( i ) = -------------------------------------------S MBL882 handbook, full pagewidth 0 -20 magnitude IMD3 -40 -60 -80 -100 -120 -140 -160 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 measured output range (MHz) Fig.15 Spectrum of a full-scale input sine wave with frequency ft. 2003 Dec 09 21 27 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling 11.5.2.1 Signal-to-noise and distortion (SINAD) 11.5.2.4 SINAD is the ratio of the signal power to the noise plus distortion power, excluding the DC component, at a given sample rate and input frequency: Signal-to-noise ratio (SNR) SNR is the ratio of the signal power to the noise power, excluding the harmonics and DC component of the signal: P signal SNR = 10log 10 ---------------- dB P noise P signal SINAD = 10log 10 -------------------------------------- dB. P noise + distortion 11.5.2.5 11.5.2.2 TDA8769 Effective number of bits (ENOB) Spurious free dynamic range (SFDR) ENOB is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the actual ADC. A good approximation is: The SFDR specifies the available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious signal, harmonic and non-harmonic, excluding the DC component. SINAD - 1.76 ENOB = ------------------------------------6.02 a1 SFDR = 10log 10 -------------------- dB max ( s ) 11.5.2.3 11.5.2.6 Total harmonic distortion (THD) Intermodulation distortion (IMD2 and IMD3) THD is the ratio of the power of the harmonics to the power of the signal frequency. The equation for k - 1 harmonics is: Figure 16 shows the spectral analysis of a dual tone sine wave input, at frequencies ft1 and ft2, meeting the coherence criterion. P harmonics THD = 10log 10 ------------------------- dB P signal The 2nd and 3rd order intermodulation distortion products, IMD2 and IMD3 respectively, are defined with a dual tone input. IMD2 is defined as the ratio of the RMS value of either tone to the RMS value of the second order intermodulation product, IMD3 with the third order intermodulation product. The IMD is given by: where: 2 2 P harmonics = a 2 + a 3 + ... + a k P signal = a 1 2 2 P intermod IMD = 10log 10 --------------------- dB P signal As usual the value of k = 6 (i.e. the calculation of THD is done with the first 5 harmonics). 2003 Dec 09 22 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling TDA8769 where: P intermod = a P signal = a a 2 im ( ft ) 2 2 ft1 im ( ft1 - ft2 ) +a 2 ft2 -a 2 im ( ft1 + ft2 ) +a 2 im ( ft1 - 2ft2 ) +a 2 im ( ft1 + 2ft2 ) +...+a 2 im ( 2ft1 - ft2 ) +a 2 im ( f2t1 + ft2 ) . is the power of the intermodulation component at ft. MBL883 handbook, full pagewidth a1 magnitude SFDR a2 a3 ak measured output range (MHz) Fig.16 Spectral analysis with dual tone. 2003 Dec 09 23 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling TDA8769 12 PACKAGE OUTLINE HTQFP48: plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad SOT545-2 c y exposed die pad side X Dh 36 25 37 A 24 ZE e E HE Eh (A 3) A A2 A1 w M bp Lp L pin 1 index 13 48 detail X 1 12 ZD w M bp v M A e D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 A2 A3 bp c D(1) Dh E(1) Eh e HD HE L Lp v w y 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 7.1 6.9 4.6 4.4 7.1 6.9 4.6 4.4 0.5 9.1 8.9 9.1 8.9 1 0.75 0.45 0.2 0.08 0.08 ZD(1) ZE(1) 0.89 0.61 7 0 0.89 0.61 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 99-08-04 03-04-07 SOT545-2 2003 Dec 09 EUROPEAN PROJECTION 24 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling To overcome these problems the double-wave soldering method was specifically developed. 13 SOLDERING 13.1 Introduction to soldering surface mount packages If wave soldering is used the following conditions must be observed for optimal results: This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 13.2 TDA8769 - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. * below 225 C (SnPb process) or below 245 C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. - for all BGA, HTSSON-T and SSOP-T packages 13.4 - for packages with a thickness 2.5 mm Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2003 Dec 09 Manual soldering 25 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling 13.5 TDA8769 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE REFLOW(2) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable PLCC(5), SO, SOJ suitable suitable not recommended(5)(6) suitable SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable LQFP, QFP, TQFP not suitable Notes 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages. 2003 Dec 09 26 Philips Semiconductors Objective specification 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling TDA8769 14 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 15 DEFINITIONS 16 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Dec 09 27 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA75 (c) Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R78/02/pp28 Date of release: 2003 Dec 09 Document order number: 9397 750 11706