CHIP
RESISTORS
www.vishay.com For technical questions, contact: efi@vishay.com Document Number: 61034
80 Revision: 14-Mar-08
CTM
Vishay Electro-Films
Megohm Center-Tap Chip Resistor
The CTM resistor chips extends the resistance range to 10M
in a center tap configuration while keeping the die size
relatively small.
The CTMs are manufactured using Vishay Electro-Films
(EFI) sophisticated thin film equipment and manufacturing
technology. The CTMs are 100 % electrically tested and
visually inspected to MIL-STD-883.
FEATURES
Wire bondable
Resistance range total: 200 kΩ to 10 MΩ
Center tap
Chip size: 0.040 inches square
Resistor material: Tantalum nitride, self-passivating
Moisture resistant
APPLICATIONS
Vishay EFI CTM tapped megohm resistor chips are designed for hybrid packages requiring high value, two resistor combinations.
Product may not
be to scale
TEMPERATURE COEFFICIENT OF RESISTANCE, VALUES AND TOLERANCES
PROCESS CODE
CLASS H* CLASS K*
100 130
101 131
099 129
098 128
*MIL-PRF-38534 inspection criteria
0.2 %
5 MΩ1.0 MΩ200 kΩ
0.1 %
Tightest Standard Tolerance Available
± 100 ppm/°C
± 50 ppm/°C
2 MΩ10 MΩ
0 to - 350 ppm/°C
0 to - 250 ppm/°C
0.5 %
STANDARD ELECTRICAL SPECIFICATIONS
PARAMETER
TCR Tracking Between Resistors ± 5 ppm/°C
Ratio/Ratio, RA/RB: Tolerance 1 ± 1 % standard
Noise - 12 dB typ.
Moisture Resistance, MIL-STD-202, Method 106 ± 0.5 % max. ΔR/R
Stability, 1000 h, + 125 °C, 10 mW ± 0.5 % max. absolute
± 0.005 % ratio
Operating Temperature Range - 55 °C to + 125 °C
Thermal Shock, MIL-STD-202, Method 107, Test Condition F ± 0.25 % max. ΔR/R
High Temperature Exposure, + 150 °C, 100 h ± 0.5 % max. ΔR/R
Dielectric Voltage Breakdown 200 V
Insulation Resistance 1012 min.
Operating Voltage 100 V max.
DC Power Rating at + 70 °C (Derated to Zero at + 175 °C) 20 mW each resistor
5 x Rated Power Short-Time Overload, + 25 °C, 5 s ± 0.25 % max. ΔR/R
CHIP
RESISTORS
Document Number: 61034 For technical questions, contact: efi@vishay.com www.vishay.com
Revision: 14-Mar-08 81
CTM
Megohm Center-Tap Chip Resistor Vishay Electro-Films
DIMENSIONS in inches
SCHEMATIC
Options: Gold back for eutectic die attach
Custom ratios available up to 4:1 RA/RB - consult Vishay EFI Sales
Consult Applications Engineer
0.040
0.005
0.036
0.005
0.0154
R
A
R
B
R
T =
R
A +
R
B
MECHANICAL SPECIFICATIONS in inches
PARAMETER
Chip Size 0.040 x 0.040 ± 0.002 (1.02 x 1.02 ± 0.05 mm)
Chip Thickness 0.010 ± 0.002 (0.254 ± 0.05 mm)
Chip Substrate Material Oxidized silicon, 10 kÅ minimum SiO2
Resistor Material Tantalum nitride, self-passivating
Bonding Pad Size 0.005 x 0.005 (0.127 x 0.127 mm)
Number of Pads 3
Pad Material 10 kÅ minimum aluminum
Backing None, lapped semiconductor silicon
ORDERING INFORMATION
Example: 100 % visual, 2 MΩ, ± 1 %, ± 100 ppm/°C TCR, aluminum pads, class H visual inspection
W
INSPECTION/
PACK AGING
W = 100 % visually inspected
parts in matrix trays per
MIL-STD-883
X = Sample, visually inspected
parts loaded in matrix
trays (4 % AQL)
CTM
PRODUCT
FAMILY
101
PROCESS
CODE
See Process Code
table
2000
RESISTANCE
VALUE
Use first 4 digits
significant digits of the
resistance (RT)
3
MULTIPLIER
CODE
2 = 100
3 = 1000
4 = 10 000
F
TOLERANCE
CODE
B = 0.1 %
C = 0.2 %
D = 0.5 %
F = 1.0 %
G = 2.0 %
H = 2.5 %
J = 5.0 %
K = 10 %
Document Number: 91000 www.vishay.com
Revision: 18-Jul-08 1
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