Atmel AT88SC0104CA
Atmel CryptoMemory
SUMMARY DATASHEET
Features
• One of a family of devices with user memories from 1Kbit to 8Kbits
• 1Kbit (128-byte) EEPROM user memory
• Four 256-bit (32-byte) zones
• Self-timed write cycle
• Single byte or 16-byte page write mode
• Programmable access rights for each zone
• 2Kbit configuration zone
• 37-byte OTP Area for User-def ined Codes
• 160-byte Area for User-defined Keys and Passwords
• High security features
• 64-bit mutual a uthentication protocol (under license of ELVA)
• Cryptographic Message Authentication Codes (MAC)
• Stream encryption
• Four key sets for authentication and encrypti on
• Eight sets of two 24-bit passwords
• Anti-tearing function
• Voltage and f r equency monito rs
• Smart card features
• ISO 7816 Class B (3V) operation
• ISO 7816-3 asynchronous T=0 protocol (Gemplus® Patent) *
• Multiple zon es , key sets and passwords for multi -a ppl ic atio n use
• Synchronous two-wire serial int erface for faster device initialization *
• Programmable 8-byte answer-to-reset r egi s ter
• ISO 7816-2 compliant modules
• Embedded application features
• Low voltag e s upply: 2.7V – 3.6V
• Secure nonvolatile s torage for sens itive system or us er information
• Two-wire serial int er face (TWI, 5V compatible)
• 1.0MHz compatibility for fast operation
• Standard 8-lead plastic pack ages, green co mpliant (exceeds RoHS)
• Same pin configurat ion as Atmel® AT24CXXX Serial EEPRO M i n S OIC and
PDIP packages
• High reliability
• Endurance: 100,000 cycles
• Data retention: 10 years
• ESD protection: 2,000V min
* Note: Modules available with eit her T = 0 / 2-wire modes or 2-wire mode only
5200FS−CRYPTO−12/11
This is a summary document.
The complete document is
available on the Atmel website
at www.atmel.com.
Atmel AT88SC0104CA [SUMMARY DATASHEET]
5200FS−CRYPTO−12/11
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Table 1. Pin Assignments
Pad Description ISO
Module TWI
Module “SOIC,
PDIP” TSSOP Mini-MAP
VCC Supply Volta ge C1 C1 8 8 4
GND Ground C5 C5 4 1 5
SCL/CLK Serial Clock Input C3 C3 6 6 2
SDA/IO Serial Data Input/Output C7 C7 5 3 7
RST Reset Input C2 NC NC NC NC
Figure 1. Pin Configuration
1
2
3
4
8
7
6
5
8-lead SOIC, PDIP
NC
NC
NC
GND
V
CC
NC
SCL
SDA
8-lead TSSOP
NC
VCC
81
NC CN72
NC
KLC63
GND
54
SDA
1
2
3
4
8
7
6
5
SDA
GND
CLK
V
CC
8-lead Ultra Thin Mini-MAP (MLP 2x3)
BottomView
NC
NC
NC
NC
TWI Smart Card Mo dule
V
CC
=C1
NC=C2
SCL/CLK=C3
NC=C4
C5=GND
C6=NC
C7=S
D
A/IO
C8=NC
ISO Smart Card Module
V
CC
=C1
RST=C2
SCL/CLK=C3
NC=C4
C5=GND
C6=NC
C7=S
D
A/IO
C8=NC
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1. Description
The Atmel AT88SC0104CA member of the Atmel CryptoMemory® family is a hi gh-performance secure memory providing
1Kbit of user memory with advanc ed security and cryptograp hic features built in. The user memory is divided into four 32-byte
zones, each of whi c h may be individually set with different security access right s or effectively combined toget her to provide
space for one to four data file s. The AT88SC0104CA features an enh anced command s et that allows direct communicat i on
with microcontroller hardware two-wire interface thereby allowing for fast er firmware dev elopment with reduced code sp ace
requirements.
1.1 Smart Card Applications
The AT88SC0104CA provides high s ecurity, low cost, and ease of implementation without the need for a microprocessor
operating system. The embedded c ryptographic engine provides for dynamic, s ymmetric-mutual authentication between the
device and host, as well as performing stream encryption for all d ata and passwords exchanged between the device and host .
Up to four uniq ue key sets may be used for these operat ions. The AT88SC0104CA offers t he abi lity to communicate with
virtually any smart card read er using the asynchronous T = 0 protoc ol (Gemplus Patent) defined in ISO 7816-3.
1.2 Embedded Applications
Through dynamic, symmetric-mutual authentication, data encryptio n, and the use of cryptographic Message Authentication
Codes (MAC), the AT88SC0104CA provides a s ecure place for s torage of sensitive i nformation withi n a system. With its
tamper detection circuits, this information r emains safe even under attack . A two-wire serial inter face running at speeds up to
1.0MHz provides fast and efficient communications with up to 15 individually addressable devices. The AT88SC0104CA is
available in i ndustry standard 8-lead packages with the same famil iar pin configur ation as AT24CXXX Serial EEPROM
devices.
Note: Does n ot apply to either the TSSOP or the ultra thin mini-map pinouts
Figure 1-1. Block Diagram
Random
Generator
Authentication,
Encryption and
Certification Unit
EEPROM
Answer to Reset
Data Transfer
Password
Verification
Reset Block
Asynchronous
ISO Interface
Synchronous
Interface
Power
Management
V
CC
GND
SCL/CLK
SDA/IO
RST
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2. Connecti on Di a gr am
Figure 2-1. Connection Diagram
2.7v - 5.5v
2.7v - 3.6v
SDA
SCL
Microprocessor CryptoMemory
3. Pin Des cription s
3.1 Supply Voltage (VCC)
The VCC input i s a 2.7V to 3.6V positiv e voltage supplied by the host.
3.2 Clock (SCL/CLK)
When using th e asynchronous T = 0 protocol, the CLK ( SCL) input provides the devic e with a carrier frequency f. The nominal
length of one bit emitted on I/O is defined as an “elem entary time unit” (ETU) and is equal to 372/ f.
When using th e synchronous prot ocol, data clocking is done on the positive edge of the clock when writing to the device and
on the negativ e edge of the clock when reading from the device.
3.3 Reset (RST)
The AT88SC0104CA provides an I SO 7816-3 compliant asynchronous Answer-To-Reset (ATR) sequence. Upon activat i on of
the reset sequence, the device outputs bytes c ontained in the 64-bit Answer-To-Reset register. An inter nal pull-up on the RS T
input pad allows the device to operate in synchronous mode without bonding RST. The AT88SC0104CA does not support an
Answer-To-Reset sequenc e in the synchronous mode of oper ation.
3.4 Serial Data (SDA/IO)
The SDA/I O pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of
other open-drain or open-collector devices. An external pull-up resistor should be c onnected between SDA/IO and V CC. The
value of this r es i s tor and the system capacitance loading the SDA/IO bus will determine t he rise time of SDA/IO. This rise time
will determine the maximum fr equency during read operations. Low value pull-up resistors will allow higher f r equency
operations while drawing h igher average p ower supply current. SDA/IO information applies to both asynchronous and
synchronous p rot ocols.
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4. *Absolute Maximum Ratings
Operating temperature .................... −40°C to +85°C
Storage temperature ................... −65°C to + 150°C
Voltage on any pin
with respect to ground ............... − 0.7 to VCC +0.7V
Maximum operating vo l tage ............................. 4.0V
DC output curr ent ......................................... 5.0mA
*
Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause perm anent damage to
the device. This is a stress rati ng only and funct i onal
operation of the device at these or any other condition
beyond those indicated in the operational sec tions of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of
time may affect device reliability.
Table 4-1. DC Characteristics
Applicable over recommended operating range from VCC = +2.7 to 3.6V, TAC = -40°C to +85°C (unless otherwise noted)
Symbol Parameter Test Conditions Min Typ Max Units
VCC(1) Suppl y Voltage 2.7 3.6 V
ICC Supply Current Async Read at 3.57MHz 5 mA
ICC Supply Current Async Write at 3.57MHz 5 mA
ICC Supply Current Synch Read at 1MHz 5 mA
ICC Supply Current Synch Write at 1MHz 5 mA
ISB Standby Current VIN = VCC or GND 100 µA
VIL SDA/IO Input Low Voltage 0 VCC x 0.2 V
VIL CLK Input Lo w Voltage 0 VCC x 0.2 V
VIL RST Input Low Voltage 0 VCC x 0.2 V
VIH(1) SDA/IO I nput High Voltage VCC x 0.7 5.5 V
VIH(1) SCL/CLK Input High Voltag e VCC x 0.7 5.5 V
VIH(1) RST Input Hig h Voltage VCC x 0.7 5.5 V
IIL SDA/IO Input Low Current 0 < V IL < VCC x 0.15 15 µA
IIL SCL/CLK Input Low Current 0 < VIL < VCC x 0.15 15 µA
IIL RST Input Low Curr ent 0 < VIL < VCC x 0.15 50 µA
IIH SDA/IO Input High Current VCC x 0.7 < VIH < VCC 20 µA
IIH SCL/CLK Input High Current VCC x 0.7 < VIH < VCC 100 µA
IIH RST Input High Cur rent VCC x 0.7 < VIH < VCC 150 µA
VOH SDA/IO Out put High Voltage 20K ohm external pull-up VCC x 0.7 VCC V
VOL SDA/IO Output Low Voltage IOL = 1mA 0 VCC x 0.15 V
IOH SDA/IO Out put High Current VOH 20 µA
IOL SDA/IO Output Low Current VOL 10 mA
Note: 1. To prevent latch up conditions f r om occurring during power up of the Atmel AT88SC0104CA, V CC must be turned
on before applying VIH. For powering do wn, VIH must be removed before turning VCC off
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Table 4-2. AC Chara cte ri sti cs
Applicable over recommended operating range from VCC = +2.7 to 3.6V, TAC = -40°C to +85°C, CL = 30pF
(unless otherwise noted)
Symbol Parameter Min Max Units
fCLK Async Clock Frequency 1 4 MHz
fCLK Synch Clock F requency 0 1 MHz
Clock Duty cycle 40 60 %
tR “Rise Time - SDA/IO, RST”
1 µS
tF “Fall Time - SDA/IO, RST”
1 µS
tR Rise Time - SCL/CLK
9% x period µS
tF Fall Time - SCL/CLK
9% x period µS
tAA Clock Low to Dat a Out Valid
250 nS
tHD.STA Start Hold Time 200
nS
tSU.STA St art Set-up Time 200
nS
tHD.DAT Data In Hold Time 10
nS
tSU.DAT Data In Set-up T im e 100
nS
tSU.STO S top Set-up Time 200
nS
tDH Data Out Hold Time 20
nS
tWR Write Cycle Time
5 mS
5. Device Operations for Synchronous Protocols
5.1 Clock and Data Transitions
The SDA pin is normally pulled high with an externa l device. Data on the SDA pin may change only during SCL low time
periods (see Figure 5-3 on page 8). Data changes during SCL high per iods will indicate a start or stop condition as defined
below.
5.1.1 Start Condition
A high-to-low transition of SDA with SCL high defines a start condition which must precede all commands (see Figure 5-4 on
page 8).
5.1.2 Stop Condition
A low-to-high transit ion of SDA with SCL high defines a stop condit i on. After a read sequence, the stop condition will place the
EEPROM in a standby power mode (s ee Figure 5-4 on page 8).
5.1.3 Acknowledge
All addresses and data words are serially transm itted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to
acknowledge that it has recei v ed each word. This happens during the ninth clock cycle (see Figure 5-5 on page 8).
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5.2 Memory Reset
After an interr uption in commu nication due protocol errors , power loss or any reason, perfor m "Acknowledge Polling" to
properly recover from the condi tion. Acknowledge polling co ns i s ts of sending a start condition foll owed by a valid
CryptoMemory command byte and determining if the device responded with an acknowledge.
Figure 5-1. Bus Time for Two-wire Serial Communications
SCL: Serial Clock, SDA: Seri al Data I/O
SCL
SDA IN
SDA OUT
t
F
t
HIGH
t
LOW
t
LOW
t
R
t
AA
t
DH
t
BUF
t
SU.STO
t
SU.DAT
t
HD.DAT
t
HD.STA
t
SU.STA
Figure 5-2. Write Cycle Timing
SCL: Serial Clock, SDA: Seri al Data I/O
t
wr
(1)
STOP
CONDITION
START
CONDITION
WORDn
ACK
8th BIT
S
CL
S
DA
Note: The write cycle time twr is the time from a valid stop condition of a writ e s equence to the end of the internal
clear/write cycle
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6. Device Archi t ect ur e
6.1 User Zones
The EEPROM user memory is divid ed i nto four zones of 256 bits each. Multiple zones allow for storage of different types of
data or files in different zones. Access to user z ones is permitted only after meeting proper securit y requirements. These
security req ui rements are user definable in the c onfiguration memory during device personalization. If the same security
requirements are selected for multiple zones, then these zones ma y effectively be accessed as one larger zone.
Figure 6-1. User Zones
Zone
$0
$1
$2
$3
$4
$5
$6
$7
User 0 $00
- 32 bytes
-
$18
User 1 $00
- 32 bytes
-
$18
User 2 $00
- 32 bytes
-
$18
User 3 $00
- 32 bytes
-
$18
7. Control Logic
Access to the us er zones occur onl y t hr ough the contr ol logic built into t he device. This logic is configurable thro ugh access
registers, key registers and k eys programmed into the configuration memory during device pers onalization. A l s o i m plemented
in the control logic is a cryptographic engine for performing the various higher-level security functions of the device.
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8. Configuration Memory
The configurat ion memory consis ts of 2048 bits of E EPROM memory used for storage of passwords, keys, codes, and also
used for definition of security access rights for the user zones. Access right s to the configuration memory are defi ned in the
control logic and are not alterable by the user after completion of personalization.
Figure 8-1. Configuration Memory
$0 $1 $2 $3 $4 $5 $6 $7
$00 Answer To Reset Identifitcation
$08 Fab Code MTZ Card Manufacturer Code
$10 Lot History Code Read Only
$18 DCR Identification Number N c
Access Control
$20 AR0 PR0 AR1 PR1 AR2 PR2 AR3 PR3
$28
Reserved $30
$38
$40 Issuer Code
$48
$50
For Authentication and Encryption use Cryptography
$58
$60
$68
$70
$78
$80
$88
$90
For Authentication and Encryption use Secret
$98
$A0
$A8
$B0 PAC W r i te 0 PAC Read 0
Password
$B8 PAC W r i te 1 PAC Read 1
$C0 PAC Write 2 PAC Read 2
$C8 PAC Write 3 PAC Read 3
$D0 PAC Write 4 PAC Read 4
$D8 PAC Write 5 PAC Read 5
$E0 PAC Wr ite 6 PAC Read 6
$E8 PAC W r i te 7 PAC Read 7
$F0 Reserved Forbidden
$F8
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8.2 Security Fuses
There are three fuses on the devic e that must be blown during the device per s onalization process. Each fuse locks certain
portions of t he configuration zone as OTP (One-Time Programmable) m emory. Fuses ar e des igned for the module
manufacturer , card manufactur er and card issuer and should be blown in sequence, although all programming of the device
and blowing of the fuses may be perfor med at one final st ep.
9. Communication Securi ty Mode s
Communications between the device and host operate in three basic modes. Standard mode is the default mode for the
device after power-up. Authentication mode is activated by a successful authentication sequ ence. Encryption m ode is
activated by a successful encryption activation following a successful authenticatio n.
Table 9-1. Communication Security Modes(1)
Mode
Configuration Data
User Data
Passwords
Data Integri t y Check
Standard Clear Clear Clear MDC(1)
Authentication Clear Clear Encrypted MAC(1)
Encryption Clear Encrypted Encrypted MAC(1)
Note: 1. Conf iguration dat a include viewable areas of the confi guration zone except the passwords:
MDC (Modification Detection C ode)
MAC (Message Authentication Code)
10. Security Options
10.1 Anti-Tearing
In the event of a power loss during a write cycle, the i ntegrity of the dev i c e’s stored data is recoverable. This function is
optional – the host may choose to activ ate the anti-tearing function, depending on app li cation requir ements. When anti-tearing
is active, write commands tak e l onger to execute, since more write cycles are required to complete t hem, and data is limited to
a maximum of eight bytes for each write request.
Data is written first into a buffer zone in EEPROM instead of the intended destination address, but with the same access
conditions. The data is then written in the requir ed location. If this second write cycle is interrupted due to a po wer los s, the
device will automatically recover the data fr om the system buffer zone at the next power-up. N on-v olatile bufferi ng of the data
is done automatically by the device.
During power-up in applications using anti-tearing, the host is requir ed to perform ACK polling in the event that the device
needs to carry out the data recovery process.
10.2 Write Lock
If a user zone is configured in the write lock mode, t he l owest address byte of an 8-byte page c onstitutes a write access b yte
for the bytes of that page.
Example: For example, the write lock byte at $080 controls the bytes from $081 to $087.
Figure 10-1. Write Lock Example
Address
$0
$1
$2
$3
$4
$5
$6
$7
$080 11011001 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
locked locked locked
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The Write-Lock byte itself may be locked by writ ing i ts least signi ficant (rightmost) bit to “0”. Moreover, whe n write lock mode is
activated, the write lock byte can only be program med – that is , bits written to “ 0” cannot return to “ 1”.
In the write lock configuration, write operations are limit ed to writing only one byte at a time. A ttempts to write more than one
byte will result in writing of j us t the first byte in to the device.
10.3 Password Verification
Passwords may be used to protect read and/or write access of any user zone. When a valid password is presented, it i s
memorized and active until power is turned off, unless a new password is present ed or RST becomes active. There are ei ght
password sets that may be used to protect any user zone. Only one password is active at a time.
Presenting the correct write password also grants read access privileges.
10.4 Authentication Protocol
The access t o a user z one may be protect ed by an authenti c ation protocol. Any one of four keys may be selected to use with a
user zone.
Authentication success is memorized and act i v e as long as the chip is powered, unless a new authentication is initialized or
RST becomes ac tive. If the new authenticatio n r equest is not val idated, the card loses its previous authentication which must
be presented again to gain ac c ess. Only the latest request is memor i z ed.
Figure 10-2. Password and Authentication Operations
Device (Card)
Card Number
VERIFY A
COMPUTE Challenge B
Challenge B
VERIFY RPW
DATA
Checksum (CS)
VERIFY WPW
VERIFY CS
Write DATA
Host (Reader)
COMPUTE Challenge A
Challenge A
VERIFY B
Read Password (RPW)
VERIFY CS
Write Password (WPW)
DATA
CS
AUTHENTICATION
READ ACCESS
WRITE ACCESS
Note: Authenticat i on and password verification may be attempted at any time and in any or der. Exceeding
corresponding authentication or password attempts tri al l imit renders s ubsequent authentication or password
verificati on attempts futile.
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10.5 Cryptographic Message Authentication Codes
AT88SC0104CA implements a data validity check function i n the standard, authentication or enc ryption modes of op eration.
In the standar d mode, data validity check is done t hrough a Modification Detection Code (MDC), in which the host may read
an MDC from the device in order to v erify that the data s ent was received c orrectly.
In authentication and encryption modes, the data v alidity ch eck becomes more powerful since it provides a bidirectional data
integrit y check and data origin authentication c apability in the form of a Message Authentication Codes (MAC). Only the
host/device that carried out a valid authentication is capa ble of computing a valid MAC. Whil e operating in the authentication
or encryption modes, the use of M AC is required. For an ingoing command, if the device calculates a MA C di fferent from the
MAC transmitted by the host, not only is the command abandoned but t he security privilege is revoked. A new authent ication
and/or encr yption activation will be required to reactivate the MAC.
10.6 Encryption
The data exchanged between the device and the host during read, write and verify password comman ds may be encrypted t o
ensure data confidentiality.
The issuer may choose to require enc ryption for a us er zone by settings made in the configuration memory. Any one of four
keys may be selected for use with a user zone. In t hi s case, activat ion of the encryption mode is required in order to read/ write
data in the zon e and only encr ypte d data will be transm i tted. Even if not required, the host may still elect to activate encryption
provided the proper keys are known.
10.7 Supervisor Mode
Enabling this feature allows the holder of one s pec i fic password to gain full access to all eight password sets, inc luding the
ability to change passwords.
10.8 Modify Forbidden
No write access is allowed in a us er zone protected with this feature at any time. The user zone must be written during devi ce
personalization prior to blowing the security fuses.
10.9 Program Only
For a user zones protected by this feature, data can only be programm ed (bits change fr om a “1” to a “0”), but not erased (bits
change from a “ 0” to a “1”).
11. Protocol Selection
The AT88SC0104CA supports two different communication protocols.
• Smartcard Applications:
Smartcard applications use ISO 7816-B protocol in asynchronous T = 0 mode for compatibility and interoperability
with industry standard smartcard readers.
• Embedded Applications:
A two-wire serial interface provides fast and efficient connectivity with other logic devices or microcontrollers.
The power-up s equence determines establishes the communicat ion protocol for us e within that power cycle. Protocol selection
is allowed only during power-up.
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11.1 Synchronous Two-wire Serial Interface
The synchronous mode is the default mode after power up. This is due to the presence of an int ernal pull-up on RST. For
embedded applications usi ng CryptoMemory in standard plastic packages, this is the only available communication protocol.
• Power-up VCC, RST goes high also
• After stable VCC, SCL(CLK) and SDA(I/O) may be driven
• Once synchronous mode has been selected, it is not possible to switch to asynchronous mode without first powering
off the device
Figure 11-1. Synchronous Two-wire Protocol
Vcc
I/O-S
DA
RST
CLK-SCL 1234 5
Note: Five clock pulses must be sent before the first command is issued
11.2 Asynchronous T = 0 Protocol
This power-up sequence complies to ISO 7816-3 for a c old reset in smar t card applicati ons.
• VCC goes high; RST, I/O (SDA) and CLK (SCL) are low
• Set I/O (SDA) in receive mode
• Provide a clock signal to CLK (SCL)
• RST goes high after 400 clock cycles
The device will respond with a 64-bi t ATR code, including hist orical bytes to indicate the memory density with in the
CryptoMemory family.
Once asynchronous mode has been selected, it i s not possible to switch to synchronous mode without first powering off the
device.
Figure 11-2. Asynchronous T = 0 Protocol (Gemplus Patent)
Vcc
I/O-SDA
RST
CLK-SCL
ATR
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12. Init ial Dev ice Programming
Enabling the security featur es of CryptoMe mory requires prior personalization. Perso nalization ent ails setting up of desired
access right s by zones, passwords and key values, programming these values into the configuration m em ory with verification
using simple write and read commands, and then blowing fuses to lock this infor m ation in place.
Gaining access to the configuration memory requ ires successful presentation of a s ecure (or transport) code. The initial
signature of t he secure (trans port) code for the AT88SC0104CA devic e i s $DD 42 97. This is the same as the write seven
password. The user may elect to change the signature of the secure code anytime after successful presentation.
After writin g and verifying data in the configuration memory, the security fuses must be blown to lock this information in t he
device. For additional inform ation on personalizing CryptoMemory, ple ase see the application notes Programming
CryptoMemor y for Embedded Applications and I ni tializing Cr yptoMemory for Smart C ard Applicat ions from the pr oduct page at
www.atmel.com/products/securemem.
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13. Orderi n g Inf or m ati on
Atmel Ordering Code
Package
Voltage Range
Temperature R ange
AT88SC0104CA-MJ
AT88SC0104CA-MP
AT88SC0104CA-MJTG
AT88SC0104CA-MPTG
M2 – J Module - ISO
M2 – P Module - ISO
M2 – J Module -TWI
M2 – P Module -TWI
2.7V–3.6V Commercial (0°C to 70°C)
AT88SC0104CA-PU
AT88SC0104CA-SH
AT88SC0104CA-TH
AT88SC0104CA-Y6H-T
8P3
8S1
8X
8MA2
2.7V–3.6V Green Compliant
(exceeds RoH S )/Industrial
(−40°C to 85°C)
AT88SC0104CA-WI 7 mil wafer 2.7V–3.6V Industrial (−40°C to 85°C)
Package Type
(1) ( 2)
M2 – J Module : ISO or TWI
M2 ISO 7816 Smart Card Module
M2 – P Module: ISO or TWI
M2 ISO 7816 Smart Card Module with Atmel® logo
8P3
8-lead, 0.300” wide, Plastic Dual Inline (PDIP)
8S1
8-lead, 0.150” wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 4.4mm body, Plastic Thin Shrink Small Out line ( TSSOP )
8MA2
8-lead, 2.0 x 3.0mm body, 0.50mm pitch, Ultra Thin Mini-map, Dual No Lead (DFN), (MLP 2x3)
Note: 1. F or mal drawings ma y be obtained from an Atmel sales office
2. Both the J and P module packages are used for either ISO (T=0 / two-wire mode) or TWI (two-wire mode only)
Atmel AT88SC0104CA [SUMMARY DATASHEET]
5200FS−CRYPTO−12/11
17
14. Pack age Information
Ordering Code: MJ or MJTG
Ordering Code: MP or MPTG
Module size: M2
Dimension*: 12.6 x 11.4 [mm]
Glob top: round – Æ 8.5 [mm]
Thickness: 0.58 [mm]
Pitch: 14.25 mm
Module size: M2
Dimension*: 12.6 x 11.4 [mm]
Glob top: square – 8.8 x 8.8 [mm]
Thickness: 0.58 [mm]
Pitch: 14.25 mm
Note: *The module dimensions listed refer to the dim ens ions of the exposed metal contact area. The actual dimensions
of the module after excise or punching from the car rier tape are gen erally 0.4mm greater in both direc tions (i.e. , a
punched M2 module will yield 13. 0 x 11.8mm).
Atmel AT88SC0104CA [SUMMARY DATASHEET]
5200FS−CRYPTO−12/11
18
14.1 Ordering Code: SH
8S1 – JEDEC SOIC
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV.TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 –0.25
A1.35 –1.75
b0.31 –0.51
C0.17 –0.25
D4.80 –5.05
E1 3.81 –3.99
E5.79 –6.20
e1.27 BSC
L0.40 –1.27
0° –8°
Ø
E
1
N
TOP VIEW
C
E1
END VIEW
A
b
L
A1
e
D
SIDE VIEW
8S1 G
6/22/11
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC) SWB
Atmel AT88SC0104CA [SUMMARY DATASHEET]
5200FS−CRYPTO−12/11
19
14.2 Ordering Code: PU
8P3 – PDIP
Pac kage D rawing Cont ac t:
packagedrawings@atmel.com
DRAWING NO. REV.TITLE
GPC
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
COMMON DI MENSI ONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
A0.210 2
A2 0.115 0.130 0.195
b0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c0.008 0.010 0.014
D0.355 0.365 0.400 3
D1 0.005 3
E0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e0.100 BSC
eA 0.300 BSC 4
L 0. 115 0.130 0.150 2
Top View
Side View
End View
8P3 D
06/21/11
8P3, 8-lead, 0.300” Wide Body, Plastic Dual
In-line Package (PDIP) PTC
Atmel AT88SC0104CA [SUMMARY DATASHEET]
5200FS−CRYPTO−12/11
20
14.3 Ordering Code: TH
8X – TSSOP
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV
.TITLE GPC
COMM ON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A - - 1.20
A1 0.05 -0.15
A2 0.80 1.00 1.05
D2.90 3.00 3.10 2, 5
E6.40 BSC
E1 4.30 4.40 4.50 3, 5
b0.19 –0.30 4
e0.65 BSC
L0.45 0.60 0.75
L1 1.00 REF
C0.09 -0.20
Side View
End View
Top View
A2
A
L
L1
D
1
E1
N
b
Pin 1 indicator
this c or ner
E
e
Notes: 1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8X D
6/22/11
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP) TNR
C
A1
Atmel AT88SC0104CA [SUMMARY DATASHEET]
5200FS−CRYPTO−12/11
21
14.4 Ordering Code: Y6H-T
8MA2 – Ultra Thin Mini-MAP
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com 8MA2YNZ B
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
COMM ON DIMENSIONS
(Unit of Measure = mm)
SYMBOLMIN NOM MAX NOTE
D2.00 BSC
E3.00 BSC
D2 1.40 1.50 1.60
E2 1.20 1.30 1.40
A 0.50 0.55 0.60
A1 0.0 0.02 0.05
A2 – – 0.55
C 0.152 REF
L0.30 0.35 0.40
e 0.50 BSC
b0.18 0.25 0.30 3
K0.20 – –
7/15/11
D2
E2
E
e (6x)
L (8x)
b (8x)
Pin#1 ID
A
A1
A2
Pin 1 ID
D
C
K
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
Atmel AT88SC0104CA [SUMMARY DATASHEET]
5200FS−CRYPTO−12/11
22
15. Revisi o n Hi stor y
Doc. Rev.
Date
Comments
5200FS 12/2011 Update template
Update package drawings and
- Replace 8A2 with 8X
- Replace 8T6 with 8MA2
Change AT88SC0104CA-SU to AT88SC0104CA-SH
5200ES 08/2009 Minor edit s and TWI module updates
5200DS 07/2009 Minor updat es to package drawing information and ordering inf ormation
5200CS 05/2009 Added Mini-M AP column to T abl e 1-1 and Mini-MAP pin-out dra wing
5200BS 02/2009 Connection diagram inserted; DC characteristics table updated
5200AS 07/2008 Initial doc um ent release
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