ANALOG DEVICES LCM0S yP-Compatible 14-Bit DAC AD7534 FEATURES All Grades 14-Bit Monotonic Over the Full Tempera- ture Range Full 4-Quadrant Multiplication Microprocessor-Compatible with Double Buffered Inputs Exceptionally Low Gsin Temperature Coefficient, O.5ppm/C typ Small 20-Pin DIP and Surface Mount Package Low Output Leakage (<20nA) Over the Full Temperature Range APPLICATIONS Microprocessor Based Control Systems Digital Audio Reconstruction High Precision Servo Control Control and Measurement in High Temperature Environments GENERAL DESCRIPTION The AD7534 is a 14-bit monolithic CMOS D/A converter which uses thin-film resistors and laser trimming to achieve excellent linearity. The device is configured to accept right-justified data in two bytes from an 8-bit data bus. Standard Chip Select and Memory Write logic is used to access the DAC. Address lines AO and Al control internal register loading and transfer. A novel low leakage configuration (patent pending) enables the AD753 to exhibit excellent output leakage current characteristics over the specified temperature range. The device is fully protected against CMOS latch up phenomena and does not require the use of external Schottky diodes or the use of a FET Input op amp. The AD7534 is manufactured using the Linear Compatible CMOS (LC2MOS) process. It is speed compatible with most microprocessors and accepts TTL or CMOS logic level inputs. REV. A Information furnished by Ansiog Devices is believed to be eccurete and reliable, However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of petents or other rights of third parties which may result from its use. No jicense is granted by implice- tion or otherwise under any petent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM Voo 19 AD7534 2 fs Vous G 14-BIT DAC 3) tour Evy 4) AGNOS se Jer 48) a1 MS 4s contro. PCS) A ee Cc 57) Wa ?) _ 66 $ ) De? 080 DGND Vs PRODUCT HIGHLIGHTS 1}. Guaranteed Montonicity The AD7534 is guarantccd monotonic to 14-bits over the full temperature range for all grades. 2. Low Output Leakage By tying Vss (Pin 20) to a negative voltage, it is possible to achieve a low output leakage current at high temperatures. 3, Microprocessor Compatibility High speed input control (TTL/SV CMOS campatible) allows direct interfacing to most of the popular 8-bit and 16-bit microprocessors. 4. Monolithic Construction For increased reliability and reduced package size - 0.3 20-pin DIP and 20-terminal surface mount package. One Technology Way; P. 0. Box 9106; Norwood, MA,02062-9106 Tel: 617/329-4700 TWX: 710/394-6577 West Coast Central Atlantic 714/641-9381 214/231-5094 218/643-7780AD7534SPECIFICATIONS: (2 tet usancot ts ae tan Parameter J, A Versions K, BVersions | S$ Version T Version Units Test Conditions/Commects ROCOURACY- Resolution 4 i 14 4 Bits Relative Accuracy 2 +) ze 21 LSB max All grades guaranteed monotonic Differential Nonlinesriry <1 +1 21 tl LSB max over temperature. Full Scale Error rt } 24 28 24 LSB max Measured using internal Ryp and includes effects of leakage current and gain T.C. Gain Temperature Coefficient? AGain/ATcmpereture es] 22.5 25 225 ppm/*C max Typical value is 0.SppmC Qutput Leakage Current lout (Pin 3) +25C +3 23 2S $s nA max All digital inputs 0V Trin 0 T mae +10 210 = 220 nA max Ves = - 00mV Fin 10 Tans 228 225 +150 2150 nA max Ves = OV REFERENCE INPUT Input Resistance, Pin! 3.5 3S 3.5 3.8 kQ min Typical Input Resistance = 6ki} 10 10 10 lo kfQinax DIGITAL INPUTS Viu (Input High Vokage) 24 2.4 2.4 2.4 Via Vy. (laput Low Voltage) 0.8 08 0.8 os V max Ten Cnput Current) +2sc zl tl zl 21 pA max Vy = OVorVap Tin tO Tax 210 . 10 210 rlo oA max Cr (Input Capacitance)? 7 ? ? 7 pF max POWER SUPPLY Vop Range L#15.75 VW.W1S.75 11,415.75 13.4/15.75 V min/V max Specifications guaranteed over Vss Range 200/ - 500 - 200/ - 500 ~ 200-500 - 20-500 | mV minmV max this range. lop 3 3 3 3 mA max All digital inputs Viz, oc Vir 500 300 5300 500 nA max All digital inpurs QV or Vop These characteristics are inchaied for Design Guidance only and are not sublect to test. (Vpgs = + 10V, Vous Vous = OV, Vs5 = 300mv, AC PERFORMANCE CHARACTERISTICS txtpt gir i A054 except where stat), Vpp + 1L.4to + 15.759 Parameter Tae 28C Ta Tair Tas Units Test Conditions Comments Output Current Settling Time 1.$ - ps max To0.003% of full scale range. lout lead = 1000), Cext = 13pF. DAC register alternately loaded with all I's and all 0's. Typical value of Sciuling Time is 0.8):5. Digital to Ansiog Glitch Impulse 100 - nV-cec typ Measured with Vege = OV. lout load = 100, Cext = 13pF. DAG register alternately loaded with all l'sand all 0's. Multiplying Feedthrough Error 3 5 mV p-ptyp Vase = + 10V, 10kHz sine wave DAC register loaded with all 0's. Power Supply Rejection. &GaivdVno 20.01 20.02 | % per % max AVpp = 25% Output Capacitance Cour (Pin 3) 200 260 pF max DAC register loaded with all L's Cour (Pin 3) 130 130 pF max DAC register loaded with all 0's Output Noise Voltage Density (10H2- 100kHz) 15 - av/VAz typ Measured between Rep and lout NOTES Temperarure range ss follows: J, K Versions: Oo + 70C A, BVersions: - 25C w + 88C $,T Versions: ~ $$Cto + 128C Specifications are querantend fora Vp of + 11.4V to + 15.759. AtVop * 5V, the device is fully functional with degraded specifications. Guaranteed by Product Assurance testing. . Feedthrough can be further reduced by ing the metal lid on th ic package to DGND. Specifications subject to change without notice.AD7534 TIMING CHARACTERISTICS cy = + 11.010 +1515, Yup= +109, Yous = Youu = @Y, Ye, = 300m) Limit at Limit at Ta=8to +70C Limit at Parameter Ta 225C Tas -25Cto + 85C Ta= ~S5Cto +125C} Unies Test Conditions/Comments ty 0 0 0 os min Address Valid to Write Sciup Time ta 0 0 0 ns min Address Valid to Write Hold Time y 140 160 180 as min Data Setup Time & 20 20 30 asmin Data Hold Time ts 0 6 0 ns min Chip Select to Write Setup Time & 0 0 0 ns min Chip Select to Write Hold Time uv 170 200 240 as min Write Pulse Width NOTES Temperature range as follows: J, K Versions: Oto + 70C A,B Versions: -25T to +35C $,T Versions: ~ 55C to + 125C Specifications subject to change without notice. ABSOLUTE MAXIMUMRATINGS . (Ta = 25C unless otherwise stated) Operating Temperature Range Vpn Pin 19)to DGOND.. 1... 2-207. ~0.3V, +17V Commercial (J, K Versions) .......... Oro +70C Ves (Pin 20)t0 AGND ............. -15V, +0.3V Industrial (A, B Versions) ........ -25C w +85C Vagr (Pin 1) to AGND 2.2. ee ee +25V Extended (S, T Versions). ........- -55C to +125C Vara (Pin 2)to AGND ..........--200-6- +2SV Storage Temperature .. 2. ......-. - 65C to + 150C Digiral Input Voltage (Pins 7-18)10 DGND .. -0.3V, Vnp Lead Temperature (Soldering, lfsecs) 2.2.2... + 300C Vems toDGND.............2085 0.3V, Vop * . . eons AGNDtoDGND........-....... ~0.3V, Von Steteet above those listed under Absolute Nisin panes Dacconal wo, permanent damage to the device. This is a stress rating only and functional Power Dissipation (Any Package) operation of the device st these or any other conditions above those To +78. ee ee ee 450mW indicated in the operational scctions of this specification is not implied. Derates above +75 2. ee es 6mW/C Exposure to absolute maximum rating conditions for extended periods may CAUTION affect device reliability. ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are inserted. WARNING! ORDERING GUIDE Temperature Relative | FuliScale | Package Modei Range Accuracy | Error Option* AD7534JN j OCto + 70C +2LSB | +8LSB N-20 AD7534KN | 0Cto + 70 +1LSB | +4LSB N-20 AD7534JP_ | 0Cto + 70C +2LSB | +8LSB P-20A AD7534KP | 0Cto +70C + LSB +4LSB P-20A AD7534AQ | '-25Cw+85C | +2LSB | +8LSB Q-20 AD7534BQ | -28C10 +85C | +1LSB | +4LSB Q-20 AD7534SQ | ~5SCto +125C} +2LSB | +8LSB Q-20 AD7534TQ | -SSCto + 125C} + 1LSB | +4LSB Q-20 *N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip.AD7534 TERMINOLOGY RELATIVE ACCURACY Relative accuracy or endpoint nonlinearity is a measure of the meximum deviation from a straight line pessing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full scale crror and is normally expressed in Least Significant Bits or as a percentage of full scale reading. DIFFERENTIAL NONLINEARITY Differential noalincarity is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. A specified differential nonlinearity of + 1LSB max over the operating temperature range ensures monotonicity. FULL-SCALE ERROR Full scale error or gain error is a measure of the output error between an ideal DAC and the actual device output. Full scale error is adjustable to zero with an external potentiometer. DIGITAL TO ANALOG GLITCH IMPULSE : The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage. The measurement takes place with Var = AGND. OUTPUT CAPACITANCE Capacitance from Ioyr to AGND. OUTPUT LEAKAGE CURRENT Current which appears at Iour with the DAC register loaded to all 0's. MULTIPLYING FEEDTHROUGH ERROR AC error due to capacitive feedthrough from Vper terminal to Iour with DAC register loaded to all zeros. PIN CONFIGURATIONS DIP PLCC \S Ver {1 1] [20] Vea fe 1 2 481 Veo four | 3 | @& aanos [4 17] WR acnos | 4] agnor [5 AD7634s [18] 0 AGNOF [6 | TOP VIEW OGNO [6 | ponp [s] (notte scale! [15] at pee pe? [2] pay | ? oes fs) ons fe 13) pes ves [3 iz) os Oa4 110 1] DBZPin Function Description AD7534 19 20 Vpp Vss Descript Reference Input Voltage Feedback resistor. Used to close the loop around an external op-amp. Current Output Terminal Analog ground sense line. Reference point for external circuitry. This pin should carry minimal current. Analog ground force line; carries current from internal analog ground connections. Agnprand Agnps are tied together internally. Digital Ground Date Bit 7 Data Bit 6 Data Bit 5 or Data Bit 13 (DAC MSB) Data Bit 4 or Data Bit 12 Data Bit 3 or Data Bit 11 Data Bit 2 or Data Bit 10 Data Bit 1 or Data Bit 9 Data BitOor Data Bit 8 Address line } Address line 0 Write input. Active low. Chip Select Input. Active low. WE CS Al Ag! Function X' t XX = X | Devicenotselected Nodata transfer DAC loaded directly from Data Bus MS Input Register loaded from Data Bus LS Input Register loaded from Data Bus eo] co} of] of = oO] of of oo] mE t Oo] oO] be ~L ol | ol 5 DAC Register loaded from Input Registers. NOTES 1. X= Dont Care 2. When A, =0, A, ~0 all DAC registers are transparent, 90 by placing all 0's or ail 1's on the dats inputs the user can load the DAC to zero or full scale output in one write operation. This fecility simplifies system calibration. +12V to + 1$V supply input. Bias pin for High Temperature Low Leakage configuration. To implement low leakage system, the pin should beats negative voltage. See Figures 4, 5 or 6 for recommended circuitry. poe oo ws ZZZILIK XLLLL | ts | & 5V ven CLK MLL ov. t . jat-t TN 5V cs ov ty 5V wa ov NOTES 4, ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. t=t;=20ns. Va + Va 2. TIMING MEASUREMENT REFERENCE LEVEL IS - Figure 1. AD7534 Timing DiagramAD7534 Figure 2, Simplified Circuit Diagram for the AD7534 D/A Section CIRCUIT INFORMATION - D/A SECTION Figure 2 shows a simplified circuit diagram for the AD7534 D/A section. The three MSBs of the 14-bit Dats Word are decoded to drive the seven switches A-G. The 11 LSBs of the Data Word drive an inverted R-2R ladder which steers the binarily weighted current available to it between lout and AGNDF. If I is taken as the input current st Vazr the input current to the R-2R ladder is 1/8. 7/8 I flows in the parallel ladder structure. Switches A-G steer binarily weighted current between lour and AGNDPF. The input resistance at Vazr is constant and may be driven by voltage source or a current source of positive or negative polarity. EQUIVALENT CIRCUIT ANALYSIS Figure 3 shows an equivalent circuit for the analog section of the AD7534 D/A converter. The current source ILEAKAGE iS composed of surface and junction leakages. The resistor Ro denotes the equivalent output resistance of the DAC which varies with input code. Cour is the capacitance due to the current steering switches and varies from about 90pF to 180pF (typical values) depending upon the digital input. g(Vpzr, N) is the Thevenin equivalent voltage generator due to the reference we lour o{Vaner. N) AGNDS AGNDF Figure 3, AD7534 Equivalent Analog Output Circuit input voltage, Vazr, and the transfer function of the R-2R ladder, N. CIRCUIT INFORMATION - DIGITAL SECTION The digital inputs are designed to be both TTL and SV CMOS compatible. All logic inputs are static protected MOS gates with typical input currents of less than InA. Internal input protection is achieved by an on-chip distributed diode from DGND to cach MOS gate. To minimize power supply currents, it is recommended that the digital input voltages be driven as close as possible to 0 and 5V logic levels.Applying the AD7534 UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) Figure 4 shows the circuit diagram for unipolar binary operation. With an ac input, the circuit performs 2-quadrant multiplication. The code table for Figure 4 is given in Table I. Capacitor Cl provides phase compensation and helps prevent overshoot and ringing when high speed op-amps are used. toon Vow 330 Vax 1 2 c1 Veer Voo Res aap Mo fie) a0 aram~(is) ar tour (3 - AD75M at - B-09 & acuos (4 + @ v, om WH nn? D50 DGND Vq_, AGnOF(S 7) (~< tz q Te a sat | + , ootal nS ANALOG aeur GROUND 38 OaATA - gro be $ yO 15 Figure 4. Unipolar Binary Operation Binary Number Ia DAC Register Analog Outpat, Vour MSB LSB WoW Wn Wn ~Von( ieee) 8192 10 0000 0000 0000 ~Vin\7e3e4) =~ /2 Vin 00 0000 6000 0001 -Von(se34a) 00 0000 0000 0000 ov Table i. Unipolar Binary Code Table for AD7534 ZERO OFFSET AND GAIN ADJUSTMENT FOR FIGURE 4. Calibration codes for zero and full scale adjust (all 0's, all 1s) can be loaded in one write operation (sce Pin Function Description). Zero Offeet Adjustment 1. Loed DAC register with all 0's. 2. Adjust offset of amplifier Al so that Vo is at a minimum {i.e., S30). Gain Adjustment 1. Load DAC register with ali 1s. " (16383 2, Trim potentiometer R3 so that Vo= -V 16383) In fixed reference applications full scale can also be adjusted by omitting R3 and R4 and trimming the reference voltage magnitude. For high temperature applications, resistors and potentiometers should have a low Temperature Coefficient. In many applications, because of the excellent Gain T.C. and Gain Error specifications of the AD7$34, Gain Error trimming is not necessary. BIPOLAR OPERATION (4QUADRANT MULTIPLICATION) - The recommended circuit diagram for bipolar operation is shown in Figure 5. Offset binary coding is used. With the DAC loaded to 10 0000 0000 0000, adjust R3 for Vo = OV. Alternatively, one can omit R3 and R4 and adjust the ratio of R7 and R8 for Vo = OV. Full scale trimming can be accomplished by adjusting the amplitude of Vin or by varying the value of R9. Resistors R7, R8 and R9 should be matched to 0.003%. Mismatch of R7 and R& causes both offset and full scale error. When operating over a wide temperature range, it is important that the resistors be of the same type so that their temperature coefficient match. The code table for Figure 5 is given in Table II. ao m =f 5 th 1 19 2 a ns Cd a Yr (Nee = aman as at apna tur G PN fa | 5 a awe (4 + aa wm ner ome ncn Van Motor a.m s te a ? i = . tr . Laan = 180 Figure . Bipolar Operation Binary Number in DAC Register Analog Output MSB LSB WoW nM Wl +Vx #33 10 0000 0000 0001 +Vmn(gis) 10 0000 0000 9000 0 O1 1011 111) 1111 -Vn iss) 00 0000 0000 0000 - Von $95) Table li. Bipolar Code Table for Offset Binary Circuit of Figure 5.AD7534 GROUNDING TECHNIQUES Since the AD7534 is specified for high accuracy, it is important to use a grounding technique. The two AGND pins (AGNDF and AGNDS) provide flexibility in this respect. In Figure 4, AGNDS and AGNDF are externally shorted and A2 js not used. Voltage drops due to bond wire resistances are not compensated for in this circuit. This means that an extra lincarity error of less than 0.11.SB is added to the DAC linearity error. If the user wishes to eliminate this extra crror, then the circuit of Figure 6 should be used. Here, A2 is used to maintain AGNDS at Signal Ground potential. By using the Force, Sense technique ail switch contacts on the DAC are at exactly the same potential and any error due to bond wire resistance is eliminated. Figure 7 shows a Printed Circuit Board layout for the AD7534 with a single output amplifier. The input to Vazr (pin 1) is shielded to reduce ac feedthrough while the digital inputs are shiclded to minimize digital feedthrough. he tracks connecting Tour and AGNDS to the inverting and noninverting op amp inputs are kept as short as possible. Gain trim componcats, R3 and R4, have been omitted. NOTE CONTROL INPUTS OMITTED FOR CLARITY Figure 6. Unipolar Binary Operation with Forced Ground V+ V- LAYOUT IS FOR DOUBLE SIDED PCB. OOTTED LINE INDICATES TRACK ON COMPONENT SIDE. Figure 7. Suggested Layout for AD7534 Incorporating Output Amplifier ZERO OFFSET AND GAIN ADJUSTMENT FOR FIGURE 6 Zero Offset Adjustment 1, Loed DAC register with all 0's. 2. Adjust offset of amplifier A2 for minimum potential at AGNDS. This potential should be <30uV with respect to Signal Ground. . 3. Adjust offset of amplifier Al 90 that Vo is at 2 minimum (i.e. $30,V). on Gain Adj Soom 1. Load DAC register with all 1s. 16383 2. Trim potentiometer R3 so that Vo= ~ Vy 1683)AD7534 LOW LEAKAGE CONFIGURATION For CMOS Multiplying D/A converters, as the device is operated at higher temperatures the output leakage current increases. For a 14-hir resolution system, this can be a significant source of ertor. The AD7534 features a leakage reduction configuration to keep the leakage current low over an extended temperature range. One may operate the device with or without this config- uration, If Vss (pin 20) is tied to AGND then the DAC wil! exhibit normal output leakage current at high temperatures. To use the low leakage facility, Vss should be ticd to a voltage of approximately 0.3V as in Figures 4, 5 and 6. A simple resistor divider (RS, R6) produces - 312mV from - 15V. The capacitor C2 in parallei with R6 is an integral part of the low leakage configuration and must be 4.7F or greater. Figure 8 is a plot of leakage current versus temperature for both conditions. It clearly shows the improvement gained by using the low leakage configuration. OP AMP SELECTION In choosing an amplifier to be used with the AD7534, three parameters are of prime importance. These are Input Offset Voltage (Vos), Input Bias Current, (Isias) and Offset Voltage Drift. To maintain specified accuracy with Vang at 10V, Vos must be jess than 30n.V while Ipsas should be less than 2nA. Also the open loop gain of the amplifier must be sufficiendy high to keep Vos=30pV for the full output voltage range. Thus for 2 max output of 10V, Avo1, must be greater than 340,000. An amplifier with low offsct voltage drift is required to give the desired system accuracy over an operating temperature range. At low frequencies the AD OP-07 satisfies the above requirements and in most cases will not need an offset adjust potentiometer. For high frequency operation, one may use a wide bandwidth amplifier such as the ADS44 or the [F356 with either an offset adjust potentiometer or sutomatic nulling circuitry. The choice of amplifier depends entirely on the required system accuracy, the required temperature range, and the operating frequency. Voo= + 15 Vee # + 10V IT e 8 8 & 8 LEAKAGE CURRENT - nA = e aA 300-40 50 O70 0 90 100 110 120 130 TEMPERATURE - C Figure 8. Graph of Typical Leakage Current vs. Temperature for AD734AD7534 MICROPROCESSOR INTERFACING ADT7534 ~ 8085A INTERFACE A typical interface circuit for dre AD7534 and the 8085A micro- processor is given in Figure 9. The microprocessor sees the DAC es four memory locations, identified by address lines AO, Al. In standard operation, three of these memory locations are used. A sample program for loading the DAC with a 14-bit word is given in Table HI. The AD7534 has address locations 3000-3003. The six MSBs are written into location 3001, and the cight LSBs are written to 3002. Then with a write instruction to 3003 As- AIG ADDRESS BUS 4 S08SA Al AO ADDRESS us ALE} LATCH DECODE AD7534 Wi Wk ADO - AD? DATA BUS p60 ~ 087 UNEAR CIRCUITRY OMITTED FOR CLARITY Figure 9. 407534 - 8085A Interface the full 14-bit word is loaded to the DAC register and the analog equivalent appears at the output. AD7534 ~ 8086 INTERFACE The AD7534 may be interfaced to the 16-bit $086 microprocessor using the circuit of Figure 10. The bottom 8 bits (ADO-AD7) of the 16-bit data bus are connected to the DAC data bus. The 14-bit word is loaded in two bytes using the MOV instruction. A further MOV loads the DAC register and causes the analog data to appear st the converter output. For the example given here, the appropriate DAC register addresses are D002, DOO, D006. The program for loading the DAC is given below in Table IV. ADDRESS BUS 5 a | sent | | aopress ay Ao ALE) vatcH DECODE - a . 08s >< 7834 Wa Wa ADO-AD1S DATA BUS DB0-087 LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 10. AD7534 - 8086 Interface Circuit Address | Op-Code | Mnemonic 2000 | 26 MVIH,# 30 01 | 30 02 | 2E MVIL,# 01 03 | Ol 04 | 3E MVIA,# MS 05 MS 06 | 77 MOVM,A 07 | 2c INRL 08 | 3E MVIA,# LS 1) LS OA | 77 MOVM,A OB | 2C INRL oc | 77 MOVM,A 200D | CF RSTI Table Ill, Program Listing for Figure 9 ASSUME DS: DACLOAD, CS : DACLOAD DACLOAD SEGMENT AT 000 00 | 8CC9 MOVCX,CS : DEFINE DATASEGMENT REGISTER EQUAL 02 | 8ED9 MOV DS, CX : TOCODE SEGMENT REGISTER 04 | BFOZDO MOV DI, # D002 : LOAD DI WITH D002 07 | C60SMS MOV MEM, # MS : MSINPUT REGISTER LOADED WITH MS OA | 47 INCDI OB | 47 INCDI . OC | C60SLS MOV MEM, # LS : LSINPUTREGISTER LOADED WITH LS OF | 47 INCDI 10 | 47 INCDI 11 | 60500 MOV MEM, #00 : CONTENTS OF INPUT REGISTERS ARE LOADED TO THE DACREGISTER. 14 | EA0000 JMP MEM : CONTROLIS RETURNED TO THE MONITOR 17 | OOFF PROGRAM Table [V. Sample Program for Loading AD7534 from 8086AD7534 AD?7534 - MC6809 INTERFACE Figure 11 shows an interface circuit which enables the AD7534 to be programmed using the MC6809 8-bit microprocessor. By making use of the 16-bit D Accumulator, the transfer of data is simplified. The two key processor instructions are: LDD Load D Accumulator from memory. STD Store D Accumulator to memory. AD- AIS ADDRESS BUS aw AO AI ADDAESS a DECODE a e AD7534* mcencs wR N 00-07 OATA BUS. 000-087 WJ. V *LINEAR CIRCUITRY OMITTED POR CLARITY Figure 11. AD7534 - MC6809 Interface Circuit AD7534 - 6502 INTERFACE The interface circuit for the 6502 microprocessor is shown in Figure 12. aG- AS ADDRESS BUS 2b < ne ADORESS a. al e502 = ap7s34* ws] Pea __N 00-07 DATA BUS. DBO-D6? LJ OY *UINEAR CIRCUITRY OMITTED FOR CLARITY Figure 12. AD7534 - 6502 interface AD7534 - 780 INTERFACE Interfacing to the Z80 microprocessor requires a minima! amount of extra components. The circuit consists of the Z80 processor, the AD7534 and an address decoder for the DAC. Figure 13, below, illustrates the circuit. A0- AS ADDRESS BUS 5 200 2b 23 & OAT NREG ADDRESS DECODE AD7534 wa wa N p0-07 DATA BUS pse-087 LS y *LINEAR CIRCLUTRY OMITTED FOR CLARITY Figure 13. AD7534 - 280 interfaceAD7534 AD7S34 MC69000 INTERFACE Interfacing between the MC68000 and the AD7534 is accomplished using the circuit of Figure 14. The following routine writes data to the DAC input registers and then outputs the data via the DAC register. *A2 003 MOVE.W Address Register 2 is loaded with E003. The desired DAC dats, W, is loaded into Deca Register 0. W may be any value between 0 and 16383 (decimal) or 0 and 3F FF (hexadecimal). The date W is transferred between DO and the Input Registers of the DAC. The high ordet byte of data is trans- ferred first. The memory sdkdiress is specified using the address register in- 01000 *,Do MOVEP.W D0,$0000(A2) (8003) is add and 20 data ie transferred on the low order half of the data bus (DO-D7). This : id . signals to transfer the daca W from the DAC Input Registers to the DAC Regis- ter, which controls the switches in the 14-bit D/A structure. Conteot ia recurned to the System Monitor MOVE.W D0,$5006 MOVE.B @ 228,D7 TRAP #16 Since only the lower half of the Data Bus is used in this interfacing system, it is also suitable for use with the MC68008. This provides ' the user with an eight bit data bus instead of the MC68000s sixteen bit data bus. DIGITAL FEEDTHROUGH In the preceeding interface configurations, most digital inputs to the AD7534 are directly connected to the microprocessor bus. Even when the device is not selected, these inputs will be constantly changing. The high frequency logic activity on the bus can feed through the DAC peckage capacitance to show up 83 noise on the saalog output. To minimize this digital feedthrough isolate the DAC from the noise source. Figure 15 shows an interface circuit which physically isolstes the DAC from the bus. One may also use other means, such as peripheral interface deviccs, to reduce the digital feedthrough. at-aa ADORESS GUS al E Me AL a Secor a AD7S34 OTR 0 | oe ite be-97 DATA BUS 4 "UNEAA CIRCUITRY OMITTED POR CLARITY Figure 14. AD7534 - MC68000 Interface *UNEAR CIRCUITRY OMITTED POR CLARITY Figure 15, AD7534 Interfece Circuit Using Latches to Minimize Digital Feedthrough MECHANICAL INFORMATION OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-PIN CERAMIC DIP (SUFFIX D) 20-PIN PLASTIC DIP (SUFFIX N) ery Hi T J i al lee