12-Bit, 2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter AD9625 Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DRGND AGND REFERENCE DIGITAL INTERFACE AND CONTROL VCM VIN+ VIN- ADC CORE DDC fS/8 OR fS/16 SERDOUT[0] SERDOUT[1] SERDOUT[2] SERDOUT[3] SERDOUT[4] SERDOUT[5] SERDOUT[6] SERDOUT[7] RBIAS CONTROL REGISTERS SYSREF CLK CLOCK MANAGEMENT AD9625 CMOS DIGITAL INPUT/OUTPUT SDIO SCLK CMOS DIGITAL INPUT/ OUTPUT LVDS DIGITAL INPUT/ OUTPUT FD RSTB IRQ SYNCINB DIVCLK 11814-001 12-bit 2.5 GSPS ADC, no missing codes SFDR = 77 dBc, AIN up to 1 GHz at -1 dBFS, 2.5 GSPS SFDR = 77 dBc, AIN up to 1.8 GHz at -1 dBFS, 2.5 GSPS SNR = 57.6 dBFS, AIN up to 1 GHz at -1 dBFS, 2.5 GSPS SNR = 57 dBFS, AIN up to 1.8 GHz at -1 dBFS, 2.5 GSPS Noise spectral density = -149.5 dBFS/Hz at 2.5 GSPS Differential analog input: 1.2 V p-p Differential clock input 3.2 GHz analog input bandwidth, full power High speed 6- or 8-lane JESD204B serial output at 2.5 GSPS Subclass 1: 6.25 Gbps at 2.5 GSPS Two independent decimate by 8 or decimate by 16 filters with 10-bit NCOs Supply voltages: 1.3 V, 2.5 V Serial port control Flexible digital output modes Built-in selectable digital test patterns Timestamp feature Conversion error rate < 10-15 JESD204B INTERFACE FEATURES CSB Figure 1. APPLICATIONS Spectrum analyzers Military communications Radar High performance digital storage oscilloscopes Active jamming/antijamming Electronic surveillance and countermeasures GENERAL DESCRIPTION The AD9625 is a 12-bit monolithic sampling analog-to-digital converter (ADC) that operates at conversion rates of up to 2.5 giga samples per second (GSPS). This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and electronic countermeasures. The analog input, clock, and SYSREF signals are differential inputs. The JESD204B-based high speed serialized output is Rev. A configurable in a variety of one-, two-, four-, six-, or eight-lane configurations. The product is specified over the industrial temperature range of -40C to +85C, measured at the case. PRODUCT HIGHLIGHTS 1. 2. 3. High performance: exceptional SFDR in high sample rate applications, direct RF sampling, and on-chip reference. Flexible digital data output formats based on the JESD204B specification. Control path SPI interface port that supports various product features and functions, such as data formatting, gain, and offset calibration values. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9625 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Low Bandwidth Decimator ....................................................... 30 Applications ....................................................................................... 1 Digital Outputs ............................................................................... 31 Functional Block Diagram .............................................................. 1 Introduction to THE JESD204B Interface .............................. 31 General Description ......................................................................... 1 Functional Overview ................................................................. 31 Product Highlights ........................................................................... 1 JESD204B Link Establishment ................................................. 33 Revision History ............................................................................... 3 Physical Layer Output................................................................ 37 Specifications..................................................................................... 4 Scrambler ..................................................................................... 37 DC Specifications ......................................................................... 4 Tail Bits ........................................................................................ 37 AC Specifications.......................................................................... 5 DDC Modes (Single and Dual) ................................................ 37 Digital Specifications ................................................................... 6 CheckSum ................................................................................... 38 Switching Specifications .............................................................. 7 8-Bit/10-Bit Encoder Control ................................................... 38 Timing Specifications .................................................................. 7 Initial Lane Alignment Sequence (ILAS) ................................ 38 Absolute Maximum Ratings ....................................................... 9 Lane Synchronization ................................................................ 38 Thermal Characteristics .............................................................. 9 JESD204B Application Layers .................................................. 42 ESD Caution .................................................................................. 9 Frame Alignment Character Insertion .................................... 45 Pin Configuration and Function Descriptions ........................... 10 Thermal Considerations............................................................ 45 Typical Performance Characteristics ........................................... 16 Power Supply Considerations ................................................... 45 Equivalent Test Circuits ................................................................. 23 Serial Port Interface (SPI) .............................................................. 46 Theory of Operation ...................................................................... 24 Configuration Using the SPI ..................................................... 46 ADC Architecture ...................................................................... 24 Hardware Interface..................................................................... 46 Fast Detect ................................................................................... 24 Memory Map .................................................................................. 47 Gain Threshold Operation ........................................................ 24 Reading the Memory Map Register ......................................... 47 Test Modes ................................................................................... 25 Memory Map Registers ............................................................. 47 Analog Input Considerations ........................................................ 26 Applications Information .............................................................. 65 Differential Input Configurations ............................................ 26 Design Guidelines ...................................................................... 65 DC Coupling ............................................................................... 27 Power and Ground Recommendations ................................... 65 Clock Input Considerations ...................................................... 27 Clock Stability Considerations ................................................. 65 Digital Downconverters (DDC) ................................................... 28 SPI Port ........................................................................................ 65 Frequency Synthesizer and Mixer ............................................ 28 Outline Dimensions ....................................................................... 66 Numerically Controlled Oscillator........................................... 28 Ordering Guide .......................................................................... 66 High Bandwidth Decimator ...................................................... 28 Rev. A | Page 2 of 66 Data Sheet AD9625 REVISION HISTORY 9/14--Rev. 0 to Rev. A Added AD9625-2.5 (Throughout) .................................................. 1 Changes to Features and General Description Sections .............. 1 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 5 Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 7 Changes to Figure 3 and Figure 4 ................................................... 8 Changes to Table 6 ............................................................................ 9 Changes to Pin K4; Figure 5, Table 8, and Table 9 ......................10 Added Typical Performance Characteristics Summary and Changes to Typical Performance Characteristics .......................16 Changes to Figure 45, Figure 49, and Figure 50; Added Figure 51 to Figure 54 .....................................................................23 Changes to Gain Threshold Operation Section ..........................24 Changes to Analog Input Considerations Section ......................26 Changes to Digital Downconverters (DDC) Section .................28 Added Figure 68 ..............................................................................32 Changes to Data Streaming Section; Added Link Setup Parameters Section ..........................................................................33 Changes to Digital Outputs, Timing, and Controls Section and Table 15 .............................................................................................34 Changes to Table 16 and Table 17 .................................................35 Added Table 18 ................................................................................36 Added Multichip Synchronization Using SYSREF Timestamp, 6 Lane Output Mode, and SYSREF Setup and Hold IRQ Sections .............................................................................................39 Added IRQ Guardband Delays (SYSREF Setup and Hold) Section .............................................................................................. 40 Added Using Rising/Falling Edges of CLK to Latch SYSREF Section .............................................................................................. 41 Changes to Configuration Using the SPI Section ....................... 46 Changes to Transfer Register Map Section, Table 26, and Table 27 ............................................................................................. 47 Changes to Table28, Table 29, and Table 30 ................................ 48 Changes to Table 33 and Table 34 ................................................. 49 Changes to Table 53 ........................................................................ 52 Changes to Table 54 ........................................................................ 52 Changes to Table 58 ........................................................................ 54 Changes to Table 71 ........................................................................ 56 Changes to Table 79 and Table 80 ................................................. 57 Changes to Table 81, Table 82, Table 83, Table 84, Table 85, and Table 86 ............................................................................................. 58 Changes to Table 89 ........................................................................ 59 Changes to Table 92 and Table 93 ................................................. 60 Changes to Table 94, Table 97, and Table 98 ............................... 61 Changes to Table 101 and Table 106 ............................................. 62 Added Table 107 and Table 108..................................................... 63 Added Table 115 and Table 116..................................................... 64 Added Applications Information Section .................................... 65 Changes to Ordering Guide ........................................................... 66 5/14--Revision 0: Initial Version Rev. A | Page 3 of 66 AD9625 Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal reference, AIN = -1.0 dBFS, default SPI settings, dc-coupled output data, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) ANALOG INPUTS Differential Input Voltage Range Resistance Capacitance Internal Common-Mode Voltage (VCM) Analog Full-Power Bandwidth (See Figure 59 and Figure 60 for networks) Input Referred Noise POWER SUPPLIES AVDD1 AVDD2 DRVDD1 DRVDD2 DVDD1 DVDD2 DVDDIO SPI_VDDIO IAVDD1 IAVDD2 IDRVDD1 IDRVDD2 IDVDD1 IDVDD2 IDVDDIO ISPI_VDDIO Power Dissipation Power-Down Dissipation 1 Test Conditions/ Comments Temperature1 Full Full Full Full Full Internal VREF = 1.2 V Internal termination 8 lane mode Full 25C 25C Full Min 12 -7 -8 -0.7 -3.6 492 AD9625-2.0 Typ Guaranteed 0.5 0.3 0.9 1.1 100 1.5 525 Max Min 12 +6.4 +8 +0.7 +3.6 -7 -9 -0.5 -2.1 563 492 AD9625-2.5 Typ Guaranteed 0.5 0.3 1.0 1.2 100 1.5 525 Max Unit Bits +6.4 +5 +0.7 +2.1 LSB %FSR LSB LSB 563 V p-p pF mV 25C 3.2 3.2 GHz 25C 3 4 LSBRMS Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 1.26 2.4 1.26 2.4 1.26 2.4 2.4 2.4 Full temperature range is -40C to +85C measured at the case (TC). Rev. A | Page 4 of 66 1.3 2.5 1.3 2.5 1.3 2.5 2.5 2.5 1120 383 456 9 410 <1 <1 <1 3.48 125 1.32 2.6 1.32 2.6 1.32 2.6 2.6 2.6 1222 460 470 10 430 3.8 3.8 1.26 2.4 1.26 2.4 1.26 2.4 2.4 2.4 1.3 2.5 1.3 2.5 1.3 2.5 2.5 2.5 1250 427 460 9 425 <1 <1 <1 3.90 125 1.32 2.6 1.32 2.6 1.32 2.6 2.6 2.6 1351 491 473 10 509 4.2 V V V V V V V V mA mA mA mA mA mA mA mA W mW Data Sheet AD9625 AC SPECIFICATIONS AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling, 1.2 V internal reference, AIN = -1.0 dBFS, sample clock input = 1.65 V p-p differential, default SPI settings, unless otherwise noted. Table 2. Parameter SPEED GRADE ANALOG INPUT NOISE DENSITY SIGNAL-TO-NOISE RATIO (SNR) fIN = 100 MHz fIN = 500 MHz fIN = 1000 MHz fIN = 1800 MHz Test Conditions/Comments Full scale Temperature Min AD9625-2.0 Typ Max 2.0 Min AD9625-2.5 Typ Max 2.5 Full 25C 1.1 -149.0 1.2 -149.5 Unit GSPS V p-p dBFS/Hz 25C 25C 25C Full 55.4 59.5 59.4 59.0 58.2 54.1 58.3 58.0 57.6 57.0 dBFS dBFS dBFS dBFS 54.1 58.4 58.4 58.0 57.2 53.1 57.2 57.0 56.5 55.9 dBc dBc dBc dBc SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 100 MHz fIN = 500 MHz fIN = 1000 MHz fIN = 1800 MHz 25C 25C 25C Full EFFECTIVE NUMBER OF BITS (ENOB) fIN = 100 MHz fIN = 500 MHz fIN = 1000 MHz fIN = 1800 MHz 25C 25C 25C 25C 9.4 9.4 9.3 9.2 9.2 9.2 9.1 9.0 Bits Bits Bits Bits 25C 25C 25C Full 80 81 80 76 77 76 79 77 dBc dBc dBc dBc -77 -76 -82 -78 dBc dBc dBc dBc SPURIOUS FREE DYNAMIC RANGE (SFDR) fIN = 100 MHz fIN = 500 MHz fIN = 1000 MHz fIN = 1800 MHz WORST OTHER SPUR Including 2nd or 3rd harmonic fIN = 100 MHz fIN = 500 MHz fIN = 1000 MHz fIN = 1800 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fIN1 = 728.5 MHz, fIN2 = 731.5 MHz fIN1 = 1805.5 MHz, fIN2 = 1808.5 MHz 67 70 Excluding 2nd or 3rd harmonic 25C 25C 25C Full -80 -86 -83 -85 25C -82.8 -81.2 dBc 25C -77.6 -76.3 dBc -73 -70 At -7 dBFS per tone Rev. A | Page 5 of 66 AD9625 Data Sheet DIGITAL SPECIFICATIONS AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal reference, AIN = -1.0 dBFS, default SPI settings, unless otherwise noted. Table 3. Parameter CLOCK INPUTS (CLK+, CLK-) Differential Input Voltage Common-Mode Input Voltage Input Resistance (Differential) Input Capacitance SYSREF INPUTS (SYSREF+, SYSREF-) Differential Input Voltage Common-Mode Input Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (SDIO, SCLK, CSB) Logic Compliance Voltage Logic 1 Logic 0 Input Resistance Input Capacitance SYNCB+/SYNCB- INPUT Logic Compliance Input Voltage Differential Common Mode Input Resistance (Differential) Input Capacitance LOGIC OUTPUT (SDIO) Logic Compliance Voltage Logic 1 (IOH = 800 A) Logic 0 (IOL = 50 A) DIGITAL OUTPUTS (SERDOUT[x]) Compliance Output Voltage Differential Offset Differential Return Loss (RLDIFF)1 Common-Mode Return Loss (RLCM) Differential Termination Impedance RESET (RSTB) Voltage Logic 1 Logic 0 Input Resistance (Differential) Input Capacitance FAST DETECT (FD), PWDN AND INTERRUPT (IRQ) Logic Compliance Voltage Logic 1 Logic 0 Input Resistance (Differential) Input Capacitance 1 Temperature Min Full Full Full Full 500 Full Full Full Full 500 Typ Max Unit 1800 mV p-p V k pF 1800 mV p-p V k pF 0.88 40 1.5 0.88 40 1.5 CMOS Full Full Full Full 0.8 x SPI_DVDDIO 0.5 30 0.5 Full Full Full Full Full V V k pF LVDS 250 1200 1.2 100 2.5 mV p-p V pF CMOS Full Full 0.8 x SPI_VDDIO 0.3 Full CML Full Full 25C 25C 25C Full Full Full Full 360 700 DRVDD/2 V V 800 8 6 100 0.8 x DVDDIO 0.5 20 2.5 mV p-p mV p-p dB dB V V k pF CMOS Full Full Full Full 0.8 x DVDDIO 0.5 20 2.5 Differential and common-mode return loss measured from 100 MHz to 0.75 x baud rate. Rev. A | Page 6 of 66 V V k pF Data Sheet AD9625 SWITCHING SPECIFICATIONS AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal reference, AIN = -1.0 dBFS, default SPI settings, unless otherwise noted. Table 4. Parameter CLOCK (CLK) Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High Clock Pulse Width Low SYSREF (SYSREF)2 Setup Time (tSU_SR) Hold Time (tH_SR) FAST DETECT OUTPUT (FD) Latency OUTPUT PARAMETERS (SERDOUT[x]) Rise Time Fall Time Pipeline Latency SYNCB Falling Edge to First K.28 Characters CGS Phase K.28 Characters Duration Differential Termination Resistance APERTURE Delay Uncertainty (Jitter) Out-of-Range Recovery Time 1 2 Test Conditions/ Comments 8 lane mode Temperature Min Full Full Full Full 3301 50 5 50 5 Typ Max Unit 2500 MSPS MSPS % duty cycle % duty cycle 25C 25C +200 -100 ps ps Full 82 Clock cycles 25C 25C 25C 25C 25C 25C 70 70 226 100 ps ps Clock cycles Multiframes Multiframes 200 80 2 ps fS rms Clock cycles 4 1 Full Full Full Must use a two-lane, generic output lane configuration for minimum sample rate. For more information, see the lane table in the JESD204B specification document. SYSREF setup and hold times are defined with respect to the rising SYSREF edge and rising clock edge. Positive setup time leads the clock edge. Negative hold time also leads the clock edge. TIMING SPECIFICATIONS Table 5. Parameter SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Test Conditions/Comments Min Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 2 40 2 2 10 10 10 ns ns ns ns ns ns ns ns 10 ns Rev. A | Page 7 of 66 Typ Max Unit AD9625 Data Sheet Timing Diagrams CLK- CLK+ tSU_SR 11814-202 tH_SR SYSREF- SYSREF+ Figure 2. SYSREF Setup and Hold Timing tDS tS tHIGH tCLK tDH tH tLOW CSB SDIO DON'T CARE DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON'T CARE 11814-203 SCLK DON'T CARE Figure 3. Serial Port Interface Timing Diagram (MSB First) SAMPLE N N - 226 ANALOG INPUT SIGNAL N - 225 N+1 N - 224 N-1 CLK- CLK+ CLK- CLK+ SERDOUT0 SAMPLE N - 226 ENCODED INTO 2 8-BIT/10-BIT SYMBOL SAMPLE N - 225 ENCODED INTO 2 8-BIT/10-BIT SYMBOL Figure 4. Data Output Timing for 8 Lane Mode Rev. A | Page 8 of 66 SAMPLE N - 224 ENCODED INTO 2 8-BIT/10-BIT SYMBOL 11814-204 SERDOUT7 Data Sheet AD9625 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD1to AGND AVDD2 to AGND DRVDD1 to DRGND DRVDD2 to DRGND DVDD1 to DGND DVDD2 to DGND DVDDIO to DGND SPI_VDDIO to DGND AGND to DRGND VIN to AGND VCM to AGND VMON to AGND CLK to AGND SYSREF to AGND SYNCINB to DRGND SCLK to DRGND SDIO to DRGND IRQ to DRGND RSTB to DRGND CSB to DRGND FD to DRGND DIVCLK to DRGND SERDOUT[x] to DRGND Environmental Storage Temperature Range Operating Case Temperature Range Maximum Junction Temperature Rating -0.3 V to +1.32 V -0.3 V to +2.75 V -0.3 V to +1.32 V -0.3 V to +2.75 V -0.3 V to +1.32 V -0.3 V to +2.75 V -0.3 V to +3.63 V -0.3 V to +3.63 V -0.3 V to +0.3 V -0.3 V to AVDD1+ 0.2 V -0.3 V to AVDD1+ 0.2 V -0.3 V to AVDD1+ 0.2 V -0.3 V to AVDD1+ 0.2 V -0.3 V to AVDD1+ 0.2 V -0.3 V to DRVDD2 + 0.2 V -0.3 V to SPI_VDDIO + 0.2 V -0.3 V to SPI_VDDIO + 0.2 V -0.3 V to DVDDIO + 0.2 V -0.3 V to DVDDIO + 0.2 V -0.3 V to SPI_VDDIO + 0.2 V -0.3 V to DVDDIO + 0.2 V -0.3 V to DRVDD2 + 0.2 V -0.3 V to DRVDD1 + 0.2 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL CHARACTERISTICS The following characteristics are for a 4-layer and 10-layer printed circuit board (PCB). Table 7. Thermal Resistance PCB 4-Layer 10-Layer 1 TA (C) 85.0 85.0 JA (C/W) 18.7 11.5 N/A means not applicable. ESD CAUTION -60C to +150C -40C to +85C (measured at case) 110C Rev. A | Page 9 of 66 JT (C/W) 0.61 0.61 JB (C/W) 6.1 4.1 JC (C/W) 1.4 N/A1 AD9625 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9625 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A AGND AGND AGND AVDD1 AGND AVDD2 VCM AGND VIN+ VIN- AGND VM_BYP AVDD2 AVDD2 B AGND AGND AGND AGND AVDD1 AGND AVDD2 AGND AGND AGND AGND AVDD2 AGND AGND C AGND AGND AGND AGND AGND AVDD1 AGND AVDD2 AGND AGND AVDD2 AGND AGND AVDD1 D DVDD1 DVDD1 DVDD1 DNC AGND AGND AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AVDD1 AVDD1 E DGND DGND DGND DVDD2 VMON AGND AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AGND AGND F DVDD1 DVDD1 DVDD1 SPI_VDDIO DVDDIO AGND AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AGND CLK+ G DGND DGND DGND CSB DVDDIO AGND AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AGND CLK- H DVDD1 DVDD1 DVDD1 SCLK IRQ AGND AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AGND AGND J DGND DGND DGND SDIO FD RBIAS_EXT AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AGND SYSREF+ K DVDD1 DVDD1 RSTB PWDN AGND AGND AGND AGND AGND AGND AGND AGND AGND SYSREF- L DGND DNC DGND DGND DGND DGND DGND DNC DNC DNC AGND AGND M DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRVDD1 REXT DRGND DRGND N DRVDD1 SERDOUT [7]+ SERDOUT [6]+ SERDOUT [5]+ SERDOUT [4]+ DRVDD1 SERDOUT [3]+ SERDOUT [2]+ SERDOUT [1]+ SERDOUT [0]+ DRVDD1 VP_BYP DRVDD2 DRVDD2 P DRVDD1 SERDOUT [7]- SERDOUT [6]- SERDOUT [5]- SERDOUT [4]- DRVDD1 SERDOUT [3]- SERDOUT [2]- SERDOUT [1]- SERDOUT [0]- DRVDD1 DRGND DIVCLK- DIVCLK+ AVDD2 AVDD1 DVDD2 DVDD1 DRVDD2 DRVDD1 DVDDIO SPI_VD DIO AGND DGND DRGND DNC OR BYPASS WITH CAP SYNCINB- SYNCINB+ NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. LEAVE THIS PIN FLOATING. Figure 5. Pin Configuration Rev. A | Page 10 of 66 11814-009 TOP VIEW (Not to Scale) Data Sheet AD9625 Table 8. Pin Function Descriptions (By Pin Number) Pin No. A1 to A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 to B4 B5 B6 B7 B8 to B11 B12 B13, B14 C1 to C5 C6 C7 C8 C9, C10 C11 C12, C13 C14 D1 to D3 D4 D5, D6 D7 D8 D9, D10 D11 D12 to D14 E1 to E3 E4 E5 E6 E7 E8 E9, E10 E11 E12 E13, E14 F1 to F3 F4 F5 F6 F7 F8 F9, F10 Mnemonic AGND AVDD1 AGND AVDD2 VCM AGND VIN+ VIN- AGND VM_BYP AVDD2 AVDD2 AGND AVDD1 AGND AVDD2 AGND AVDD2 AGND AGND AVDD1 AGND AVDD2 AGND AVDD2 AGND AVDD1 DVDD1 DNC AGND AVDD1 AVDD2 AGND AVDD2 AVDD1 DGND DVDD2 VMON AGND AVDD1 AVDD2 AGND AVDD2 AVDD1 AGND DVDD1 SPI_VDDIO DVDDIO AGND AVDD1 AVDD2 AGND Type Ground Power Ground Power Output Ground Input Input Ground Input Power Power Ground Power Ground Power Ground Power Ground Ground Power Ground Power Ground Power Ground Power Power N/A Ground Power Power Ground Power Power Ground Power Output Ground Power Power Ground Power Power Ground Power Power Power Ground Power Power Ground Description ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (1.30 V). ADC Analog Ground. This pin connects to the analog ground plane. ADC Analog Power Supply (2.50 V). Analog Input, Common Mode (0.525 V). ADC Analog Ground. This pin connects to the analog ground plane. Differential Analog Input, True. Differential Analog Input, Complement. ADC Analog Ground. This pin connects to the analog ground plane. Voltage Bypass. ADC Analog Power Supply (2.50 V). ADC Analog Power Supply (2.50 V). ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (1.30 V). ADC Analog Ground. This pin connects to the analog ground plane. ADC Analog Power Supply (2.50 V). ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (2.50 V). ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (1.30 V). ADC Analog Ground. This pin connects to the analog ground plane. ADC Analog Power Supply (2.50 V). ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (2.50 V). ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (1.30 V). ADC Digital Power Supply (1.30 V). Do Not Connect. Do not connect to this pin. Leave this pin floating. ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (1.30 V). ADC Analog Power Supply (2.50 V). ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (2.50 V). ADC Analog Power Supply (1.30 V). Digital Control Ground Supply. These pins connect to the digital ground plane. ADC Digital Power Supply (2.5 V). CTAT Voltage Monitor Output. ADC Analog Ground. This pin connects to the analog ground plane. ADC Analog Power Supply (1.30 V). ADC Analog Power Supply (2.50 V). ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (2.50 V). ADC Analog Power Supply (1.30 V). ADC Analog Ground. These pins connect to the analog ground plane. ADC Digital Power Supply (1.30 V). SPI Digital Power Supply (2.50 V). Digital I/O Power Supply (2.50 V). ADC Analog Ground. This pin connects to the analog ground plane. ADC Analog Power Supply (1.30 V). ADC Analog Power Supply (2.50 V). ADC Analog Ground. These pins connect to the analog ground plane. Rev. A | Page 11 of 66 AD9625 Pin No. F11 F12 F13 F14 G1 to G3 G4 G5 G6 G7 G8 G9, G10 G11 G12 G13 G14 H1 to H3 H4 H5 H6 H7 H8 H9, H10 H11 H12 H13, H14 J1 to J3 J4 J5 J6 J7 J8 J9, J10 J11 J12 J13 J14 K1 to K2 K3 K4 K5 to K13 K14 L1 L2 L3 L4 L5 to L9 L10 to L12 L13, L14 M1 to M10 M11 M12 M13, M14 Data Sheet Mnemonic AVDD2 AVDD1 AGND CLK+ DGND CSB DVDDIO AGND AVDD1 AVDD2 AGND AVDD2 AVDD1 AGND CLK- DVDD1 SCLK IRQ AGND AVDD1 AVDD2 AGND AVDD2 AVDD1 AGND DGND SDIO FD RBIAS_EXT AVDD1 AVDD2 AGND AVDD2 AVDD1 AGND SYSREF+ DVDD1 RSTB PWDN AGND SYSREF- DGND DNC SYNCINB- SYNCINB+ DGND DNC AGND DRGND DRVDD1 REXT DRGND Type Power Power Ground Input Ground Input Power Ground Power Power Ground Power Power Ground Input Power Input Output Ground Power Power Ground Power Power Ground Ground I/O Output Input Power Power Ground Power Power Ground Input Power Input Input Ground Input Ground N/A Input Input Ground N/A Ground Ground Power Input Ground Description ADC Analog Power Supply (2.50 V). ADC Analog Power Supply (1.30 V). ADC Analog Ground. This pin connects to the analog ground plane. ADC Clock Input, True. Digital Control Ground Supply. These pins connect to the digital ground plane. SPI Chip Select CMOS Input. Active low. Digital I/O Power Supply (2.50 V). ADC Analog Ground. This pin connects to the analog ground plane. ADC Analog Power Supply (1.30 V). ADC Analog Power Supply (2.50 V). ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (2.50 V). ADC Analog Power Supply (1.30 V). ADC Analog Ground. This pin connects to the analog ground plane. ADC Clock Input, Complement. ADC Digital Power Supply (1.30 V). SPI Serial Clock CMOS Input. Interrupt Request Output Signal. ADC Analog Ground. This pin connects to the analog ground plane. ADC Analog Power Supply (1.30 V). ADC Analog Power Supply (2.50 V). ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (2.50 V). ADC Analog Power Supply (1.30 V). ADC Analog Ground. These pins connect to the analog ground plane. Digital Control Ground Supply. These pins connect to the digital ground plane. SPI Serial Data CMOS Input/Output; Scan Output 1. Fast Detect Output. This pin requires an external 10 k resistor connected to ground. Reference Bias. This pin requires an external 10 k resistor connected to ground. ADC Analog Power Supply (1.30 V). ADC Analog Power Supply (2.50 V). ADC Analog Ground. These pins connect to the analog ground plane. ADC Analog Power Supply (2.50 V). ADC Analog Power Supply (1.30 V). ADC Analog Ground. This pin connects to the analog ground plane. System Reference Chip Synchronization, True. ADC Digital Power Supply (1.30 V). Chip Digital Reset, Active Low. Power-down. ADC Analog Ground. These pins connect to the analog ground plane. System Reference Chip Synchronization, Complement. Digital Control Ground Supply. This pin connects to the digital ground plane. Do Not Connect. Do not connect to this pin. Leave this pin floating. Synchronization, Complement. Synchronization, True. SYNCINB LVDS input (active low, true). Digital Control Ground Supply. These pins connect to the digital ground plane. Do Not Connect. Do not connect to these pins. Leave these pins floating. ADC Analog Ground. These pins connect to the analog ground plane. Digital Driver Ground Supply. These pins connect to the digital driver ground plane. Power Supply (1.3 V) Reference Clock Divider, VCO, and Synthesizer. External Resistor, 10 k to Ground. Digital Driver Ground Supply. This pin connects to the digital driver ground plane. Rev. A | Page 12 of 66 Data Sheet Pin No. N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13, N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Mnemonic DRVDD1 SERDOUT[7]+ SERDOUT[6]+ SERDOUT[5]+ SERDOUT[4]+ DRVDD1 SERDOUT[3]+ SERDOUT[2]+ SERDOUT[1]+ SERDOUT[0]+ DRVDD1 VP_BYP DRVDD2 DRVDD1 SERDOUT[7]- SERDOUT[6]- SERDOUT[5]- SERDOUT[4]- DRVDD1 SERDOUT[3]- SERDOUT[2]- SERDOUT[1]- SERDOUT[0]- DRVDD1 DRGND DIVCLK- DIVCLK+ AD9625 Type Power Output Output Output Output Power Output Output Output Output Power Input Power Power Output Output Output Output Power Output Output Output Output Power Ground Output Output Description Serial Digital Power Supply (1.3 V). Lane 7 CML Output Data, True. Lane 6 CML Output Data, True. Lane 5 CML Output Data, True. Lane 4 CML Output Data, True. Serial Digital Power Supply (1.3 V). Lane 3 CML Output Data, True. Lane 2 CML Output Data, True. Lane 1 CML Output Data, True. Lane 0 CML Output Data, True. Serial Digital Power Supply (1.3 V). Voltage Bypass. Power Supply (2.5 V) Reference Clock Divider for SYNCINB, DIVCLK. Serial Digital Power Supply (1.3 V). Lane 7 CML Output Data, Complement. Lane 6 CML Output Data, Complement. Lane 5 CML Output Data, Complement. Lane 4 CML Output Data, Complement. Serializer Digital Power Supply (1.30 V). Lane 3 CML Output Data, Complement. Lane 2 CML Output Data, Complement. Lane 1 CML Output Data, Complement. Lane 0 CML Output Data, Complement. Serializer Digital Power Supply (1.30 V). Digital Driver Ground Supply. This pin connects to the digital driver ground plane. Divide-by-4 Reference Clock LVDS, Complement. Divide-by-4 Reference Clock LVDS, True. Table 9. Pin Function Descriptions (By Function)1 Pin No. General Power and Ground Supply Pins A1 to A3, A5, A8, A11, B1 to B4, B6, B8 to B11, B13, B14, C1 to C5, C7, C9, C10, C12, C13, D5, D6, D9, D10, E6, E9, E10, E13, E14, F6, F9, F10, F13, G6, G9, G10, G13, H6, H9, H10, H13, H14, J9, J10, J13, K5 to K13, L13, L14 J6 Clock Pins F14 G14 ADC Analog Power and Ground Supplies Pins A6, A13, A14, B7, B12, C8, C11, D8, D11, E8, E11, F8, F11, G8, G11, H8, H11, J8, J11 A4, B5, C6, C14, D7, D12 to D14, E7, E12, F7, F12, G7, G12, H7, H12, J7, J12 A12 A1 to A3, A5, A8, A11, B1 to B4, B6, B8 to B11, B13, B14, C1 to C5, C7, C9, C10, C12, C13,D5, D6, D9, D10, E6, E9, E10, E13, E14, F6, F9, F10, F13, G6, G9, G10, G13, H6, H9, H10, H13, H14, J9, J10, J13, K5 to K13, L13, L14 Mnemonic Type Description AGND Ground ADC Analog Ground. These pins connect to the analog ground plane. RBIAS_EXT Input Reference Bias. This pin requires an external 10 k resistor connected to ground. CLK+ CLK- Input Input ADC Clock Input, True. ADC Clock Input, Complement. AVDD2 Power ADC Analog Power Supply (2.50 V). AVDD1 Power ADC Analog Power Supply (1.30 V). VM_BYP AGND Input Ground Voltage Bypass. ADC Analog Ground. These pins connect to the analog ground plane. Rev. A | Page 13 of 66 AD9625 Pin No. ADC Analog Input and Outputs Pins A9 A10 A7 E5 JESD204B High Speed Power and Ground Pins N1, N6, N11, P1, P6, P11 M1 to M10, M13, M14, P12 Data Sheet Mnemonic Type Description VIN+ VIN- VCM VMON Input Input Output Output Differential Analog Input, True. Differential Analog Input, Complement. Analog Input, Common Mode (0.525 V). CTAT Voltage Monitor Output (Diode Temperature Sensor). DRVDD1 DRGND Power Ground N13, N14 DRVDD2 Power M11 DRVDD1 Power N12 L2 JESD204B High Speed Serial I/O Pins J14 K14 L4 L3 VP_BYP DNC Input N/A Serial Digital Power Supply (1.3 V). Digital Driver Ground Supply. These pins connect to the digital driver ground plane. Power Supply (2.5 V) Reference Clock Divider, SYNCINB, DIVCLK. Power Supply (1.3 V) Reference Clock Divider, VCO, and Synthesizer. Voltage Bypass. Do Not Connect. Do not connect to this pin. SYSREF+ SYSREF- SYNCINB+ SYNCINB- Input Input Input Input N10 P10 N9 P9 N8 P8 N7 P7 N5 P5 N4 P4 N3 P3 N2 P2 P14 P13 Digital Supply and Ground Pins D1 to D3, F1 to F3, H1 to H3, K1 to K2 F5, G5 F4 E4 E1 to E3, G1 to G3, J1 to J3, L1, L5 to L9 SERDOUT[0]+ SERDOUT[0]- SERDOUT[1]+ SERDOUT[1]- SERDOUT[2]+ SERDOUT[2]- SERDOUT[3]+ SERDOUT[3]- SERDOUT[4]+ SERDOUT[4]- SERDOUT[5]+ SERDOUT[5]- SERDOUT[6]+ SERDOUT[6]- SERDOUT[7]+ SERDOUT[7]- DIVCLK+ DIVCLK- Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output DVDD1 DVDDIO SPI_VDDIO DVDD2 DGND Power Power Power Power Ground DNC N/A RSTB PWDN REXT CSB SCLK Input Input Input Input Input D4 Digital Control Pins K3 K4 M12 G4 H4 Rev. A | Page 14 of 66 System Reference Chip Synchronization, True. System Reference Chip Synchronization, Complement. Synchronization, True. SYNCINB LVDS input (active low, true). Synchronization, Complement. SYNCINB LVDS input (active low, complement). Lane 0 CML Output Data, True. Lane 0 CML Output Data, Complement. Lane 1 CML Output Data, True. Lane 1 CML Output Data, Complement. Lane 2 CML Output Data, True. Lane 2 CML Output Data, Complement. Lane 3 CML Output Data, True. Lane 3 CML Output Data, Complement. Lane 4 CML Output Data, True. Lane 4 CML Output Data, Complement. Lane 5 CML Output Data, True. Lane 5 CML Output Data, Complement. Lane 6 CML Output Data, True. Lane 6 CML Output Data, Complement. Lane 7 CML Output Data, True. Lane 7 CML Output Data, Complement. Divide-by-4 Reference Clock LVDS, True. Divide-by-4 Reference Clock LVDS, Complement. ADC Digital Power Supply (1.3 V). Digital I/O Power Supply (2.5 V). SPI Digital Power Supply (2.5 V). ADC Digital Power Supply (2.5 V). Digital Control Ground Supply. These pins connect to the digital ground plane. Do Not Connect. Do not connect to this pin. Leave this pin floating. Chip Digital Reset, Active Low. Power-down for the AD9625. External Resistor, 10 k to Ground. SPI Chip Select CMOS Input. Active low. SPI Serial Clock CMOS Input. Data Sheet Pin No. J4 J5 H5 L10 to L12 1 AD9625 Mnemonic SDIO FD Type I/O Output IRQ DNC Output N/A Description SPI Serial Data CMOS Input/Output. Fast Detect Output. This pin requires an external 10 k resistor connected to ground. Interrupt Request Output Signal. Do Not Connect. Do not connect to these pins. Leave these pins floating. Note that when pins are relevant to multiple categories, they are repeated in Table 9. Pins may not appear in alphanumeric order within Table 9. Rev. A | Page 15 of 66 AD9625 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS For the -2.5 model, full-scale range used is 1.2 V. For the -2.0 model, the full-scale range used is 1.1 V. 0 0 2500MSPS 1816.7MHz AT -1.0dBFS SNR = 57.1dBFS SFDR = 80.35dBc -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -40 -60 -80 0 250 500 750 1000 1250 FREQUENCY (MHz) -120 11814-306 -120 0 750 1000 1250 Figure 9. FFT Plot at 2.5 GSPS, fIN = 115 MHz at AIN (SFDR = 78.4 dBc, SNR = 58.1 dBFS) 0 0 2500MSPS 730.3MHz AT -1.0dBFS SNR = 57.8dBFS SFDR = 77.1dBc 2500MSPS 2990.11MHz AT -1.0dBFS SNR = 55.3dBFS SFDR = 70.6dBc -20 AMPLITUDE (dBFS) -20 -40 -60 -80 -100 -40 -60 -80 -100 0 250 500 750 1000 1250 FREQUENCY (MHz) -120 11814-307 -120 Figure 7. FFT Plot at 2.5 GSPS, fIN = 730.3 MHz at AIN (SFDR = 77.8 dBc, SNR = 57.8 dBFS) 0 250 500 750 1000 1250 FREQUENCY (MHz) 11814-310 AMPLITUDE (dBFS) 500 FREQUENCY (MHz) Figure 6. FFT Plot at 2.5 GSPS, fIN = 1816.7 MHz at AIN (SFDR = 80.4 dBc, SNR = 57.1 dBFS) Figure 10. FFT Plot at 2.5 GSPS, fIN = 2990.1 MHz at AIN (SFDR = 70.6 dBc, SNR = 55.3 dBFS) (Input Network in Figure 59 Used) -140 0 NOISE SPECTRAL DENSITY (dBFS/Hz) 2000MSPS 3010MHz AT -1.0dBFS SNR = 56.2dBFS SFDR = 73.1dBc -20 -40 -60 -80 -100 -120 0 200 400 600 800 1000 FREQUENCY (MHz) Figure 8. FFT Plot at 2.0 GSPS, fIN = 3010 MHz at AIN (SFDR = 73 dBc, SNR = 56 dBFS) (Input Network in Figure 60 Used) -142 -144 -146 -148 -150 11814-308 AMPLITUDE (dBFS) 250 11814-309 -100 0 1000 2000 3000 4000 INPUT FREQUENCY (MHz) 5000 6000 11814-311 AMPLITUDE (dBFS) -20 2500MSPS 115.05MHz AT -1.0dBFS SNR = 58.1dBFS SFDR = 78.4dBc Figure 11. NSD vs. Ain at 2.5GSPS (Input Network in Figure 60 Used <2 GHz, Input Network in Figure 59 Used >2 GHz) Rev. A | Page 16 of 66 Data Sheet AD9625 0 100 2000MSPS 1807.3MHz AT -1dBFS SNR = 58.12dBFS SFDR = 75.5dBc -20 90 SFDR (dBFS) 70 -40 SNR/SFDR (dB) AMPLITUDE (dBFS) 80 -60 -80 SNR (dBFS) 60 50 SFDR (dBc) 40 30 SNR (dB) -100 20 200 400 600 800 1000 FREQUENCY (MHz) 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 AMPLITUDE (dB) Figure 12. FFT Plot at 2.0 GSPS, fIN = 1807.3 MHz at AIN (SFDR = 75.5 dBc, SNR = 58.1 dBFS) Figure 15. SNR/SFDR vs. Analog Input Amplitude at 2 GSPS, fIN = 241.1 MHz at AIN 0 100 2000MSPS 730.3MHz AT -1dBFS SNR = 59.19dBFS -20 SFDR = 80.9dBc 90 80 SFDR (dBFS) 70 -40 SNR/SFDR (dB) AMPLITUDE (dBFS) 11814-108 0 11814-104 10 -120 -60 -80 SNR (dBFS) 60 50 SFDR (dBc) 40 30 SNR (dB) 20 -100 200 400 600 800 1000 FREQUENCY (MHz) 0 -90 SFDR (dB) 20 -120 Figure 14. FFT Plot at 2.0 GSPS, fIN = 310.3 MHz at AIN (SFDR = 82.2 dBc, SNR = 59.6 dBFS) 1000 0 -90 11814-106 AMPLITUDE (dBFS) -100 FREQUENCY (MHz) -10 0 SFDR (dBFS) SFDR (dBc) 40 800 -20 60 -80 600 -30 IMD3 (dBFS) -60 400 -40 100 80 200 -50 120 -40 0 -60 Figure 16. SNR/SFDR vs. Analog Input Amplitude at 2 GSPS, fIN = 1811.3 MHz at AIN 2000MSPS 310.3MHz AT -1dBFS SNR = 59.6dBFS SFDR = 82.2dBc -20 -70 AMPLITUDE (dB) Figure 13. FFT Plot at 2.0 GSPS, fIN = 730.3 MHz at AIN (SFDR = 80.9 dBc, SNR = 59.2 dBFS) 0 -80 -80 -70 -60 -50 -40 -30 AMPLITUDE (dBFS) -20 -10 0 11814-112 0 11814-105 -120 11814-109 10 Figure 17. Two Tone SFDR and IMD3 vs. Analog Input Amplitude at 2.0 GSPS at 1800 MHz AIN Rev. A | Page 17 of 66 AD9625 Data Sheet 100 120 IMD3 (dBFS) 90 100 70 80 SFDR (dBFS) SNR (dBFS) SNR/SFDR (dB) SFDR (dB) SFDR (dBFS) 80 60 SFDR (dBc) 40 60 50 SFDR (dBc) 40 30 SNR (dB) 20 20 -70 -60 -50 -40 -30 -20 -10 0 AMPLITUDE (dBFS) 0 -90 -70 -60 1200 -20 -10 4L MODE 8L MODE 4.0 1000 CURRENT (mA) 3.5 3.0 2.5 2.0 0 4.5 2L MODE 1100 4.0 IAVDD1 900 TOTAL POWER 3.5 800 700 IDRVDD1 600 IAVDD2 3.0 500 400 300 1.0 2.5 200 0.5 IDVDD1 100 N-2 N N+2 N+4 MORE BINS 0 300 11814-114 N-4 Figure 19. Input Referred Noise Histogram with 2.0 GHz Sample Clock 500 700 IDVDD2 , IDRVDD2 2.0 900 1100 1300 1500 1700 1900 2100 2300 2500 11814-322 1.5 SAMPLE RATE (MSPS) Figure 22. Current and Power vs. Sample Rate: 2 Lane, 4 Lane, and 8 Lane Output Modes 60 100 -40C 59 90 +25C 58 SFDR (dBFS) 57 70 +85C 56 SNR (dBFS) SNR (dBFS) 60 50 SFDR (dBc) 40 55 54 53 52 30 20 50 10 49 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 AMPLITUDE (dB) Figure 20. SNR/SFDR vs. Analog Input Amplitude at 2 .5 GSPS, fIN = 241 MHz at AIN 48 0 500 1000 1500 2000 INPUT FREQUENCY (MHz) 2500 3000 11814-323 51 SNR (dB) 11814-320 SNR/SFDR (dB) -30 1300 4.5 80 -40 Figure 21. SNR/SFDR vs. Analog Input Amplitude at 2 .5 GSPS, fIN = 1811 MHz at AIN 5.0 0 MORE -50 AMPLITUDE (dB) Figure 18. Two Tone SFDR and IMD3 vs. Analog Input Amplitude at 2.0 GSPS at 230 MHz AIN HITS (Millions) -80 POWER (W) -80 11814-215 0 -90 11814-321 10 Figure 23. SNR at 2.5GSPS vs. Temperature(Input Network in Figure 60 Used <2 GHz, Input Network in Figure 59 Used >2 GHz) Rev. A | Page 18 of 66 Data Sheet AD9625 120 85 +25C 80 100 IMD3 (dBFS) 75 -40C 80 SFDR (dB) SFDR (dBc) 70 65 +85C 60 SFDR (dBFS) 60 40 55 SFDR (dBc) 50 20 0 500 1000 1500 2000 2500 3000 INPUT FREQUENCY (MHz) Figure 24. SFDR at 2.5GSPS vs. Temperature (Input Network in Figure 60 Used <2 GHz, Input Network in Figure 59 Used >2 GHz) 90 0 -90 11814-324 40 -70 -60 -50 -40 -30 -20 -10 AMPLITUDE (dBFS) Figure 27. Two Tone SFDR and IMD3 vs. Analog Input Amplitude at 2.5 GSPS at 1800 MHz AIN 120 TA = +90C TA = +25C TA = -55C 85 -80 11814-327 45 IMD3 (dBFS) 100 80 SFDR (dBc) 75 SFDR (dB) SNR/SFDR (dB) 80 70 SFDR (dBFS) 60 65 40 SFDR (dBc) 60 20 SNR (dBFS) 300 500 700 900 1100 1300 1500 1700 1900 ANALOG INPUT FREQUENCY (MHz) 0 -90 11814-113 50 100 Figure 25. SNR/SFDR vs. Analog Input Frequency at Different Temperatures at 2.0 GSPS -80 -70 -60 -50 -40 -30 -20 -10 AMPLITUDE (dBFS) 11814-328 55 Figure 28. Two Tone SFDR and IMD3 vs. Analog Input Amplitude at 2.5 GSPS at 230 MHz AIN 0 120 IMD3 (dBFS) -1 100 -3 80 SFDR (dB) AMPLITUDE (dBFS) -2 -4 -5 -6 SFDR (dBFS) 60 40 SFDR (dBc) -7 20 100 1000 INPUT FREQUENCY (MHz) 5000 0 -90 11814-326 -9 10 Figure 26. Full Power Input Bandwidth (Input Network in Figure 60 Used <2 GHz, Input Network in Figure 59 Used >2 GHz) -80 -70 -60 -50 -40 AMPLITUDE (dBFS) -30 -20 -10 11814-329 -8 Figure 29. Two Tone SFDR and IMD3 vs. Analog Input Amplitude at 2.5 GSPS at 730 MHz AIN Rev. A | Page 19 of 66 AD9625 Data Sheet 100 4.0 95 3.5 90 SFDR (dBc), 240MHz 3.0 80 HITS (Millions) SNR/SFDR (dB) 85 75 70 65 SFDR (dBc), 1821MHz SNR (dBFS), 240MHz 2.5 2.0 1.5 60 55 1.0 SNR (dBc), 1821MHz 50 0.5 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 SAMPLE RATE (MSPS) 0 MORE N - 6 11814-330 40 300 Figure 30. SNR/SFDR vs. Sample Rate N-2 N N+2 N+4 N + 6 MORE CODE Figure 33. Input Referred Noise Histogram with 2.5 GHz Sample Clock 85 0 2500MSPS fIN1 = 1808.5MHz AT -7.0dBFS fIN2 = 1805.5MHz AT -7.0dBFS SFDR = 75.9dBc 80 -20 AMPLITUDE (dBFS) 75 70 SFDR (dBc) N-4 11814-333 45 65 60 55 -40 -60 -80 50 -100 1000 6000 ANALOG INPUT FREQUENCY (MHz) -120 11814-331 40 100 0 250 500 750 1000 1250 FREQUENCY (MHz) 11814-334 45 Figure 34. Two Tone FFT Plot at 2.5 GSPS, fIN1 = 1808.5 MHz and fIN2 = 1805.5 MHz at AIN, -7 dBFS (SFDR = 76 dBc) Figure 31. SFDR vs. AIN frequency at 2.5 GSPS (Input Network in Figure 60 Used <2 GHz, Input Network in Figure 59 used >2 GHz) 0 59 2500MSPS fIN1 = 728.5MHz AT -7.0dBFS fIN2 = 731.5MHz AT -7.0dBFS SFDR = 79.3dBc 58 -20 57 AMPLITUDE (dBFS) SNR (dBFS) 56 55 54 53 52 -40 -60 -80 51 50 -100 1000 INPUT FREQUENCY (MHz) 6000 Figure 32. SNRFS vs. AIN Frequency at 2.5 GSPS (Input Network in Figure 60 Used <2 GHz, Input Network in Figure 59 Used >2 GHz) Rev. A | Page 20 of 66 -120 0 250 500 750 1000 1250 FREQUENCY (MHz) Figure 35. Two Tone FFT Plot at 2.5 GSPS, fIN1 = 728.5 MHz and fIN2 = 731.5 MHz at AIN, -7 dBFS (SFDR = 79 dBc) 11814-335 48 100 11814-332 49 Data Sheet AD9625 0 0 2500MSPS fIN1 = 228.5MHz AT -7.0dBFS fIN2 = 231.5MHz AT -7.0dBFS SFDR = 76.7dBc -20 AMPLITUDE (dBFS) -40 -60 -80 -40 -60 -80 -100 -100 0 250 500 750 1000 1250 FREQUENCY (MHz) -120 11814-336 -120 0 0 400 600 800 1000 Figure 39. Two Tone FFT Plot at 2.0 GSPS, fIN1 = 228.5 MHz and fIN2 = 231.5 MHz at AIN, -7 dBFS (SFDR = 81 dBc) 0.5 2000MSPS fIN1 = 1805.5MHz AT -7.0dBFS fIN2 = 1808.5MHz AT -7.0dBFS -20 200 FREQUENCY (MHz) Figure 36. Two Tone FFT Plot at 2.5 GSPS, fIN1 = 228.5 MHz and fIN2 = 231.5 MHz at AIN, -7 dBFS (SFDR = 76 dBc) 0.4 SFDR = 78.117dBc 0.3 0.2 -40 DNL (LSB) AMPLITUDE (dBFS) SFDR = 80.76dBc 11814-221 AMPLITUDE (dBFS) -20 2000MSPS fIN1 = 228.5MHz AT -7.0dBFS fIN2 = 231.5MHz AT -7.0dBFS -60 0.1 0 -0.1 -80 -0.2 -0.3 -100 200 400 600 800 1000 FREQUENCY (MHz) -0.5 -1 11814-219 0 4095 0.5 0.4 0.3 0.2 DNL (LSB) -40 -60 -80 0.1 0 -0.1 -0.2 -0.3 -100 -120 0 200 400 600 800 1000 FREQUENCY (MHz) Figure 38. Two Tone FFT Plot at 2.0 GSPS, fIN1 = 728.5 MHz and fIN2 = 731.5 MHz at AIN, -7 dBFS (SFDR = 81 dBc) -0.5 0 1024 2048 3072 4096 CODES Figure 41. Differential Nonlinearity (DNL), 0.3 LSB at 2.5 GSPS Rev. A | Page 21 of 66 11814-341 -0.4 11814-220 AMPLITUDE (dBFS) 3071 Figure 40. Differential Nonlinearity (DNL), 0.2 LSB at 2.0 GSPS 2000MSPS fIN1 = 728.5MHz AT -7.0dBFS fIN2 = 731.5MHz AT -7.0dBFS SFDR = 80.98dBc -20 2047 CODES Figure 37. Two Tone FFT Plot at 2.0 GSPS, fIN1 = 1805.5 MHz and fIN2 = 1808.5 MHz at AIN, -7 dBFS (SFDR = 78.1 dBc) 0 1023 11814-222 -0.4 -120 AD9625 Data Sheet 0.6 1.0 0.4 0.9 VMON (V) INL (LSB) 0.2 0 0.8 0.7 -0.2 0 1024 2048 3072 4096 CODES 11814-223 -0.6 1.5 1.0 0 -0.5 -1.0 1024 2048 3072 4096 CODES 11814-343 INL (LSB) 0.5 0 -25 0 25 50 75 100 125 INPUT FREQUENCY (MHz) Figure 44. VMON Output Voltage vs. Junction Temperature VMON (V) = -0.0013 x TEMP(C) + 0.8675 Figure 42. Integral Nonlinearity (INL), 0.4 LSB at 2.0 GSPS -1.5 0.5 -50 Figure 43. Integral Nonlinearity (INL), 1.0 LSB at 2.5 GSPS Rev. A | Page 22 of 66 11814-344 0.6 -0.4 Data Sheet AD9625 EQUIVALENT TEST CIRCUITS VDD 15 DRVDD 890nH 50 0.5pF 0.2pF 0.2pF 11814-010 AIN EMPHASIS/SWING CONTROL (SPI) 0.6pF DATA+ OUTPUT DRIVER Figure 45. Equivalent Analog Input Circuit DRVDD DRGND 11814-400 DATA- VDD VDD DRGND 1k Figure 51. Digital Outputs 11814-011 SCLK DVDD2 DVDD2 DVDD2 Figure 46. Equivalent SCLK Circuit 200 SYNCIN+ VDD SYNCIN- 100 2k 11814-153 11814-012 1k 2pF Figure 52. Equivalent SYNCINB Input Figure 47. Equivalent VMON Temperature Sensor Circuit (DVDDD) DRVDD AVDD AVDD AVDD 0.88V 20k CLK+ 200 ESD PROTECTED 20k SDO CLK- DRVDD 1k SDIO SDI 11814-013 30k 11814-401 ESD PROTECTED Figure 48. Equivalent Clock Input Circuit Figure 53. Equivalent SDIO Circuit DVDD ESD PROTECTED AVDD 30k AVDD CSB AVDD 0.9V 1k SYSREF+ 20k 20k SYSREF- 11814-015 11814-014 ESD PROTECTED Figure 54. Equivalent SYSREF Input Circuit Figure 49. Equivalent CSB/PWDN Input Circuit DRVDD DRVDD 11814-150 DIVCLK Figure 50. Equivalent DIVCLK Output Circuit (DRVDD) Rev. A | Page 23 of 66 AD9625 Data Sheet THEORY OF OPERATION clears only when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time, thereby providing hysteresis and preventing the FD bit from excessive toggling. ADC ARCHITECTURE The AD9625 is a pipelined ADC. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. GAIN THRESHOLD OPERATION For best performance, the AD9625 needs an input signal to perform internal calibration. This signal needs to exceed a set threshold that is established through register settings. The threshold prohibits background calibration updates for small signal amplitudes. The threshold for gain calibration is enabled by default. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. Threshold Operation The absolute value of every sample is accumulated to produce an average voltage estimate. The input stage contains a differential sampling circuit that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output drive current. When the calibration has run for its predetermined number of samples, the voltage estimate is compared to the data set threshold. If the voltage estimate is greater than the threshold, the calibration coefficients update; otherwise, no update occurs. Threshold Format Synchronization capability is provided to allow synchronized timing between multiple devices. The threshold registers are all 16-bit registers loaded via the SPI one byte at a time. The threshold values range from 0 to 16,384, corresponding to a voltage range of 0.0 V to 1.2 V (full scale). FAST DETECT The fast detect block within the AD9625 generates a fast detection bit (FD), which, when used with variable gain amplifier front-end blocks, reduces the gain and prevents the ADC input signal levels from exceeding the converter range. The calibration threshold range is 0 to 16,384 (0x00 to 0x4000, hexadecimal) and represents the average magnitude of the input. For example, to set the threshold so that a -6 dBFS input sine wave sits precisely at the threshold requires a threshold setting of Figure 55 shows the rapidity by which the detection bit is programmable using an upper threshold, lower threshold, and dwell time. 6 16,384 x 10 20 x 2 5228 The FD bit is set when the absolute value of the input signal exceeds the programmable upper threshold level. The FD bit UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LT DWELL TIME FD Figure 55. Fast Detection Bit Rev. A | Page 24 of 66 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LT 11814-016 LOWER THRESHOLD Data Sheet AD9625 TEST MODES ADC TEST PATTERNS 12 BIT SPI REGISTER 0x0D BITS 3:0 0000 JESD204X TEST PATTERNS 10 BIT SPI REGISTER 0x61 BITS 5:4 = 01 AND BITS 3:0 0000 JESD204X TEST PATTERNS 16 BIT SPI REGISTER 0x61 BITS 5:4 = 00 AND BITS 3:0 0000 SERALIZER JESD204X SAMPLE CONSTRUCTION ADC CORE FRAME CONSTRUCTION SCRAMBLER (OPTIONAL) 8b/10b ENCODER OUTPUT 11814-018 FRAMER TAIL BITS Figure 56. Test Modes Table 10. Flexible Output Test Modes from SPI Register 0x00D Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0111 1000 Pattern Name Off (default) Midscale short Positive full scale Negative full scale Alternating checkerboard PN sequence long One-/zero-word toggle User test mode 1111 Ramp output Digital Output Word 1 (Default Twos Complement Format) Not applicable 0000 0000 0000 0111 1111 1111 1000 0000 0000 1010 1010 1010 Not applicable 1111 1111 1111 User data from Register 0x019 to Register 0x020 N Rev. A | Page 25 of 66 Digital Output Word 2 (Default Twos Complement Format) Not applicable = Word1 = Word1 = Word1 0101 0101 0101 Not applicable 0000 0000 0000 User data from Register 0x019 to Register 0x020 N+1 Subject to Data Format Select Yes Yes Yes Yes No Yes No Yes No AD9625 Data Sheet ANALOG INPUT CONSIDERATIONS AVDD ANALOG INPUT Small series resistors (R3 and R4) limit input bandwidth, but can be installed to further improve performance. Choose the input network components such that its equivalent impedance, in parallel with the 100 input impedance of the AD9625, is matched to the output impedance of the balun or amplifier. Using a larger value for R3 and R4 will suppress the input kickback from the sampling capacitor seen at the input to the AD9625. However, the tradeoff will be a lower usable input bandwidth and an increase in the amount of signal power needed to drive into the network for the AD9625 to sample a full-scale signal. 25 33 33 0.1F 33 0.1F AD9625 100 INTERNAL 25 Figure 59. Input Network Example for Passive Balun and >2 GHz ADC Bandwidth 0.1F 25 EXTERNAL BALUN/AMP 33 33 33 0.1F 25 0.1F 33 AD9625 100 INTERNAL Figure 60. Input Network Example for Passive Balun and <2 GHz ADC Bandwidth DRVDD AD9625 11814-024 VCM Figure 57. Recommended Front-End Network Table 11. Recommended Front-End Components Component R1 R2 R3 R4 R5 R6 33 11814-360 EXTERNAL BALUN/AMP R5 R6 0.1F Figure 58. Input Network Example for Passive Balun with High Bandwidth R2 R4 50 0.1F R1 0.1F AD9625 1.5pF ADC INTERNAL INPUT Z VCM 11814-359 INPUT Z = 50 Series isolation resistors (R5 and R6) are recommended to reduce bandwidth peaking and minimize kickback from the ADC sampling capacitor. Table 11 lists the front-end requirements. R3 33 100 0.1F 33 Optimum performance is achieved while driving the AD9625 in a differential input configuration. A passive input configuration can be used with a single to differential balun at the analog input to the AD9625. Because the AD9625 does not make use of an internal input buffer, an external network needs to be designed to reduce bandwidth peaking and minimize kickback from the ADC sampling capacitor. AVDD 0.1F 50 DIFFERENTIAL INPUT CONFIGURATIONS 0.1F 0.1F DRVDD 11814-361 The AD9625 has a differential analog input, which is optimized to provide superior wideband performance and must be driven differentially. For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common-mode settling errors are symmetrical. Mismatch between VIN+ and VIN- introduces undesired distortion. A wideband transformer, balun or amplifier can provide the differential analog inputs for applications that require a singleended to differential conversion. Component Value 33-50 (termination) 33-50 (termination) 0 to 33 (lower for higher bandwidth) 0 to 33 (lower for higher bandwidth) 33 33 Rev. A | Page 26 of 66 Data Sheet AD9625 DC COUPLING 130 The AD9625 can operate using a dc-coupled input configuration. The differential analog common-mode input signal would need to be referenced to the VCM output of the AD9625. 120 12.5fS 25fS 50fS 100fS 200fS 400fS 800fS 110 For optimum performance, drive the AD9625 sample clock inputs (CLK+ and CLK-) with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK- pins via a transformer or capacitors. These pins are biased internally and require no additional biasing. 90 80 70 60 50 40 30 10 Clock Jitter Considerations 100 1000 10000 ANALOG INPUT FREQUENCY (MHz) High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by SNR = 20 x log 10(1/(2 x x fA x tJ)) In this equation, the rms aperture jitter represents the rootmean-square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 61). 11814-366 CLOCK INPUT CONSIDERATIONS SNR (dB) 100 Figure 61. Ideal SNR vs. Analog Input Frequency and Jitter In cases where aperture jitter may affect the dynamic range of the AD9625, treat the clock input as an analog signal. To avoid modulating the clock signal with digital noise, separate power supplies for clock drivers from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more information about jitter performance as it relates to ADCs. Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. Rev. A | Page 27 of 66 AD9625 Data Sheet DIGITAL DOWNCONVERTERS (DDC) MODE SELECT: 185MHz OR 93MHz BW I-PHASE NCO MIXER 8 x 13-BIT @ 250MHz SYNTHESIZER 16-BIT @ 125MHz GAIN SELECT: 0dB, 6dB, 12dB, 18dB TUNER SELECT: -1.0GHz TO +1.0GHz MIXER 8 x 12-BIT @ 250MHz 16-BIT @ 250MHz DECIMATION BY 8 8 x 13-BIT @ 250MHz DECIMATION BY 2 GAIN SELECT: 0dB, 6dB, 12dB, 18dB DECIMATION BY 8 TO FRAMER 16-BIT @ 125MHz TO FRAMER 16-BIT @ 250MHz Q-PHASE 11814-019 12-BIT ADC @ 2.0GHz 8 x 12-BIT @ 250MHz Figure 62. Digital Downconverter Block Diagram Operating at 2.0 GSPS The AD9625 architecture includes two DDCs, each designed to extract a portion of the full digital spectrum captured by the ADC. Each tuner consists of an independent frequency synthesizer and quadrature mixer; a chain of low-pass filters for rate conversion follows these components. Assuming a sampling frequency of 2.500 GSPS, the frequency synthesizer (10-bit NCO) allows for 1024 discrete tuning frequencies, ranging from -1.2499 GHz to +1.2500 GHz, in steps of 2500/1024 = 2.44 MHz. The low-pass filters allow for two modes of decimation. * * A high bandwidth mode, 240 MHz wide (from -120 MHz to +120 MHz), sampled at 2.5 GHz/8 = 312.5 MHz for the I and Q branches separately. The 16-bit samples from the I and Q branches are transmitted through a dedicated JESD204B interface. A low bandwidth mode, 120 MHz wide (from -60 MHz to +60 MHz), sampled at 2.5 GHz/16 = 156.25 MHz for the I and Q branches separately. The 16-bit samples from the I and Q branches are transmitted through a dedicated JESD204B interface. By design, all of the blocks operate at a single clock frequency of 2.5 GHz/8 = 312.5 MHz. Each filter stage includes a gain control block that is programmable by the user. The gain varies from 0 dB to 18 dB, in steps of 6 dB, and the gain is applied before final scaling and rounding. The gain control feature may be useful in cases where the tuner filters out a strong out-of-band interferer, leaving a weak inband signal. FREQUENCY SYNTHESIZER AND MIXER For a sampling rate of 2.500 GHz, the synthesizer (10-bit NCO) outputs one of 1024 possible complex frequencies from -1.249 GHz to +1.250 GHz. The synthesizer employs the direct digital synthesis technique, using look-up sine tables and a phase accumulator. The user specifies the tuner frequency by writing to a 10-bit phase increment register. NUMERICALLY CONTROLLED OSCILLATOR Each DDC has a 10-bit oscillator that is synthesized and mixed with the ADC output data. The 10-bit phase can be tuned for each DDC based on the value used in its NCO registers. The phase for DDC0 is located with Register 0x132 and Register 0x131. The phase for DDC1 is located with Register 0x13A and Register 0x139. The NCO output frequency for DDC0 = (decimal(Register 0x132[1:0]; Register 0x131[7:0]) x fS)/1024. The NCO output frequency for DDC1 = (decimal(Register 0x13A[1:0]; Register 0x139[7:0]) x fS)/1024. HIGH BANDWIDTH DECIMATOR The first filter stage is designed for a rate reduction factor of 8, yielding a sample rate of 2.500 GHz/8 = 312.5 MHz. To achieve a combination of low complexity and low clock rate, the DDC employs a decimate-by-8 polyphase fuse filter that receives eight 13-bit samples from the mixer block at every clock cycle. The block design provides user specified gain control, from 0 dB to 18 dB in steps of 6 dB. The gain is applied before final scaling and rounding to 16 bits. Rev. A | Page 28 of 66 Data Sheet AD9625 10 Table 12. Filter Tap Coefficients for High Bandwidth Decimator 0 -10 MAGNITUDE (dB) -20 -30 -40 -50 -60 -70 -80 FS/2 FREQUENCY (MHz) 11814-020 -90 -100 Figure 63. Magnitude Response of the Decimate-by-8 Polyphase Fuse Filter Filter performance is shown in Figure 63 and Figure 64. The filter yields an effective bandwidth of 120 MHz, with a transition band of 156.5 - 120 = 36.5 MHz. Hence, the twosided complex bandwidth of the filter is 240 MHz. A rejection ratio of 85 dB ensures that the seven aliases that fold back into the pass band yield an SNR of 85 dB - 10log10(7) = 76.5 dB, which ensures that the aliases remain sufficiently below the noise floor of the input signal. The pass-band ripple is 0.05 dB, as shown in Figure 64. 0.25 0.20 MAGNITUDE (dB) 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 0 20 40 60 80 100 120 FREQUENCY (MHz) 11814-021 -0.20 Figure 64. Magnitude Ripple in the High Bandwidth Pass Band The high bandwidth decimator has a filter architecture that consists of a 142 tap delay line. The coefficients are 17 bits each and are listed in Table 12. Tap # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Rev. A | Page 29 of 66 Coefficient -38 -57 -92 -132 -172 -204 -219 -207 -162 -79 43 196 369 540 685 780 800 727 554 289 -48 -420 -778 -1069 -1238 -1242 -1055 -677 -135 513 1186 1785 2210 2372 2209 1698 869 -200 -1382 -2516 -3425 -3945 -3944 -3353 -2179 -519 1446 3467 Tap # 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Coefficient 5250 6496 6945 6412 4831 2276 -1031 -4725 -8330 -11304 -13098 -13222 -11306 -7160 -808 7498 17281 27882 38515 48340 56550 62451 65536 65536 62451 56550 48340 38515 27882 17281 7498 -808 -7160 -11306 -13222 -13098 -11304 -8330 -4725 -1031 2276 4831 6412 6945 6496 5250 3467 1446 Tap # 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Coefficient -519 -2179 -3353 -3944 -3945 -3425 -2516 -1382 -200 869 1698 2209 2372 2210 1785 1186 513 -135 -677 -1055 -1242 -1238 -1069 -778 -420 -48 289 554 727 800 780 685 540 369 196 43 -79 -162 -207 -219 -204 -172 -132 -92 -57 -38 AD9625 Data Sheet LOW BANDWIDTH DECIMATOR 0.4 0.3 MAGNITUDE (dB) The performance of the low bandwidth decimation filter is shown in Figure 65 and Figure 66. The filter yields an effective bandwidth of 60 MHz, with a transition band of 81.25 MHz - 60 = 21.25 MHz. Thus, the two sided, complex bandwidth of the filter is 120 MHz. A rejection ratio of 85 dB ensures that the alias region folds back well below the noise floor of the input signal. As with the high bandwidth filter, this block provides user specified gain control, from 0 dB to 18 dB, in steps of 6 dB. The gain is applied before final quantization at the output of the low bandwidth decimation filter to 16 bits. 10 -10 -30 -40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 0 -0.2 0 10 20 30 40 50 60 FREQUENCY (MHz) Figure 66. Magnitude Ripple in the Low Bandwidth Pass Band The low bandwidth decimator has a filter architecture that consists of a 31 tap delay line. The coefficients are 17 bits each and are listed in Table 13. Table 13. Filter Tap Coefficients for Low Bandwidth Decimator 11814-022 MAGNITUDE (dB) -20 0.1 -0.1 Tap # 1 2 3 4 5 6 7 8 9 10 0 0.2 11814-023 Use the second filter stage in the optional low bandwidth mode only. It achieves an additional rate reduction factor of 2, yielding a final sample rate of 2.500 GHz/16 = 156.25 MHz. The internal architecture of the low bandwidth decimation filter is similar to that of a high bandwidth decimator. Moreover, for ease of physical design, the block operates at 250 MHz, a result of which both the I- and Q-phases can share the filter engine. Figure 65. Magnitude Response of Decimate-by-2 Filter Rev. A | Page 30 of 66 Coefficient 126 312 -16 -859 -628 1217 1428 -1944 -3227 2511 Tap # 11 12 13 14 15 16 17 18 19 20 Coefficient 6302 -3099 -13075 3441 43442 65536 43442 3441 -13075 -3099 Tap # 21 22 23 24 25 26 27 28 29 30 31 Coefficient 6302 2511 -3227 -1944 1428 1217 -628 -859 -16 312 126 Data Sheet AD9625 DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE The AD9625 adheres to the JESD204B draft specification, which provides a high speed, serial, embedded clock interface standard for data converters and logic devices. It is designed as an MCDA-ML, Subclass 1 device that uses the SYSREF input signal for multichip synchronization and deterministic latency. This design adheres to the following basic JESD204B link configuration parameters: The AD9625 digital output complies with the JEDEC Standard No. JESD204B, Serial Interface for Data Converters. JESD204B is a protocol to link the AD9625 to a digital processing device over a serial interface up to and above 6.5 Gbps link speeds. The benefits of the JESD204B interface over LVDS include a reduction in required board area for data interface routing, and enabling smaller packages for converter and logic devices. The AD9625 supports one, two, four, six, or eight output lanes. * * * * * * The JESD204B data transmit block assembles the parallel data from the ADC into frames and uses 8-bit/10-bit encoding as well as optional scrambling to form serial output data. Lane synchronization is supported using special characters during the initial establishment of the link. Additional data that is used to maintain synchronization is embedded in the data stream thereafter. A JESD204B receiver is required to complete the serial link. For additional details on the JESD204B interface, users are encouraged to refer to the JESD204B standard. FUNCTIONAL OVERVIEW The block diagram in Figure 67 shows the flow of data through the JESD204B hardware from the sample input to the physical output. The processing can be divided into layers that are derived from the OSI model widely used to describe the abstraction layers of communications systems. These are the transport layer, data link layer, and physical layer (serializer). Each of these layers are described in detail in the following sections. The AD9625 JESD204B transmit block maps to two digital down converters for the outputs of the ADC over a link. A link can be configured to use up to eight JESD204B lanes. The JESD204B specification refers to a number of parameters to define the link, and these parameters must match between the JESD204B transmitter (AD9625 output) and receiver (FPGA, ASIC, or logic device). Transport Layer The transport layer handles packing the data (consisting of samples and optional control bits) into 8-bit words that are sent to the data link layer. The transport layer is controlled by rules derived from the link configuration data. It packs data according to the rules, adding tail bits to fill gaps when required. Table 14 describes the JESD204B interface nomenclature (the terms, converter device and link, are used interchangeably in the specification). Table 14. JESD204B Interface Nomenclature CS K HD F C T Data Link Layer Description Samples transmitted per single converter per frame cycle Number of converters per converter device (link) Number of lanes per converter device (link) Converter resolution Total number of bits per sample Number of control words per frame clock cycle per converter device (link) Number of control bits per conversion sample Number of frames per multiframe High density mode Octets per frame Control bit (overrange, time stamp) Tail bit TRANSPORT LAYER PROCESSED SAMPLES FROM ADC SAMPLE CONSTRUCTION FRAME CONSTRUCTION The data link layer is responsible for the low level functions of passing data across the link. These include optionally scrambling the data, handling the synchronization process for characters, frames, and lanes across the links, encoding 8-bit data-words into 10-bit characters, and inserting appropriate control characters into the data output. The data link layer is also responsible for sending the initial lane alignment sequence (ILAS), which contains the link configuration data, used by the receiver (Rx) to verify the settings in the transport layer. Physical Layer The physical layer consists of the high speed circuitry clocked at the serial clock rate. The physical layer includes the serialization circuits and the high speed drivers. DATA LINK LAYER SCRAMBLER ALIGNMENT CHARACTER GENERATION Figure 67. Data Flow Rev. A | Page 31 of 66 8-BIT/10-BIT ENCODER PHYSICAL LAYER CROSSBAR MUX SERIALIZER OUTPUT 11814-242 Symbol S M L N N' CF M = 1 (single converter, always for AD9625) L = 1 to 8 (up to eight lanes) S = 4 (four samples per JESD204B frame) F = 1, 2, 4, 8 (up to 8 octets per frame) N' = 12, 16 (12- or 16-bit JESD204B word size) HD = 0, 1 (high density mode, sample span multiple lanes) AD9625 Data Sheet JESD204B INTERFACE M = 1; L = 8; N = 12; N' = 16; CF = 0; CS = 0; CS = 0...4; K = 32; HD = 1; F = 1 400ps MIN (2.5GHz) CLK+ (ENCODE CLOCK) f g h i j a b F = 1 OCTETS F = 1 OCTETS F = 1 OCTETS SAMPLE N + 4 [11:4] SAMPLE N + 8 [11:4] SAMPLE N + 12 [11:4] c d e f g h i j a SAMPLE N [3:0], CTTTT LANE B @ 6.25Gbps f g h i j a b c d e f g h f g h i j a b c d e f g h i j a f g h i j a b c d e f g h i j a f g h i j a b c d e f g h i j a f g h i j a b c d e f g h i j a f g h i j a b c d e f g h i j a f g h i j a b c d e f g h a i i b c d e f g h i b c d e f g h i b c d e f g h i b c d e f g h i b c d e f g h i j a b c d e f g h i j a a b c d e f g h i c d b c d j a b c d f g h i j a e f g h i e f g h i j a b c d e f g h i j a a b c d e f g h i j a a b c d e f g h i j a a b c d e f g h i j a a b c d e f g h i i j b c d e f g h i j b c d e f g h i j b c d e f g h i j b c d e f g h i j SAMPLE N + 14 [3:0], CTTTT j a b c d e f g h i j SAMPLE N + 15 [11:4] j a SAMPLE N + 11 [3:0], CTTTT j f g h SAMPLE N + 14 [11:4] SAMPLE N + 11 [11:4] j e SAMPLE N + 13 [3:0], CTTTT SAMPLE N + 10 [3:0], CTTTT j c d SAMPLE N + 13 [11:4] SAMPLE N + 10 [11:4] j b SAMPLE N + 12 [3:0], CTTTT SAMPLE N + 9 [3:0], CTTTT Figure 68. JESD204B Lane Data Mapping Rev. A | Page 32 of 66 e SAMPLE N + 9 [11:4] SAMPLE N + 7 [3:0], CTTTT j b SAMPLE N + 8 [3:0], CTTTT SAMPLE N + 7 [11:4] SAMPLE N + 3 [3:0], CTTTT LANE H @ 6.25Gbps j SAMPLE N + 6 [3:0], CTTTT SAMPLE N + 3 [11:4] LANE G @ 6.25Gbps i SAMPLE N + 6 [11:4] SAMPLE N + 2 [3:0], CTTTT LANE F @ 6.25Gbps f g h SAMPLE N + 5 [3:0], CTTTT SAMPLE N + 2 [11:4] LANE E @ 6.25Gbps e SAMPLE N + 5 [11:4] SAMPLE N + 1 [3:0], CTTTT LANE D @ 6.25Gbps c d SAMPLE N + 4 [3:0], CTTTT SAMPLE N + 1 [11:4] LANE C @ 6.25Gbps b b c d e f g h i j SAMPLE N + 15 [3:0], CTTTT j a b c d e f g h i j 11814-373 LANE A @ 6.25Gbps F = 1 OCTETS SAMPLE N [11:4] Data Sheet AD9625 JESD204B LINK ESTABLISHMENT Data Streaming The AD9625 JESD204B Tx interface operates in Subclass 1 as defined in the JEDEC Standard No. 204B-July 2011 specification. It is divided into the following steps: code group synchronization, initial lane alignment sequence, and data streaming. After the initial lane alignment sequence is complete, the user data is sent. In a usual frame, all characters are user data. However, to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /F/ or /A/ alignment characters when the data meets certain conditions. These conditions are different for unscrambled and scrambled data. The scrambling operation is enabled by default but may be disabled using SPI. Code Group Synchronization (CGS) and SYNCINB CGS is the process where the JESD204B receiver finds the boundaries between the 10-bit characters in the stream of data. During the CGS phase, the JESD204B transmit block transmits /K28.5/ characters. The receiver (external logic device) must locate the /K28.5/ characters in its input data stream using clock and data recovery (CDR) techniques. The receiver issues a synchronization request by activating the SYNCINB pins of the AD9625. The JESD204B Tx begins sending /K28.5/ characters until the next LMFC boundary. When the receiver has synchronized, it waits for the correct reception of at least four consecutive /K28.5/ symbols. It then deactivates SYNCINB. The AD9625 then transmits an initial lane alignment sequence (ILAS) on the following LMFC boundary. For more information on the code group synchronization phase, please refer to the JEDEC Standard No. 204B-July 2011, Section 5.3.3.1. The SYNCINB pin operation can be controlled by SPI. The SYNCINB signal is a differential LVDS mode signal by default, but it can also be driven single ended. For more information on configuring the SYNCINB pin operation, refer to the Memory Map section. Initial Lane Alignment Sequence (ILAS) The ILAS phase follows the CGS phase and begins on the next LMFC boundary. The ILAS consists of four mulitframes, with an /R/ character marking the beginning and an /A/ character marking the end. The ILAS begins by sending an /R/ character followed by 0 to 255 ramp data for one multiframe. On the second multiframe, the link configuration data is sent starting with the third character. The second character is a /Q/ character to confirm that the link configuration data follows. All undefined data slots are filled with ramp data. The ILAS sequence is never scrambled. The ILAS sequence construction is shown in Figure 70. The four multiframes include the following: * Multiframe 1: begins with an /R/ character (K28.0) and ends with an /A/ character (K28.3). * Multiframe 2: begins with an /R/ character followed by a /Q/ [K28.4] character, followed by link configuration parameters over 14 configuration octets and ends with an /A/ character. Many of the parameter values are of the notation of the value, -1. * Multiframe 3: this is the same as Multiframe 1. * Multiframe 4: this is the same as Multiframe 1. For scrambled data, any 0xFC character at the end of a frame is replaced by an /F/, and any 0x7C character at the end of a multiframe is replaced with an /A/. The JESD204B Rx checks for /F/ and /A/ characters in the received data stream and verifies that they only occur in the expected locations. If an unexpected /F/ or /A/ character is found, the receiver handles the situation by using dynamic realignment or activating the SYNCINB signal for more than four frames to initiate a resynchronization. For unscrambled data, if the final character of two subsequent frames is equal, the second character is replaced with an /F/ if it is at the end of a frame, and an /A/ if it is at the end of a multiframe. Insertion of alignment characters may be modified using SPI. The frame alignment character insertion is enabled by default. More information on the link controls is available in the Memory Map section, Register 0x062. Link Setup Parameters The following steps demonstrate how to configure the AD9625 JESD204B interface and the output: 1. 2. 3. 4. 5. 6. Disable the lanes before changing configuration. Select one quick configuration option. Configure the detailed options. Check FCHK, checksum of JESD204B interface parameters. Set additional digital output configuration options. Reenable the required lane(s). Before modifying the JESD204B link parameters, disable the link and hold it in reset. 8-Bit/10-Bit Encoder The 8-bit/10-bit encoder converts 8-bit octets into 10-bit characters and inserts control characters into the stream when needed. The control characters used in JESD204B are shown in Table 15. The 8-bit/10-bit encoding allows the signal to be dc balanced by using the same number of ones and zeros. The 8-bit/10-bit interface has options that may be controlled via SPI. These operations include bypass, invert or mirror. These options are intended to be a troubleshooting tool for the verification of the digital front end (DFE). Rev. A | Page 33 of 66 AD9625 Data Sheet Digital Outputs, Timing, and Controls VRXCM The AD9625 physical layer consists of drivers that are defined in the JEDEC Standard No. 204B-July 2011. The differential digital outputs are powered up by default. The drivers utilize a dynamic 100 internal termination to reduce unwanted reflections. 50 100 DIFFERENTIAL 0.1F TRACE PAIR DRVDD 50 SERDOUTx+ 100 RECEIVER 0.1F OUTPUT SWING = 300mV p-p 11814-243 SERDOUTx- Place a 100 differential termination resistor at each receiver input to result in a nominal 300 mV p-p swing at the receiver (see Figure 69). Alternatively, single-ended 50 termination can be used. When single-ended termination is used, the termination voltage should be DRVDD/2; otherwise, 0.1 F ac coupling capacitors can be used to terminate to any single-ended voltage. OR VCM = VRXCM Figure 69. AC-Coupled Digital Output Termination Example If there is no far end receiver termination, or if there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. The AD9625 digital outputs can interface with custom ASICs and FPGA receivers, providing superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a single differential 100 termination resistor placed as close to the receiver inputs as possible. De-Emphasis De-emphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the JESD204B specification. The de-emphasis feature should only be used when the receiver is unable to recover the clock due to excessive insertion loss. Under normal conditions, it is disabled to conserve power. Additionally, enabling and setting too high a de-emphasis value on a short link may cause the receiver eye diagram to fail. Using the de-emphasis setting may increase EMI. See the Memory Map section for details. K K R D D A R Q C C D D A R D D A R D D A D START OF ILAS START OF LINK CONFIGURATION DATA START OF USER DATA Figure 70. Initial Lane Alignment Sequence Table 15. AD9625 Control Characters Used in JESD204B Abbreviation /R/ /A/ /Q/ /K/ /F/ Control Symbol /K28.0/ /K28.3/ /K28.4/ /K28.5/ /K28.7/ 8-Bit Value 000 11100 011 11100 100 11100 101 11100 111 11100 10-Bit Value RD (Running Disparity) = -1 001111 0100 001111 0011 001111 0010 001111 1010 001111 1000 Rev. A | Page 34 of 66 10-Bit Value RD (Running Disparity) = +1 110000 1011 110000 1100 110000 1101 110000 0101 110000 0111 Description Start of multiframe Lane alignment Start of link configuration data Group synchronization Frame alignment 11814-132 END OF MULTIFRAME Data Sheet AD9625 Table 16. JESD204B Mode of Operation (M = 1, S = 4, N' = 16, Unless Otherwise Noted) Quick Configuration Value 0x02 0x04 0x06 0x08 0x42 0x44 0x48 0x81 0x82 0x91 0xC1 0xC2 0xC4 0xE1 0xE2 0xE4 0xD1 0xD2 1 Description1 Generic Generic Generic (N' = 12) Generic fS x 8 fS x 4 fS x 2 Single DDC, high BW Single DDC, high BW Single DDC, low BW Dual DDC, high BW Dual DDC, high BW Dual DDC, high BW Dual DDC, mixed BW Dual DDC, mixed BW Dual DDC, mixed BW Dual DDC, low BW Dual DDC, low BW Lanes (L) 2 4 6 Octets/ Frame (F) 4 2 1 Sample Clock Rate Minimum Maximum MSPS MSPS 330 650 650 1300 1300 2500 Sample Clock Multiplier 10 5 2.5 JESD204B Lane Rate Minimum Maximum Mbps Mbps 3300 6500 3250 6500 3250 6250 8 2 4 8 1 2 1 1 2 4 1 2 4 1 2 1 4 2 1 8 4 8 8 4 2 8 4 2 8 4 1300 406 813 1625 650 1300 1300 330 650 1300 330 650 1300 650 1300 2.5 8 4 2 5 2.5 2.5 10 5 2.5 10 5 2.5 5 2.5 3250 3250 3250 3250 3250 3250 3250 3300 3250 3250 3300 3250 3250 3250 3250 2500 813 1625 2500 1300 2500 2500 650 1300 2500 650 1300 2500 1300 2500 6250 6500 6500 5000 6500 6250 6250 6500 6500 6250 6500 6500 6250 6500 6250 DDC means digital downconverter, BW means bandwidth, fS x x means sample rate multiplied by an integer (where x is an integer: 2, 4, 8). Table 17. JESD204B Logical Lane Mapping Quick Configuration Value 0x02 0x04 0x06 Description Generic Lanes (L) 2 Generic Generic (N' = 12) Generic fS x 8 fS x 4 fS x 2 4 6 0x81 Single DDC, high BW 1 0x82 Single DDC, high BW Single DDC, low BW 2 0x08 0x42 0x44 0x48 0x91 8 2 4 8 1 0xC1 Dual DDC, high BW 1 0xC2 Dual DDC, high BW Dual DDC, high BW Dual DDC, mixed BW 2 0xC4 0xE1 4 1 Logical Logical Logical Logical Logical Logical Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 S[N], S[N + 2], Off Off Off Off S[N + 1] S[N + 3] S[N] S[N + 1] S[N + 2] S[N + 3] Off Off SMSB[N], SLSB[N], SMSB[N + 1], SLSB[N + 1], SMSB[N + 2], SLSB[N + 2], SMSB[N + 3], SLSB[N + 3] SMSB[N] SLSB[N] I0[N], Q0[N], I1[N], Q1[N] Off Logical Lane 6 Off Logical Lane 7 Off Off Off Off Off SMSB[N + 1] SLSB[N + 1] SMSB[N + 2] SLSB[N + 2] SMSB[N + 3] SLSB[N + 3] See Figure 84, fS x 2 mode application layer (transmit) See Figure 84, fS x 2 mode application layer (transmit) SMSB[N], SLSB[N], SMSB[N + 1], SLSB[N + 1], SMSB[N + 2], SLSB[N + 2], SMSB[N + 3], SLSB[N + 3], SMSB[N + 4], SLSB[N + 4]; see Figure 84, fS x 2 mode application layer (transmit) I0[N], Off Off Off Off Off Off Off Q0[N], I0[N + 1], Q0[N + 1] I0[N], I0[N+1], Off Off Off Off Off Off Q0[N] Q0[N+1] I0[N], Off Off Off Off Off Off Off Q0[N], I0[N + 1], Q0[N + 1] I0[N], Off Off Off Off Off Off Off Q0[N], I1[N], Q1[N] I0[N], I1[N], Off Off Off Off Off Off Q0[N] Q1[N] I0[N] Q0[N] I1[N] Q1[N] Off Off Off Off Off Off Rev. A | Page 35 of 66 Off Off Off Off AD9625 Quick Configuration Value 0xE2 0xE4 0xD1 0xD2 Data Sheet Description Dual DDC, mixed BW Dual DDC, mixed BW Dual DDC, low BW Dual DDC, low BW Lanes (L) 2 4 1 2 Logical Lane 0 I0[N], Q0[N] I0[N] Logical Lane 1 I1[N], Q1[N] Q0[N] Logical Lane 2 Off Logical Lane 3 Off Logical Lane 4 Off Logical Lane 5 Off Logical Lane 6 Off Logical Lane 7 Off I1[N] Q1[N] Off Off Off Off I0[N], Q0[N], I1[N], Q1[N] I0[N], Q0[N] Off Off Off Off Off Off Off I1[N], Q1[N] Off Off Off Off Off Off Table 18. Typical Current Consumption per ADC Mode (Unused Output Lanes are Powered Down) Typical Current Consumption (A) Quick Configuration Value 0x02 Mode Generic, 2 lane Lanes (L) 2 Sample Rate (MSPS) 650 IAVDD1 0.7 IAVDD2 0.3 IDRVDD1 0.2 IDRVDD2 0.0 IDVDD1 0.1 IDVDD2 0.0 Total Power (W) 2.1 0x04 0x06 0x08 0x42 0x44 0x48 0x81 0x82 0x91 0xC1 0xC2 0xC4 0xE1 0xE2 0xE4 0xD1 0xD2 Generic, 4 lane Generic, 6 lane Generic, 8 lane fS x 8 fS x 4 fS x 2 Single DDC high BW, 1 lane Single DDC high BW, 2 lane Single DDC low BW, 1 lane Dual DDC high BW, 1 lane Dual DDC high BW, 2 lane Dual DDC high BW, 4 lane Dual DDC mixed BW, 1 lane Dual DDC mixed BW, 2 lane Dual DDC mixed BW, 4 lane Dual DDC low BW, 1 lane Dual DDC low BW, 2 lane 4 6 8 2 4 8 1 2 1 1 2 4 1 2 4 1 2 1300 2500 2500 813 1625 2500 1300 2500 2500 650 1300 2500 650 1300 2500 1300 2500 0.9 1.2 1.2 0.7 1.0 1.2 0.9 1.2 1.2 0.7 0.9 1.2 0.7 0.9 1.2 0.9 1.2 0.3 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.3 0.4 0.5 0.2 0.3 0.5 0.1 0.2 0.1 0.1 0.2 0.3 0.1 0.2 0.3 0.1 0.2 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.1 0.2 0.4 0.4 0.2 0.3 0.4 0.3 0.6 0.6 0.2 0.5 0.8 0.2 0.5 0.8 0.4 0.8 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 2.6 3.4 3.9 2.3 3.0 3.8 2.7 3.6 3.5 2.3 2.9 4.0 2.3 2.9 4.0 2.8 4.0 Rev. A | Page 36 of 66 Data Sheet AD9625 PHYSICAL LAYER OUTPUT 180 160 400 140 300 120 100 100 0 80 -100 60 -200 40 -300 20 -400 0 -100 -50 0 50 100 150 TIME (ps) 11814-026 -15 -150 Figure 71. Recovered Data Eye of JESD204B Lane at 6.25 Gbps -10 -5 0 5 10 15 TIME (ps) 11814-028 HITS VOLTAGE (mV) 200 Figure 73. Time Interval Histogram Error of JESD204B Output at 6.25 Gbps SCRAMBLER 1 The scrambler polynomial is 1 + x14 + x15. The scrambler enable bit is located in Register 0x06E[7]. 1-2 1-4 1-6 Setting Bit 7 to 0 disables the scrambler. Setting Bit 7 to 1 enables the scrambler. BER TAIL BITS 1-8 The tail bit, PN generator, is located in Register 0x05F[6]. 1-10 Setting Bit 6 to 0 disables the tail bit generator. Setting Bit 6 to 1 enables the tail bit generator. 1-12 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 UI Figure 72. Bathtub Plot of JESD204B Output at 6.25 Gbps 0.5 11814-027 DDC MODES (SINGLE AND DUAL) 1-14 -0.5 The AD9625 contains two separate DDCs that can digitally downconvert real ADC output data into I/Q decimated data at a reduced bandwidth. This feature is useful when the full bandwidth supplied by the 2.5 GSPS converter is not needed. Figure 74 shows a simplified block diagram of the DDC blocks as they traverse through the AD9625. Because all JESD204B frames contain four samples (S = 4), the output from the DDCs must also output four samples. Table 19 shows the remapping of I/Q samples to converter samples for the JESD204B interface, specific to the AD9625. When in mixed bandwidth mode, DDC 0 is always in high bandwidth mode and DDC 1 is always in low bandwidth mode. To match the data throughput of the high bandwidth mode, the low bandwidth samples are repeated twice in mixed bandwidth mode. Table 20 lists the four frames of data for both DDC 0 (high bandwidth mode) and DDC 1 (low bandwidth mode). Rev. A | Page 37 of 66 AD9625 Data Sheet LOGICAL LANE 0 (L0) ADC 16 LOGICAL LANE 1 (L1) Q0 16 48 I1 DCC 1 SAMPLE [N] 16 SAMPLE [N + 1] REMAP I/Q TO CONVERTER SAMPLES SAMPLE [N + 2] JESD204X LOGICAL LANE 2 (L2) INTERFACE (M = 1; L = 8; S = 4; F = 1; N = 16; N' = 16; LOGICAL LANE 3 (L3) CF = 0; SCR = 0, 1; HD = 1; LOGICAL LANE 4 (L4) K = SEE SPECS) LOGICAL LANE 5 (L5) LOGICAL LANE 6 (L6) Q1 16 SAMPLE [N + 3] LOGICAL LANE 7 (L7) 11814-029 12-BIT ADC SAMPLES [N] THROUGH [N + 3] DCC 0 I0 Figure 74. DDC Mapping Table 19. DDC Remap I/Q to Converter Samples Application Mode Single DDC Dual DDCs Sample[N] I0[N] I0[N] Sample[N + 1] Q0[N] Q0[N] Sample[N + 2] I0[N + 1] I1[N] Sample[N + 3] Q0[N + 1] Q1[N] Table 20. DDC Mixed Bandwidth Mode JESD204B Frame Number Frame 0 Frame 1 Frame 2 Frame 3 Sample[N] I0[N] I0[N + 1] I0[N + 2] I0[N + 3] Sample[N + 1] Q0[N] Q0[N + 1] Q0[N + 2] Q0[N + 3] CHECKSUM The JESD204B checksum value is sent with the configuration parameters during the initial lane alignment sequence. Disabling the checksum is primarily for debug purposes only. 8-BIT/10-BIT ENCODER CONTROL The 8-bit/10-bit encoder must be controlled in the following manner: * * * The bypass 8-bit/10-bit encoder is controlled by Register 0x60, Bit 2 (0 = 8-bit/10-bit enabled; 1 = 8-bit/10-bit bypassed). The invert 10-bit encoder is controlled by Register 0x060, Bit 1 (0 = normal; 1 = invert). The mirror 10-bit encoder is controlled by Register 0x060, Bit 0 (0 = normal; 1 = mirrored). The inversion of the 10-bit values allows the user to swap the true/complement differential pins swapped on the boards. For details about Register 0x060, see the Memory Map Register section. Sample[N + 3] Q1[N] Q1[N] Q1[N + 1] Q1[N + 1] When enabled, the device must also support the capability to repeat the ILAS using Bits[7:0] in Register 0x062 to determine the number of times ILAS is repeated (0 = repeat 0 times, ILAS runs one time only, 1 = repeat one time, ILAS runs twice, and so forth). Because the number of frames per multiframe is determined by the value of K, the total number of frames transmitted during the initial lane alignment sequence is 4 x (K + 1) x (ILAS_COUNT + 1) where the value of K is defined in Register 0x070, Bits[4:0]. Note that only values divisible by four can be used. For details about Register 0x05F and Register 0x062, see the Memory Map Register section. LANE SYNCHRONIZATION Lane synchronization is defined by Register 0x05F, Bit 4 (0 = disabled, 1 = enabled). For more information, see the Memory Map Register section. INITIAL LANE ALIGNMENT SEQUENCE (ILAS) The AD9625 must support three different ILAS modes that are controlled using Bits[3:2] in Register 0x05F as follows: * * * * Sample[N + 2] I1[N] I1[N] I1[N + 1] I1[N + 1] 00: disabled 01: enabled 10: reserved 11: always on test mode Rev. A | Page 38 of 66 Data Sheet AD9625 Multichip Synchronization Using SYSREF Timestamp ADC Output Control Bits on JESD204B Samples The SYSREF pin in the AD9625 can also be used as a timestamp of data as it passes through the ADC and out the JESD204B interface. This can be accomplished in two ways: When N' = 16 and the ADC resolution is 12, there are four spare bits available per sample. Two of these spare bits can be used as control bits, depending on the configuration options. The control bits are set in Register 0x072, Bits[7:6]. (CS means control bits per sample.) * * Replace the least significant converter bit with the synchronous low to high captured SYSREF signal. If the AD9625 were configured as a 12-bit converter, this would effectively reduce it to a 11-bit converter. This is accomplished by setting Register 0x03A[7] = 1 in the register map. Use the extra output JESD204B control bits to insert the synchronous low to high captured SYSREF signal. These extra control bits are only available while in the JESD204B generic 2, 4, and 8 lane modes. The generic 6 lane mode does not support control bits as both N and N' = 12. * * 00: no control bits sent per sample (CS = 0). 01: one control bit sent per sample, overrange bit enabled, (CS = 1). 10: two control bits sent per sample, overrange and time stamped SYSREF control bit (marks the sample of a rising edge seen on the SYSREF pin), (CS = 2). Use of the SYSREF control bit (CS = 2) time stamps a particular analog sample that is seen coincident with a rising signal on the SYSREF pins. * 6 Lane Output Mode SYSREF Setup and Hold IRQ The full data output bandwidth of the 8 lane mode can alternately by output using a 6 lane mode. This is achieved by using an N' = 12 in the 6 lane mode vs. N' = 16 in the 8 lane mode for N = 12 ADC data. The differential SYSREF inputs to AD9625 are critical for JESD204B deterministic latency and sample timestamping. At a 2.5 GSPS sample rate, the clock period is only 400 ps in duration from which to accurately latch a SYSREF edge to meet setup and hold time to the sample clock. Therefore, it is important to know the location of the SYSREF edge relative to the sampling edge of the encode clock. To help identify the SYSREF edge location within the clock period, the AD9625 provides a setup and hold time edge detector circuit to provide feedback to the system for SYSREF timing skew and other alignment procedures. This is a fine timing detector (<1 clock cycle) and will not provide useful information if coarse timing (>1 clock cycle) skew adjustment is needed on SYSREF. The benefit of using the 6 lane mode is that only 6 lanes of output data are needed instead of 8 lanes and 2 output data lanes can be powered down. A drawback of the 6 lane mode is that because there is full efficiency of the link for N = N' = 12, there is no spare bandwidth available for control bits. Therefore, control bit timestamping using SYSREF cannot be used in the 6 lane mode. The LSB of the 12-bit ADC data can be substituted to output the SYSREF timestamp. N-1 N+3 The AD9625 provides an interrupt request (IRQ) bit that identifies either a setup or a hold time error for the SYSREF edge relative to the sampling clock. The error indicates that the SYSREF edge is present within the designated time window. There is a default detector window for both the actual setup and hold time, with each being nominally 35 ps in time. This error flag can be identified internal to the AD9625 IRQ register or the status can be sent externally via the IRQ pin, provided that the appropriate interrupts are masked or enabled as desired. AD9625 N+1 PIPELINE LATENCY ENCODE CLK SYSREF SYSREF CONTROL BIT N-1 N N+1 N+2 N+3 12-BIT ADC SAMPLES 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 4-BIT CONTROL AND TAIL BITS 11814-480 SAMPLES Figure 75. A SYSREF Control Bit Can Be Used to Mark the Same Analog Sample that is Coincident with a Sampled SYSREF Edge by CLK A SYSREF edge located in either the setup or hold violation window will cause ambiguity as to whether the event will be latched on CLK[N] or CLK[N + 1]. As a best practice, the SYSREF edge needs to be earlier than both the setup and hold violation windows so that a deterministic clock can be used to latch SYSREF. CLK- CLK+ SYSREF- SYSREF+ SETUP IRQ ERROR 11814-481 N+2 N AIN Figure 76. SYSREF Edge Falls Within the Actual Setup Time Window and Triggers an IRQ Error Rev. A | Page 39 of 66 AD9625 Data Sheet there is no edge in the hold guardband delays, those would all be 0 if they were set. CLK- CLK+ Table 21. IRQ Outcomes for All Setup or Hold Guardband Settings for the Case in Figure 78 After each IRQ alert, the status will need to be cleared, as it will not automatically clear itself, even if the alert conditions are no longer valid. For either the SYSREF setup or hold IRQ alert, the status will be cleared using Register 0x03A[6]. Setting Register 0x03A[6] = 1 will clear and hold the IRQ in a reset value of 0. To allow IRQ flags pertaining to SYSREF again, set Register 0x03A[6] = 0. SETUP GUARDBAND IRQ DELAYS HOLD GUARDBAND IRQ DELAYS CLK+ SYSREF- 11814-483 111 110 101 100 011 010 001 000 000 010 001 011 100 101 110 111 SYSREF+ HOLD AND GUARDBAND TIME 111 110 101 100 011 010 HOLD AND GUARDBAND TIME 11814-484 SETUP AND GUARDBAND TIME 001 SYSREF+ Figure 79. SYSREF Edge Falls Within the Guardbanded Hold Time Window and Triggers an IRQ Error In Figure 79, the SYSREF edge misses the default setup and hold time of the clock, but would trigger an IRQ event only if certain hold time guardband delays were used. For this figure, all of the hold guardband delays that would place the SYSREF crossing edge between it and the dotted black line would incur an IRQ event equal to 1. All other settings would be 0. Because there is no edge in the setup guardband delays, those would all be 0 if they were set. Table 22. IRQ Outcomes for All Setup or Hold Guardband Settings Using the Case in Figure 79 CLK- SETUP AND GUARDBAND TIME CLK+ SYSREF- 000 The IRQ flag for the SYSREF setup window is in Register 0x100[2], while the IRQ flag for the SYSREF hold window is in Register 0x100[3]. The IRQ flag mask for the SYSREF setup window is in Register 0x101[2], while the IRQ flag mask for the SYSREF hold window is in Register 0x101[3]. CLK- 000 There are 3 bits that define the SYSREF setup time guardband located in Register 0x13C[7:5]. There are 3 bits that define the SYSREF hold time guardband located in Register 0x13B[7:5]. A setting of 000b for either will be the default of no additional timing guardband, with just the actual setup and hold time window used as the IRQ. Hold 0 0 0 0 0 0 0 0 HOLD GUARDBAND IRQ DELAYS SETUP GUARDBAND IRQ DELAYS 010 001 Additional guardband delays can be added to each of the default setup and hold time windows. This will yield more information to the system about the placement of the SYSREF edge within the clock period and help identify the proximity of the SYSREF edge to the actual setup and hold time windows. With a default setting of 00b for both setup and hold, each has 7 additional settings to increase the guardband timing feedback information. 011 IRQ Guardband Delays (SYSREF Setup and Hold) Setup 0 0 0 0 1 1 1 1 100 Figure 77. SYSREF Edge Falls Within the Actual Hold Time Window and Triggers an IRQ Error Setting/IRQ 000 001 010 011 100 101 110 111 101 HOLD IRQ ERROR 110 11814-482 SYSREF+ 111 SYSREF- Figure 78. SYSREF Edge Falls Within the Guardbanded Setup Time Window and Triggers an IRQ Error Setting/IRQ 000 001 010 011 100 101 110 111 In Figure 78, the SYSREF edge meets the default setup and hold time of the clock, but would trigger an IRQ event only if certain setup time guardband delays were used. For this figure, all of the setup guardband delays that would place the SYSREF crossing edge between it and the dotted black line would incur an IRQ event equal to 1. All other settings would be 0. Because Rev. A | Page 40 of 66 Setup 0 0 0 0 0 0 0 0 Hold 0 0 0 0 1 1 1 1 Data Sheet AD9625 HOLD GUARDBAND [N] IRQ DELAYS SETUP GUARDBAND [N +1] IRQ DELAYS CLK[N + 1] OVERLAP CLK[N] SYSREF- SETUP AND GUARDBAND TIME [N + 1] 11814-485 000 001 010 011 HOLD AND GUARDBAND TIME [N] 111 110 101 100 011 010 001 000 000 001 010 011 100 101 110 111 010 001 000 SYSREF+ Figure 80. SYSREF Edge Falls Within Both the Latest Hold Time Guardbanded of CLK[N] and the Earliest Setup Time Guardband of CLK[N + 1] and Triggers an IRQ Error Table 23. IRQ Outcomes for All Setup or Hold Guardband Settings Using the Case in Figure 80 Setting/IRQ 000 001 010 011 100 101 110 111 Setup 0 0 0 0 0 0 0 1 Hold 0 0 0 0 0 0 0 1 As a secondary use, the SYSREF edge detector can also alert the system about phase shift drift between SYSREF and CLK due to temperature or supply changes. For example, a conservative guardband setting could be used, such that an IRQ status of 0 would be seen in ideal conditions. If timing drifts were significant enough to trigger the IRQ, the system would take action to adjust the skew of the SYSREF to CLK accordingly to re-establish an IRQ of 0. HOLD GUARDBAND IRQ DELAYS CLK- CLK+ SYSREF- 111 110 101 100 011 010 001 HOLD AND GUARDBAND TIME 11814-486 SETUP AND GUARDBAND TIME 000 000 010 001 011 100 101 110 SYSREF+ Figure 81. SYSREF Edge Changes Phase Relative to the Encode Clock, Which can be Detected When the Edge Crosses Through the Guardband Setup Time Table 24. IRQ Outcomes for all Setup or Hold Guardband Settings Using the Case in Figure 81 Setting/IRQ 000 001 010 011 100 101 110 111 CLK- CLK+ SETUP GUARDBAND IRQ DELAYS 111 In the case where the encode clock used for the AD9625 is sufficiently fast (>1.75 GSPS), the guardband delays for the earliest setup and latest hold condition will start to overlap in time due to the fast clock period. This case occurs when the encode clock period is smaller than 16x the nominal delay guardband window of 35 ps or (1/fS < 16 x 35 ps). The earliest setup guardband delays from clock N can overlap with the latest guardband delays from CLK[N + 1]. When this is the case, a SYSREF edge located in one of these overlapped guardband delays will trigger an IRQ event for both the setup and hold detection. While it is possible to make use of this information, it is suggested to limit the number of valid settings to no more than 5 (100b) and below when sampling above 1.75 GSPS to avoid this situation. Setup 0 0 0 0 1 1 1 1 Hold 0 0 0 0 0 0 0 0 Setting/IRQ 000 001 010 011 100 101 110 111 Setup 0 0 1 1 1 1 1 1 Hold 0 0 0 0 0 0 0 0 Using Rising/Falling Edges of the CLK to Latch SYSREF The SYSREF signal can be latched on either the rising or falling edge of the encode clock, based on the value of register 0x03A[3] = 0 (latch on rising edge) or 0x03A[3] = 1 (latch on falling edge). This will not impact the analog input, which will always be sampled on the rising edge of the encode clock. For sampling SYSREF, the falling edge encode capture of CLK[N] will precede the rising edge encode capture of CLK[N], both corresponding to the same analog sample. For synchronous sampling of multiple converters using SYSREF, it may be possible to have a scenario shown in Figure 82. This case uses a SYSREF capture with the falling edge of the encode clock first to test the SYSREF position using the edge detection window. The three ADC's each receive a SYSREF input that may be skewed in time due to board trace length or source variance. For ADC[0] SYSREF meets SU/ HLD to CLK[N], ADC[1] misses SU/HLD to CLK[N], and ADC[2] is indeterminate as it falls within the SU/HLD window and may be latched by either CLK[N] or CLK[N + 1]. Rev. A | Page 41 of 66 AD9625 CLK+ Data Sheet CLOCK[N] FALLING CLOCK[N] RISING CLOCK[N + 1] FALLING CLK- SYSREF- ADC[0] SYSREF+ SYSREF- SYSREF+ ADC[1] ADC[2] 11814-487 SYSREF- ? SYSREF+ As a solution to this case, the SYSREF capture edge can be changed from falling to rising, which will still be captured to the analog sample from CLK[N]. When this is done, all three ADC's now meet the SU/HLD time for the rising edge capture of CLK[N]. CLOCK[N + 1] FALLING CLK- SYSREF- ADC[1] 11814-488 SYSREF- ADC[2] SYSREF+ Figure 83. Changing the Latching Edge to Rising for All Three ADCs, SYSREF Can Now be Aligned to CLK[N] Test Modes Bits[5:4] in Register 0x061 control the JESD204B interface test injection points. 00: 16-bit test generation data injected at the sample input to the link. 01: 10-bit test generation data injected at the output of the 8-bit/10-bit encoder (at the input to PHY). 10: 8-bit test generation data injected at the input of the scrambler. 11: reserved. Bits[3:0] in Register 0x061 determine the type of test patterns that are injected, as follows: SYSREF- ADC[0] SYSREF+ SYSREF+ CLK+ CLOCK[N] RISING JESD204B APPLICATION LAYERS The AD9625 supports the following application layer modes via Register 0x063[3:0]: Figure 82. SYSREF Case From Three ADCs Having Various Phase Delays Relative to the Falling Edge of the Encode Clock and will be Latched on Different Sample Clock Edges CLK[N] or CLK[N + 1] CLOCK[N] FALLING 0111: Ramp output (dependent on test injection point and number of bits, N). 1000: modified RPAT test sequence. 1001: unused. 1010: JSPAT test sequence. 1011: JTSPAT test sequence. 1100 to 1111: unused. 0000: normal operation (test mode disabled). 0001: alternating checkerboard. 0010: 1/0 word toggle. 0011: PN sequence: long (x23 + x18 + 1). 0101: continuous/repeat user test mode; most significant bits from 16-bit user pattern (1, 2, 3, 4) are placed on the output for one clock cycle and then repeated. (Output user pattern: 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, ....) 0110: single user test mode; most significant bits from the 16-bit user pattern (1, 2, 3, 4) placed on the output for one clock cycle and then outputs all zeros. (Output user pattern: 1, 2, 3, 4, then output all zeros.) 0100: fS x x mode which supports line rates at integer multiples of the sample rates 1000: single DDC mode, high bandwidth mode (only DDC 0 used) 1001: single DDC mode, low bandwidth mode (only DDC 0 used) 1010 to 1011: unused 1100: dual DDC mode, high bandwidth mode (both DDC 0 and DDC 1 used) 1101: dual DDC mode, low bandwidth mode (both DDC 0 and DDC 1 used) 1110: dual DDC mode, mixed bandwidth mode (DDC 0 high bandwidth mode, DDC 1 low bandwidth mode, samples repeated) fS x 2, fS x 4, fS x 8 Modes The JESD204B low multiplier mode application layer adds a rate conversion on top of a JESD204B transmitter/receiver with the following configuration parameters: M = 1; L = 8; S = 4; F = 1; N = 16; N' = 16; CS = 0; CF = 0; SCR = 0, 1; HD = 1; K = reference JESD204B specification. In this mode, there are five actual samples per frame and scrambling can be optionally enabled in the JESD204B interface. The transmit portion of the low multiplier mode JESD204B application layer is shown in Figure 84. The first step in this application layer is where 12-bit ADC samples are divided into six bytes. To allow the line rate of the JESD204B interface to map directly into an integer of the converter sample rate, a four to five rate conversion takes place to group the 12-bit ADC samples into blocks of five samples. During this rate conversion, for every five 12-bit ADC sample, an extra user defined, 4-bit nibble is appended to create a 64-bit frame. Next, the 64-bit low multiplier frame maps into the four 16-bit JESD204B samples. The most significant 16-bits of the 64-bit low multiplier frame map to the oldest 16-bit JESD204Bsample and the least significant 16-bits of the 64-bit low multiplier frame map to the most recent 16-bit JESD204B sample. The receive portion of the fS x 2 JESD204B application layer is shown in Figure 85. Rev. A | Page 42 of 66 Data Sheet AD9625 fS x 2 APPLICATION LAYER (TRANSMIT) ADC SAMPLE N + 2 (12 BITS) CONTROL BITS FOR SAMPLE N + 3 (CS = 0, 2 OR 4 BITS) ADC CONVERTER SAMPLE N + 3 (N = 8, 10 OR 12 BITS) CONTROL BITS FOR SAMPLE N + 2 (CS = 0, 2 OR 4 BITS) ADC CONVERTER SAMPLE N + 2 (N = 8, 10 OR 12 BITS) CONTROL BITS FOR SAMPLE N + 1 (CS = 0, 2 OR 4 BITS) ADC SAMPLE N + 1 (12 BITS) ADC SAMPLE N + 3 (12 BITS) 4/5 RATE EXCHANGE ADC SAMPLE N + 1 (12 BITS) JESD SAMPLE N + 1 (16 BITS) S[N][15:0] ADC SAMPLE N + 4 (4 BITS) (12 BITS) S[N + 1][7:0], S[N + 2][11:4] S[N + 2][3:0], S[N + 3][11:0] (16 BITS) (16 BITS) JESD SAMPLE N + 2 (16 BITS) S[N + 1][15:0] JESD SAMPLE N (16 BITS) JESD SAMPLE N + 3 (16 BITS) Figure 84. fS x 2 Mode Application Layer (Transmit) Rev. A | Page 43 of 66 LANE 7 LANE6 LANE 5 LANE 3 LANE 2 LANE 1 APPLICATION LAYER S[N + 4][11:0], UD[3:0] (16 BITS) JESD204x FRAMER + PHY (M = 1; L = 8; S = 4; F = 1; N = 16; N' = 16; CF = 0; SCR = 0, 1; HD = 1; K = SEE SPEC LANE 0 64-BITS @ fS/5 ADC SAMPLE N + 3 (12 BITS) S[N + 3][15:0] S[N][11:0], S[N + 1][11:8] (16 BITS) ADC SAMPLE N + 2 (12 BITS) S[N + 2][15:0] ADC SAMPLE N (12 BITS) LANE 4 64-BITS @ fS/5 USER DEFINED (FSYNC[3:0]) DATA LINK, TRANSPORT, AND PHY LAYERS 11814-032 ADC SAMPLE N (12 BITS) 48-BITS @ fS/4 ADC CONVERTER SAMPLE N + 1 (N = 8, 10 OR 12 BITS) CONTROL BITS FOR SAMPLE N (CS = 0, 2 OR 4 BITS) ADC CONVERTER SAMPLE N (N = 8, 10, OR 12 BITS) ADC AD9625 Data Sheet LANE 7 LANE6 LANE 4 LANE 3 LANE 2 LANE 1 LANE 0 LANE 5 fS x 2 APPLICATION LAYER (RECEIVE) DATA LINK, TRANSPORT, AND PHY LAYERS S[N + 2][15:0] S[N + 1][15:0] S[N][15:0] 64-BITS @ fS/5 S[N + 1][7:0], S[N + 2][11:4] S[N + 2][3:0], S[N + 3][11:0] (16 BITS) (16 BITS) S[N][11:0], S[N + 1][11:8] (16 BITS) 64-BITS @ fS/5 ADC SAMPLE N (12 BITS) JESD SAMPLE N + 3 (16 BITS) JESD SAMPLE N + 2 (16 BITS) JESD SAMPLE N + 1 (16 BITS) JESD SAMPLE N (16 BITS) S[N + 3][15:0] JESD204x FRAMER + PHY (M = 1; L = 8; S = 4; F = 1; N = 16; N' = 16; CF = 0; SCR = 0, 1; HD = 1; K = SEE SPEC ADC SAMPLE N + 1 (12 BITS) ADC SAMPLE N + 2 (12 BITS) ADC SAMPLE N + 3 (12 BITS) S[N + 4][11:0], UD[3:0] (16 BITS) ADC SAMPLE N + 4 (4 BITS) (12 BITS) APPLICATION LAYER USER DEFINED 4/5 RATE EXCHANGE CUSTOMER APPLICATION Figure 85. fS x 2 Application Layer (Receive) Rev. A | Page 44 of 66 11814-033 CONTROL BITS FOR SAMPLE N + 3 (CS = 0, 2 OR 4 BITS) ADC SAMPLE N + 3 (12 BITS) ADC CONVERTER SAMPLE N + 3 (N = 8, 10 OR 12 BITS) CONTROL BITS FOR SAMPLE N + 2 (CS = 0, 2 OR 4 BITS) ADC SAMPLE N + 2 (12 BITS) ADC CONVERTER SAMPLE N + 2 (N = 8, 10 OR 12 BITS) CONTROL BITS FOR SAMPLE N + 1 (CS = 0, 2 OR 4 BITS) ADC SAMPLE N + 1 (12 BITS) ADC CONVERTER SAMPLE N + 1 (N = 8, 10 OR 12 BITS) CONTROL BITS FOR SAMPLE N (CS = 0, 2 OR 4 BITS) ADC SAMPLE N (12 BITS) ADC CONVERTER SAMPLE N (N = 8, 10, OR 12 BITS) 48-BITS @ fS/4 Data Sheet AD9625 FRAME ALIGNMENT CHARACTER INSERTION Frame alignment character insertion (FACI) is defined in the register map (see the Memory Map Register section). Disable FACI only when it is used as a test feature. The FACI disable bit is located in Register 0x05F, Bit 1. Use the following settings: Setting Bit 1 to 0 = FACI enabled Setting Bit 1 to 1 = FACI disabled For applications requiring an optimal high power efficiency and low noise performance, it is recommended that ADP2386 switching regulator is used to convert the 12 V input rail into two intermediate rails (2.1 V and 3.6 V). These intermediate rails are then postregulated by very low noise, low dropout (LDO) regulators (ADP1740, ADP7104, and ADP125). Figure 86 shows the recommended method. ADP1740 12V INPUT THERMAL CONSIDERATIONS ADP2386 2.1V BUCK REGULATOR LDO ADP1740 LDO 1.3V: AVDD1 1.3V: DRVDD1 1.3V: DVDD1 Because of the high power nature of the device, it is critical to provide airflow and/or install a heat sink when operating at a high temperature. This ensures that the maximum case temperature does not exceed 85C. ADP2386 BUCK REGULATOR 3.6V ADP1740 LDO ADP1740 LDO 2.5V: AVDD2 2.5V: DRVDD2 2.5V: DVDD2 ADP125 LDO The AD9625 must be powered by the following two supplies: AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V. An optional DVDDIO and SPI_DVDDIO may be required at 2.5 V. Rev. A | Page 45 of 66 ADP125 LDO 2.5V: DVDDIO 2.5V: SPI_DVDDIO Figure 86. Power Supply Recommendation 11814-054 POWER SUPPLY CONSIDERATIONS AD9625 Data Sheet SERIAL PORT INTERFACE (SPI) The AD9625 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 25). The SCLK (serial clock) pin is used to synchronize the read and write data presented from/to the ADC. The SDIO (serial data input/output) pin is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 25. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial Clock. The serial shift clock input, which is used to synchronize serial interface, reads and writes. Serial Data Input/Output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip Select Bar. An active low control that gates the read and write cycles. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. Other modes involving the CSB pin are available. The CSB pin can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB pin can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued. This allows the SDIO pin to change direction from an input to an output. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a read operation, performing a read causes the SDIO pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or in LSB first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. HARDWARE INTERFACE The pins described in Table 25 comprise the physical interface between the user programming device and the serial port of the AD9625. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during read. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. Do not activate the SPI port during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9625 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Rev. A | Page 46 of 66 Data Sheet AD9625 MEMORY MAP Default Values READING THE MEMORY MAP REGISTER Each row in the memory map register contains eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x000 to Address 0x002); the transfer register (Address 0x0FF); and the ADC functions registers, including setup, control, and test (Address 0x008 to Address 0x13A). The memory map register tables provide the default hexadecimal value for each hexadecimal address that is listed. The column with the heading, Bit 7 (MSB), is the start of the default hexadecimal value given. For example, Address 0x14, the output mode register, has a hexadecimal default value of 0x01. This means that Bit 0 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Open and Reserved Locations All address and bit locations are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when a portion of an address location is open. If the entire address location is open, this address location should not be written. After the AD9625 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register tables. Logic Levels An explanation of logic level terminology follows: * * "Bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." "Clear a bit" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit." Transfer Register Map Register addresses for the AD9625 are shadowed. Register writes do not affect device operation until a transfer command is issued by writing 0x01 to Address 0x0FF, thereby setting the transfer bit. This allows the registers to update internally and simultaneously when the transfer bit is set. The internal update occurs when the transfer bit is set, and then the bit automatically clears. MEMORY MAP REGISTERS Address and bit locations that are not included in Table 26 through Table 116 are not currently supported for this device. Table 26. SPI Configuration Register, Address 0x000 (Default = 0x18) Bit No. 7 6 Access 5 RW 4 3 2 R R RW 1 RW 0 Unused RW Bit Description Unused. SPI least significant bit (LSB) first. 1: LSB shifted first for all SPI operations. For multibyte SPI operations, the addressing increments automatically. 0: most significant bit (MSB) shifted first for all SPI operations. For multibyte SPI operations, the addressing decrements automatically. Self clearing soft reset. 1: reset the SPI registers (self clearing). 0: do nothing. 13-bit addressing enabled. 13-bit addressing enabled. Self clearing soft reset. 1: reset the SPI registers(self clearing). 0: do nothing. SPI LSB first. 1: LSB shifted first for all SPI operations. For multi-byte SPI operations, the addressing increments automatically. 0: MSB shifted first for all SPI operations. For multi-byte SPI operations, the addressing decrements automatically. Unused. Table 27. Chip ID Register, Address 0x001 (Default = 0x41) Bit No. [7:0] Access R Bit Description Chip ID. Rev. A | Page 47 of 66 AD9625 Data Sheet Table 28. Chip Grade Register, Address 0x002 (Default = 0x14) Bit No. [7:6] [5:4] 3 [2:0] Access R R Bit Description Unused. Chip ID/speed grade. 10: 2.5 GSPS 01: 2.0 GSPS Unused. Chip die revision. 100: silicon revision code. 101 to 111: reserved. Table 29. Power Control Mode Register, Address 0x008 (Default = 0x80) Bit No. 7 6 5 [4:2] [1:0] Access RW Bit Description Reserved Reserved Reserved Reserved Chip power modes. 00: normal mode (power-up). 01: Power-down 10: standby mode; digital datapath clocks disabled, JESD204B interface enabled, outputs enabled. 11: digital datapath reset mode; digital data path clocks enabled, digital data path held in reset, JESD204B interface held in reset, outputs enabled. Table 30. PLL Status Register, Address 0x00A (Default = 0x00) Bit No. 7 Access RO [6:0] Bit Description PLL locked status bit. 0: PLL is unlocked. 1: PLL is locked. Reserved Table 31. ADC Test Control Register, Address 0x00D (Default = 0x00) Bit No. 7 Access RW 6 5 RW 4 [3:0] RW RW Bit Description ADC datapath user test mode control. Note: These bits are only used when Register 0x00D, Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000); otherwise, they are ignored. 0 = continuous/repeat pattern mode. Place each user pattern (1, 2, 3, 4) on the output for one clock cycle and then repeat. (Output user pattern: 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, ...) 1 = single pattern mode. Place each user pattern (1, 2, 3, 4) on the output for one clock cycle and then output all zeros. (Output user pattern: 1, 2, 3, 4, then output all zeros.) Unused. ADC long psuedo random number test generator reset. 0: long PN enabled. 1: long PN held in reset. Unused. ADC data output test generation mode. 0000: off, normal operation. 0001: midscale short. 0010: positive full scale. 0011: negative full scale. 0100: alternating checkerboard. 0101: PN sequence, long. 0110: unused. 0111: one-/zero-word toggle. 1000: user test mode. Used with Register 0x00D[7] and user pattern (1, 2, 3, 4) registers. 1001 to 1110: unused. 1111: ramp output. Rev. A | Page 48 of 66 Data Sheet AD9625 Table 32. Data Path Customer Offset Register, Address 0x010 (Default = 0x00) Bit No. [7:6] [5:0] Access RW Bit Description Unused. Digital datapath offset. Twos complement offset adjustment aligned with least converter resolution. 011111: +31 011110: +30 ... 000001: 1 000000: 0 111111: -1 ... 100001: -31 100000: -32 Table 33. Output Mode Register, Address 0x014 (Default = 0x01) Bit No. [7:5] 4 Access RW 3 2 RW [1:0] RW Bit Description Unused. Chip output disable. Bit 4 enables and disables the digital outputs from the ADC. 0: enable. 1: disable. Unused. Digital ADC sample invert. 0: ADC sample data is not inverted. 1: ADC sample data is inverted. Digital ADC data format select (DFS). Note: the use of the muxed SDIO pin to control Register 0x014[1:0] is not supported on the AD9625. 00: offset binary. 01: twos complement (default). 10: reserved. 11: reserved. Table 34. Serializer Output Adjust, Register, Address 0x015 (Default = 0x54) Bit No. 7 Access RW [6:5] RW [4:0] RW Bit Description Serializer output polarity selection. 0: normal, not inverted. 1: output driver polarity inverted. Serializer output emphasis amplitude control. 00: 0 mV de-emphasis differential p-p. 01: 160 mV de-emphasis differential p-p. 10: 80 mV de-emphasis differential p-p. 11: 40 mV de-emphasis differential p-p. Reserved. Table 35. User Test Pattern 1 LSB Register, Address 0x019 (Default = 0x00) Bit No. [7:0] Access RW Bit Description User Test Pattern 1 least significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000), or when Register 0x061, Bits[3:0] is in the scrambler or 10-bit test modes (Register 0x061[3:0] = 0100 to 0111). Otherwise, these bits are ignored. Table 36. User Test Pattern 1 MSB Register, Address 0x01A (Default = 0x00) Bit No. [7:0] Access RW Bit Description User Test Pattern 1 most significant byte. Note: These bits are used only when Register 0x00D, Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored. Rev. A | Page 49 of 66 AD9625 Data Sheet Table 37. User Test Pattern 2 LSB Register, Address 0x01B (Default = 0x00) Bit No. [7:0] Access RW Bit Description User Test Pattern 2 least significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored. Table 38. User Test Pattern 2 MSB Register, Address 0x01C (Default = 0x00) Bit No. [7:0] Access RW Bit Description User Test Pattern 2 most significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored. Table 39. User Test Pattern 3 LSB Register, Address 0x01D (Default = 0x00) Bit No. [7:0] Access RW Bit Description User Test Pattern 3 least significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored. Table 40. User Test Pattern 3 MSB Register, Address 0x01E (Default = 0x00) Bit No. [7:0] Access RW Bit Description User Test Pattern 3 most significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored. Table 41. User Test Pattern 4 LSB Register, Address 0x01F (Default = 0x00) Bit No. [7:0] Access RW Bit Description User Test Pattern 4 least significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored. Table 42. User Test Pattern 4 MSB Register, Address 0x020 (Default = 0x00) Bit No. [7:0] Access RW Bit Description User Test Pattern 4 most significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored. Table 43. Synthesizer PLL Control Register, Address 0x021 (Default = 0x00) Bit No. [7:5] 4 3 [2:0] Access RW RW Bit Description Unused. 1 = force power-down of VCO LDO Reserved for future use. Unused. Table 44. ADC Analog Input Control Register, Address 0x02C (Default = 0x00) Bit No. [7:3] 2 Access RW [1:0] Bit Description Unused. Set function on VMON pin. 0: unused. 1: allows external reference on VMON pin. Unused. Table 45. SYSREF Control Register, Address 0x03A (Default = 0x00) Bit No. 7 Access RW 6 RW 5 Bit Description SYSREF status bit replaces the LSB from the converter. 0: normal mode. 1: SYSREF status bit replaces the LSB. SYSREF status bit flag reset. To use the flags, Register 0x03A, Bit 1 must be set to high. 0: normal flag operation. 1: SYSREF status bit flags held in reset. Unused. Rev. A | Page 50 of 66 Data Sheet Bit No. 4 Access RW 3 RW 2 RW 1 RW 0 AD9625 Bit Description SYSREF transition selection. 0: SYSREF is valid on low to high transitions using selected CLK edge. 1: SYSREF is valid on high to low transitions using selected CLK edge. SYSREF capture edge selection. 0: captured on rising edge of CLK input. 1: captured on falling edge of CLK input. SYSREF next mode. 0: continuous mode. 1: next SYSREF mode: uses the next valid edge only of the SYSREF pin. Subsequent edges of the SYSREF pin are ignored. When the next system reference is found, Bit 1 of Register 0x03A clears. SYSREF pins enable. 0: SYSREF disabled. 1: SYSREF enabled. When Register 0x03A, Bit 2 = 1, only the next valid edge of the SYSREF pins is used. Subsequent edges of the SYSREF pin are ignored. Unused. Table 46. Fast Detect Control Register, Address 0x045 (Default = 0x00) Bit No. [7:4] 3 Access 2 1 0 RW RW RW Bit Description Unused. Force the fast detect output pin. 0: normal operation of fast detect pin. 1: force a value on the fast detect pin (see Bit 2 in this table, Table 46). The fast detect output pin is set to the value in this bit (Register 0x045[2]) when the output is forced. Unused. Enable fast detect on the corrected ADC data. 0: fine fast detect disabled. 1: fine fast detect enabled. Table 47. Fast Detect Upper Threshold Register, Address 0x047 (Default = 0x00) Bit No. [7:0] Access RW Bit Description These bits are the LSBs of the fast detect upper threshold. These eight LSBs of the programmable 12-bit upper threshold are compared to the fine ADC magnitude. Table 48. Fast Detect Upper Threshold Register, Address 0x048 (Default = 0x00) Bit No. [7:4] [3:0] Access RW Bit Description Unused. These bits are the MSBs of the fast detect upper threshold. These four MSBs of the programmable 12-bit upper threshold are compared to the fine ADC magnitude. Table 49. Fast Detect Lower Threshold Register, Address 0x049 (Default = 0x00) Bit No. [7:0] Access RW Bit Description These bits are the LSBs of the fast detect lower threshold. These eight LSBs of the programmable 12-bit lower threshold are compared to the fine ADC magnitude. Table 50. Fast Detect Lower Threshold Register, Address 0x04A (Default = 0x00) Bit No. [7:4] [3:0] Access RW Bit Description Unused. MSBs of the fast detect lower threshold. These four MSBs of the programmable 12-bit lower threshold are compared to the fine ADC magnitude. Table 51. Fast Detect Dwell Time Counter Threshold Register, Address 0x04B (Default = 0x00) Bit No. [7:0] Access RW Bit Description These bits are the LSBs of the fast detect dwell time counter target. This is the value for a 16-bit counter that determines the length of time that the ADC data must remain below the lower threshold before the FD pin reset to 0. Rev. A | Page 51 of 66 AD9625 Data Sheet Table 52. Fast Detect Dwell Time Counter Threshold Register, Address 0x04C (Default = 0x00) Bit No. [7:0] Access RW Bit Description These bits are the MSBs of the fast detect dwell time counter target. This is the value for a 16-bit counter that determines the length of time that the ADC data must remain below the lower threshold before the FD pin resets to 0. Note that the fast detect (FD) pin de-asserts after the ADC codes stay below the lower target for the number of samples indicated by the value in Register 0x04C[7:0]. Table 53. JESD204B Quick Configuration Register, Address 0x05E (Default = 0x00) Bit No. [7:0] Access RW Bit Description JESD204B serial quick configuration (self clearing). This register is self clearing and does not control anything in the AD9625 directly; it only changes the value of the other JESD240B registers that control the chip. Because this register is self clearing, it always returns to 000 after each write. To use the quick configuration feature, write to this register first, then, if there are any changes that need to be made to any of the following settings, write to the other JESD204B registers. 0x00: configuration determined by other registers. Because the register is self clearing, it always returns to this value after each write. 0x01: reserved. 0x02: Generic 2 Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xB; Register 0x073[4:0] = 0xF. 0x04: Generic 4 Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x3; Register 0x072[4:0] = 0xB; Register 0x073[4:0] = 0xF. 0x06: Generic 6 Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x5; Register 0x072[4:0] = 0xB; Register 0x073[4:0] = 0xB. 0x08: Generic 8 Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x7; Register 0x072[4:0] = 0xB; Register 0x073[4:0] = 0xF. 0x42: reserved. 0x44: reserved. 0x48: fS x 2 mode, eight lanes. Register 0x063[3:0] = 0x4; Register 0x06E[4:0] = 0x7; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. 0x81: 1 DDC (high BW), one lane. Register 0x063[3:0] = 0x8; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. 0x82: 1 DDC (high BW), two lanes. Register 0x063[3:0] = 0x8; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. 0x91: 1 DDC (low BW), one lane. Register 0x063[3:0] = 0x9; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. 0xC1: 2 DDCs (high BW), one lane. Register 0x063[3:0] = 0xC; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. 0xC2: 2 DDCs (high BW), two lanes. Register 0x063[3:0] = 0xC; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. 0xC4: 2 DDCs (high BW), four lanes. Register 0x063[3:0] = 0xC; Register 0x06E[4:0] = 0x3; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. 0xD1: 2 DDCs (low BW), one lane. Register 0x063[3:0] = 0xD; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. 0xD2: 2 DDCs (low BW), two lanes. Register 0x063[3:0] = 0xD; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. 0xE1: 2 DDCs (mixed BW), one lane. Register 0x063[3:0] = 0xE; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. 0xE2: 2 DDCs (mixed BW), two lanes. Register 0x063[3:0] = 0xE; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. 0xE4: 2 DDCs (mixed BW), four lanes. Register 0x063[3:0] = 0xE; Register 0x06E[4:0] = 0x3; Register 0x072[4:0] = 0xF; Register 0x073[4:0] = 0xF. All other values have no effect. Rev. A | Page 52 of 66 Data Sheet AD9625 Table 54. JESD204B Link Control Register 1, Address 0x05F (Default = 0x14) Bit No. 7 6 Access 5 RW 4 RW [3:2] RW 1 RW 0 RW RW Bit Description Unused. JESD204B serial tail bit, PN, enable. Note: the following equation can be used to determine the number of PN bits sent per sample = N' - N - CS (the number of control bits per sample). 0: serial tail bit, PN, disabled. Unused extra tail bits are padded with zeros. 1: serial tail bit, PN, enabled. Unused extra tail bits are padded with a pseudo random number sequence from a 31-bit LFSR (see JESD204B 5.1.4). JESD204B serial test sample enable. 0: JESD204B test samples disabled. 1: JESD204B test samples enabled. The transport layer test sample sequence (as specified in JESD204B Section 5.1.6.2) is sent on all link lanes. JESD204B serial lane synchronization enable. Note that the frame character insertion must be enabled (Register 0x05F[1] = 0) to enable lane synchronization. 0: lane synchronization disabled. Both sides do not perform lane synchronization; frame alignment character insertion always uses /K28.7/ control characters (see JESD204B 5.3.3.4). 1: lane synchronization enabled. Both sides perform lane sync; frame alignment character insertion uses either /K28.3/ or /K28.7/ control characters (see JESD204B 5.3.3.4). JESD204B serial initial lane alignment sequence mode. 00: initial lane alignment sequence disabled (JESD204B 5.3.3.5). 01: initial lane alignment sequence enabled (JESD204B 5.3.3.5). 10: reserved. 11: initial lane alignment sequence always on test mode; the JESD204B data link layer test mode (where repeated lane alignment sequence, as specified in JESD204B section 5.3.3.9.2) is sent on all lanes. JESD204B serial frame alignment character insertion (FACI) disable. 0: frame alignment character insertion enabled (JESD204B 5.3.3.4). 1: frame alignment character insertion disabled. Note that this is for debug only (JESD204B 5.3.3.4). JESD204B serial transmit link power-down (active high). Note that the JESD204B transmitter link must be powered down while changing any of the link configuration bits. 0: JESD204B serial transmit link enabled. Transmission of the /K28.5/ characters for code group synchronization is controlled by the SYNCINB pins. 1: JESD204B serial transmit link powered down (held in reset and clock gated). Table 55. JESD204B Link Control Register 2, Address 0x060 (Default = 0x00) Bit No. [7:6] Access RW 5 RW [4:3] 2 RW 1 RW 0 RW Bit Description JESD204B serial synchronization mode. 00: normal mode. 01: reserved. 10: SYNCINB active mode. SYNCINB pins are active: force code group synchronization. 11: SYNCINB pins disabled. JESD204B serial synchronization pin invert. 0: SYNCINB pins not inverted. 1: SYNCINB pins inverted. Unused. JESD204B Serial 8-bit/10-bit bypass (test mode only). 0: 8-bit/10-bit enabled. 1: 8-bit/10-bit bypassed (most significant two bits are 0). JESD204B 10-bit serial transmit bit invert. Note that in the event that the CML signals are reversed in a system board layout, this bit effectively inverts the differential outputs from the PHY. 0: normal. 1: invert the a, b, c, d, e, f, g, h, i, j bits. JESD204B 10-bit serial transmit bit mirror. 0: 10-bit serial bits are not mirrored. Transmit bit order is alphabetical: a, b, c, d, e, f, g, h, i, j. 1: 10-bit serial bits are mirrored. Transmit bit order is alphabetically reversed: j, i, h, g, f, e, d, c, b, a. Rev. A | Page 53 of 66 AD9625 Data Sheet Table 56. JESD204B Link Control Register 3, Address 0x061 (Default = 0x00) Bit No. 7 Access RW 6 RW [5:4] RW [3:0] RW Bit Description JESD204B checksum disable. 0: checksum enabled in the link configuration parameter. Normal operation. 1: checksum disabled in the link configuration parameter (set to zero). For testing purposes only. JESD204B checksum mode. 0: checksum is the sum of all 8-bit registers in the link configuration fields. 1: checksum is the sum of all individual link configuration fields (LSB aligned). JESD204B serial test generation input selection. 00: 16-bit test generation data injected at the sample input to the link. 01: 10-bit test generation data injected at the output of the 8-bit/10-bit encoder (at the input to PHY). 10: 8-bit test generation data injected at the input of the scrambler. 11: reserved. JESD204B serial test generation mode. 0000: normal operation (test mode disabled). 0001: alternating checkerboard. 0010: 1/0 word toggle. 0011: PN sequence (long). 0100: unused. 0101: continuous/repeat user test mode. The most significant bits from the user pattern (1, 2, 3, 4) are placed on the output for one clock cycle and then repeated (the output user pattern is 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, ...). 0110: single user test mode. The most significant bits from the user pattern (1, 2, 3, 4) are placed on the output for one clock cycle and then output all zeros (the output user pattern is 1, 2, 3, 4, and then outputs all zeros). 0111: ramp output. 1000: modified RPAT test sequence (10-bit value). 1001: unused. 1010: JSPAT test sequence (10-bit value). 1011: JTSPAT test sequence (10-bit value). 1100 to 1111: unused. Table 57. JESD204B Link Control Register 4, Address 0x062 (Default 0x00) Bit No. [7:0] Access RW Bit Description Initial lane alignment sequence repeat count. Bits[7:0] specify the number of times the initial lane alignment sequence repeats. For ADCs, the JESD204B specification states that the initial lane alignment sequence always spans four multiframes (JESD204B 5.3.3.5). Because Register 0x070, Bits[4:0] determine the number of frames per multiframe, the total number of frames transmitted during the initial lane alignment sequence = 4 x (Register 0x070[4:0] + 1) x (Register 0x062[7:0] + 1). Table 58. JESD204B Link Control Register 5, Address 0x063 (Default = 0x80) Bit No. 7 [6:4] [3:0] Access RW Bit Description Reserved Reserved JESD204B application layer mode. DDC bandwidth modes are as follows: high bandwidth, decimate by 8 (effective output bandwidth = fS/10) and low bandwidth, decimate by 16 (effective output bandwidth = fS/20). 0000: generic (no application layer used). 0001: unused. 0010: unused. 0011: unused. 0100: fS x x mode (where x is an integer: 2, 4, 8). 0101 to 0111: unused. 1000: single DDC mode (high bandwidth mode (only DDC0 used). 1001: single DDC mode (low bandwidth mode (only DDC0 used). 1010 to 1011: unused. 1100: dual DDC mode, high bandwidth mode (both DDC 0 and DDC 1 used). 1101: dual DDC mode, low bandwidth mode (both DDC 0 and DDC 1 used). 1110: dual DDC mode, mixed bandwidth mode (DDC 0 high bandwidth mode, DDC 1 low bandwidth mode, samples repeated). 1111: unused. Rev. A | Page 54 of 66 Data Sheet AD9625 Table 59. JESD204B Configuration Register, Address 0x064 (Default = 0x00) Bit No. [7:0] Access RW Bit Description JESD204B serial device identification (DID) number. Table 60. JESD204B Configuration Register, Address 0x065 (Default = 0x00) Bit No. [7:4] [3:0] Access RW Bit Description Unused. JESD204B serial bank identification (BID) number (extension to DID). Table 61. JESD204B Configuration Register, Address 0x066 (Default = 0x00) Bit No. [7:5] [4:0] Access RW Bit Description Unused. JESD204B serial lane identification (LID) number for Lane 0. Table 62. JESD204B Configuration Register, Address 0x067 (Default = 0x01) Bit No. [7:5] [4:0] Access RW Bit Description Unused. JESD204B serial lane identification (LID) number for Lane 1. Table 63. JESD204B Configuration Register, Address 0x068 (Default = 0x02) Bit No. [7:5] [4:0] Access RW Bit Description Unused. JESD204B serial lane identification (LID) number for Lane 2. Table 64. JESD204B Configuration Register, Address 0x069 (Default = 0x03) Bit No. [7:5] [4:0] Access RW Bit Description Unused. JESD204B serial lane identification (LID) number for Lane 3. Table 65. JESD204B Configuration Register, Address 0x06A (Default = 0x04) Bit No. [7:5] [4:0] Access RW Bit Description Unused. JESD204B serial lane identification (LID) number for Lane 4. Table 66. JESD204B Configuration Register, Address 0x06B (Default = 0x05) Bit No. [7:5] [4:0] Access RW Bit Description Unused. JESD204B serial lane identification (LID) number for Lane 5. Table 67. JESD204B Configuration Register, Address 0x06C (Default = 0x06) Bit No. [7:5] [4:0] Access RW Bit Description Unused. JESD204B serial lane identification (LID) number for Lane 6. Table 68. JESD204B Configuration Register, Address 0x06D (Default = 0x07) Bit No. [7:5] [4:0] Access RW Bit Description Unused. JESD204B serial lane identification (LID) number for Lane 7. Table 69. JESD204B Configuration Register, Address 0x06E (Default = 0x87) Bit No. 7 [6:5] Access RW Bit Description JESD204B serial scrambler mode. 0: JESD204B scrambler disabled (SCR = 0). 1: JESD204B scrambler enabled (SCR = 1). Unused. Rev. A | Page 55 of 66 AD9625 Data Sheet Bit No. [4:0] Access RW Bit Description JESD204B serial lane control (L = Register 0x06E[4:0] + 1). 0: one lane per link (L = 1). 1:two lanes per link (L = 2). 2: unused. 3: four lanes per link (L = 4). 4: unused. 5: six lanes per link (L = 6). 6: unused. 7: eight lanes per link (L = 8). 8 to 31: unused. Table 70. JESD204B Configuration Register, Address 0x06F (Default = 0x00) Bit No. [7:0] Access RO Bit Description JESD204B number of octets per frame (F = Register 0x06F[7:0] + 1). These bits are calculated using the following equation: F = (N)/(2 x L) The following are valid values of F: M = 1, S = 4, N' = 16, L = 1, F = 8. M = 1, S = 4, N' = 16, L = 2, F = 4. M = 1, S = 4, N' = 16, L = 4, F = 2. M = 1, S = 4, N' = 12, L = 6, F = 1. M = 1, S = 4, N' = 16, L = 8, F = 1 (default). Table 71. JESD204B Configuration Register, Address 0x070 (Default = 0x1F) Bit No. [7:5] [4:0] Access RW Bit Description Unused. JESD204B number of frames per multiframe (K = Register 0x070[4:0] + 1). Only those values that are divisible by four can be used. Table 72. JESD204B Configuration Register, Address 0x071 (Default = 0x00) Bit No. [7:0] Access RO Bit Description JESD204B number of converters per link/device. 0: link connected to one ADC (M = 1). 1 to 255: unused. Table 73. JESD204B Configuration Register, Address 0x072 (Default = 0x0B) Bit No. [7:6] Access RW 5 [4:0] RW Bit Description JESD204B number of control bits per sample (CS, based on the JESD204B specification). 00: no control bits sent per sample (CS = 0). 01: one control bit sent per sample, overrange bit enabled (CS = 1). 10: two control bits sent per sample, overrange + timestamp SYSREF bit (CS = 2). 11: reserved. Unused. JESD204B converter resolution (N = Register 0x072[4:0] + 1). 0x00 to 0x06: reserved. 0x07 to 0x09: reserved. 0x0A: reserved. 0x0B: N = 12-bit ADC converter resolution. 0x0C to 0x0E: reserved. 0x0F: N = 16-bit ADC converter resolution. 0x10 to 0x1F: reserved. Rev. A | Page 56 of 66 Data Sheet AD9625 Table 74. JESD204B Configuration Register, Address 0x073 (Default = 0x2F) Bit No. [7:5] Access RW [4:0] RW Bit Description JESD204B device subclass version. 0x0: Subclass 0. 0x1: Subclass 1 (default). 0x2: Subclass 2 (not supported). 0x3: undefined. JESD204B total number of bits per sample (N' = Register 0x073[4:0] + 1). 0x0 to 0xA: unused. 0xB: N' = 12 (L must be equal to 6). 0xC to 0xE: unused. 0xF: N'=16 (L must be equal to 1, 2, 4, or 8). Table 75. JESD204B Configuration Register, Address 0x074 (Default = 0x23) Bit No. [7:5] Access RW [4:0] RO Bit Description JESD204B version. 0x0: JESD204A. SYNCINB pins input are internally gated by the frame clock. SYNCINB must be low for at least two frame clock cycles to be interpreted as a synchronization request. 0x1: JESD204B. SYNCINB pins input are internally gated by the local multiframe clock. SYNCINB must be low for at least four frame clock cycles to be interpreted as a synchronization request. 0x2 to 0x7: undefined. JESD204B samples per converter frame cycle (S = Register 0x074[4:0] + 1). These are read-only bits. For the AD9625, S must be equal to 4 (Register 0x074[4:0] = 3). Table 76. JESD204B Configuration Register, Address 0x075 (Default = 0x80) Bit No. 7 Access RO [6:5] [4:0] RO Bit Description JESD204B high density (HD) format. This is a read-only bit. 0: HD format disabled. 1: HD format enabled. High density mode is automatically enabled based on the values of N' and L. The values of HD for the AD9625 are as follows: N' = 16, L = 1, HD = 0. N' = 16, L = 2, HD = 0. N' = 16, L = 4, HD = 0. N' = 12, L = 6, HD = 1. N' = 16, L = 8, HD = 1 (default). Unused. JESD204B Number of control words per frame clock cycle per link (CF). These are read-only bits. For the AD9625, CF must equal 0 (Register 0x075[4:0] = 0). Table 77. JESD204B Configuration Register, Address 0x076 (Default = 0x00) Bit No. [7:0] Access RW Bit Description JESD204B Serial Reserved Field 1. Table 78. JESD204B Configuration Register, Address 0x077 (Default = 0x00) Bit No. [7:0] Access RW Bit Description JESD204B Serial Reserved Field 2. Table 79. JESD204B Configuration Register, Address 0x078 (Default = 0xC3) Bit No. [7:0] Access RO Bit Description JESD204B serial checksum value for Lane 0. This value is automatically calculated The value = (the sum of all link configuration parameters for Lane 0) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7. Table 80. JESD204B Configuration Register, Address 0x079 (Default = 0xC4) Bit No. [7:0] Access RO Bit Description JESD204B serial checksum value for Lane 1. This value is automatically calculated. The value = (the sum of all link configuration parameters for Lane 1) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7. Rev. A | Page 57 of 66 AD9625 Data Sheet Table 81. JESD204B Configuration Register, Address 0x07A (Default = 0xC5) Bit No. [7:0] Access RO Bit Description JESD204B serial checksum value for Lane 2. This value is automatically calculated. The value = (the sum of all link configuration parameters for Lane 2) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7. Table 82. JESD204B Configuration Register, Address 0x07B (Default = 0xC6) Bit No. [7:0] Access RO Bit Description JESD204B serial checksum value for Lane 3. This value is automatically calculated. The value = (the sum of all link configuration parameters for Lane 3) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7. Table 83. JESD204B Configuration Register, Address 0x07C (Default = 0xC7) Bit No. [7:0] Access RO Bit Description JESD204B serial checksum value for Lane 4. This value is automatically calculated. The value = (the sum of all link configuration parameters for Lane 4) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7. Table 84. JESD204B Configuration Register, Address 0x07D (Default = 0xC8) Bit No. [7:0] Access RO Bit Description JESD204B serial checksum value for Lane 5. This value is automatically calculated. The value = (the sum of all link configuration parameters for Lane 5) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7. Table 85. JESD204B Configuration Register, Address 0x07E (Default = 0xC9) Bit No. [7:0] Access RO Bit Description JESD204B serial checksum value for Lane 6. This value is automatically calculated. The value = (the sum of all link configuration parameters for Lane 6) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7. Table 86. JESD204B Configuration Register, Address 0x07F (Default = 0xCA) Bit No. [7:0] Access RO Bit Description JESD204B serial checksum value for Lane 6. This value is automatically calculated. The value = (the sum of all link configuration parameters for Lane 6) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7. Table 87. JESD204B Lane Power-Down Register, Address 0x080 (Default = 0x00) Bit No. 7 Access RW 6 RW 5 RW 4 RW 3 RW 2 RW 1 RW 0 RW Bit Description Physical Lane H power-down. 0: Lane H enabled. 1: Lane H powered down. Physical Lane G power-down. 0: Lane G enabled. 1: Lane G powered down. Physical Lane F power-down. 0: Lane F enabled. 1: Lane F powered down. Physical Lane E power-down. 0: Lane E enabled. 1: Lane E powered down. Physical Lane D power-down. 0: Lane D enabled. 1: Lane D powered down. Physical Lane C power-down. 0: Lane C enabled. 1: Lane C powered down. Physical Lane B power-down. 0: Lane B enabled. 1: Lane B powered down. Physical Lane A power-down. 0: Lane A enabled. 1: Lane A powered down. Rev. A | Page 58 of 66 Data Sheet AD9625 Table 88. JESD204B Lane Control Register 1, Address 0x082 (Default = 0x10) Bit No. 7 [6:4] 3 [2:0] Access RW RW Bit Description Unused. Physical Lane B assignment. 000: Logical Lane 0. 001: Logical Lane 1 (default). 010: Logical Lane 2. 011: Logical Lane 3. 100: Logical Lane 4. 101: Logical Lane 5. 110: Logical Lane 6. 111: Logical Lane 7. Unused. Physical Lane A assignment. 000: Logical Lane 0 (default). 001: Logical Lane 1. 010: Logical Lane 2. 011: Logical Lane 3. 100: Logical Lane 4. 101: Logical Lane 5. 110: Logical Lane 6. 111: Logical Lane 7. Table 89. JESD204B Lane Control Register 2, Address 0x083 (Default = 0x32) Bit No. 7 [6:4] Access RW 3 [2:0] RW Bit Description Unused. Physical Lane D assignment. 000: Logical Lane 0. 001: Logical Lane 1. 010: Logical Lane 2. 011: Logical Lane 3 (default). 100: Logical Lane 4. 101: Logical Lane 5. 110: Logical Lane 6. 111: Logical Lane 7. Unused. Physical Lane C assignment. 000: Logical Lane 0. 001: Logical Lane 1. 010: Logical Lane 2 (default). 011: Logical Lane 3. 100: Logical Lane 4. 101: Logical Lane 5. 110: Logical Lane 6. 111: Logical Lane 7. Rev. A | Page 59 of 66 AD9625 Data Sheet Table 90. JESD204B Lane Control Register 3, Address 0x084 (Default = 0x54) Bit No. 7 [6:4] 3 [2:0] Access Bit Description Unused. Physical Lane F assignment. 000: Logical Lane 0. 001: Logical Lane 1. 010: Logical Lane 2. 011: Logical Lane 3. 100: Logical Lane 4. 101: Logical Lane 5 (default). 110: Logical Lane 6. 111: Logical Lane 7. Unused. Physical Lane E assignment. 000: Logical Lane 0. 001: Logical Lane 1. 010: Logical Lane 2. 011: Logical Lane 3. 100: Logical Lane 4 (default). 101: Logical Lane 5. 110: Logical Lane 6. 111: Logical Lane 7. RW RW Table 91. JESD204B Lane Control Register 4, Address 0x085 (Default = 0x76) Bit No. 7 [6:4] Access RW 3 [2:0] RW Bit Description Unused. Physical Lane H assignment. 000: Logical Lane 0. 001: Logical Lane 1. 010: Logical Lane 2. 011: Logical Lane 3. 100: Logical Lane 4. 101: Logical Lane 5. 110: Logical Lane 6. 111: Logical Lane 7 (default). Unused. Physical Lane G assignment. 000: Logical Lane 0. 001: Logical Lane 1. 010: Logical Lane 2. 011: Logical Lane 3. 100: Logical Lane 4. 101: Logical Lane 5. 110: Logical Lane 6 (default). 111: Logical Lane 7. Table 92. Unused, Address 0x088 (Default = 0x67) Bit No. [7:0] Access RW Bit Description Unused. Table 93. Unused, Address 0x089 (Default = 0xF0) Bit No. [7:0] Access RW Bit Description Unused. Rev. A | Page 60 of 66 Data Sheet AD9625 Table 94. Control Register, Address 0x08A (Default = 0x20) Bit No. [7:6] [5:4] [3:2] [1:0] Access RW RW Bit Description Unused. Reserved; Bits[5:4] must be set to 10. Unused. Reserved; Bits[1:0] must be set to 00. Table 95. JESD204B Local Multiframe Clock Offset Control Register, Address 0x08B (Default = 0x00) Bit No. [7:5] [4:0] Access RW Bit Description Unused. Local multiframe clock (LMFC) phase offset value. These bits provide the reset value for LMFC phase counter when SYSREF pins are asserted; this is used for deterministic delay applications. Table 96. JESD204B Local Frame Clock Offset Control Register, Address 0x08C (Default = 0x00) Bit No. [7:0] Access RW Bit Description Local frame clock phase offset value. Reset value for frame clock phase counter when SYSREF pins are asserted. For the AD9625, only values from 0 to 7 are valid. This is used for deterministic delay applications. Table 97. DIVCLK Register, Address 0x0F8 (Default = 0x00) Bit No. [7:1] 0 Access RW RW Bit Description Spare customer register. Register control to set the ratio between ADC sampling clock and DIVCLK. 0 = divide by 4. 1 = not used. Table 98. Reserved Register, Address 0x0F9 Bit No. [7:0] Access RW Bit Description Reserved Table 99. Customer Spare Register, Address 0x0FF (Default = 0x00) Bit No. [7:1] 0 Access RW Bit Description Unused. Register map master/slave transfer bit. Self-clearing bit used to synchronize the transfer of data from the master to the slave registers. 0: no effect. 1: transfers data from the master registers, written by the register maps, to the slave registers. Table 100. Interrupt Request (IRQ) Status Register, Address 0x100 (Default = 0x00) Bit No. 7 Access RO 6 5 4 3 RO RO RO 2 RO 1 0 RO Bit Description Interrupt request PLL lock error. 1: the PLL is unlocked. Unused. Unused. Unused. Interrupt request SYSREF hold error. 1: a hold error has occurred with the last SYSREF signal received. To clear this error, set and clear Bit 6 in Register 0x03A. Interrupt request SYSREF setup error. 1: a setup error has occurred with the last SYSREF signal received. To clear this error, set and clear Bit 6 in Register 0x03A. Unused. Interrupt request clock error. Rev. A | Page 61 of 66 AD9625 Data Sheet Table 101. Interrupt Request (IRQ) Mask Control Register, Address 0x101 (Default = 0xBC) Bit No. 7 Access RW 6 5 4 3 RW RW RW 2 RW 1 0 RW Bit Description Interrupt request PLL lock error masked. 1: PLL unlocked events are masked. Unused. Must be set to 1. Must be set to 1. Interrupt request SYSREF hold error. 1: a hold error has occurred with the last SYSREF signal received. To clear this error, set and clear Bit 6 in Register 0x03A. Interrupt request SYSREF setup error. 1: a setup error has occurred with the last SYSREF signal received. To clear this error, set and clear Bit 6 in Register 0x03A. Unused. Interrupt request clock error mask. 1: clock error has occurred and the validity of the output data cannot be guaranteed. The only way to recover from this error is to reset the device. Table 102. Digital Control Register, Address 0x105 (Default = 0x00) Bit No. [7:5] 4 3 2 1 0 Access RW RW RW RW RW Bit Description Unused. Must be set to 0. Must be set to 0. Must be set to 0. Must be set to 0. Must be set to 0. Table 103. Digital Calibration Threshold Control Register, Address 0x10A (Default = 0x10) Bit No. [7:5] 4 [0:3] Access RW Bit Description Unused. Enable data set threshold logic for background gain. Unused. Table 104. Digital Calibration Data Set Threshold Register, Address 0x10D (Default = 0x3D) Bit No. [7:0] Access RW Bit Description Data set threshold for background gain calibration. Table 105. Digital Calibration Data Set Threshold Register, Address 0x10E (Default = 0x14) Bit No. [7:0] Access RW Bit Description Data set threshold for background gain calibration. Table 106. DIVCLK Output Control Register, Address 0x120 (Default = 0x11) Bit No. [7:5] 4 Access 3 RW 2 [1:0] RW RW Bit Description Unused. DIVCLK output disable. DIVCLK is 1/4th of the sample clock frequency. 0: DIVCLK output is disabled. 1: DIVCLK output is enabled. DIVCLK output termination selection. 0: DIVCLK output uses an external 100 resistive termination. 1: DIVCLK output uses no external resistive termination. Unused. Control the differential swing for the DIVCLK output. 00 = 100 mV p-p differential. 01 = 200 mV p-p differential. 10 = 300 mV p-p differential. 11 = 400 mV p-p differential. Rev. A | Page 62 of 66 Data Sheet AD9625 Table 107. Trim Setting Control Register, Address 0x121 (Default = 0x00 for AD9625-2.5; Default = 0x03 for AD9625-2.0) Bit No. [7:2] [1:0] Access RW Bit Description Reserved. Select trim setting, based on sample rate: 00 = Trim 0: for 2.5 GSPS encode rate (default for AD9625-2.5) 01 = Trim 1: for 2.4 GSPS to 2.5 GSPS encode rate 10 = Trim 2: for 2.2 GSPS to 2.4 GSPS encode rate 11 = Trim 3: for 330 MSPS to 2.2 GSPS encode rate (default for AD9625-2.0) Table 108. Unused Register, Address 0x12A (Default = 0x05) Bit No. [7:0] Access RW Bit Description Reserved; maintain default setting of 0x05. Table 109. DDC 0 Gain Control Register, Address 0x130 (Default = 0x00) Bit No. [7:6] [5:4] Access RW [3:2] [1:0] RW Bit Description Unused. DDC 0 polyphase (decimate by 2) gain in units of 6 dB. 00: 0 dB gain. 01: 6 dB gain. 10: 12 dB gain. 11: 18 dB gain. Unused. DDC 0 polyphase (decimate by 8) gain in units of 6 dB. 00: 0 dB gain. 01: 6 dB gain. 10: 12 dB gain. 11: 18 dB gain. Table 110. DDC 0 Phase Increment Least Significant Bits Register, Address 0x131 (Default = 0x00) Bit No. [7:0] Access RW Bit Description DDC 0 NCO phase increment value. Phase increment for the NCO within DDC 0. The output frequency = (decimal(Register 0x132[1:0]; Register 0x131[7:0]) x fS)/1024. Table 111. DDC 0 Phase Increment Most Significant Bits Register, Address 0x132 (Default = 0x00) Bit No. [7:2] [1:0] Access RW Bit Description Unused. DDC 0 NCO phase increment value. Phase increment for the NCO within DDC 0. Table 112. DDC 1 Gain Control Register, Address 0x138 (Default = 0x00) Bit No. [7:6] [5:4] [3:2] [1:0] Access RW RW Bit Description Unused. DDC 1 polyphase (decimate by 2) gain in units of 6 dB. 00: 0 dB gain. 01: 6 dB gain. 10: 12 dB gain. 11: 18 dB gain. Unused. DDC 1 polyphase (decimate by 8) gain in units of 6 dB. 00: 0 dB gain. 01: 6 dB gain 10: 12 dB gain. 11: 18 dB gain. Rev. A | Page 63 of 66 AD9625 Data Sheet Table 113. DDC 1 Phase Increment Least Significant Bits Register, Address 0x139 (Default = 0x00) Bit No. [7:0] Access RW Bit Description DDC 1 NCO phase increment value. Phase increment for the NCO within DDC 1. The output frequency = (decimal(Register 0x13A[1:0]; Register 0x139[7:0]) x fS)/1024. Table 114. DDC 1 Phase Increment Most Significant Bits Register, Address 0x13A (Default = 0x00) Bit No. [7:2] [1:0] Access RW Bit Description Unused. DDC1 NCO phase increment value. Table 115. SYSREFHold Time Guardband Register, Address 0x13B (Default = 0x00) Bit No. [7:5] Access RW [4:0] RW Bit Description These bits increase the SYSREF hold time guardband that is used to assert the SYSREF hold IRQ flag in register 0x100[3]. This time is informational only and does not change the actual hold time for SYSREF. 000: No additional guardband hold time. 001: 35 ps of additional hold time guardband for 0x100[3]. 010: 70 ps of additional hold time guardband for 0x100[3]. 011: 105 ps of additional hold time guardband for 0x100[3]. 100: 140 ps of additional hold time guardband for 0x100[3]. 101: 175 ps of additional hold time guardband for 0x100[3]. 110: 210 ps of additional hold time guardband for 0x100[3]. 111: 245 ps of additional hold time guardband for 0x100[3]. Reserved Table 116. SYSREF Setup Time Guardband Register, Address 0x13C (Default = 0x00) Bit No. [7:5] Access RW [4:0] RW Bit Description These bits increase the SYSREF setup time guardband that is used to assert the SYSREF setup IRQ flag in register 0x100[2]. This time is informational only and does not change the actual setup time for SYSREF. 000: No additional guardband setup time. 001: 35 ps of additional setup time guardband for 0x100[2]. 010: 70 ps of additional setup time guardband for 0x100[2]. 011: 105 ps of additional setup time guardband for 0x100[2]. 100: 140 ps of additional setup time guardband for 0x100[2]. 101: 175 ps of additional setup time guardband for 0x100[2]. 110: 210 ps of additional setup time guardband for 0x100[2]. 111: 245 ps of additional setup time guardband for 0x100[2]. Reserved Rev. A | Page 64 of 66 Data Sheet AD9625 APPLICATIONS INFORMATION DESIGN GUIDELINES CLOCK STABILITY CONSIDERATIONS Before starting system level design and layout of the AD9625, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. When powered on, the AD9625 enters an initialization phase during which an internal state machine sets up the biases and the registers for proper operation. During the initialization process, the AD9625 needs a stable clock. If the ADC clock source is not present or not stable during ADC power-up, it disrupts the state machine and causes the ADC to start up in a less than optimum state. To correct this, an initialization sequence must be invoked after the ADC clock is stable or any change in the sampling clock frequency is made. By issuing a digital reset via Register 0x00. The pseudo code sequence for a digital reset is as follows: POWER AND GROUND RECOMMENDATIONS When connecting power to the AD9625, it is recommended that separate supplies are used: one supply for the analog output (AVDD), and a separate supply for the digital outputs (DRVDD and DVDD). The designer can use several different decoupling capacitors to cover both high and low frequencies. Locate these capacitors close to the point of entry at the printed circuit board (PCB) level and close to the pins of the part with minimal trace length. When using the AD9625, a single PCB ground plane is sufficient. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved #Stable Clock at the input to the AD9625 SPI_Write (0x00, 0x3C); # Reset SPI_Write (0x080 0xFF) #SPI register transfer #Write further configurations SPI PORT When the full dynamic performance of the converter is required, do not activate the SPI port. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9625 to keep these signals from transitioning at the converter input pins during critical sampling periods. Rev. A | Page 65 of 66 AD9625 Data Sheet OUTLINE DIMENSIONS A1 BALL PAD CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1 8.20 SQ 11.20 SQ TOP VIEW 1.70 1.59 1.50 A B C D E F G H J K L M N P 10.40 SQ 0.80 0.80 REF BOTTOM VIEW DETAIL A 0.75 REF DETAIL A 1.33 1.26 1.19 0.38 0.33 0.28 0.51 REF SEATING PLANE 0.50 0.45 0.40 BALL DIAMETER COPLANARITY 0.12 07-20-2012-A A1 BALL PAD CORNER 12.10 12.00 SQ 11.90 COMPLIANT TO JEDEC STANDARDS MO-275-GGAA-1. Figure 87. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] (BP-196-2) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9625BBPZ-2.5 AD9625BBPZ-2.0 AD9625BBP-2.5 AD9625BBPZRL-2.5 AD9625BBPZRL-2.0 AD9625BBPRL-2.5 AD9625-2.5EBZ AD9625-2.0EBZ 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] 196-Ball Ball Grid Array, PbSn, Thermally Enhanced [BGA_ED] 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED], 13" Tape and Reel 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED], 13" Tape and Reel 196-Ball BGA, PbSn, Thermally Enhanced [BGA_ED], 13" Tape and Reel Evaluation Board with AD9625 Evaluation Board with AD9625 Package Option BP-196-2 BP-196-2 BP-196-2 BP-196-2 BP-196-2 BP-196-2 Z = RoHS Compliant Part. (c)2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11814-0-9/14(A) www.analog.com/AD9625 Rev. A | Page 66 of 66