12-Bit, 2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V
Analog-to-Digital Converter
Data Sheet
AD9625
FEATURES
12-bit 2.5 GSPS ADC, no missing codes
SFDR = 77 dBc, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
SFDR = 77 dBc, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
SNR = 57.6 dBFS, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
SNR = 57 dBFS, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
Noise spectral density = −149.5 dBFS/Hz at 2.5 GSPS
Differential analog input: 1.2 V p-p
Differential clock input
3.2 GHz analog input bandwidth, full power
High speed 6- or 8-lane JESD204B serial output at 2.5 GSPS
Subclass 1: 6.25 Gbps at 2.5 GSPS
Two independent decimate by 8 or decimate by 16 filters
with 10-bit NCOs
Supply voltages: 1.3 V, 2.5 V
Serial port control
Flexible digital output modes
Built-in selectable digital test patterns
Timestamp feature
Conversion error rate < 10−15
APPLICATIONS
Spectrum analyzers
Military communications
Radar
High performance digital storage oscilloscopes
Active jamming/antijamming
Electronic surveillance and countermeasures
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD9625 is a 12-bit monolithic sampling analog-to-digital
converter (ADC) that operates at conversion rates of up to
2.5 giga samples per second (GSPS). This product is designed
for sampling wide bandwidth analog signals up to the second
Nyquist zone. The combination of wide input bandwidth, high
sampling rate, and excellent linearity of the AD9625 is ideally
suited for spectrum analyzers, data acquisition systems, and a
wide assortment of military electronics applications, such as
radar and electronic countermeasures.
The analog input, clock, and SYSREF± signals are differential
inputs. The JESD204B-based high speed serialized output is
configurable in a variety of one-, two-, four-, six-, or eight-lane
configurations. The product is specified over the industrial
temperature range of −40°C to +85°C, measured at the case.
PRODUCT HIGHLIGHTS
1. High performance: exceptional SFDR in high sample rate
applications, direct RF sampling, and on-chip reference.
2. Flexible digital data output formats based on the JESD204B
specification.
3. Control path SPI interface port that supports various
product features and functions, such as data formatting,
gain, and offset calibration values.
AVDD AGND DRVDD DRGND
CMOS DIGITAL
INPUT/OUTPUT
DDC
f
S
/8 OR
f
S
/16
DIGITAL INTERFACE
AND CONT ROL
CONTROL
REGISTERS
VIN+
VIN–
VCM
SYSREF±
CLK±
RBIAS
ADC
CORE
REFERENCE
CLOCK
MANAGEMENT
SDIO SCLK CSB
FD
SERDOUT[0]±
SERDOUT[1]±
SERDOUT[2]±
SERDOUT[3]±
SERDOUT[4]±
SERDOUT[5]±
SERDOUT[6]±
SERDOUT[7]±
SYNCINB±
DIVCLK±
RSTB
IRQ
AD9625
JESD204B
INTERFACE
CMOS
DIGITAL
INPUT/
OUTPUT
LVDS
DIGITAL
INPUT/
OUTPUT
11814-001
Rev. A Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
AD9625 Data Sheet
Rev. A | Page 2 of 66
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications .......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 7
Absolute Maximum Ratings ....................................................... 9
Thermal Characteristics .............................................................. 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 16
Equivalent Test Circuits ................................................................. 23
Theory of Operation ...................................................................... 24
ADC Architecture ...................................................................... 24
Fast Detect ................................................................................... 24
Gain Threshold Operation ........................................................ 24
Test Modes ................................................................................... 25
Analog Input Considerations ........................................................ 26
Differential Input Configurations ............................................ 26
DC Coupling ............................................................................... 27
Clock Input Considerations ...................................................... 27
Digital Downconverters (DDC) ................................................... 28
Frequency Synthesizer and Mixer ............................................ 28
Numerically Controlled Oscillator ........................................... 28
High Bandwidth Decimator ...................................................... 28
Low Bandwidth Decimator ....................................................... 30
Digital Outputs ............................................................................... 31
Introduction to THE JESD204B Interface .............................. 31
Functional Overview ................................................................. 31
JESD204B Link Establishment ................................................. 33
Physical Layer Output ................................................................ 37
Scrambler ..................................................................................... 37
Tail Bits ........................................................................................ 37
DDC Modes (Single and Dual) ................................................ 37
CheckSum ................................................................................... 38
8-Bit/10-Bit Encoder Control ................................................... 38
Initial Lane Alignment Sequence (ILAS) ................................ 38
Lane Synchronization ................................................................ 38
JESD204B Application Layers .................................................. 42
Frame Alignment Character Insertion .................................... 45
Thermal Considerations ............................................................ 45
Power Supply Considerations ................................................... 45
Serial Port Interface (SPI) .............................................................. 46
Configuration Using the SPI ..................................................... 46
Hardware Interface ..................................................................... 46
Memory Map .................................................................................. 47
Reading the Memory Map Register ......................................... 47
Memory Map Registers ............................................................. 47
Applications Information .............................................................. 65
Design Guidelines ...................................................................... 65
Power and Ground Recommendations ................................... 65
Clock Stability Considerations ................................................. 65
SPI Port ........................................................................................ 65
Outline Dimensions ....................................................................... 66
Ordering Guide .......................................................................... 66
Data Sheet AD9625
REVISION HISTORY
9/14—Rev. 0 to Rev. A
Added AD9625-2.5 (Throughout) .................................................. 1
Changes to Features and General Description Sections .............. 1
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 6
Changes to Table 4 ............................................................................ 7
Changes to Figure 3 and Figure 4 ................................................... 8
Changes to Table 6 ............................................................................ 9
Changes to Pin K4; Figure 5, Table 8, and Table 9 ...................... 10
Added Typical Performance Characteristics Summary and
Changes to Typical Performance Characteristics ....................... 16
Changes to Figure 45, Figure 49, and Figure 50; Added
Figure 51 to Figure 54 ..................................................................... 23
Changes to Gain Threshold Operation Section .......................... 24
Changes to Analog Input Considerations Section ...................... 26
Changes to Digital Downconverters (DDC) Section ................. 28
Added Figure 68 .............................................................................. 32
Changes to Data Streaming Section; Added Link Setup
Parameters Section .......................................................................... 33
Changes to Digital Outputs, Timing, and Controls Section and
Table 15 ............................................................................................. 34
Changes to Table 16 and Table 17 ................................................. 35
Added Table 18 ................................................................................ 36
Added Multichip Synchronization Using SYSREF± Timestamp,
6 Lane Output Mode, and SYSREF± Setup and Hold IRQ
Sections ............................................................................................. 39
Added IRQ Guardband Delays (SYSREF± Setup and Hold)
Section .............................................................................................. 40
Added Using Rising/Falling Edges of CLK to Latch SYSREF±
Section .............................................................................................. 41
Changes to Configuration Using the SPI Section ....................... 46
Changes to Transfer Register Map Section, Table 26, and
Table 27 ............................................................................................. 47
Changes to Table28, Table 29, and Table 30 ................................ 48
Changes to Table 33 and Table 34 ................................................. 49
Changes to Table 53 ........................................................................ 52
Changes to Table 54 ........................................................................ 52
Changes to Table 58 ........................................................................ 54
Changes to Table 71 ........................................................................ 56
Changes to Table 79 and Table 80 ................................................. 57
Changes to Table 81, Table 82, Table 83, Table 84, Table 85, and
Table 86 ............................................................................................. 58
Changes to Table 89 ........................................................................ 59
Changes to Table 92 and Table 93 ................................................. 60
Changes to Table 94, Table 97, and Table 98 ............................... 61
Changes to Table 101 and Table 106 ............................................. 62
Added Table 107 and Table 108..................................................... 63
Added Table 115 and Table 116..................................................... 64
Added Applications Information Section .................................... 65
Changes to Ordering Guide ........................................................... 66
5/14—Revision 0: Initial Version
Rev. A | Page 3 of 66
AD9625 Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal
reference, AIN = −1.0 dBFS, default SPI settings, dc-coupled output data, unless otherwise noted.
Table 1.
Parameter
Test Conditions/
Comments Temperature1
AD9625-2.0 AD9625-2.5
Unit Min Typ Max Min Typ Max
RESOLUTION 12 12 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed
Offset Error Full −7 ±0.5 +6.4 −7 ±0.5 +6.4 LSB
Gain Error
Full
−8
+8
−9
+5
%FSR
Differential Nonlinearity (DNL)
Full
−0.7
±0.3
+0.7
−0.5
±0.3
+0.7
LSB
Integral Nonlinearity (INL)
Full
−3.6
±0.9
+3.6
−2.1
±1.0
+2.1
LSB
ANALOG INPUTS
Differential Input
Voltage Range Internal VREF = 1.2 V Full 1.1 1.2 V p-p
Resistance 25°C 100 100 Ω
Capacitance 25°C 1.5 1.5 pF
Internal Common-Mode
Voltage (VCM)
Full 492 525 563 492 525 563 mV
Analog Full-Power
Bandwidth (See Figure 59
and Figure 60 for networks)
Internal termination 25°C 3.2 3.2 GHz
Input Referred Noise 25°C 3 4 LSBRMS
POWER SUPPLIES
AVDD1 Full 1.26 1.3 1.32 1.26 1.3 1.32 V
AVDD2 Full 2.4 2.5 2.6 2.4 2.5 2.6 V
DRVDD1 Full 1.26 1.3 1.32 1.26 1.3 1.32 V
DRVDD2 Full 2.4 2.5 2.6 2.4 2.5 2.6 V
DVDD1 Full 1.26 1.3 1.32 1.26 1.3 1.32 V
DVDD2 Full 2.4 2.5 2.6 2.4 2.5 2.6 V
DVDDIO Full 2.4 2.5 2.6 2.4 2.5 2.6 V
SPI_VDDIO Full 2.4 2.5 2.6 2.4 2.5 2.6 V
I
AVDD1
Full
1120
1222
1250
1351
mA
I
AVDD2
Full
383
460
427
491
mA
I
DRVDD1
Full
456 470 460 473
mA
I
DRVDD2
Full
9 10 9 10
mA
I
DVDD1
Full
410 430 425 509
mA
I
DVDD2
Full
<1
<1
mA
IDVDDIO Full <1 <1 mA
ISPI_VDDIO Full <1 <1 mA
Power Dissipation 8 lane mode Full 3.48 3.8 3.90 4.2 W
Power-Down Dissipation 125 3.8 125 mW
1 Full temperature range is −40°C to +85°C measured at the case (TC).
Rev. A | Page 4 of 66
Data Sheet AD9625
AC SPECIFICATIONS
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling, 1.2 V internal reference,
AIN = −1.0 dBFS, sample clock input = 1.65 V p-p differential, default SPI settings, unless otherwise noted.
Table 2.
Parameter
Test
Conditions/Comments Temperature
AD9625-2.0 AD9625-2.5
Unit Min Typ Max Min Typ Max
SPEED GRADE 2.0 2.5 GSPS
ANALOG INPUT Full scale Full 1.1 1.2 V p-p
NOISE DENSITY
25°C
−149.0
−149.5
dBFS/Hz
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 100 MHz
25°C
59.5 58.3
dBFS
f
IN
= 500 MHz
25°C
59.4 58.0
dBFS
f
IN
= 1000 MHz
25°C
59.0 57.6
dBFS
f
IN
= 1800 MHz
Full
55.4 58.2 54.1 57.0
dBFS
SIGNAL-TO-NOISE AND
DISTORTION (SINAD)
f
IN
= 100 MHz
25°C
58.4 57.2
dBc
f
IN
= 500 MHz
25°C
58.4 57.0
dBc
f
IN
= 1000 MHz
25°C
58.0 56.5
dBc
f
IN
= 1800 MHz
Full
54.1 57.2 53.1 55.9
dBc
EFFECTIVE NUMBER OF BITS
(ENOB)
f
IN
= 100 MHz
25°C
9.4 9.2
Bits
f
IN
= 500 MHz
25°C
9.4 9.2
Bits
f
IN
= 1000 MHz
25°C
9.3 9.1
Bits
f
IN
= 1800 MHz
25°C
9.2 9.0
Bits
SPURIOUS FREE DYNAMIC
RANGE (SFDR)
Including 2nd or 3rd
harmonic
f
IN
= 100 MHz
25°C
80 77
dBc
f
IN
= 500 MHz
25°C
81
76
dBc
f
IN
= 1000 MHz
25°C
80 79
dBc
f
IN
= 1800 MHz
Full
67
76
70
77
dBc
WORST OTHER SPUR
Excluding 2nd or 3rd
harmonic
f
IN
= 100 MHz
25°C
−80 −77
dBc
f
IN
= 500 MHz
25°C
−86 −76
dBc
f
IN
= 1000 MHz
25°C
−83 −82
dBc
f
IN
= 1800 MHz
Full
−85 −73 −78 −70
dBc
TWO-TONE INTERMODULATION
DISTORTION (IMD)
At −7 dBFS per tone
f
IN1
= 728.5 MHz, f
IN2
=
731.5 MHz
25°C
−82.8 −81.2
dBc
f
IN1
= 1805.5 MHz, f
IN2
=
1808.5 MHz
25°C
−77.6 −76.3
dBc
Rev. A | Page 5 of 66
AD9625 Data Sheet
DIGITAL SPECIFICATIONS
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal
reference, AIN = −1.0 dBFS, default SPI settings, unless otherwise noted.
Table 3.
Parameter Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage Full 500 1800 mV p-p
Common-Mode Input Voltage Full 0.88 V
Input Resistance (Differential) Full 40 kΩ
Input Capacitance Full 1.5 pF
SYSREF INPUTS (SYSREF+, SYSREF−)
Differential Input Voltage Full 500 1800 mV p-p
Common-Mode Input Voltage Full 0.88 V
Input Resistance (Differential) Full 40 kΩ
Input Capacitance Full 1.5 pF
LOGIC INPUTS (SDIO, SCLK, CSB)
Logic Compliance CMOS
Voltage
Logic 1 Full 0.8 × SPI_DVDDIO V
Logic 0 Full 0.5 V
Input Resistance Full 30 kΩ
Input Capacitance Full 0.5 pF
SYNCB+/SYNCB− INPUT
Logic Compliance Full LVDS
Input Voltage
Differential Full 250 1200 mV p-p
Common Mode Full 1.2 V
Input Resistance (Differential) Full 100 Ω
Input Capacitance Full 2.5 pF
LOGIC OUTPUT (SDIO)
Logic Compliance CMOS
Voltage
Logic 1 (IOH = 800 μA) Full 0.8 × SPI_VDDIO V
Logic 0 (IOL = 50 μA) Full 0.3 V
DIGITAL OUTPUTS (SERDOUT[x]±)
Compliance Full CML
Output Voltage
Differential Full 360 700 800 mV p-p
Offset Full DRVDD/2 mV p-p
Differential Return Loss (RLDIFF)1 25°C 8 dB
Common-Mode Return Loss (RLCM) 25°C 6 dB
Differential Termination Impedance 25°C 100 Ω
RESET (RSTB)
Voltage
Logic 1
Full
0.8 × DVDDIO
V
Logic 0 Full 0.5 V
Input Resistance (Differential) Full 20 kΩ
Input Capacitance Full 2.5 pF
FAST DETECT (FD), PWDN AND INTERRUPT (IRQ)
Logic Compliance CMOS
Voltage
Logic 1 Full 0.8 × DVDDIO V
Logic 0 Full 0.5 V
Input Resistance (Differential) Full 20 kΩ
Input Capacitance Full 2.5 pF
1 Differential and common-mode return loss measured from 100 MHz to 0.75 × baud rate.
Rev. A | Page 6 of 66
Data Sheet AD9625
SWITCHING SPECIFICATIONS
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal
reference, AIN = −1.0 dBFS, default SPI settings, unless otherwise noted.
Table 4.
Parameter
Test Conditions/
Comments Temperature Min Typ Max Unit
CLOCK (CLK)
Maximum Clock Rate Full 2500 MSPS
Minimum Clock Rate Full 3301 MSPS
Clock Pulse Width High Full 50 ± 5 % duty cycle
Clock Pulse Width Low Full 50 ± 5 % duty cycle
SYSREF (SYSREF±)
2
Setup Time (tSU_SR) 25°C +200 ps
Hold Time (tH_SR) 25°C −100 ps
FAST DETECT OUTPUT (FD)
Latency Full 82 Clock cycles
OUTPUT PARAMETERS (SERDOUT[x]±)
Rise Time
25°C
70
ps
Fall Time 25°C 70 ps
Pipeline Latency 8 lane mode 25°C 226 Clock cycles
SYNCB± Falling Edge to First K.28 Characters 25°C 4 Multiframes
CGS Phase K.28 Characters Duration 25°C 1 Multiframes
Differential Termination Resistance
25°C
100
Ω
APERTURE
Delay Full 200 ps
Uncertainty (Jitter) Full 80 fS rms
Out-of-Range Recovery Time Full 2 Clock cycles
1 Must use a two-lane, generic output lane configuration for minimum sample rate. For more information, see the lane table in the JESD204B specification document.
2 SYSREF± setup and hold times are defined with respect to the rising SYSREF± edge and rising clock edge. Positive setup time leads the clock edge. Negative hold time
also leads the clock edge.
TIMING SPECIFICATIONS
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
SPI TIMING REQUIREMENTS
tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
t
CLK
Period of the SCLK
40
ns
t
S
Setup time between CSB and SCLK
2
ns
tH Hold time between CSB and SCLK 2 ns
tHIGH Minimum period that SCLK should be in a logic high state 10 ns
tLOW Minimum period that SCLK should be in a logic low state 10 ns
tEN_SDIO Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
10 ns
tDIS_SDIO Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
10 ns
Rev. A | Page 7 of 66
AD9625 Data Sheet
Rev. A | Page 8 of 66
Timing Diagrams
Figure 2. SYSREF± Setup and Hold Timing
Figure 3. Serial Port Interface Timing Diagram (MSB First)
Figure 4. Data Output Timing for 8 Lane Mode
11814-202
CLK+
CLK–
SYSREF+
SYSREF–
tSU_SR tH_SR
DON’ T CARE
DON ’ T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DS
t
DH
t
HIGH
t
LOW
t
CLK
t
H
R/W W1W0A12A11A10A9A8A7 D5D4D3D2D1D0
11814-203
S
ERDOUT0±
N – 225
N – 226
N – 224 N – 1
SAMPLE N
N + 1
CLK+
CLK–
CLK+
CLK–
S
ERDOUT7±
ANALOG
INPUT
SIGNAL
SAMPLE N – 226
ENCODED INTO 2
8-BI T/ 1 0- BIT S Y M B O L
SAM PLE N – 225
ENCODED I NT O 2
8-BIT /10-B IT S Y M BOL
SAMP LE N – 224
ENCODED I N TO 2
8-BIT /10-BIT SYMBOL
11814-204
Data Sheet AD9625
Rev. A | Page 9 of 66
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Electrical
AVDD1to AGND −0.3 V to +1.32 V
AVDD2 to AGND −0.3 V to +2.75 V
DRVDD1 to DRGND −0.3 V to +1.32 V
DRVDD2 to DRGND −0.3 V to +2.75 V
DVDD1 to DGND −0.3 V to +1.32 V
DVDD2 to DGND −0.3 V to +2.75 V
DVDDIO to DGND −0.3 V to +3.63 V
SPI_VDDIO to DGND −0.3 V to +3.63 V
AGND to DRGND −0.3 V to +0.3 V
VIN± to AGND −0.3 V to AVDD1+ 0.2 V
VCM to AGND −0.3 V to AVDD1+ 0.2 V
VMON to AGND −0.3 V to AVDD1+ 0.2 V
CLK± to AGND −0.3 V to AVDD1+ 0.2 V
SYSREF± to AGND −0.3 V to AVDD1+ 0.2 V
SYNCINB± to DRGND −0.3 V to DRVDD2 + 0.2 V
SCLK to DRGND −0.3 V to SPI_VDDIO + 0.2 V
SDIO to DRGND −0.3 V to SPI_VDDIO + 0.2 V
IRQ to DRGND −0.3 V to DVDDIO + 0.2 V
RSTB to DRGND −0.3 V to DVDDIO + 0.2 V
CSB to DRGND −0.3 V to SPI_VDDIO + 0.2 V
FD to DRGND −0.3 V to DVDDIO + 0.2 V
DIVCLK± to DRGND −0.3 V to DRVDD2 + 0.2 V
SERDOUT[x]± to DRGND −0.3 V to DRVDD1 + 0.2 V
Environmental
Storage Temperature Range −60°C to +150°C
Operating Case Temperature Range −40°C to +85°C
(measured at case)
Maximum Junction Temperature 110°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CHARACTERISTICS
The following characteristics are for a 4-layer and 10-layer
printed circuit board (PCB).
Table 7. Thermal Resistance
PCB TA (°C)
θJA
(°C/W)
ΨJT
(°C/W)
ΨJB
(°C/W)
θJC
(°C/W)
4-Layer 85.0 18.7 0.61 6.1 1.4
10-Layer 85.0 11.5 0.61 4.1 N/A1
1 N/A means not applicable.
ESD CAUTION
AD9625 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. Pin Configuration
AVDD2 AVDD1 DVDD2 DVDD1 DRVDD2 DRVDD1 DVDDIO
SPI_VD
DIO AGND DGND DRGND DNC OR
BYPASS
WITH
CAP
AGND
AGND
AGND
DVDD1
DGND
DVDD1
DGND
DVDD1
DGND
DVDD1
DGND
DRGND
DRVDD1
DRVDD1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
DNC
AGND
AGND
AGND
DVDD1
DGND
DVDD1
DGND
DVDD1
DGND
DVDD1
DRGND
SERDOUT
[7]+
SERDOUT
[7]–
AGND
AGND
AGND
DVDD1
DGND
DVDD1
DGND
DVDD1
DGND
RSTB
SYNCINB–
DRGND
SERDOUT
[6]+
SERDOUT
[6]–
AVDD1
AGND
AGND
DNC
DVDD2
SPI_VDDIO
CSB
SCLK
SDIO
PWDN
SYNCINB+
DRGND
SERDOUT
[5]+
SERDOUT
[5]–
AGND
AVDD1
AGND
AGND
VMON
DVDDIO
DVDDIO
IRQ
FD
AGND
DGND
DRGND
SERDOUT
[4]+
SERDOUT
[4]–
AVDD2
AGND
AVDD1
AGND
AGND
AGND
AGND
AGND
RBIAS_EXT
AGND
DGND
DRGND
DRVDD1
DRVDD1
VCM
AVDD2
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
DGND
DRGND
SERDOUT
[3]+
SERDOUT
[3]–
AGND
AGND
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AGND
DGND
DRGND
SERDOUT
[2]+
SERDOUT
[2]–
VIN+
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DGND
DRGND
SERDOUT
[1]+
SERDOUT
[1]–
VIN–
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DNC
DRGND
SERDOUT
[0]+
SERDOUT
[0]–
AGND
AGND
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AGND
DNC
DRVDD1
DRVDD1
DRVDD1
VM_BYP
AVDD2
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
DNC
REXT
VP_BYP
DRGND
AVDD2
AGND
AGND
AVDD1
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DRGND
DRVDD2
DIVCLK–
AVDD2
12345678910 11 12 13 14
AGND
AVDD1
AVDD1
AGND
CLK+
CLK–
AGND
SYSREF+
SYSREF–
AGND
DRGND
DRVDD2
DIVCLK+
AD9625
TOP VIEW
(Not t o Scale)
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. LEAVE THIS PIN FLOATING.
11814-009
Rev. A | Page 10 of 66
Data Sheet AD9625
Table 8. Pin Function Descriptions (By Pin Number)
Pin No. Mnemonic Type Description
A1 to A3 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
A4 AVDD1 Power ADC Analog Power Supply (1.30 V).
A5 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane.
A6 AVDD2 Power ADC Analog Power Supply (2.50 V).
A7 VCM Output Analog Input, Common Mode (0.525 V).
A8 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane.
A9 VIN+ Input Differential Analog Input, True.
A10 VIN− Input Differential Analog Input, Complement.
A11 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane.
A12 VM_BYP Input Voltage Bypass.
A13 AVDD2 Power ADC Analog Power Supply (2.50 V).
A14 AVDD2 Power ADC Analog Power Supply (2.50 V).
B1 to B4 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
B5 AVDD1 Power ADC Analog Power Supply (1.30 V).
B6 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane.
B7
AVDD2
Power
ADC Analog Power Supply (2.50 V).
B8 to B11 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
B12 AVDD2 Power ADC Analog Power Supply (2.50 V).
B13, B14 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
C1 to C5 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
C6
AVDD1
Power
ADC Analog Power Supply (1.30 V).
C7 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane.
C8 AVDD2 Power ADC Analog Power Supply (2.50 V).
C9, C10 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
C11 AVDD2 Power ADC Analog Power Supply (2.50 V).
C12, C13 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
C14 AVDD1 Power ADC Analog Power Supply (1.30 V).
D1 to D3 DVDD1 Power ADC Digital Power Supply (1.30 V).
D4 DNC N/A Do Not Connect. Do not connect to this pin. Leave this pin floating.
D5, D6 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
D7 AVDD1 Power ADC Analog Power Supply (1.30 V).
D8 AVDD2 Power ADC Analog Power Supply (2.50 V).
D9, D10 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
D11 AVDD2 Power ADC Analog Power Supply (2.50 V).
D12 to D14 AVDD1 Power ADC Analog Power Supply (1.30 V).
E1 to E3 DGND Ground Digital Control Ground Supply. These pins connect to the digital ground plane.
E4 DVDD2 Power ADC Digital Power Supply (2.5 V).
E5
VMON
Output
CTAT Voltage Monitor Output.
E6 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane.
E7 AVDD1 Power ADC Analog Power Supply (1.30 V).
E8 AVDD2 Power ADC Analog Power Supply (2.50 V).
E9, E10 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
E11 AVDD2 Power ADC Analog Power Supply (2.50 V).
E12 AVDD1 Power ADC Analog Power Supply (1.30 V).
E13, E14 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
F1 to F3 DVDD1 Power ADC Digital Power Supply (1.30 V).
F4 SPI_VDDIO Power SPI Digital Power Supply (2.50 V).
F5 DVDDIO Power Digital I/O Power Supply (2.50 V).
F6
AGND
Ground
ADC Analog Ground. This pin connects to the analog ground plane.
F7 AVDD1 Power ADC Analog Power Supply (1.30 V).
F8 AVDD2 Power ADC Analog Power Supply (2.50 V).
F9, F10 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
Rev. A | Page 11 of 66
AD9625 Data Sheet
Pin No. Mnemonic Type Description
F11 AVDD2 Power ADC Analog Power Supply (2.50 V).
F12 AVDD1 Power ADC Analog Power Supply (1.30 V).
F13 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane.
F14 CLK+ Input ADC Clock Input, True.
G1 to G3
DGND
Ground
Digital Control Ground Supply. These pins connect to the digital ground plane.
G4 CSB Input SPI Chip Select CMOS Input. Active low.
G5 DVDDIO Power Digital I/O Power Supply (2.50 V).
G6 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane.
G7 AVDD1 Power ADC Analog Power Supply (1.30 V).
G8 AVDD2 Power ADC Analog Power Supply (2.50 V).
G9, G10 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
G11 AVDD2 Power ADC Analog Power Supply (2.50 V).
G12 AVDD1 Power ADC Analog Power Supply (1.30 V).
G13 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane.
G14 CLK− Input ADC Clock Input, Complement.
H1 to H3 DVDD1 Power ADC Digital Power Supply (1.30 V).
H4 SCLK Input SPI Serial Clock CMOS Input.
H5 IRQ Output Interrupt Request Output Signal.
H6 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane.
H7 AVDD1 Power ADC Analog Power Supply (1.30 V).
H8 AVDD2 Power ADC Analog Power Supply (2.50 V).
H9, H10
AGND
Ground
ADC Analog Ground. These pins connect to the analog ground plane.
H11 AVDD2 Power ADC Analog Power Supply (2.50 V).
H12 AVDD1 Power ADC Analog Power Supply (1.30 V).
H13, H14 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
J1 to J3 DGND Ground Digital Control Ground Supply. These pins connect to the digital ground plane.
J4 SDIO I/O SPI Serial Data CMOS Input/Output; Scan Output 1.
J5 FD Output Fast Detect Output. This pin requires an external 10 kΩ resistor connected to ground.
J6 RBIAS_EXT Input Reference Bias. This pin requires an external 10 kΩ resistor connected to ground.
J7 AVDD1 Power ADC Analog Power Supply (1.30 V).
J8 AVDD2 Power ADC Analog Power Supply (2.50 V).
J9, J10 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
J11
AVDD2
Power
ADC Analog Power Supply (2.50 V).
J12 AVDD1 Power ADC Analog Power Supply (1.30 V).
J13 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane.
J14 SYSREF+ Input System Reference Chip Synchronization, True.
K1 to K2 DVDD1 Power ADC Digital Power Supply (1.30 V).
K3 RSTB Input Chip Digital Reset, Active Low.
K4 PWDN Input Power-down.
K5 to K13 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
K14 SYSREF− Input System Reference Chip Synchronization, Complement.
L1 DGND Ground Digital Control Ground Supply. This pin connects to the digital ground plane.
L2 DNC N/A Do Not Connect. Do not connect to this pin. Leave this pin floating.
L3 SYNCINB− Input Synchronization, Complement.
L4 SYNCINB+ Input Synchronization, True. SYNCINB LVDS input (active low, true).
L5 to L9 DGND Ground Digital Control Ground Supply. These pins connect to the digital ground plane.
L10 to L12 DNC N/A Do Not Connect. Do not connect to these pins. Leave these pins floating.
L13, L14 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane.
M1 to M10 DRGND Ground Digital Driver Ground Supply. These pins connect to the digital driver ground plane.
M11
DRVDD1
Power
Power Supply (1.3 V) Reference Clock Divider, VCO, and Synthesizer.
M12 REXT Input External Resistor, 10 kΩ to Ground.
M13, M14 DRGND Ground Digital Driver Ground Supply. This pin connects to the digital driver ground plane.
Rev. A | Page 12 of 66
Data Sheet AD9625
Pin No. Mnemonic Type Description
N1 DRVDD1 Power Serial Digital Power Supply (1.3 V).
N2 SERDOUT[7]+ Output Lane 7 CML Output Data, True.
N3 SERDOUT[6]+ Output Lane 6 CML Output Data, True.
N4 SERDOUT[5]+ Output Lane 5 CML Output Data, True.
N5
SERDOUT[4]+
Output
Lane 4 CML Output Data, True.
N6 DRVDD1 Power Serial Digital Power Supply (1.3 V).
N7 SERDOUT[3]+ Output Lane 3 CML Output Data, True.
N8 SERDOUT[2]+ Output Lane 2 CML Output Data, True.
N9 SERDOUT[1]+ Output Lane 1 CML Output Data, True.
N10 SERDOUT[0]+ Output Lane 0 CML Output Data, True.
N11 DRVDD1 Power Serial Digital Power Supply (1.3 V).
N12 VP_BYP Input Voltage Bypass.
N13, N14 DRVDD2 Power Power Supply (2.5 V) Reference Clock Divider for SYNCINB±, DIVCLK±.
P1 DRVDD1 Power Serial Digital Power Supply (1.3 V).
P2 SERDOUT[7]− Output Lane 7 CML Output Data, Complement.
P3 SERDOUT[6]− Output Lane 6 CML Output Data, Complement.
P4 SERDOUT[5]− Output Lane 5 CML Output Data, Complement.
P5 SERDOUT[4]− Output Lane 4 CML Output Data, Complement.
P6 DRVDD1 Power Serializer Digital Power Supply (1.30 V).
P7 SERDOUT[3]− Output Lane 3 CML Output Data, Complement.
P8 SERDOUT[2]− Output Lane 2 CML Output Data, Complement.
P9
SERDOUT[1]−
Output
Lane 1 CML Output Data, Complement.
P10 SERDOUT[0]− Output Lane 0 CML Output Data, Complement.
P11 DRVDD1 Power Serializer Digital Power Supply (1.30 V).
P12 DRGND Ground Digital Driver Ground Supply. This pin connects to the digital driver ground plane.
P13 DIVCLK− Output Divide-by-4 Reference Clock LVDS, Complement.
P14 DIVCLK+ Output Divide-by-4 Reference Clock LVDS, True.
Table 9. Pin Function Descriptions (By Function)1
Pin No. Mnemonic Type Description
General Power and Ground Supply Pins
A1 to A3, A5, A8, A11, B1 to B4, B6, B8 to B11,
B13, B14, C1 to C5, C7, C9, C10, C12, C13, D5,
D6, D9, D10, E6, E9, E10, E13, E14, F6, F9, F10,
F13, G6, G9, G10, G13, H6, H9, H10, H13, H14,
J9, J10, J13, K5 to K13, L13, L14
AGND Ground ADC Analog Ground. These pins connect to the analog
ground plane.
J6 RBIAS_EXT Input Reference Bias. This pin requires an external 10 kΩ resistor
connected to ground.
Clock Pins
F14
CLK+
Input
ADC Clock Input, True.
G14 CLK− Input ADC Clock Input, Complement.
ADC Analog Power and Ground Supplies Pins
A6, A13, A14, B7, B12, C8, C11, D8, D11, E8,
E11, F8, F11, G8, G11, H8, H11, J8, J11
AVDD2 Power ADC Analog Power Supply (2.50 V).
A4, B5, C6, C14, D7, D12 to D14, E7, E12, F7,
F12, G7, G12, H7, H12, J7, J12
AVDD1 Power ADC Analog Power Supply (1.30 V).
A12 VM_BYP Input Voltage Bypass.
A1 to A3, A5, A8, A11, B1 to B4, B6, B8 to B11,
B13, B14, C1 to C5, C7, C9, C10, C12, C13,D5,
D6, D9, D10, E6, E9, E10, E13, E14, F6, F9, F10,
F13, G6, G9, G10, G13, H6, H9, H10, H13, H14,
J9, J10, J13, K5 to K13, L13, L14
AGND Ground ADC Analog Ground. These pins connect to the analog
ground plane.
Rev. A | Page 13 of 66
AD9625 Data Sheet
Pin No. Mnemonic Type Description
ADC Analog Input and Outputs Pins
A9 VIN+ Input Differential Analog Input, True.
A10 VIN− Input Differential Analog Input, Complement.
A7 VCM Output Analog Input, Common Mode (0.525 V).
E5
VMON
Output
CTAT Voltage Monitor Output (Diode Temperature Sensor).
JESD204B High Speed Power and Ground Pins
N1, N6, N11, P1, P6, P11 DRVDD1 Power Serial Digital Power Supply (1.3 V).
M1 to M10, M13, M14, P12 DRGND Ground Digital Driver Ground Supply. These pins connect to the
digital driver ground plane.
N13, N14 DRVDD2 Power Power Supply (2.5 V) Reference Clock Divider, SYNCINB±,
DIVCLK±.
M11 DRVDD1 Power Power Supply (1.3 V) Reference Clock Divider, VCO, and
Synthesizer.
N12 VP_BYP Input Voltage Bypass.
L2 DNC N/A Do Not Connect. Do not connect to this pin.
JESD204B High Speed Serial I/O Pins
J14 SYSREF+ Input System Reference Chip Synchronization, True.
K14 SYSREF− Input System Reference Chip Synchronization, Complement.
L4 SYNCINB+ Input Synchronization, True. SYNCINB LVDS input (active low, true).
L3 SYNCINB− Input Synchronization, Complement. SYNCINB LVDS input (active
low, complement).
N10 SERDOUT[0]+ Output Lane 0 CML Output Data, True.
P10 SERDOUT[0]− Output Lane 0 CML Output Data, Complement.
N9 SERDOUT[1]+ Output Lane 1 CML Output Data, True.
P9 SERDOUT[1]− Output Lane 1 CML Output Data, Complement.
N8 SERDOUT[2]+ Output Lane 2 CML Output Data, True.
P8 SERDOUT[2]− Output Lane 2 CML Output Data, Complement.
N7 SERDOUT[3]+ Output Lane 3 CML Output Data, True.
P7 SERDOUT[3]− Output Lane 3 CML Output Data, Complement.
N5 SERDOUT[4]+ Output Lane 4 CML Output Data, True.
P5 SERDOUT[4]− Output Lane 4 CML Output Data, Complement.
N4 SERDOUT[5]+ Output Lane 5 CML Output Data, True.
P4
SERDOUT[5]−
Output
Lane 5 CML Output Data, Complement.
N3 SERDOUT[6]+ Output Lane 6 CML Output Data, True.
P3 SERDOUT[6]− Output Lane 6 CML Output Data, Complement.
N2 SERDOUT[7]+ Output Lane 7 CML Output Data, True.
P2 SERDOUT[7]− Output Lane 7 CML Output Data, Complement.
P14 DIVCLK+ Output Divide-by-4 Reference Clock LVDS, True.
P13 DIVCLK− Output Divide-by-4 Reference Clock LVDS, Complement.
Digital Supply and Ground Pins
D1 to D3, F1 to F3, H1 to H3, K1 to K2 DVDD1 Power ADC Digital Power Supply (1.3 V).
F5, G5 DVDDIO Power Digital I/O Power Supply (2.5 V).
F4 SPI_VDDIO Power SPI Digital Power Supply (2.5 V).
E4 DVDD2 Power ADC Digital Power Supply (2.5 V).
E1 to E3, G1 to G3, J1 to J3, L1, L5 to L9 DGND Ground Digital Control Ground Supply. These pins connect to the
digital ground plane.
D4 DNC N/A Do Not Connect. Do not connect to this pin. Leave this pin
floating.
Digital Control Pins
K3
RSTB
Input
Chip Digital Reset, Active Low.
K4 PWDN Input Power-down for the AD9625.
M12 REXT Input External Resistor, 10 kΩ to Ground.
G4 CSB Input SPI Chip Select CMOS Input. Active low.
H4 SCLK Input SPI Serial Clock CMOS Input.
Rev. A | Page 14 of 66
Data Sheet AD9625
Pin No. Mnemonic Type Description
J4 SDIO I/O SPI Serial Data CMOS Input/Output.
J5 FD Output Fast Detect Output. This pin requires an external 10 kΩ
resistor connected to ground.
H5 IRQ Output Interrupt Request Output Signal.
L10 to L12 DNC N/A Do Not Connect. Do not connect to these pins. Leave these
pins floating.
1 Note that when pins are relevant to multiple categories, they are repeated in Table 9. Pins may not appear in alphanumeric order within Table 9.
Rev. A | Page 15 of 66
AD9625 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
For the -2.5 model, full-scale range used is 1.2 V. For the -2.0 model, the full-scale range used is 1.1 V.
Figure 6. FFT Plot at 2.5 GSPS, fIN = 1816.7 MHz at AIN
(SFDR = 80.4 dBc, SNR = 57.1 dBFS)
Figure 7. FFT Plot at 2.5 GSPS, fIN = 730.3 MHz at AIN
(SFDR = 77.8 dBc, SNR = 57.8 dBFS)
Figure 8. FFT Plot at 2.0 GSPS, fIN = 3010 MHz at AIN
(SFDR = 73 dBc, SNR = 56 dBFS) (Input Network in Figure 60 Used)
Figure 9. FFT Plot at 2.5 GSPS, fIN = 115 MHz at AIN
(SFDR = 78.4 dBc, SNR = 58.1 dBFS)
Figure 10. FFT Plot at 2.5 GSPS, fIN = 2990.1 MHz at AIN
(SFDR = 70.6 dBc, SNR = 55.3 dBFS) (Input Network in Figure 59 Used)
Figure 11. NSD vs. Ain at 2.5GSPS (Input Network in Figure 60 Used <2 GHz,
Input Network in Figure 59 Used >2 GHz)
0
–120
–100
–80
–60
–40
–20
0250 500 750 1000 1250
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2500MSPS
1816.7M Hz AT –1.0dBF S
SNR = 57. 1dBF S
SF DR = 80.35d Bc
11814-306
0
–120
–100
–80
–60
–40
–20
0250 500 750 1000 1250
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2500MSPS
730.3M Hz AT –1.0dBF S
SNR = 57. 8dBF S
SF DR = 77.1d Bc
11814-307
0
–120
–100
–80
–60
–40
–20
0200 400 600 800 1000
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2000MSPS
3010MHz AT –1. 0dBFS
SNR = 56. 2dBF S
SF DR = 73.1d Bc
11814-308
0
–120
–100
–80
–60
–40
–20
0250 500 750 1000 1250
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2500MSPS
115.05M Hz AT –1.0dBF S
SNR = 58. 1dBF S
SF DR = 78.4d Bc
11814-309
0
–120
–100
–80
–60
–40
–20
0250 500 750 1000 1250
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2500MSPS
2990.11M Hz AT –1.0dBF S
SNR = 55. 3dBF S
SF DR = 70.6d Bc
11814-310
–140
–150
–148
–146
–144
–142
01000 2000 3000 4000 5000 6000
NOISE SPECTRAL DENSITY (dBFS/Hz)
INPUT F RE QUENCY ( M Hz )
11814-311
Rev. A | Page 16 of 66
Data Sheet AD9625
Figure 12. FFT Plot at 2.0 GSPS, fIN = 1807.3 MHz at AIN
(SFDR = 75.5 dBc, SNR = 58.1 dBFS)
Figure 13. FFT Plot at 2.0 GSPS, fIN = 730.3 MHz at AIN
(SFDR = 80.9 dBc, SNR = 59.2 dBFS)
Figure 14. FFT Plot at 2.0 GSPS, fIN = 310.3 MHz at AIN
(SFDR = 82.2 dBc, SNR = 59.6 dBFS)
Figure 15. SNR/SFDR vs. Analog Input Amplitude at 2 GSPS,
fIN = 241.1 MHz at AIN
Figure 16. SNR/SFDR vs. Analog Input Amplitude at 2 GSPS,
fIN = 1811.3 MHz at AIN
Figure 17. Two Tone SFDR and IMD3 vs. Analog Input Amplitude at 2.0 GSPS
at 1800 MHz AIN
0
–120
–100
–80
–60
–40
–20
01000800600
400
200
11814-104
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2000MSPS
1807.3MHz AT –1d BFS
SNR = 58. 12dBF S
SFDR = 75.5d Bc
0
–120
–100
–80
–60
–40
–20
01000800600400200
11814-105
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2000MSPS
730.3M Hz AT –1d BFS
SNR = 59. 19dBF S
SF DR = 80.9d Bc
0
–120
–100
–80
–60
–40
–20
01000800600400200
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2000MSPS
310.3M Hz AT –1d BFS
SNR = 59. 6dBF S
SF DR = 82.2d Bc
11814-106
100
90
80
70
60
50
40
30
20
10
0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
11814-108
SNR/S FDR (dB)
AMPLITUDE ( dB)
SF DR ( dBF S)
SNR (dBF S)
SF DR ( dBc)
SNR (dB)
100
90
80
70
60
50
40
30
20
10
0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
11814-109
SNR/S FDR (dB)
AMPLITUDE ( dB)
SF DR ( dBF S)
SNR (dBF S)
SF DR ( dBc)
SNR (dB)
120
100
80
60
40
20
0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
11814-112
SF DR ( dB)
AMPLITUDE (dBFS)
IM D3 ( dBF S )
SF DR ( dBF S )
SF DR ( dBc)
Rev. A | Page 17 of 66
AD9625 Data Sheet
Figure 18. Two Tone SFDR and IMD3 vs. Analog Input Amplitude at 2.0 GSPS
at 230 MHz AIN
Figure 19. Input Referred Noise Histogram with 2.0 GHz Sample Clock
Figure 20. SNR/SFDR vs. Analog Input Amplitude at 2 .5 GSPS,
fIN = 241 MHz at AIN
Figure 21. SNR/SFDR vs. Analog Input Amplitude at 2 .5 GSPS,
fIN = 1811 MHz at AIN
Figure 22. Current and Power vs. Sample Rate: 2 Lane, 4 Lane, and 8 Lane
Output Modes
Figure 23. SNR at 2.5GSPS vs. Temperature(Input Network in Figure 60 Used
<2 GHz, Input Network in Figure 59 Used >2 GHz)
120
100
80
60
40
20
0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
11814-215
SF DR ( dB)
AMPLITUDE (dBFS)
IM D3 ( dBF S )
SF DR ( dBF S)
SF DR ( dBc)
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
MORE N – 4 N – 2 NMOREN + 4N + 2
11814-114
HITS (Millions)
BINS
100
90
80
70
60
50
40
30
20
10
0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
SNR/S FDR (dB)
AMPLITUDE ( dB)
SF DR ( dBF S )
SNR (dBF S )
SF DR ( dBc)
SNR (dB)
11814-320
100
90
80
70
60
50
40
30
20
10
0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
SNR/S FDR (dB)
AMPLITUDE ( dB)
SF DR ( dBF S)
SNR (dBF S)
SF DR ( dBc)
SNR (dB)
11814-321
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
4.5
2.0
2.5
3.0
3.5
4.0
300 25002300210019001700150013001100900700500
CURRENT ( mA)
POWER (W)
SAMPLE RATE (MSPS)
I
DVDD2
, I
DRVDD2
I
DRVDD1
TOTAL
POWER
I
AVDD1
2L M ODE 4L MO DE 8L M ODE
I
DVDD1
I
AVDD2
11814-322
60
48
49
50
51
52
53
54
55
56
57
58
59
030002500200015001000500
SNR (dBF S)
INPUT F RE QUENCY ( M Hz )
–40°C +25°C
+85°C
11814-323
Rev. A | Page 18 of 66
Data Sheet AD9625
Figure 24. SFDR at 2.5GSPS vs. Temperature (Input Network in Figure 60 Used
<2 GHz, Input Network in Figure 59 Used >2 GHz)
Figure 25. SNR/SFDR vs. Analog Input Frequency at Different Temperatures
at 2.0 GSPS
Figure 26. Full Power Input Bandwidth (Input Network in Figure 60 Used
<2 GHz, Input Network in Figure 59 Used >2 GHz)
Figure 27. Two Tone SFDR and IMD3 vs. Analog Input Amplitude at 2.5 GSPS
at 1800 MHz AIN
Figure 28. Two Tone SFDR and IMD3 vs. Analog Input Amplitude at 2.5 GSPS
at 230 MHz AIN
Figure 29. Two Tone SFDR and IMD3 vs. Analog Input Amplitude at 2.5 GSPS
at 730 MHz AIN
85
40
45
50
55
60
65
70
75
80
030002500200015001000500
SF DR ( dBc)
INPUT F RE QUENCY ( M Hz )
–40°C
+25°C
+85°C
11814-324
90
85
80
75
70
65
60
55
50
100 300 500 700 900 1100 1300 1500 1700 1900
11814-113
SNR/S FDR (dB)
ANALOG INPUT F RE QUENCY ( M Hz )
SF DR ( dBc)
SNR (dBF S)
TA = +90°C
TA = +25°C
TA = –55° C
0
–9
–8
–7
–6
–5
–4
–3
–2
–1
10 50001000100
AMPLITUDE (dBFS)
INPUT F RE QUENCY ( M Hz )
11814-326
120
0
100
80
60
40
20
–90 –10–20–30–40–50–60–70–80
SF DR ( dB)
AMPLITUDE (dBFS)
IM D3 ( dBF S )
SF DR ( dBF S)
SF DR ( dBc)
11814-327
120
0
100
80
60
40
20
–90 –10–20–30–40–50–60–70–80
SF DR ( dB)
AMPLITUDE (dBFS)
IM D3 ( dBF S )
SF DR ( dBF S)
SF DR ( dBc)
11814-328
120
0
100
80
60
40
20
–90 –10–20–30
–40–50–60–70–80
SF DR ( dB)
AMPLITUDE (dBFS)
IM D3 ( dBF S )
SF DR ( dBF S )
SF DR ( dBc)
11814-329
Rev. A | Page 19 of 66
AD9625 Data Sheet
Figure 30. SNR/SFDR vs. Sample Rate
Figure 31. SFDR vs. AIN frequency at 2.5 GSPS (Input Network in Figure 60
Used <2 GHz, Input Network in Figure 59 used >2 GHz)
Figure 32. SNRFS vs. AIN Frequency at 2.5 GSPS (Input Network in Figure 60
Used <2 GHz, Input Network in Figure 59 Used >2 GHz)
Figure 33. Input Referred Noise Histogram with 2.5 GHz Sample Clock
Figure 34. Two Tone FFT Plot at 2.5 GSPS, fIN1 = 1808.5 MHz and
fIN2 = 1805.5 MHz at AIN, −7 dBFS (SFDR = 76 dBc)
Figure 35. Two Tone FFT Plot at 2.5 GSPS, fIN1 = 728.5 MHz and
fIN2 = 731.5 MHz at AIN, −7 dBFS (SFDR = 79 dBc)
100
40
45
50
55
60
65
70
80
90
95
75
85
300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
SNR/S FDR (dB)
SAMPLE RATE (MSPS)
SNR (dBF S), 240MHz
SF DR ( dBc), 240MHz
SNR (dBc), 1821MHz
SF DR ( dBc), 1821MHz
11814-330
85
40
45
50
55
60
65
70
75
80
100 60001000
SF DR ( dBc)
ANALOG INPUT F RE QUENCY ( M Hz )
11814-331
59
48
49
50
51
52
53
54
55
57
58
56
100 60001000
SNR (dBF S)
INPUT F RE QUENCY ( M Hz )
11814-332
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
MORE N – 4N – 6 N – 2 NMOREN + 4 N + 6N + 2
HITS (Millions)
CODE
11814-333
0
–120
–100
–80
–60
–40
–20
0250 500 750 1000 1250
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2500MSPS
fIN1
= 1808.5M Hz AT –7. 0dBF S
fIN2
= 1805.5M Hz AT –7. 0dBF S
SF DR = 75.9d Bc
11814-334
0
–120
–100
–80
–60
–40
–20
0250 500 750 1000 1250
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2500MSPS
fIN1
= 728.5M Hz AT –7. 0dBF S
fIN2
= 731.5M Hz AT –7. 0dBF S
SF DR = 79.3d Bc
11814-335
Rev. A | Page 20 of 66
Data Sheet AD9625
Figure 36. Two Tone FFT Plot at 2.5 GSPS, fIN1 = 228.5 MHz and
fIN2 = 231.5 MHz at AIN, −7 dBFS (SFDR = 76 dBc)
Figure 37. Two Tone FFT Plot at 2.0 GSPS, fIN1 = 1805.5 MHz and fIN2 =
1808.5 MHz at AIN, −7 dBFS (SFDR = 78.1 dBc)
Figure 38. Two Tone FFT Plot at 2.0 GSPS, fIN1 = 728.5 MHz and
fIN2 = 731.5 MHz at AIN, −7 dBFS (SFDR = 81 dBc)
Figure 39. Two Tone FFT Plot at 2.0 GSPS, fIN1 = 228.5 MHz and
fIN2 = 231.5 MHz at AIN, −7 dBFS (SFDR = 81 dBc)
Figure 40. Differential Nonlinearity (DNL), ±0.2 LSB at 2.0 GSPS
Figure 41. Differential Nonlinearity (DNL), ±0.3 LSB at 2.5 GSPS
0
–120
–100
–80
–60
–40
–20
0250 500 750 1000 1250
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2500MSPS
fIN1
= 228.5M Hz AT –7. 0dBF S
fIN2
= 231.5M Hz AT –7. 0dBF S
SF DR = 76.7d Bc
11814-336
0
–120
–100
–80
–60
–40
–20
01000800600400200
11814-219
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2000MSPS
fIN1 = 1805. 5M Hz AT –7. 0dBF S
fIN2 = 1808. 5M Hz AT –7. 0dBF S
SF DR = 78.117d Bc
0
–120
–100
–80
–60
–40
–20
01000800600400200
11814-220
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2000MSPS
f
IN1
= 728.5M Hz AT –7. 0dBF S
f
IN2
= 731.5M Hz AT –7. 0dBF S
SF DR = 80.98d Bc
0
–120
–100
–80
–60
–40
–20
01000800600400200
11814-221
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2000MSPS
f
IN1
= 228.5M Hz AT –7. 0dBF S
f
IN2
= 231.5M Hz AT –7. 0dBF S
SF DR = 80.76d Bc
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–1 4095307120471023
11814-222
DNL ( LSB)
CODES
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
04096307220481024
DNL ( LSB)
CODES
11814-341
Rev. A | Page 21 of 66
AD9625 Data Sheet
Figure 42. Integral Nonlinearity (INL), ±0.4 LSB at 2.0 GSPS
Figure 43. Integral Nonlinearity (INL), ±1.0 LSB at 2.5 GSPS
Figure 44. VMON Output Voltage vs. Junction Temperature
VMON (V) = -0.0013 × TEMP(C) + 0.8675
0.6
–0.6
–0.4
–0.2
0
0.2
0.4
04096307220481024
11814-223
INL (LSB)
CODES
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
04096307220481024
INL (LSB)
CODES
11814-343
1.0
0.9
0.8
0.7
0.6
0.5
–50 –25 025 50 75 100 125
VMON (V)
INPUT F RE QUENCY ( M Hz )
11814-344
Rev. A | Page 22 of 66
Data Sheet AD9625
EQUIVALENT TEST CIRCUITS
Figure 45. Equivalent Analog Input Circuit
Figure 46. Equivalent SCLK Circuit
Figure 47. Equivalent VMON Temperature Sensor Circuit (DVDDD)
Figure 48. Equivalent Clock Input Circuit
Figure 49. Equivalent CSB/PWDN Input Circuit
Figure 50. Equivalent DIVCLK Output Circuit (DRVDD)
Figure 51. Digital Outputs
Figure 52. Equivalent SYNCINB± Input
Figure 53. Equivalent SDIO Circuit
Figure 54. Equivalent SYSREF± Input Circuit
15Ω 0.6pF
50Ω 0.2pF0.5pF 0.2pF
VDD
AIN 890nH
11814-010
VDD
1kΩ
VDD
SCLK
11814-011
2pF
VDD
2kΩ
1kΩ
11814-012
AVDD
CLK+
AVDD
CLK–
0.88V
AVDD
20kΩ20kΩ
11814-013
30kΩ
ESD
PROTECTED
ESD
PROTECTED
1kΩ
DVDD
CSB
11814-015
DIVCLK
DRVDD DRVDD
11814-150
DRGND
DRGND
DATA+
DATA–
DRVDD
DRVDD
OUTPUT
DRIVER
EMPHASIS/SWING
CONTROL (SPI)
11814-400
11814-153
DVDD2
DVDD2
SYNCIN–
200Ω
DVDD2
SYNCIN+ 200Ω
100Ω
30kΩ
ESD
PROTECTED
ESD
PROTECTED
1kΩ
DRVDD
DRVDD
SDI
SDIO
SDO
11814-401
AVDD
SYSREF+
AVDD
SYSREF–
0.9V
AVDD
20kΩ20kΩ
11814-014
Rev. A | Page 23 of 66
AD9625 Data Sheet
Rev. A | Page 24 of 66
THEORY OF OPERATION
ADC ARCHITECTURE
The AD9625 is a pipelined ADC. The pipelined architecture
permits the first stage to operate on a new input sample and the
remaining stages to operate on the preceding samples. Sampling
occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The residue amplifier magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage contains a differential sampling circuit that can
be ac- or dc-coupled in differential or single-ended modes. The
output staging block aligns the data, corrects errors, and passes
the data to the output buffers. The output buffers are powered
from a separate supply, allowing adjustment of the output drive
current.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
FAST DETECT
The fast detect block within the AD9625 generates a fast
detection bit (FD), which, when used with variable gain
amplifier front-end blocks, reduces the gain and prevents the
ADC input signal levels from exceeding the converter range.
Figure 55 shows the rapidity by which the detection bit is
programmable using an upper threshold, lower threshold, and
dwell time.
The FD bit is set when the absolute value of the input signal
exceeds the programmable upper threshold level. The FD bit
clears only when the absolute value of the input signal drops
below the lower threshold level for greater than the programmable
dwell time, thereby providing hysteresis and preventing the FD
bit from excessive toggling.
GAIN THRESHOLD OPERATION
For best performance, the AD9625 needs an input signal to
perform internal calibration. This signal needs to exceed a set
threshold that is established through register settings. The
threshold prohibits background calibration updates for small
signal amplitudes. The threshold for gain calibration is enabled
by default.
Threshold Operation
The absolute value of every sample is accumulated to produce
an average voltage estimate.
When the calibration has run for its predetermined number of
samples, the voltage estimate is compared to the data set threshold.
If the voltage estimate is greater than the threshold, the cali-
bration coefficients update; otherwise, no update occurs.
Threshold Format
The threshold registers are all 16-bit registers loaded via the SPI
one byte at a time. The threshold values range from 0 to 16,384,
corresponding to a voltage range of 0.0 V to 1.2 V (full scale).
The calibration threshold range is 0 to 16,384 (0x00 to 0x4000,
hexadecimal) and represents the average magnitude of the
input. For example, to set the threshold so that a −6 dBFS input
sine wave sits precisely at the threshold requires a threshold
setting of
16,384 × 20
6
10
×
2
≥ 5228
Figure 55. Fast Detection Bit
UPPER THRESHOLD
LOWER T HRESHOLD
FD
DWELL TIME
TIMER RESET BY
RISE ABOVE LT
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE LT
DWELL TIME
11814-016
Data Sheet AD9625
Rev. A | Page 25 of 66
TEST MODES
Figure 56. Test Modes
Table 10. Flexible Output Test Modes from SPI Register 0x00D
Output Test
Mode Bit
Sequence Pattern Name
Digital Output Word 1
(Default Twos Complement
Format)
Digital Output Word 2 (Default Twos
Complement Format)
Subject to
Data Format
Select
0000 Off (default) Not applicable Not applicable Yes
0001 Midscale short 0000 0000 0000 = Word1 Yes
0010 Positive full scale 0111 1111 1111 = Word1 Yes
0011 Negative full scale 1000 0000 0000 = Word1 Yes
0100 Alternating checkerboard 1010 1010 1010 0101 0101 0101 No
0101 PN sequence long Not applicable Not applicable Yes
0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No
1000 User test mode User data from
Register 0x019 to
Register 0x020
User data from Register 0x019 to
Register 0x020
Yes
1111 Ramp output N N + 1 No
ADC CORE
FRAMER
SERALIZER OUTPUT
JESD204X TEST PATTERNS
10 BIT
SPI REGISTER 0x61
BITS 5:4 = 01 AND
BITS 3:0 ≠ 0000
JESD204X
TEST PATTERNS
16 BIT
SPI REGISTER 0x61
BITS 5:4 = 00
AND BITS 3:0 ≠ 0000
JESD204X
SAMPLE
CONSTRUCTION
ADC TEST PATTERNS
12 BIT
SPI REGISTER 0x0D
BITS 3:0 ≠ 0000
TAIL
BITS
FRAME
CONSTRUCTION
8b/10b
ENCODER
SCRAMBLER
(OPTIONAL)
11814-018
AD9625 Data Sheet
ANALOG INPUT CONSIDERATIONS
The AD9625 has a differential analog input, which is optimized
to provide superior wideband performance and must be driven
differentially. For best dynamic performance, the source
impedances driving VIN+ and VIN− should be matched such
that common-mode settling errors are symmetrical. Mismatch
between VIN+ and VIN− introduces undesired distortion. A
wideband transformer, balun or amplifier can provide the
differential analog inputs for applications that require a single-
ended to differential conversion.
DIFFERENTIAL INPUT CONFIGURATIONS
Optimum performance is achieved while driving the AD9625
in a differential input configuration. A passive input configura-
tion can be used with a single to differential balun at the analog
input to the AD9625. Because the AD9625 does not make use
of an internal input buffer, an external network needs to be
designed to reduce bandwidth peaking and minimize kickback
from the ADC sampling capacitor.
Small series resistors (R3 and R4) limit input bandwidth, but can
be installed to further improve performance. Choose the input
network components such that its equivalent impedance, in
parallel with the 100 Ω input impedance of the AD9625, is
matched to the output impedance of the balun or amplifier.
Using a larger value for R3 and R4 will suppress the input
kickback from the sampling capacitor seen at the input to the
AD9625. However, the tradeoff will be a lower usable input
bandwidth and an increase in the amount of signal power
needed to drive into the network for the AD9625 to sample a
full-scale signal.
Series isolation resistors (R5 and R6) are recommended to
reduce bandwidth peaking and minimize kickback from the
ADC sampling capacitor. Table 11 lists the front-end
requirements.
Figure 57. Recommended Front-End Network
Table 11. Recommended Front-End Components
Component Component Value
R1 33-50 Ω (termination)
R2 33-50 Ω (termination)
R3 0 Ω to 33 Ω (lower for higher bandwidth)
R4
0 Ω to 33 Ω (lower for higher bandwidth)
R5 33 Ω
R6 33 Ω
Figure 58. Input Network Example for Passive Balun with High Bandwidth
Figure 59. Input Network Example for Passive Balun and >2 GHz ADC
Bandwidth
Figure 60. Input Network Example for Passive Balun and <2 GHz ADC
Bandwidth
AD9625
AVDD
VCM
DRVDD
R5
R6
R3
R4
0.1µF
0.1µF
R1
R2
11814-024
AD9625
AVDD
VCM
DRVDD
33Ω
33Ω
0.1µF
0.1µF
50Ω
50Ω
1.5pF
0.1µF
100Ω
0.1µF
ANALOG
INPUT
INPUT
Z = 50Ω ADC INTERNAL
INPUT Z
11814-359
AD9625
25Ω
25Ω
33Ω
33Ω
0.1µF
0.1µF
33Ω
33Ω
100Ω
INTERNAL
0.1µF
EXTERNAL
BALUN/AMP
11814-360
AD9625
33Ω
33Ω
25Ω
25Ω
0.1µF
0.1µF
33Ω
33Ω
100Ω
INTERNAL
0.1µF
EXTERNAL
BALUN/AMP
11814-361
Rev. A | Page 26 of 66
Data Sheet AD9625
DC COUPLING
The AD9625 can operate using a dc-coupled input
configuration. The differential analog common-mode input
signal would need to be referenced to the VCM output of the
AD9625.
CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD9625 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled to the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally and
require no additional biasing.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) can be calculated by
SNR = 20 × log 10(1/(2 × π × fA × tJ))
In this equation, the rms aperture jitter represents the root-
mean-square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter specifications. IF
undersampling applications are particularly sensitive to jitter
(see Figure 61).
Figure 61. Ideal SNR vs. Analog Input Frequency and Jitter
In cases where aperture jitter may affect the dynamic range of the
AD9625, treat the clock input as an analog signal. To avoid
modulating the clock signal with digital noise, separate power
supplies for clock drivers from the ADC output driver supplies.
Low jitter, crystal-controlled oscillators make the best clock
sources. If the clock is generated from another type of source (by
gating, dividing, or other methods), it should be retimed by the
original clock at the last step. Refer to the AN-501 Application
Note and the AN-756 Application Note for more information
about jitter performance as it relates to ADCs.
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics.
130
120
110
100
90
80
70
60
50
40
3010 100 1000 10000
SNR (dB)
ANALOG INPUT F RE QUENCY ( M Hz )
12.5
f
S
25
f
S
50
f
S
100
f
S
200
f
S
400
f
S
800
f
S
11814-366
Rev. A | Page 27 of 66
AD9625 Data Sheet
DIGITAL DOWNCONVERTERS (DDC)
Figure 62. Digital Downconverter Block Diagram Operating at 2.0 GSPS
The AD9625 architecture includes two DDCs, each designed to
extract a portion of the full digital spectrum captured by the
ADC. Each tuner consists of an independent frequency
synthesizer and quadrature mixer; a chain of low-pass filters for
rate conversion follows these components. Assuming a
sampling frequency of 2.500 GSPS, the frequency synthesizer
(10-bit NCO) allows for 1024 discrete tuning frequencies,
ranging from −1.2499 GHz to +1.2500 GHz, in steps of
2500/1024 = 2.44 MHz. The low-pass filters allow for two
modes of decimation.
• A high bandwidth mode, 240 MHz wide (from −120 MHz
to +120 MHz), sampled at 2.5 GHz/8 = 312.5 MHz for the
I and Q branches separately. The 16-bit samples from the I
and Q branches are transmitted through a dedicated
JESD204B interface.
• A low bandwidth mode, 120 MHz wide (from −60 MHz to
+60 MHz), sampled at 2.5 GHz/16 = 156.25 MHz for the I
and Q branches separately. The 16-bit samples from the I
and Q branches are transmitted through a dedicated
JESD204B interface.
By design, all of the blocks operate at a single clock frequency of
2.5 GHz/8 = 312.5 MHz.
Each filter stage includes a gain control block that is programmable
by the user. The gain varies from 0 dB to 18 dB, in steps of 6 dB,
and the gain is applied before final scaling and rounding. The
gain control feature may be useful in cases where the tuner
filters out a strong out-of-band interferer, leaving a weak in-
band signal.
FREQUENCY SYNTHESIZER AND MIXER
For a sampling rate of 2.500 GHz, the synthesizer (10-bit NCO)
outputs one of 1024 possible complex frequencies from
−1.249 GHz to +1.250 GHz. The synthesizer employs the direct
digital synthesis technique, using look-up sine tables and a
phase accumulator. The user specifies the tuner frequency by
writing to a 10-bit phase increment register.
NUMERICALLY CONTROLLED OSCILLATOR
Each DDC has a 10-bit oscillator that is synthesized and mixed
with the ADC output data. The 10-bit phase can be tuned for
each DDC based on the value used in its NCO registers. The
phase for DDC0 is located with Register 0x132 and Register
0x131. The phase for DDC1 is located with Register 0x13A and
Register 0x139. The NCO output frequency for DDC0 =
(decimal(Register 0x132[1:0]; Register 0x131[7:0]) × fS)/1024.
The NCO output frequency for DDC1 = (decimal(Register
0x13A[1:0]; Register 0x139[7:0]) × fS)/1024.
HIGH BANDWIDTH DECIMATOR
The first filter stage is designed for a rate reduction factor of 8,
yielding a sample rate of 2.500 GHz/8 = 312.5 MHz. To achieve
a combination of low complexity and low clock rate, the DDC
employs a decimate-by-8 polyphase fuse filter that receives
eight 13-bit samples from the mixer block at every clock cycle.
The block design provides user specified gain control, from 0 dB to
18 dB in steps of 6 dB. The gain is applied before final scaling
and rounding to 16 bits.
SYNTHESIZERNCO
12-BI T ADC
@ 2.0G Hz DECIMATION
BY 8
GAIN SELECT:
0dB, 6dB, 12d B, 18d B
MODE SELECT:
185MHz OR 93MHz BW
MIXER
MIXER
8 × 12-BI T
@ 250MHz
DECIMATION
BY 8
DECIMATION
BY 2
8 × 13-BI T
@ 250MHz
8 × 12-BI T
@ 250MHz 8 × 13-BI T
@ 250MHz
16-BI T @ 250MHz
16-BIT
@ 125MHz
16-BIT
@ 125MHz
I-PHASE
16-BI T @ 250MHz
Q-PHASE
TUNE R SE LECT:
–1.0G Hz TO + 1.0G Hz
GAIN SELECT:
0dB, 6dB,
12dB, 18dB
TO
FRAMER
TO
FRAMER
11814-019
Rev. A | Page 28 of 66
Data Sheet AD9625
Rev. A | Page 29 of 66
Figure 63. Magnitude Response of the Decimate-by-8 Polyphase Fuse Filter
Filter performance is shown in Figure 63 and Figure 64. The
filter yields an effective bandwidth of 120 MHz, with a
transition band of 156.5 − 120 = 36.5 MHz. Hence, the two-
sided complex bandwidth of the filter is 240 MHz.
A rejection ratio of 85 dB ensures that the seven aliases that fold
back into the pass band yield an SNR of 85 dB − 10log10(7) =
76.5 dB, which ensures that the aliases remain sufficiently below
the noise floor of the input signal. The pass-band ripple is
±0.05 dB, as shown in Figure 64.
Figure 64. Magnitude Ripple in the High Bandwidth Pass Band
The high bandwidth decimator has a filter architecture that
consists of a 142 tap delay line. The coefficients are 17 bits each
and are listed in Table 12.
Table 12. Filter Tap Coefficients for High Bandwidth
Decimator
Tap # Coefficient Tap # Coefficient Tap # Coefficient
1 −38 49 5250 97 −519
2 −57 50 6496 98 −2179
3 −92 51 6945 99 −3353
4 −132 52 6412 100 −3944
5 −172 53 4831 101 −3945
6 −204 54 2276 102 −3425
7 −219 55 −1031 103 −2516
8 −207 56 −4725 104 −1382
9 −162 57 −8330 105 −200
10 −79 58 −11304 106 869
11 43 59 −13098 107 1698
12 196 60 −13222 108 2209
13 369 61 −11306 109 2372
14 540 62 −7160 110 2210
15 685 63 -808 111 1785
16 780 64 7498 112 1186
17 800 65 17281 113 513
18 727 66 27882 114 −135
19 554 67 38515 115 −677
20 289 68 48340 116 −1055
21 −48 69 56550 117 −1242
22 −420 70 62451 118 −1238
23 −778 71 65536 119 −1069
24 −1069 72 65536 120 −778
25 −1238 73 62451 121 −420
26 −1242 74 56550 122 −48
27 −1055 75 48340 123 289
28 −677 76 38515 124 554
29 −135 77 27882 125 727
30 513 78 17281 126 800
31 1186 79 7498 127 780
32 1785 80 −808 128 685
33 2210 81 −7160 129 540
34 2372 82 −11306 130 369
35 2209 83 −13222 131 196
36 1698 84 −13098 132 43
37 869 85 −11304 133 −79
38 −200 86 −8330 134 −162
39 −1382 87 −4725 135 −207
40 −2516 88 −1031 136 −219
41 −3425 89 2276 137 −204
42 −3945 90 4831 138 −172
43 −3944 91 6412 139 −132
44 −3353 92 6945 140 −92
45 −2179 93 6496 141 −57
46 −519 94 5250 142 −38
47 1446 95 3467
48 3467 96 1446
10
–100
–90
–80
–70
–60
–50
–40
–30
–20
0
–10
F
S
/2
MAGNIT UDE (d B)
FREQUENCY (MHz)
11814-020
0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
012010080604020
MAGNI TUDE (dB)
FREQUENCY (MHz)
11814-021
AD9625 Data Sheet
Rev. A | Page 30 of 66
LOW BANDWIDTH DECIMATOR
Use the second filter stage in the optional low bandwidth mode
only. It achieves an additional rate reduction factor of 2, yielding a
final sample rate of 2.500 GHz/16 = 156.25 MHz. The internal
architecture of the low bandwidth decimation filter is similar to
that of a high bandwidth decimator. Moreover, for ease of
physical design, the block operates at 250 MHz, a result of
which both the I- and Q-phases can share the filter engine.
The performance of the low bandwidth decimation filter is
shown in Figure 65 and Figure 66. The filter yields an effective
bandwidth of 60 MHz, with a transition band of 81.25 MHz −
60 = 21.25 MHz. Thus, the two sided, complex bandwidth of
the filter is 120 MHz. A rejection ratio of 85 dB ensures that the
alias region folds back well below the noise floor of the input
signal.
As with the high bandwidth filter, this block provides user
specified gain control, from 0 dB to 18 dB, in steps of 6 dB. The
gain is applied before final quantization at the output of the low
bandwidth decimation filter to 16 bits.
Figure 65. Magnitude Response of Decimate-by-2 Filter
Figure 66. Magnitude Ripple in the Low Bandwidth Pass Band
The low bandwidth decimator has a filter architecture that
consists of a 31 tap delay line. The coefficients are 17 bits each
and are listed in Table 13.
Table 13. Filter Tap Coefficients for Low Bandwidth
Decimator
Tap # Coefficient Tap # Coefficient Tap # Coefficient
1 126 11 6302 21 6302
2 312 12 −3099 22 2511
3 −16 13 −13075 23 −3227
4 −859 14 3441 24 −1944
5 −628 15 43442 25 1428
6 1217 16 65536 26 1217
7 1428 17 43442 27 −628
8 −1944 18 3441 28 −859
9 −3227 19 −13075 29 −16
10 2511 20 −3099 30 312
31 126
10
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
016014012010080604020
MAGNI TUDE (dB)
FREQUENCY (MHz)
11814-022
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0605040302010
MAGNI TUDE (dB)
FRE Q U E NCY ( M Hz )
11814-023
Data Sheet AD9625
DIGITAL OUTPUTS
INTRODUCTION TO THE JESD204B INTERFACE
The AD9625 digital output complies with the JEDEC Standard
No. JESD204B, Serial Interface for Data Converters. JESD204B is
a protocol to link the AD9625 to a digital processing device
over a serial interface up to and above 6.5 Gbps link speeds. The
benefits of the JESD204B interface over LVDS include a
reduction in required board area for data interface routing, and
enabling smaller packages for converter and logic devices. The
AD9625 supports one, two, four, six, or eight output lanes.
The JESD204B data transmit block assembles the parallel data
from the ADC into frames and uses 8-bit/10-bit encoding as
well as optional scrambling to form serial output data. Lane
synchronization is supported using special characters during
the initial establishment of the link. Additional data that is used
to maintain synchronization is embedded in the data stream
thereafter. A JESD204B receiver is required to complete the
serial link. For additional details on the JESD204B interface,
users are encouraged to refer to the JESD204B standard.
The AD9625 JESD204B transmit block maps to two digital
down converters for the outputs of the ADC over a link. A link
can be configured to use up to eight JESD204B lanes. The
JESD204B specification refers to a number of parameters to
define the link, and these parameters must match between the
JESD204B transmitter (AD9625 output) and receiver (FPGA,
ASIC, or logic device).
Table 14 describes the JESD204B interface nomenclature (the
terms, converter device and link, are used interchangeably in
the specification).
Table 14. JESD204B Interface Nomenclature
Symbol
Description
S Samples transmitted per single converter per frame cycle
M Number of converters per converter device (link)
L Number of lanes per converter device (link)
N Converter resolution
N
'
Total number of bits per sample
CF
Number of control words per frame clock cycle per
converter device (link)
CS Number of control bits per conversion sample
K
Number of frames per multiframe
HD
High density mode
F
Octets per frame
C
Control bit (overrange, time stamp)
T
Tail bit
The AD9625 adheres to the JESD204B draft specification,
which provides a high speed, serial, embedded clock interface
standard for data converters and logic devices. It is designed as
an MCDA-ML, Subclass 1 device that uses the SYSREF± input
signal for multichip synchronization and deterministic latency.
This design adheres to the following basic JESD204B link config-
uration parameters:
•M = 1 (single converter, always for AD9625)
•L = 1 to 8 (up to eight lanes)
•S = 4 (four samples per JESD204B frame)
•F = 1, 2, 4, 8 (up to 8 octets per frame)
•N’ = 12, 16 (12- or 16-bit JESD204B word size)
•HD = 0, 1 (high density mode, sample span multiple lanes)
FUNCTIONAL OVERVIEW
The block diagram in Figure 67 shows the flow of data through
the JESD204B hardware from the sample input to the physical
output. The processing can be divided into layers that are
derived from the OSI model widely used to describe the
abstraction layers of communications systems. These are the
transport layer, data link layer, and physical layer (serializer).
Each of these layers are described in detail in the following
sections.
Transport Layer
The transport layer handles packing the data (consisting of
samples and optional control bits) into 8-bit words that are sent
to the data link layer. The transport layer is controlled by rules
derived from the link configuration data. It packs data according to
the rules, adding tail bits to fill gaps when required.
Data Link Layer
The data link layer is responsible for the low level functions of
passing data across the link. These include optionally scrambling
the data, handling the synchronization process for characters,
frames, and lanes across the links, encoding 8-bit data-words
into 10-bit characters, and inserting appropriate control
characters into the data output. The data link layer is also
responsible for sending the initial lane alignment sequence
(ILAS), which contains the link configuration data, used by the
receiver (Rx) to verify the settings in the transport layer.
Physical Layer
The physical layer consists of the high speed circuitry clocked at
the serial clock rate. The physical layer includes the serialization
circuits and the high speed drivers.
Figure 67. Data Flow
SAMPLE
CONSTRUCTION FRAME
CONSTRUCTION SCRAMBLER ALIGNMENT
CHARACTER
GENERATION 8-BIT/10-BIT
ENCODER CROSSBAR
MUX SERIALIZER OUTPUT
PROCESSED
SAMPLES
FROM ADC
DATA LINK
LAYER
TRANSPORT
LAYER PHYSICAL
LAYER
11814-242
Rev. A | Page 31 of 66
AD9625 Data Sheet
Figure 68. JESD204B Lane Data Mapping
a b c d e f g h i j a b c d e f g h i j
fg h i j a b c d e f g h i j a bc d e f gh i j
a b c d e f g h i j a b c d e f g h i j
fg h i j a b c d e f g h i j a b c d e fg h i j
a b c d e f g h i j ab c d e fg h i jf g h i j a b c d e f g h i j a b c d e f g h i j
a b c d e f g h i j a b c d e f g h i jf g h i j a b c d e f g h i j a b c d e f g h i j
a b c d e f g h i j a b c d e f g h i jf g h i j a b c d e f g h i j a b c d e f g h i j
a b c d e f g h i j a b c d e f g h i jf g h i j a b c d e f g h i j a b c d e f g h i j
a b c d e f g h i j a b c d e f g h i jf g h i j a b c d e f g h i j a b c d e f g h i j
a b c d e f g h i j a b c d e f g h i jf g h i j a b c d e f g h i j a b c d e f g h i j
JE SD2 04B INTERFACE
M = 1; L = 8; N = 12; N' = 16; CF = 0; CS = 0; CS = 0.. .4; K = 32; HD = 1; F = 1
400ps M IN (2.5GHz )
CLK+
(ENCODE CL OCK)
LANE A±
@ 6.25Gbps
LANE B±
@ 6.25Gbps
LANE C±
@ 6.25Gbps
LANE D±
@ 6.25Gbps
LANE E±
@ 6.25Gbps
LANE F±
@ 6.25Gbps
LANE G ±
@ 6.25Gbps
LANE H±
@ 6.25Gbps
SAMPLE N + 3 [3:0],
CTTTT SAMPLE N + 7 [3:0],
CTTTT SAMPLE N + 11 [3:0],
CTTTT SAMPLE N + 15 [3:0],
CTTTT
SAMPLE N + 2 [3:0],
CTTTT SAMPLE N + 6 [3:0],
CTTTT SAMPLE N + 10 [3:0],
CTTTT SAMPLE N + 14 [3:0],
CTTTT
SAMPLE N + 1 [3:0],
CTTTT SAMPLE N + 5 [3:0],
CTTTT SAMPLE N + 9 [3:0],
CTTTT SAMPLE N + 13 [3:0],
CTTTT
SAMPLE N [3:0],
CTTTT SAMPLE N + 4 [3:0],
CTTTT SAMPLE N + 8 [3:0],
CTTTT SAMPLE N + 12 [3:0],
CTTTT
SAMP LE N + 3 [ 11: 4] SAM P LE N + 7 [ 11: 4] S AM P LE N + 11 [ 11: 4] SAMP LE N + 15 [ 11: 4]
SAMP LE N + 2 [ 11: 4] SAM P LE N + 6 [ 11: 4] S AM P LE N + 10 [ 11: 4] SAMP LE N + 14 [ 11: 4]
SAMP LE N + 1 [ 11: 4] SAM P LE N + 5 [ 11: 4] SAMP LE N + 9 [ 11: 4] SAM P LE N + 13 [ 11: 4]
SAMPLE N [11:4] SAMP LE N + 4 [ 11: 4] SAM P LE N + 8 [ 11: 4] SAMP LE N + 12 [ 11: 4]
F = 1 OCTETS F = 1 OCTETS F = 1 OCTETS F = 1 OCTETS
11814-373
Rev. A | Page 32 of 66
Data Sheet AD9625
JESD204B LINK ESTABLISHMENT
The AD9625 JESD204B Tx interface operates in Subclass 1 as
defined in the JEDEC Standard No. 204B-July 2011 specification.
It is divided into the following steps: code group synchronization,
initial lane alignment sequence, and data streaming.
Code Group Synchronization (CGS) and SYNCINB±
CGS is the process where the JESD204B receiver finds the
boundaries between the 10-bit characters in the stream of data.
During the CGS phase, the JESD204B transmit block transmits
/K28.5/ characters. The receiver (external logic device) must
locate the /K28.5/ characters in its input data stream using clock
and data recovery (CDR) techniques.
The receiver issues a synchronization request by activating the
SYNCINB± pins of the AD9625. The JESD204B Tx begins
sending /K28.5/ characters until the next LMFC boundary.
When the receiver has synchronized, it waits for the correct
reception of at least four consecutive /K28.5/ symbols. It then
deactivates SYNCINB±. The AD9625 then transmits an initial
lane alignment sequence (ILAS) on the following LMFC
boundar y.
For more information on the code group synchronization
phase, please refer to the JEDEC Standard No. 204B-July 2011,
Section 5.3.3.1.
The SYNCINB± pin operation can be controlled by SPI. The
SYNCINB± signal is a differential LVDS mode signal by default,
but it can also be driven single ended. For more information on
configuring the SYNCINB± pin operation, refer to the Memory
Map section.
Initial Lane Alignment Sequence (ILAS)
The ILAS phase follows the CGS phase and begins on the next
LMFC boundary. The ILAS consists of four mulitframes, with
an /R/ character marking the beginning and an /A/ character
marking the end. The ILAS begins by sending an /R/ character
followed by 0 to 255 ramp data for one multiframe. On the
second multiframe, the link configuration data is sent starting
with the third character. The second character is a /Q/ character
to confirm that the link configuration data follows. All
undefined data slots are filled with ramp data. The ILAS
sequence is never scrambled.
The ILAS sequence construction is shown in Figure 70. The
four multiframes include the following:
•Multiframe 1: begins with an /R/ character (K28.0) and ends
with an /A/ character (K28.3).
•Multiframe 2: begins with an /R/ character followed by a /Q/
[K28.4] character, followed by link configuration
parameters over 14 configuration octets and ends with an /A/
character. Many of the parameter values are of the notation of
the value, −1.
•Multiframe 3: this is the same as Multiframe 1.
•Multiframe 4: this is the same as Multiframe 1.
Data Streaming
After the initial lane alignment sequence is complete, the user
data is sent. In a usual frame, all characters are user data.
However, to monitor the frame clock and multiframe clock
synchronization, there is a mechanism for replacing characters
with /F/ or /A/ alignment characters when the data meets
certain conditions. These conditions are different for unscrambled
and scrambled data. The scrambling operation is enabled by
default but may be disabled using SPI.
For scrambled data, any 0xFC character at the end of a frame is
replaced by an /F/, and any 0x7C character at the end of a
multiframe is replaced with an /A/. The JESD204B Rx checks
for /F/ and /A/ characters in the received data stream and
verifies that they only occur in the expected locations. If an
unexpected /F/ or /A/ character is found, the receiver handles
the situation by using dynamic realignment or activating the
SYNCINB± signal for more than four frames to initiate a
resynchronization. For unscrambled data, if the final character
of two subsequent frames is equal, the second character is
replaced with an /F/ if it is at the end of a frame, and an /A/ if it
is at the end of a multiframe.
Insertion of alignment characters may be modified using SPI.
The frame alignment character insertion is enabled by default.
More information on the link controls is available in the
Memory Map section, Register 0x062.
Link Setup Parameters
The following steps demonstrate how to configure the AD9625
JESD204B interface and the output:
1. Disable the lanes before changing configuration.
2. Select one quick configuration option.
3. Configure the detailed options.
4. Check FCHK, checksum of JESD204B interface parameters.
5. Set additional digital output configuration options.
6. Reenable the required lane(s).
Before modifying the JESD204B link parameters, disable
the link and hold it in reset.
8-Bit/10-Bit Encoder
The 8-bit/10-bit encoder converts 8-bit octets into 10-bit
characters and inserts control characters into the stream when
needed. The control characters used in JESD204B are shown in
Table 15. The 8-bit/10-bit encoding allows the signal to be dc
balanced by using the same number of ones and zeros.
The 8-bit/10-bit interface has options that may be controlled via
SPI. These operations include bypass, invert or mirror. These
options are intended to be a troubleshooting tool for the
verification of the digital front end (DFE).
Rev. A | Page 33 of 66
AD9625 Data Sheet
Rev. A | Page 34 of 66
Digital Outputs, Timing, and Controls
The AD9625 physical layer consists of drivers that are defined in
the JEDEC Standard No. 204B-July 2011. The differential digital
outputs are powered up by default. The drivers utilize a
dynamic 100 internal termination to reduce unwanted
reflections.
Place a 100 Ω differential termination resistor at each receiver
input to result in a nominal 300 mV p-p swing at the receiver
(see Figure 69). Alternatively, single-ended 50 Ω termination
can be used. When single-ended termination is used, the termi-
nation voltage should be DRVDD/2; otherwise, 0.1 F ac coupling
capacitors can be used to terminate to any single-ended voltage.
The AD9625 digital outputs can interface with custom ASICs
and FPGA receivers, providing superior switching performance
in noisy environments. Single point-to-point network topologies
are recommended with a single differential 100 termination
resistor placed as close to the receiver inputs as possible.
Figure 69. AC-Coupled Digital Output Termination Example
If there is no far end receiver termination, or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches, and that the differential output traces be
close together and at equal lengths.
De-Emphasis
De-emphasis enables the receiver eye diagram mask to be met
in conditions where the interconnect insertion loss does not
meet the JESD204B specification. The de-emphasis feature
should only be used when the receiver is unable to recover the
clock due to excessive insertion loss. Under normal conditions,
it is disabled to conserve power. Additionally, enabling and
setting too high a de-emphasis value on a short link may cause
the receiver eye diagram to fail. Using the de-emphasis setting
may increase EMI. See the Memory Map section for details.
Figure 70. Initial Lane Alignment Sequence
Table 15. AD9625 Control Characters Used in JESD204B
Abbreviation Control Symbol 8-Bit Value
10-Bit Value
RD (Running
Disparity) = −1
10-Bit Value
RD (Running
Disparity) = +1 Description
/R/ /K28.0/ 000 11100 001111 0100 110000 1011 Start of multiframe
/A/ /K28.3/ 011 11100 001111 0011 110000 1100 Lane alignment
/Q/ /K28.4/ 100 11100 001111 0010 110000 1101 Start of link configuration data
/K/ /K28.5/ 101 11100 001111 1010 110000 0101 Group synchronization
/F/ /K28.7/ 111 11100 001111 1000 110000 0111 Frame alignment
11814-243
OR
SERDOUTx+
DRVDD
V
RXCM
SERDOUTx–
OUTPUT SWING = 300mV p-p
0.1µF
100Ω
50Ω50Ω
0.1µF
RECEIVER
V
CM
= V
RXCM
100Ω
DIFFERENTIAL
TRACE PAIR
KKRD DARD DARD DADDARQC CD
END OF
MULTIFRAME
START OF
USER DATA
START OF LINK
CONFIGURATION
DATA
START OF
ILAS
11814-132
Data Sheet AD9625
Table 16. JESD204B Mode of Operation (M = 1, S = 4, N' = 16, Unless Otherwise Noted)
Quick
Configuration
Value Description1
Lanes
(L)
Octets/
Frame (F)
Sample Clock Rate
Sample Clock
Multiplier
JESD204B Lane Rate
Minimum
MSPS
Maximum
MSPS
Minimum
Mbps
Maximum
Mbps
0x02 Generic 2 4 330 650 10 3300 6500
0x04 Generic 4 2 650 1300 5 3250 6500
0x06 Generic (N
'
= 12) 6 1 1300 2500 2.5 3250 6250
0x08 Generic 8 1 1300 2500 2.5 3250 6250
0x42 fS × 8 2 4 406 813 8 3250 6500
0x44 fS × 4 4 2 813 1625 4 3250 6500
0x48 fS × 2 8 1 1625 2500 2 3250 5000
0x81 Single DDC, high BW 1 8 650 1300 5 3250 6500
0x82 Single DDC, high BW 2 4 1300 2500 2.5 3250 6250
0x91 Single DDC, low BW 1 8 1300 2500 2.5 3250 6250
0xC1 Dual DDC, high BW 1 8 330 650 10 3300 6500
0xC2 Dual DDC, high BW 2 4 650 1300 5 3250 6500
0xC4 Dual DDC, high BW 4 2 1300 2500 2.5 3250 6250
0xE1 Dual DDC, mixed BW 1 8 330 650 10 3300 6500
0xE2 Dual DDC, mixed BW 2 4 650 1300 5 3250 6500
0xE4 Dual DDC, mixed BW 4 2 1300 2500 2.5 3250 6250
0xD1 Dual DDC, low BW 1 8 650 1300 5 3250 6500
0xD2 Dual DDC, low BW 2 4 1300 2500 2.5 3250 6250
1 DDC means digital downconverter, BW means bandwidth, fS × x means sample rate multiplied by an integer (where x is an integer: 2, 4, 8).
Table 17. JESD204B Logical Lane Mapping
Quick
Configuration
Value Description
Lanes
(L)
Logical
Lane 0
Logical
Lane 1
Logical
Lane 2
Logical
Lane 3
Logical
Lane 4
Logical
Lane 5
Logical
Lane 6
Logical
Lane 7
0x02
Generic
2
S[N],
S[N + 1]
S[N + 2],
S[N + 3]
Off
Off
Off
Off
Off
Off
0x04 Generic 4 S[N] S[N + 1] S[N + 2] S[N + 3] Off Off Off Off
0x06
Generic
(N
'
= 12)
6
S
MSB
[N], S
LSB
[N], S
MSB
[N + 1], S
LSB
[N + 1], S
MSB
[N + 2], S
LSB
[N + 2], S
MSB
[N + 3], S
LSB
[N + 3]
Off
Off
0x08 Generic 8 SMSB[N] SLSB[N] SMSB[N + 1] SLSB[N + 1] SMSB[N + 2] SLSB[N + 2] SMSB[N + 3] SLSB[N + 3]
0x42 fS × 8 2 See Figure 84, fS × 2 mode application layer (transmit)
0x44 fS × 4 4 See Figure 84, fS × 2 mode application layer (transmit)
0x48 fS × 2 8 SMSB[N], SLSB[N], SMSB[N + 1], SLSB[N + 1], SMSB[N + 2], SLSB[N + 2], SMSB[N + 3], SLSB[N + 3], SMSB[N + 4], SLSB[N + 4];
see Figure 84, fS × 2 mode application layer (transmit)
0x81 Single DDC,
high BW
1 I0[N],
Q0[N],
I0[N + 1],
Q0[N + 1]
Off Off Off Off Off Off Off
0x82
Single DDC,
high BW
2
I
0
[N],
Q0[N]
I
0
[N+1],
Q0[N+1]
Off Off Off Off Off Off
0x91 Single DDC,
low BW
1 I0[N],
Q0[N],
I0[N + 1],
Q0[N + 1]
Off Off Off Off Off Off Off
0xC1 Dual DDC,
high BW
1 I0[N],
Q0[N],
I1[N],
Q1[N]
Off Off Off Off Off Off Off
0xC2 Dual DDC,
high BW
2 I0[N],
Q0[N]
I1[N],
Q1[N]
Off Off Off Off Off Off
0xC4 Dual DDC,
high BW
4 I0[N] Q0[N] I1[N] Q1[N] Off Off Off Off
0xE1
Dual DDC,
mixed BW
1
I
0
[N],
Q0[N],
I1[N],
Q1[N]
Off Off Off Off Off Off Off
Rev. A | Page 35 of 66
AD9625 Data Sheet
Quick
Configuration
Value Description
Lanes
(L)
Logical
Lane 0
Logical
Lane 1
Logical
Lane 2
Logical
Lane 3
Logical
Lane 4
Logical
Lane 5
Logical
Lane 6
Logical
Lane 7
0xE2 Dual DDC,
mixed BW
2 I0[N],
Q0[N]
I1[N],
Q1[N]
Off Off Off Off Off Off
0xE4
Dual DDC,
mixed BW
4 I0[N] Q0[N] I1[N] Q1[N] Off Off Off Off
0xD1 Dual DDC,
low BW
1 I0[N],
Q0[N],
I1[N],
Q1[N]
Off Off Off Off Off Off Off
0xD2 Dual DDC,
low BW
2 I0[N],
Q0[N]
I1[N],
Q1[N]
Off Off Off Off Off Off
Table 18. Typical Current Consumption per ADC Mode (Unused Output Lanes are Powered Down)
Quick Configuration
Value Mode Lanes (L)
Sample Rate
(MSPS)
Typical Current Consumption (A)
IAVDD1 IAVDD2 IDRVDD1 IDRVDD2 IDVDD1 IDVDD2 Total Power (W)
0x02 Generic, 2 lane 2 650 0.7 0.3 0.2 0.0 0.1 0.0 2.1
0x04 Generic, 4 lane 4 1300 0.9 0.3 0.3 0.0 0.2 0.0 2.6
0x06 Generic, 6 lane 6 2500 1.2 0.4 0.4 0.0 0.4 0.0 3.4
0x08 Generic, 8 lane 8 2500 1.2 0.4 0.5 0.0 0.4 0.0 3.9
0x42 fS × 8 2 813 0.7 0.4 0.2 0.0 0.2 0.0 2.3
0x44 fS × 4 4 1625 1.0 0.4 0.3 0.0 0.3 0.0 3.0
0x48 fS × 2 8 2500 1.2 0.4 0.5 0.0 0.4 0.0 3.8
0x81 Single DDC high BW, 1 lane 1 1300 0.9 0.4 0.1 0.0 0.3 0.0 2.7
0x82 Single DDC high BW, 2 lane 2 2500 1.2 0.4 0.2 0.0 0.6 0.0 3.6
0x91
Single DDC low BW, 1 lane
1
2500
1.2
0.4
0.1
0.0
0.6
0.0
3.5
0xC1 Dual DDC high BW, 1 lane 1 650 0.7 0.4 0.1 0.0 0.2 0.0 2.3
0xC2
Dual DDC high BW, 2 lane
2
1300
0.9
0.4
0.2
0.0
0.5
0.0
2.9
0xC4 Dual DDC high BW, 4 lane 4 2500 1.2 0.4 0.3 0.0 0.8 0.0 4.0
0xE1 Dual DDC mixed BW, 1 lane 1 650 0.7 0.4 0.1 0.0 0.2 0.0 2.3
0xE2 Dual DDC mixed BW, 2 lane 2 1300 0.9 0.4 0.2 0.0 0.5 0.0 2.9
0xE4 Dual DDC mixed BW, 4 lane 4 2500 1.2 0.4 0.3 0.0 0.8 0.0 4.0
0xD1 Dual DDC low BW, 1 lane 1 1300 0.9 0.4 0.1 0.0 0.4 0.0 2.8
0xD2 Dual DDC low BW, 2 lane 2 2500 1.2 0.4 0.2 0.1 0.8 0.0 4.0
Rev. A | Page 36 of 66
Data Sheet AD9625
Rev. A | Page 37 of 66
PHYSICAL LAYER OUTPUT
Figure 71. Recovered Data Eye of JESD204B Lane at 6.25 Gbps
Figure 72. Bathtub Plot of JESD204B Output at 6.25 Gbps
Figure 73. Time Interval Histogram Error of JESD204B Output at 6.25 Gbps
SCRAMBLER
The scrambler polynomial is 1 + x14 + x15. The scrambler enable
bit is located in Register 0x06E[7].
Setting Bit 7 to 0 disables the scrambler.
Setting Bit 7 to 1 enables the scrambler.
TAIL BITS
The tail bit, PN generator, is located in Register 0x05F[6].
Setting Bit 6 to 0 disables the tail bit generator.
Setting Bit 6 to 1 enables the tail bit generator.
DDC MODES (SINGLE AND DUAL)
The AD9625 contains two separate DDCs that can digitally
downconvert real ADC output data into I/Q decimated data at a
reduced bandwidth. This feature is useful when the full
bandwidth supplied by the 2.5 GSPS converter is not needed.
Figure 74 shows a simplified block diagram of the DDC blocks
as they traverse through the AD9625. Because all JESD204B
frames contain four samples (S = 4), the output from the DDCs
must also output four samples. Table 19 shows the remapping of
I/Q samples to converter samples for the JESD204B interface,
specific to the AD9625.
When in mixed bandwidth mode, DDC 0 is always in high
bandwidth mode and DDC 1 is always in low bandwidth mode.
To match the data throughput of the high bandwidth mode, the
low bandwidth samples are repeated twice in mixed bandwidth
mode. Table 20 lists the four frames of data for both DDC 0
(high bandwidth mode) and DDC 1 (low bandwidth mode).
400
–400
–300
–200
–100
0
100
200
300
–150 –100 –50 0 50 100 150
VOLT AGE (mV)
TIME (ps)
11814-026
1
1
–2
1
–4
1
–6
1
–8
1
–10
1
–12
1
–14
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5
BER
UI
11814-027
180
160
140
120
100
80
60
40
20
0–15 –10 –5 0 5 10 15
HITS
TIME (ps)
11814-028
AD9625 Data Sheet
Figure 74. DDC Mapping
Table 19. DDC Remap I/Q to Converter Samples
Application Mode
Sample[N]
Sample[N + 1]
Sample[N + 2]
Sample[N + 3]
Single DDC I0[N] Q0[N] I0[N + 1] Q0[N + 1]
Dual DDCs I0[N] Q0[N] I1[N] Q1[N]
Table 20. DDC Mixed Bandwidth Mode
JESD204B Frame Number Sample[N] Sample[N + 1] Sample[N + 2] Sample[N + 3]
Frame 0
I
0
[N]
Q
0
[N]
I
1
[N]
Q
1
[N]
Frame 1
I0[N + 1]
Q0[N + 1]
I1[N]
Q1[N]
Frame 2
I0[N + 2]
Q0[N + 2]
I1[N + 1]
Q1[N + 1]
Frame 3
I0[N + 3]
Q0[N + 3]
I1[N + 1]
Q1[N + 1]
CHECKSUM
The JESD204B checksum value is sent with the configuration
parameters during the initial lane alignment sequence. Disabling
the checksum is primarily for debug purposes only.
8-BIT/10-BIT ENCODER CONTROL
The 8-bit/10-bit encoder must be controlled in the following
manner:
• The bypass 8-bit/10-bit encoder is controlled by
Register 0x60, Bit 2 (0 = 8-bit/10-bit enabled; 1 =
8-bit/10-bit bypassed).
• The invert 10-bit encoder is controlled by Register 0x060,
Bit 1 (0 = normal; 1 = invert).
• The mirror 10-bit encoder is controlled by Register 0x060,
Bit 0 (0 = normal; 1 = mirrored).
The inversion of the 10-bit values allows the user to swap the
true/complement differential pins swapped on the boards. For
details about Register 0x060, see the Memory Map Register
section.
INITIAL LANE ALIGNMENT SEQUENCE (ILAS)
The AD9625 must support three different ILAS modes that are
controlled using Bits[3:2] in Register 0x05F as follows:
• 00: disabled
• 01: enabled
• 10: reserved
• 11: always on test mode
When enabled, the device must also support the capability to
repeat the ILAS using Bits[7:0] in Register 0x062 to determine
the number of times ILAS is repeated (0 = repeat 0 times, ILAS
runs one time only, 1 = repeat one time, ILAS runs twice, and
so forth). Because the number of frames per multiframe is
determined by the value of K, the total number of frames
transmitted during the initial lane alignment sequence is
4 × (K + 1) × (ILAS_COUNT + 1)
where the value of K is defined in Register 0x070, Bits[4:0].
Note that only values divisible by four can be used.
For details about Register 0x05F and Register 0x062, see the
Memory Map Register section.
LANE SYNCHRONIZATION
Lane synchronization is defined by Register 0x05F, Bit 4 (0 =
disabled, 1 = enabled). For more information, see the Memory
Map Register section.
I0
Q0
I1
Q1
LOGICAL LANE 0 (L0)
LOGICAL LANE 1 (L1)
LOGICAL LANE 2 (L2)
LOGICAL LANE 3 (L3)
16
16
16
16
LOGICAL LANE 4 (L4)
LOGICAL LANE 5 (L5)
LOGICAL LANE 6 (L6)
LOGICAL LANE 7 (L7)
REMAP
I/Q TO
CONVERTER
SAMPLES
SAMPLE [N]
SAMPLE [N + 1]
SAMPLE [N + 2]
SAMPLE [N + 3]
48
ADC
JESD204X
INTERFACE
(M = 1; L = 8; S = 4;
F = 1; N = 16; N' = 16;
CF = 0; SCR = 0, 1;
HD = 1;
K = SEE SPECS)
12-BI T ADC
SAMPLES [N]
THROUGH [ N + 3]
11814-029
DCC 0DCC 1
Rev. A | Page 38 of 66
Data Sheet AD9625
Multichip Synchronization Using SYSREF± Timestamp
The SYSREF± pin in the AD9625 can also be used as a
timestamp of data as it passes through the ADC and out the
JESD204B interface. This can be accomplished in two ways:
• Replace the least significant converter bit with the
synchronous low to high captured SYSREF± signal. If
the AD9625 were configured as a 12-bit converter, this
would effectively reduce it to a 11-bit converter. This is
accomplished by setting Register 0x03A[7] = 1 in the
register map.
• Use the extra output JESD204B control bits to insert the
synchronous low to high captured SYSREF± signal. These
extra control bits are only available while in the JESD204B
generic 2, 4, and 8 lane modes. The generic 6 lane mode
does not support control bits as both N and N’ = 12.
6 Lane Output Mode
The full data output bandwidth of the 8 lane mode can
alternately by output using a 6 lane mode. This is achieved by
using an N’ = 12 in the 6 lane mode vs. N’ = 16 in the 8 lane
mode for N = 12 ADC data.
The benefit of using the 6 lane mode is that only 6 lanes of
output data are needed instead of 8 lanes and 2 output data
lanes can be powered down. A drawback of the 6 lane mode is
that because there is full efficiency of the link for N = N’ = 12,
there is no spare bandwidth available for control bits. Therefore,
control bit timestamping using SYSREF± cannot be used in the
6 lane mode. The LSB of the 12-bit ADC data can be substituted
to output the SYSREF± timestamp.
Figure 75. A SYSREF± Control Bit Can Be Used to Mark the Same Analog
Sample that is Coincident with a Sampled SYSREF± Edge by CLK±
ADC Output Control Bits on JESD204B Samples
When N' = 16 and the ADC resolution is 12, there are four
spare bits available per sample. Two of these spare bits can be
used as control bits, depending on the configuration options.
The control bits are set in Register 0x072, Bits[7:6]. (CS means
control bits per sample.)
• 00: no control bits sent per sample (CS = 0).
• 01: one control bit sent per sample, overrange bit enabled,
(CS = 1).
• 10: two control bits sent per sample, overrange and time
stamped SYSREF± control bit (marks the sample of a rising
edge seen on the SYSREF± pin), (CS = 2). Use of the
SYSREF± control bit (CS = 2) time stamps a particular
analog sample that is seen coincident with a rising signal
on the SYSREF± pins.
SYSREF± Setup and Hold IRQ
The differential SYSREF± inputs to AD9625 are critical for
JESD204B deterministic latency and sample timestamping. At
a 2.5 GSPS sample rate, the clock period is only 400 ps in
duration from which to accurately latch a SYSREF± edge to
meet setup and hold time to the sample clock. Therefore, it is
important to know the location of the SYSREF± edge relative to
the sampling edge of the encode clock. To help identify the
SYSREF± edge location within the clock period, the AD9625
provides a setup and hold time edge detector circuit to provide
feedback to the system for SYSREF± timing skew and other
alignment procedures. This is a fine timing detector (<1 clock
cycle) and will not provide useful information if coarse timing
(>1 clock cycle) skew adjustment is needed on SYSREF±.
The AD9625 provides an interrupt request (IRQ) bit that
identifies either a setup or a hold time error for the SYSREF±
edge relative to the sampling clock. The error indicates that the
SYSREF± edge is present within the designated time window.
There is a default detector window for both the actual setup and
hold time, with each being nominally 35 ps in time. This error
flag can be identified internal to the AD9625 IRQ register or the
status can be sent externally via the IRQ pin, provided that the
appropriate interrupts are masked or enabled as desired.
A SYSREF± edge located in either the setup or hold violation
window will cause ambiguity as to whether the event will be
latched on CLK±[N] or CLK±[N + 1]. As a best practice, the
SYSREF± edge needs to be earlier than both the setup and hold
violation windows so that a deterministic clock can be used to
latch SYSREF±.
Figure 76. SYSREF± Edge Falls Within the Actual Setup Time Window and
Triggers an IRQ Error
N – 1 N + 1
N + 2 N + 3
N
AIN
ENCODE
CLK
SYSREF
AD9625
PIPELINE
LATENCY
N – 1
N
N + 1
N + 2
N + 3
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SYSREF
CONT ROL BIT
12- BIT ADC
SAMPLES 4 - BIT CONTROL
AND TAI L BITS
SAMPLES
11814-480
CLK+
SYSREF–
SYSREF+
CLK–
SET UP IRQ E RROR
11814-481
Rev. A | Page 39 of 66
AD9625 Data Sheet
Figure 77. SYSREF± Edge Falls Within the Actual Hold Time Window and
Triggers an IRQ Error
IRQ Guardband Delays (SYSREF± Setup and Hold)
Additional guardband delays can be added to each of the default
setup and hold time windows. This will yield more information
to the system about the placement of the SYSREF± edge within
the clock period and help identify the proximity of the SYSREF±
edge to the actual setup and hold time windows. With a default
setting of 00b for both setup and hold, each has 7 additional
settings to increase the guardband timing feedback information.
There are 3 bits that define the SYSREF± setup time guardband
located in Register 0x13C[7:5]. There are 3 bits that define the
SYSREF± hold time guardband located in Register 0x13B[7:5].
A setting of 000b for either will be the default of no additional
timing guardband, with just the actual setup and hold time
window used as the IRQ.
The IRQ flag for the SYSREF± setup window is in Register
0x100[2], while the IRQ flag for the SYSREF± hold window is
in Register 0x100[3]. The IRQ flag mask for the SYSREF± setup
window is in Register 0x101[2], while the IRQ flag mask for the
SYSREF± hold window is in Register 0x101[3].
After each IRQ alert, the status will need to be cleared, as it will
not automatically clear itself, even if the alert conditions are no
longer valid. For either the SYSREF± setup or hold IRQ alert,
the status will be cleared using Register 0x03A[6]. Setting
Register 0x03A[6] = 1 will clear and hold the IRQ in a reset
value of 0. To allow IRQ flags pertaining to SYSREF± again, set
Register 0x03A[6] = 0.
Figure 78. SYSREF± Edge Falls Within the Guardbanded Setup Time Window
and Triggers an IRQ Error
In Figure 78, the SYSREF± edge meets the default setup and
hold time of the clock, but would trigger an IRQ event only if
certain setup time guardband delays were used. For this figure,
all of the setup guardband delays that would place the SYSREF±
crossing edge between it and the dotted black line would incur
an IRQ event equal to 1. All other settings would be 0. Because
there is no edge in the hold guardband delays, those would all
be 0 if they were set.
Table 21. IRQ Outcomes for All Setup or Hold Guardband
Settings for the Case in Figure 78
Setting/IRQ Setup Hold
000 0 0
001 0 0
010 0 0
011 0 0
100 1 0
101 1 0
110
1
0
111
1
0
Figure 79. SYSREF± Edge Falls Within the Guardbanded Hold Time Window
and Triggers an IRQ Error
In Figure 79, the SYSREF± edge misses the default setup and
hold time of the clock, but would trigger an IRQ event only if
certain hold time guardband delays were used. For this figure,
all of the hold guardband delays that would place the SYSREF±
crossing edge between it and the dotted black line would incur
an IRQ event equal to 1. All other settings would be 0. Because
there is no edge in the setup guardband delays, those would all
be 0 if they were set.
Table 22. IRQ Outcomes for All Setup or Hold Guardband
Settings Using the Case in Figure 79
Setting/IRQ Setup Hold
000 0 0
001 0 0
010 0 0
011
0
0
100 0 1
101 0 1
110 0 1
111 0 1
CLK+
SYSREF–
SYSREF+
CLK–
HOLD IRQ ERROR
11814-482
CLK+
SYSREF–
SYSREF+
CLK–
111
110
101
100
011
010
001
000
000
001
010
011
100
101
110
111
SET UP AND
GUARDBAND TIM E HOL D AND
GUARDBAND TIM E
SET UP GUARDBAND
IRQ DE LAYS HOLD GUARDBAND
IRQ DE LAYS
11814-483
CLK+
SYSREF–
SYSREF+
CLK–
111
110
101
100
011
010
001
000
000
001
010
011
100
101
110
111
SET UP AND
GUARDBAND TIM E HOL D AND
GUARDBAND TIM E
SET UP GUARDBAND
IRQ DE LAYS HOL D GUARDBAND
IRQ DE LAYS
11814-484
Rev. A | Page 40 of 66
Data Sheet AD9625
In the case where the encode clock used for the AD9625 is
sufficiently fast (>1.75 GSPS), the guardband delays for the
earliest setup and latest hold condition will start to overlap in
time due to the fast clock period. This case occurs when the
encode clock period is smaller than 16× the nominal delay
guardband window of 35 ps or (1/fS < 16 × 35 ps). The earliest
setup guardband delays from clock N can overlap with the latest
guardband delays from CLK±[N + 1]. When this is the case, a
SYSREF± edge located in one of these overlapped guardband
delays will trigger an IRQ event for both the setup and hold
detection. While it is possible to make use of this information, it
is suggested to limit the number of valid settings to no more
than 5 (100b) and below when sampling above 1.75 GSPS to
avoid this situation.
Figure 80. SYSREF± Edge Falls Within Both the Latest Hold Time
Guardbanded of CLK±[N] and the Earliest Setup Time Guardband of
CLK±[N + 1] and Triggers an IRQ Error
Table 23. IRQ Outcomes for All Setup or Hold Guardband
Settings Using the Case in Figure 80
Setting/IRQ Setup Hold
000 0 0
001 0 0
010 0 0
011 0 0
100 0 0
101 0 0
110 0 0
111 1 1
As a secondary use, the SYSREF± edge detector can also alert
the system about phase shift drift between SYSREF± and CLK
due to temperature or supply changes. For example, a
conservative guardband setting could be used, such that an IRQ
status of 0 would be seen in ideal conditions. If timing drifts
were significant enough to trigger the IRQ, the system would
take action to adjust the skew of the SYSREF± to CLK
accordingly to re-establish an IRQ of 0.
Figure 81. SYSREF± Edge Changes Phase Relative to the Encode Clock, Which
can be Detected When the Edge Crosses Through the Guardband Setup Time
Table 24. IRQ Outcomes for all Setup or Hold Guardband
Settings Using the Case in Figure 81
Setting/IRQ Setup Hold Setting/IRQ Setup Hold
000
0
0
000
0
0
001 0 0 001 0 0
010 0 0 010 1 0
011 0 0 011 1 0
100 1 0 100 1 0
101 1 0 101 1 0
110 1 0 110 1 0
111 1 0 111 1 0
Using Rising/Falling Edges of the CLK to Latch SYSREF±
The SYSREF± signal can be latched on either the rising or
falling edge of the encode clock, based on the value of register
0x03A[3] = 0 (latch on rising edge) or 0x03A[3] = 1 (latch on
falling edge). This will not impact the analog input, which will
always be sampled on the rising edge of the encode clock. For
sampling SYSREF±, the falling edge encode capture of
CLK±[N] will precede the rising edge encode capture of
CLK±[N], both corresponding to the same analog sample.
For synchronous sampling of multiple converters using
SYSREF±, it may be possible to have a scenario shown in
Figure 82. This case uses a SYSREF± capture with the falling
edge of the encode clock first to test the SYSREF± position
using the edge detection window. The three ADC’s each receive
a SYSREF± input that may be skewed in time due to board trace
length or source variance. For ADC[0] SYSREF± meets SU/
HLD to CLK±[N], ADC[1] misses SU/HLD to CLK±[N], and
ADC[2] is indeterminate as it falls within the SU/HLD window
and may be latched by either CLK±[N] or CLK±[N + 1].
CLK+
SYSREF–
SYSREF+
CLK–
111
110
101
100
011
010
001
000
000
001
010
011
HOL D AND
GUARDBAND T IM E [N]
SETUP AND
GUARDBAND T IM E [N + 1]
HOLD GUARDBAND
[N] IRQ DELAYS SE TUP GUARDBAND
[N +1] IRQ DE LAYS
010
001
000
000
001
010
011
100
101
110
111 OVERLAP
CLK±[N] CLK± [N + 1 ]
11814-485
CLK+
SYSREF–
SYSREF+
CLK–
111
110
101
100
011
010
001
000
000
001
010
011
100
101
110
111
SET UP AND
GUARDBAND TIM E HOL D AND
GUARDBAND TIM E
SET UP GUARDBAND
IRQ DE LAYS HOL D GUARDBAND
IRQ DE LAYS
11814-486
Rev. A | Page 41 of 66
AD9625 Data Sheet
Rev. A | Page 42 of 66
Figure 82. SYSREF± Case From Three ADCs Having Various Phase Delays
Relative to the Falling Edge of the Encode Clock and will be Latched on
Different Sample Clock Edges CLK±[N] or CLK±[N + 1]
As a solution to this case, the SYSREF± capture edge can be
changed from falling to rising, which will still be captured to the
analog sample from CLK±[N]. When this is done, all three
ADC’s now meet the SU/HLD time for the rising edge capture
of CLK±[N].
Figure 83. Changing the Latching Edge to Rising for All Three ADCs, SYSREF±
Can Now be Aligned to CLK±[N]
Test Modes
Bits[5:4] in Register 0x061 control the JESD204B interface test
injection points.
00: 16-bit test generation data injected at the sample input
to the link.
01: 10-bit test generation data injected at the output of the
8-bit/10-bit encoder (at the input to PHY).
10: 8-bit test generation data injected at the input of the
scrambler.
11: reserved.
Bits[3:0] in Register 0x061 determine the type of test patterns
that are injected, as follows:
0000: normal operation (test mode disabled).
0001: alternating checkerboard.
0010: 1/0 word toggle.
0011: PN sequence: long (x23 + x18 + 1).
0101: continuous/repeat user test mode; most significant
bits from 16-bit user pattern (1, 2, 3, 4) are placed on the
output for one clock cycle and then repeated. (Output user
pattern: 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, ….)
0110: single user test mode; most significant bits from the
16-bit user pattern (1, 2, 3, 4) placed on the output for one
clock cycle and then outputs all zeros. (Output user
pattern: 1, 2, 3, 4, then output all zeros.)
0111: Ramp output (dependent on test injection point and
number of bits, N).
1000: modified RPAT test sequence.
1001: unused.
1010: JSPAT test sequence.
1011: JTSPAT test sequence.
1100 to 1111: unused.
JESD204B APPLICATION LAYERS
The AD9625 supports the following application layer modes via
Register 0x063[3:0]:
0100: fS × x mode which supports line rates at integer
multiples of the sample rates
1000: single DDC mode, high bandwidth mode (only
DDC 0 used)
1001: single DDC mode, low bandwidth mode (only
DDC 0 used)
1010 to 1011: unused
1100: dual DDC mode, high bandwidth mode (both
DDC 0 and DDC 1 used)
1101: dual DDC mode, low bandwidth mode (both DDC 0
and DDC 1 used)
1110: dual DDC mode, mixed bandwidth mode (DDC 0
high bandwidth mode, DDC 1 low bandwidth mode,
samples repeated)
fS × 2, fS × 4, fS × 8 Modes
The JESD204B low multiplier mode application layer adds a
rate conversion on top of a JESD204B transmitter/receiver with
the following configuration parameters: M = 1; L = 8; S = 4;
F = 1; N = 16; N' = 16; CS = 0; CF = 0; SCR = 0, 1; HD = 1;
K = reference JESD204B specification.
In this mode, there are five actual samples per frame and
scrambling can be optionally enabled in the JESD204B
interface. The transmit portion of the low multiplier mode
JESD204B application layer is shown in Figure 84.
The first step in this application layer is where 12-bit ADC
samples are divided into six bytes.
To allow the line rate of the JESD204B interface to map directly
into an integer of the converter sample rate, a four to five rate
conversion takes place to group the 12-bit ADC samples into
blocks of five samples. During this rate conversion, for every
five 12-bit ADC sample, an extra user defined, 4-bit nibble is
appended to create a 64-bit frame. Next, the 64-bit low
multiplier frame maps into the four 16-bit JESD204B samples.
The most significant 16-bits of the 64-bit low multiplier frame
map to the oldest 16-bit JESD204Bsample and the least
significant 16-bits of the 64-bit low multiplier frame map to the
most recent 16-bit JESD204B sample.
The receive portion of the fS × 2 JESD204B application layer is
shown in Figure 85.
CLK+
CLK–
SYSREF–
S
YSREF+
SYSREF–
S
YSREF+
SYSREF–
S
YSREF+
ADC[0]
ADC[1]
ADC[2]
CLOCK[N]
FALLING CLO CK[N + 1 ]
FALLING
CLOCK[N]
RISING
?
11814-487
CLK+
CLK–
SYSREF–
S
YSREF+
SYSREF–
S
YSREF+
SYSREF–
S
YSREF+
ADC[0]
ADC[1]
ADC[2]
CLOCK[N]
FALLING CLO CK[N + 1 ]
FALLING
CLOCK[N]
RISING
11814-488
Data Sheet AD9625
Figure 84. fS × 2 Mode Application Layer (Transmit)
ADC SAMPL E N
(12 BITS)
ADC
JESD SAMPLE N
(16 BITS)
APPLICATION
LAYER
DATA LINK,
TRANSPORT,
AND PHY L AY E RS
fS
× 2 APPLI CATI ON L AY E R ( TRANSM IT )
4/5 RATE EX CHANGE
ADC CONVE RTER S AM P LE N
(N = 8, 10, O R 12 BITS)
CONT ROL BITS F OR SAMPLE N
(CS = 0, 2 OR 4 BITS )
ADC CONVE RTER S AM P LE N + 1
(N = 8, 10 O R 12 BITS)
CONT ROL BITS F OR SAMPLE N + 1
(CS = 0, 2 OR 4 BITS )
ADC CONVE RTER S AM P LE N + 2
(N = 8, 10 O R 12 BITS)
CONT ROL BITS F OR SAMPLE N + 2
(CS = 0, 2 OR 4 BITS )
ADC CONVE RTER S AM P LE N + 3
(N = 8, 10 O R 12 BITS)
CONT ROL BITS F OR SAMPLE N + 3
(CS = 0, 2 OR 4 BITS )
LANE 0
S[N][15:0]
S[N + 1][15: 0]
S[N + 2][15: 0]
S[N + 3][15: 0]
LANE 1
LANE 2
LANE 3
LANE 4
LANE 5
LANE6
LANE 7
USER DEFI NE D
(FSYNC[3:0])
ADC SAMPL E N + 1
(12 BITS) ADC SAMPLE N + 2
(12 BITS) ADC SAMPLE N + 3
(12 BITS)
48-BITS
@
fS
/4
64-BITS
@
fS
/5
64-BITS
@
fS
/5
ADC SAMPL E N
(12 BITS) ADC SAMPL E N + 1
(12 BITS) ADC SAMPL E N + 2
(12 BITS) ADC SAMPL E N + 3
(12 BITS) ADC SAMPL E N + 4
(12 BITS) (4 BITS)
S[N][11:0], S[N + 1][11:8]
(16 BITS) S[N + 1][7:0], S[N + 2][11:4]
(16 BITS) S[N + 2][3:0], S[N + 3][11:0]
(16 BITS) S[N + 4][11:0], UD[3:0]
(16 BITS)
JESD SAMPLE N + 1
(16 BITS) JESD SAM PLE N + 2
(16 BITS) JESD SAM PLE N + 3
(16 BITS)
JESD204x F RAMER + P HY
(M = 1; L = 8; S = 4; F = 1; N = 16; N' = 16; CF = 0; S CR = 0, 1; HD = 1; K = S E E S P E C
11814-032
Rev. A | Page 43 of 66
AD9625 Data Sheet
Figure 85. fS × 2 Application Layer (Receive)
APPLICATION
LAYER
DATA L INK,
TRANSPORT,
AND PHY L AY E RS
fS× 2 APPLI CATI ON L AY E R ( RE CE IVE )
4/5 RAT E E X CHANGE
CUSTOMER APPLICATION
ADC CONVE RTER S AM P LE N
(N = 8, 10, O R 12 BITS)
CONT ROL BITS F OR SAM P LE N
(CS = 0, 2 OR 4 BITS)
ADC CONVE RTER S AM P LE N + 1
(N = 8, 10 O R 12 BITS)
CONT ROL BITS F OR SAM P LE N + 1
(CS = 0, 2 OR 4 BITS)
ADC CONVE RTER S AM P LE N + 2
(N = 8, 10 O R 12 BITS)
CONT ROL BITS F OR SAM P LE N + 2
(CS = 0, 2 OR 4 BITS)
ADC CONVE RTER S AM P LE N + 3
(N = 8, 10 O R 12 BITS)
CONT ROL BITS F OR SAM P LE N + 3
(CS = 0, 2 OR 4 BITS)
LANE 0
S[N][15:0]
S[N + 1] [15:0]
S[N + 2] [15:0]
S[N + 3] [15:0]
LANE 1
LANE 2
LANE 3
LANE 4
LANE 5
LANE6
LANE 7
USER
DEFINED
ADC SAMPL E N
(12 BITS) ADC SAMPL E N + 1
(12 BITS) ADC SAMPL E N + 2
(12 BITS) ADC SAMPL E N + 3
(12 BITS)
48-BITS
@fS/4
64-BITS
@fS/5
64-BITS
@fS/5
ADC SAMPL E N
(12 BITS) ADC SAMP LE N + 1
(12 BITS) ADC SAMP LE N + 2
(12 BITS) ADC SAMP LE N + 3
(12 BITS) ADC SAMP LE N + 4
(12 BITS) (4 BITS )
S[N][11:0], S[N + 1][11:8]
(16 BITS) S[N + 1][7:0], S[N + 2][11:4]
(16 BITS) S[N + 2][3:0], S[N + 3][11:0]
(16 BITS) S[N + 4][11:0], UD[3:0]
(16 BITS)
JESD SAMPLE N
(16 BITS) JESD SAMPLE N + 1
(16 BITS) JESD SAMPL E N + 2
(16 BITS) JESD SAMPL E N + 3
(16 BITS)
JESD204x F RAM E R + P HY
(M = 1; L = 8; S = 4; F = 1; N = 16; N' = 16; CF = 0; S CR = 0, 1; HD = 1; K = S E E S P E C
11814-033
Rev. A | Page 44 of 66
Data Sheet AD9625
Rev. A | Page 45 of 66
FRAME ALIGNMENT CHARACTER INSERTION
Frame alignment character insertion (FACI) is defined in the
register map (see the Memory Map Register section). Disable
FACI only when it is used as a test feature.
The FACI disable bit is located in Register 0x05F, Bit 1. Use the
following settings:
Setting Bit 1 to 0 = FACI enabled
Setting Bit 1 to 1 = FACI disabled
THERMAL CONSIDERATIONS
Because of the high power nature of the device, it is critical to
provide airflow and/or install a heat sink when operating at a
high temperature. This ensures that the maximum case
temperature does not exceed 85°C.
POWER SUPPLY CONSIDERATIONS
The AD9625 must be powered by the following two supplies:
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 =
DRVDD2 = 2.5 V. An optional DVDDIO and SPI_DVDDIO
may be required at 2.5 V.
For applications requiring an optimal high power efficiency and
low noise performance, it is recommended that ADP2386
switching regulator is used to convert the 12 V input rail into
two intermediate rails (2.1 V and 3.6 V). These intermediate
rails are then postregulated by very low noise, low dropout (LDO)
regulators (ADP1740, ADP7104, and ADP125). Figure 86
shows the recommended method.
Figure 86. Power Supply Recommendation
11814-054
ADP1740
LDO
ADP1740
LDO
ADP1740
LDO
ADP1740
LDO
ADP125
LDO
ADP125
LDO
ADP2386
BUCK
REGULATOR
2.1V
ADP2386
BUCK
REGULATOR
3.6V
1.3V: AVDD1
2.5V: AVDD2
1.3V: DRVDD1
1.3V: DVDD1
2.5V: DRVDD2
2.5V: DVDDI O
2.5V: S PI_DVDDI O
2.5V: DVDD2
12V
INPUT
AD9625 Data Sheet
SERIAL PORT INTERFACE (SPI)
The AD9625 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields. These fields are documented
in the Memory Map section.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CSB pin (see Table 25). The SCLK (serial clock) pin is
used to synchronize the read and write data presented from/to the
ADC. The SDIO (serial data input/output) pin is a dual-purpose
pin that allows data to be sent and read from the internal ADC
memory map registers. The CSB (chip select bar) pin is an active
low control that enables or disables the read and write cycles.
Table 25. Serial Port Interface Pins
Pin Function
SCLK Serial Clock. The serial shift clock input, which is used to
synchronize serial interface, reads and writes.
SDIO Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
CSB Chip Select Bar. An active low control that gates the read
and write cycles.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing.
Other modes involving the CSB pin are available. The CSB pin
can be held low indefinitely, which permanently enables the
device; this is called streaming. The CSB pin can stall high
between bytes to allow for additional external timing. When
CSB is tied high, SPI functions are placed in a high impedance
mode. This mode turns on any SPI pin secondary functions.
All data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether a read or write command is
issued. This allows the SDIO pin to change direction from an
input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a read
operation, performing a read causes the SDIO pin to change
direction from an input to an output at the appropriate point in
the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register.
HARDWARE INTERFACE
The pins described in Table 25 comprise the physical interface
between the user programming device and the serial port of the
AD9625. The SCLK pin and the CSB pin function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during read.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
Do not activate the SPI port during periods when the full dynamic
performance of the converter is required. Because the SCLK signal,
the CSB signal, and the SDIO signal are typically asynchronous to
the ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9625 to prevent these signals from transitioning at the
converter inputs during critical sampling periods.
Rev. A | Page 46 of 66
Data Sheet AD9625
MEMORY MAP
READING THE MEMORY MAP REGISTER
Each row in the memory map register contains eight bit
locations. The memory map is roughly divided into three
sections: the chip configuration registers (Address 0x000 to
Address 0x002); the transfer register (Address 0x0FF); and the
ADC functions registers, including setup, control, and test
(Address 0x008 to Address 0x13A).
The memory map register tables provide the default hexadecimal
value for each hexadecimal address that is listed.
The column with the heading, Bit 7 (MSB), is the start of the
default hexadecimal value given. For example, Address 0x14,
the output mode register, has a hexadecimal default value of
0x01. This means that Bit 0 = 1, and the remaining bits are 0s.
This setting is the default output format value, which is twos
complement. For more information on this function and others,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
Open and Reserved Locations
All address and bit locations are not currently supported for this
device. Unused bits of a valid address location should be written
with 0s. Writing to these locations is required only when a
portion of an address location is open. If the entire address
location is open, this address location should not be written.
Default Values
After the AD9625 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register tables.
Logic Levels
An explanation of logic level terminology follows:
•“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
•“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Register addresses for the AD9625 are shadowed. Register
writes do not affect device operation until a transfer command
is issued by writing 0x01 to Address 0x0FF, thereby setting the
transfer bit. This allows the registers to update internally and
simultaneously when the transfer bit is set. The internal update
occurs when the transfer bit is set, and then the bit
automatically clears.
MEMORY MAP REGISTERS
Address and bit locations that are not included in Table 26
through Table 116 are not currently supported for this device.
Table 26. SPI Configuration Register, Address 0x000 (Default = 0x18)
Bit No. Access Bit Description
7 Unused.
6 RW SPI least significant bit (LSB) first.
1: LSB shifted first for all SPI operations. For multibyte SPI operations, the addressing increments
automatically.
0: most significant bit (MSB) shifted first for all SPI operations. For multibyte SPI operations, the
addressing decrements automatically.
5 RW Self clearing soft reset.
1: reset the SPI registers (self clearing).
0: do nothing.
4 R 13-bit addressing enabled.
3 R 13-bit addressing enabled.
2 RW Self clearing soft reset.
1: reset the SPI registers(self clearing).
0: do nothing.
1 RW SPI LSB first.
1: LSB shifted first for all SPI operations. For multi-byte SPI operations, the addressing increments
automatically.
0: MSB shifted first for all SPI operations. For multi-byte SPI operations, the addressing decrements
automatically.
0 Unused Unused.
Table 27. Chip ID Register, Address 0x001 (Default = 0x41)
Bit No. Access Bit Description
[7:0] R Chip ID.
Rev. A | Page 47 of 66
AD9625 Data Sheet
Table 28. Chip Grade Register, Address 0x002 (Default = 0x14)
Bit No. Access Bit Description
[7:6] Unused.
[5:4] R Chip ID/speed grade.
10: 2.5 GSPS
01: 2.0 GSPS
3 Unused.
[2:0] R Chip die revision.
100: silicon revision code.
101 to 111: reserved.
Table 29. Power Control Mode Register, Address 0x008 (Default = 0x80)
Bit No. Access Bit Description
7 Reserved
6 Reserved
5 Reserved
[4:2] Reserved
[1:0]
RW
Chip power modes.
00: normal mode (power-up).
01: Power-down
10: standby mode; digital datapath clocks disabled, JESD204B interface enabled, outputs enabled.
11: digital datapath reset mode; digital data path clocks enabled, digital data path held in reset, JESD204B interface
held in reset, outputs enabled.
Table 30. PLL Status Register, Address 0x00A (Default = 0x00)
Bit No. Access Bit Description
7
RO
PLL locked status bit.
0: PLL is unlocked.
1: PLL is locked.
[6:0] Reserved
Table 31. ADC Test Control Register, Address 0x00D (Default = 0x00)
Bit No. Access Bit Description
7 RW ADC datapath user test mode control. Note: These bits are only used when Register 0x00D, Bits[3:0] is in user input mode
(Register 0x00D[3:0] = 1000); otherwise, they are ignored.
0 = continuous/repeat pattern mode. Place each user pattern (1, 2, 3, 4) on the output for one clock cycle and then repeat.
(Output user pattern: 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, …)
1 = single pattern mode. Place each user pattern (1, 2, 3, 4) on the output for one clock cycle and then output all zeros.
(Output user pattern: 1, 2, 3, 4, then output all zeros.)
6 Unused.
5 RW ADC long psuedo random number test generator reset.
0: long PN enabled.
1: long PN held in reset.
4 RW Unused.
[3:0] RW ADC data output test generation mode.
0000: off, normal operation.
0001: midscale short.
0010: positive full scale.
0011: negative full scale.
0100: alternating checkerboard.
0101: PN sequence, long.
0110: unused.
0111: one-/zero-word toggle.
1000: user test mode. Used with Register 0x00D[7] and user pattern (1, 2, 3, 4) registers.
1001 to 1110: unused.
1111: ramp output.
Rev. A | Page 48 of 66
Data Sheet AD9625
Table 32. Data Path Customer Offset Register, Address 0x010 (Default = 0x00)
Bit No. Access Bit Description
[7:6] Unused.
[5:0] RW Digital datapath offset. Twos complement offset adjustment aligned with least converter resolution.
011111: +31
011110: +30
…
000001: 1
000000: 0
111111: −1
…
100001: −31
100000: −32
Table 33. Output Mode Register, Address 0x014 (Default = 0x01)
Bit No.
Access
Bit Description
[7:5] Unused.
4 RW Chip output disable. Bit 4 enables and disables the digital outputs from the ADC.
0: enable.
1: disable.
3 Unused.
2 RW Digital ADC sample invert.
0: ADC sample data is not inverted.
1: ADC sample data is inverted.
[1:0] RW Digital ADC data format select (DFS). Note: the use of the muxed SDIO pin to control Register 0x014[1:0] is not
supported on the AD9625.
00: offset binary.
01: twos complement (default).
10: reserved.
11: reserved.
Table 34. Serializer Output Adjust, Register, Address 0x015 (Default = 0x54)
Bit No. Access Bit Description
7 RW Serializer output polarity selection.
0: normal, not inverted.
1: output driver polarity inverted.
[6:5] RW Serializer output emphasis amplitude control.
00: 0 mV de-emphasis differential p-p.
01: 160 mV de-emphasis differential p-p.
10: 80 mV de-emphasis differential p-p.
11: 40 mV de-emphasis differential p-p.
[4:0] RW Reserved.
Table 35. User Test Pattern 1 LSB Register, Address 0x019 (Default = 0x00)
Bit No.
Access
Bit Description
[7:0] RW User Test Pattern 1 least significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input
mode (Register 0x00D[3:0] = 1000), or when Register 0x061, Bits[3:0] is in the scrambler or 10-bit test modes
(Register 0x061[3:0] = 0100 to 0111). Otherwise, these bits are ignored.
Table 36. User Test Pattern 1 MSB Register, Address 0x01A (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW User Test Pattern 1 most significant byte. Note: These bits are used only when Register 0x00D, Bits[3:0] is in user input
mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.
Rev. A | Page 49 of 66
AD9625 Data Sheet
Table 37. User Test Pattern 2 LSB Register, Address 0x01B (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW User Test Pattern 2 least significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input
mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.
Table 38. User Test Pattern 2 MSB Register, Address 0x01C (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW User Test Pattern 2 most significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input
mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.
Table 39. User Test Pattern 3 LSB Register, Address 0x01D (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW User Test Pattern 3 least significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input
mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.
Table 40. User Test Pattern 3 MSB Register, Address 0x01E (Default = 0x00)
Bit
No. Access Bit Description
[7:0] RW User Test Pattern 3 most significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user
input mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.
Table 41. User Test Pattern 4 LSB Register, Address 0x01F (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW User Test Pattern 4 least significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input
mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.
Table 42. User Test Pattern 4 MSB Register, Address 0x020 (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW User Test Pattern 4 most significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input
mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.
Table 43. Synthesizer PLL Control Register, Address 0x021 (Default = 0x00)
Bit No. Access Bit Description
[7:5] Unused.
4 RW 1 = force power-down of VCO LDO
3 RW Reserved for future use.
[2:0] Unused.
Table 44. ADC Analog Input Control Register, Address 0x02C (Default = 0x00)
Bit No. Access Bit Description
[7:3] Unused.
2 RW Set function on VMON pin.
0: unused.
1: allows external reference on VMON pin.
[1:0] Unused.
Table 45. SYSREF± Control Register, Address 0x03A (Default = 0x00)
Bit No. Access Bit Description
7 RW SYSREF± status bit replaces the LSB from the converter.
0: normal mode.
1: SYSREF± status bit replaces the LSB.
6 RW SYSREF± status bit flag reset. To use the flags, Register 0x03A, Bit 1 must be set to high.
0: normal flag operation.
1: SYSREF± status bit flags held in reset.
5 Unused.
Rev. A | Page 50 of 66
Data Sheet AD9625
Bit No. Access Bit Description
4 RW SYSREF± transition selection.
0: SYSREF± is valid on low to high transitions using selected CLK edge.
1: SYSREF± is valid on high to low transitions using selected CLK edge.
3 RW SYSREF± capture edge selection.
0: captured on rising edge of CLK input.
1: captured on falling edge of CLK input.
2 RW SYSREF± next mode.
0: continuous mode.
1: next SYSREF± mode: uses the next valid edge only of the SYSREF± pin. Subsequent edges of the SYSREF± pin are
ignored. When the next system reference is found, Bit 1 of Register 0x03A clears.
1 RW SYSREF± pins enable.
0: SYSREF± disabled.
1: SYSREF± enabled. When Register 0x03A, Bit 2 = 1, only the next valid edge of the SYSREF± pins is used. Subsequent
edges of the SYSREF± pin are ignored.
0 Unused.
Table 46. Fast Detect Control Register, Address 0x045 (Default = 0x00)
Bit No. Access Bit Description
[7:4] Unused.
3 RW Force the fast detect output pin.
0: normal operation of fast detect pin.
1: force a value on the fast detect pin (see Bit 2 in this table, Table 46).
2 RW The fast detect output pin is set to the value in this bit (Register 0x045[2]) when the output is forced.
1 Unused.
0 RW Enable fast detect on the corrected ADC data.
0: fine fast detect disabled.
1: fine fast detect enabled.
Table 47. Fast Detect Upper Threshold Register, Address 0x047 (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW These bits are the LSBs of the fast detect upper threshold. These eight LSBs of the programmable 12-bit upper threshold
are compared to the fine ADC magnitude.
Table 48. Fast Detect Upper Threshold Register, Address 0x048 (Default = 0x00)
Bit No. Access Bit Description
[7:4] Unused.
[3:0] RW These bits are the MSBs of the fast detect upper threshold. These four MSBs of the programmable 12-bit upper
threshold are compared to the fine ADC magnitude.
Table 49. Fast Detect Lower Threshold Register, Address 0x049 (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW These bits are the LSBs of the fast detect lower threshold. These eight LSBs of the programmable 12-bit lower threshold
are compared to the fine ADC magnitude.
Table 50. Fast Detect Lower Threshold Register, Address 0x04A (Default = 0x00)
Bit No. Access Bit Description
[7:4]
Unused.
[3:0] RW MSBs of the fast detect lower threshold. These four MSBs of the programmable 12-bit lower threshold are compared
to the fine ADC magnitude.
Table 51. Fast Detect Dwell Time Counter Threshold Register, Address 0x04B (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW These bits are the LSBs of the fast detect dwell time counter target. This is the value for a 16-bit counter that determines
the length of time that the ADC data must remain below the lower threshold before the FD pin reset to 0.
Rev. A | Page 51 of 66
AD9625 Data Sheet
Table 52. Fast Detect Dwell Time Counter Threshold Register, Address 0x04C (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW These bits are the MSBs of the fast detect dwell time counter target. This is the value for a 16-bit counter that
determines the length of time that the ADC data must remain below the lower threshold before the FD pin resets to 0.
Note that the fast detect (FD) pin de-asserts after the ADC codes stay below the lower target for the number of samples
indicated by the value in Register 0x04C[7:0].
Table 53. JESD204B Quick Configuration Register, Address 0x05E (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW JESD204B serial quick configuration (self clearing). This register is self clearing and does not control anything in the
AD9625 directly; it only changes the value of the other JESD240B registers that control the chip. Because this register is
self clearing, it always returns to 000 after each write. To use the quick configuration feature, write to this register first,
then, if there are any changes that need to be made to any of the following settings, write to the other JESD204B
registers.
0x00: configuration determined by other registers. Because the register is self clearing, it always returns to this value
after each write.
0x01: reserved.
0x02: Generic 2 Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xB;
Register 0x073[4:0] = 0xF.
0x04: Generic 4 Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x3; Register 0x072[4:0] = 0xB;
Register 0x073[4:0] = 0xF.
0x06: Generic 6 Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x5; Register 0x072[4:0] = 0xB;
Register 0x073[4:0] = 0xB.
0x08: Generic 8 Lane Configuration Register 0x063[3:0] = 0x0; Register 0x06E[4:0] = 0x7; Register 0x072[4:0] = 0xB;
Register 0x073[4:0] = 0xF.
0x42: reserved.
0x44: reserved.
0x48: fS × 2 mode, eight lanes. Register 0x063[3:0] = 0x4; Register 0x06E[4:0] = 0x7; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0x81: 1 DDC (high BW), one lane. Register 0x063[3:0] = 0x8; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0x82: 1 DDC (high BW), two lanes. Register 0x063[3:0] = 0x8; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0x91: 1 DDC (low BW), one lane. Register 0x063[3:0] = 0x9; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF; Register
0x073[4:0] = 0xF.
0xC1: 2 DDCs (high BW), one lane. Register 0x063[3:0] = 0xC; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xC2: 2 DDCs (high BW), two lanes. Register 0x063[3:0] = 0xC; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xC4: 2 DDCs (high BW), four lanes. Register 0x063[3:0] = 0xC; Register 0x06E[4:0] = 0x3; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xD1: 2 DDCs (low BW), one lane. Register 0x063[3:0] = 0xD; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xD2: 2 DDCs (low BW), two lanes. Register 0x063[3:0] = 0xD; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xE1: 2 DDCs (mixed BW), one lane. Register 0x063[3:0] = 0xE; Register 0x06E[4:0] = 0x0; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xE2: 2 DDCs (mixed BW), two lanes. Register 0x063[3:0] = 0xE; Register 0x06E[4:0] = 0x1; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
0xE4: 2 DDCs (mixed BW), four lanes. Register 0x063[3:0] = 0xE; Register 0x06E[4:0] = 0x3; Register 0x072[4:0] = 0xF;
Register 0x073[4:0] = 0xF.
All other values have no effect.
Rev. A | Page 52 of 66
Data Sheet AD9625
Table 54. JESD204B Link Control Register 1, Address 0x05F (Default = 0x14)
Bit No. Access Bit Description
7 Unused.
6 RW JESD204B serial tail bit, PN, enable. Note: the following equation can be used to determine the number of PN bits sent
per sample = N' − N – CS (the number of control bits per sample).
0: serial tail bit, PN, disabled. Unused extra tail bits are padded with zeros.
1: serial tail bit, PN, enabled. Unused extra tail bits are padded with a pseudo random number sequence from a 31-bit
LFSR (see JESD204B 5.1.4).
5 RW JESD204B serial test sample enable.
0: JESD204B test samples disabled.
1: JESD204B test samples enabled. The transport layer test sample sequence (as specified in JESD204B Section 5.1.6.2) is
sent on all link lanes.
4 RW JESD204B serial lane synchronization enable. Note that the frame character insertion must be enabled (Register 0x05F[1] = 0)
to enable lane synchronization.
0: lane synchronization disabled. Both sides do not perform lane synchronization; frame alignment character insertion
always uses /K28.7/ control characters (see JESD204B 5.3.3.4).
1: lane synchronization enabled. Both sides perform lane sync; frame alignment character insertion uses either /K28.3/
or /K28.7/ control characters (see JESD204B 5.3.3.4).
[3:2] RW JESD204B serial initial lane alignment sequence mode.
00: initial lane alignment sequence disabled (JESD204B 5.3.3.5).
01: initial lane alignment sequence enabled (JESD204B 5.3.3.5).
10: reserved.
11: initial lane alignment sequence always on test mode; the JESD204B data link layer test mode (where repeated lane
alignment sequence, as specified in JESD204B section 5.3.3.9.2) is sent on all lanes.
1 RW JESD204B serial frame alignment character insertion (FACI) disable.
0: frame alignment character insertion enabled (JESD204B 5.3.3.4).
1: frame alignment character insertion disabled. Note that this is for debug only (JESD204B 5.3.3.4).
0 RW JESD204B serial transmit link power-down (active high). Note that the JESD204B transmitter link must be powered
down while changing any of the link configuration bits.
0: JESD204B serial transmit link enabled. Transmission of the /K28.5/ characters for code group synchronization is
controlled by the SYNCINB± pins.
1: JESD204B serial transmit link powered down (held in reset and clock gated).
Table 55. JESD204B Link Control Register 2, Address 0x060 (Default = 0x00)
Bit No. Access Bit Description
[7:6]
RW
JESD204B serial synchronization mode.
00: normal mode.
01: reserved.
10: SYNCINB± active mode. SYNCINB± pins are active: force code group synchronization.
11: SYNCINB± pins disabled.
5 RW JESD204B serial synchronization pin invert.
0: SYNCINB± pins not inverted.
1: SYNCINB± pins inverted.
[4:3] Unused.
2 RW JESD204B Serial 8-bit/10-bit bypass (test mode only).
0: 8-bit/10-bit enabled.
1: 8-bit/10-bit bypassed (most significant two bits are 0).
1 RW JESD204B 10-bit serial transmit bit invert. Note that in the event that the CML signals are reversed in a system board
layout, this bit effectively inverts the differential outputs from the PHY.
0: normal.
1: invert the a, b, c, d, e, f, g, h, i, j bits.
0 RW JESD204B 10-bit serial transmit bit mirror.
0: 10-bit serial bits are not mirrored. Transmit bit order is alphabetical: a, b, c, d, e, f, g, h, i, j.
1: 10-bit serial bits are mirrored. Transmit bit order is alphabetically reversed: j, i, h, g, f, e, d, c, b, a.
Rev. A | Page 53 of 66
AD9625 Data Sheet
Table 56. JESD204B Link Control Register 3, Address 0x061 (Default = 0x00)
Bit No. Access Bit Description
7
RW
JESD204B checksum disable.
0: checksum enabled in the link configuration parameter. Normal operation.
1: checksum disabled in the link configuration parameter (set to zero). For testing purposes only.
6 RW JESD204B checksum mode.
0: checksum is the sum of all 8-bit registers in the link configuration fields.
1: checksum is the sum of all individual link configuration fields (LSB aligned).
[5:4] RW JESD204B serial test generation input selection.
00: 16-bit test generation data injected at the sample input to the link.
01: 10-bit test generation data injected at the output of the 8-bit/10-bit encoder (at the input to PHY).
10: 8-bit test generation data injected at the input of the scrambler.
11: reserved.
[3:0]
RW
JESD204B serial test generation mode.
0000: normal operation (test mode disabled).
0001: alternating checkerboard.
0010: 1/0 word toggle.
0011: PN sequence (long).
0100: unused.
0101: continuous/repeat user test mode. The most significant bits from the user pattern (1, 2, 3, 4) are placed on the
output for one clock cycle and then repeated (the output user pattern is 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, …).
0110: single user test mode. The most significant bits from the user pattern (1, 2, 3, 4) are placed on the output for one
clock cycle and then output all zeros (the output user pattern is 1, 2, 3, 4, and then outputs all zeros).
0111: ramp output.
1000: modified RPAT test sequence (10-bit value).
1001: unused.
1010: JSPAT test sequence (10-bit value).
1011: JTSPAT test sequence (10-bit value).
1100 to 1111: unused.
Table 57. JESD204B Link Control Register 4, Address 0x062 (Default 0x00)
Bit No. Access Bit Description
[7:0]
RW
Initial lane alignment sequence repeat count. Bits[7:0] specify the number of times the initial lane alignment sequence
repeats. For ADCs, the JESD204B specification states that the initial lane alignment sequence always spans four multiframes
(JESD204B 5.3.3.5). Because Register 0x070, Bits[4:0] determine the number of frames per multiframe, the total number of
frames transmitted during the initial lane alignment sequence = 4 × (Register 0x070[4:0] + 1) × (Register 0x062[7:0] + 1).
Table 58. JESD204B Link Control Register 5, Address 0x063 (Default = 0x80)
Bit No. Access Bit Description
7 Reserved
[6:4]
Reserved
[3:0] RW JESD204B application layer mode. DDC bandwidth modes are as follows: high bandwidth, decimate by 8 (effective output
bandwidth = fS/10) and low bandwidth, decimate by 16 (effective output bandwidth = fS/20).
0000: generic (no application layer used).
0001: unused.
0010: unused.
0011: unused.
0100: f
S
× x mode (where x is an integer: 2, 4, 8).
0101 to 0111: unused.
1000: single DDC mode (high bandwidth mode (only DDC0 used).
1001: single DDC mode (low bandwidth mode (only DDC0 used).
1010 to 1011: unused.
1100: dual DDC mode, high bandwidth mode (both DDC 0 and DDC 1 used).
1101: dual DDC mode, low bandwidth mode (both DDC 0 and DDC 1 used).
1110: dual DDC mode, mixed bandwidth mode (DDC 0 high bandwidth mode, DDC 1 low bandwidth mode, samples
repeated).
1111: unused.
Rev. A | Page 54 of 66
Data Sheet AD9625
Table 59. JESD204B Configuration Register, Address 0x064 (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW JESD204B serial device identification (DID) number.
Table 60. JESD204B Configuration Register, Address 0x065 (Default = 0x00)
Bit No. Access Bit Description
[7:4] Unused.
[3:0] RW JESD204B serial bank identification (BID) number (extension to DID).
Table 61. JESD204B Configuration Register, Address 0x066 (Default = 0x00)
Bit No. Access Bit Description
[7:5] Unused.
[4:0]
RW
JESD204B serial lane identification (LID) number for Lane 0.
Table 62. JESD204B Configuration Register, Address 0x067 (Default = 0x01)
Bit No. Access Bit Description
[7:5] Unused.
[4:0] RW JESD204B serial lane identification (LID) number for Lane 1.
Table 63. JESD204B Configuration Register, Address 0x068 (Default = 0x02)
Bit No. Access Bit Description
[7:5] Unused.
[4:0] RW JESD204B serial lane identification (LID) number for Lane 2.
Table 64. JESD204B Configuration Register, Address 0x069 (Default = 0x03)
Bit No. Access Bit Description
[7:5] Unused.
[4:0] RW JESD204B serial lane identification (LID) number for Lane 3.
Table 65. JESD204B Configuration Register, Address 0x06A (Default = 0x04)
Bit No. Access Bit Description
[7:5] Unused.
[4:0] RW JESD204B serial lane identification (LID) number for Lane 4.
Table 66. JESD204B Configuration Register, Address 0x06B (Default = 0x05)
Bit No. Access Bit Description
[7:5] Unused.
[4:0] RW JESD204B serial lane identification (LID) number for Lane 5.
Table 67. JESD204B Configuration Register, Address 0x06C (Default = 0x06)
Bit No. Access Bit Description
[7:5] Unused.
[4:0] RW JESD204B serial lane identification (LID) number for Lane 6.
Table 68. JESD204B Configuration Register, Address 0x06D (Default = 0x07)
Bit No. Access Bit Description
[7:5]
Unused.
[4:0] RW JESD204B serial lane identification (LID) number for Lane 7.
Table 69. JESD204B Configuration Register, Address 0x06E (Default = 0x87)
Bit No. Access Bit Description
7 RW JESD204B serial scrambler mode.
0: JESD204B scrambler disabled (SCR = 0).
1: JESD204B scrambler enabled (SCR = 1).
[6:5] Unused.
Rev. A | Page 55 of 66
AD9625 Data Sheet
Bit No. Access Bit Description
[4:0] RW JESD204B serial lane control (L = Register 0x06E[4:0] + 1).
0: one lane per link (L = 1).
1:two lanes per link (L = 2).
2: unused.
3: four lanes per link (L = 4).
4: unused.
5: six lanes per link (L = 6).
6: unused.
7: eight lanes per link (L = 8).
8 to 31: unused.
Table 70. JESD204B Configuration Register, Address 0x06F (Default = 0x00)
Bit No. Access Bit Description
[7:0] RO JESD204B number of octets per frame (F = Register 0x06F[7:0] + 1). These bits are calculated using the following
equation:
F = (Nʹ)/(2 × L)
The following are valid values of F:
M = 1, S = 4, N' = 16, L = 1, F = 8.
M = 1, S = 4, N' = 16, L = 2, F = 4.
M = 1, S = 4, N' = 16, L = 4, F = 2.
M = 1, S = 4, N' = 12, L = 6, F = 1.
M = 1, S = 4, N' = 16, L = 8, F = 1 (default).
Table 71. JESD204B Configuration Register, Address 0x070 (Default = 0x1F)
Bit No. Access Bit Description
[7:5] Unused.
[4:0] RW JESD204B number of frames per multiframe (K = Register 0x070[4:0] + 1). Only those values that are divisible by
four can be used.
Table 72. JESD204B Configuration Register, Address 0x071 (Default = 0x00)
Bit No. Access Bit Description
[7:0] RO JESD204B number of converters per link/device.
0: link connected to one ADC (M = 1).
1 to 255: unused.
Table 73. JESD204B Configuration Register, Address 0x072 (Default = 0x0B)
Bit No.
Access
Bit Description
[7:6] RW JESD204B number of control bits per sample (CS, based on the JESD204B specification).
00: no control bits sent per sample (CS = 0).
01: one control bit sent per sample, overrange bit enabled (CS = 1).
10: two control bits sent per sample, overrange + timestamp SYSREF bit (CS = 2).
11: reserved.
5 Unused.
[4:0] RW JESD204B converter resolution (N = Register 0x072[4:0] + 1).
0x00 to 0x06: reserved.
0x07 to 0x09: reserved.
0x0A: reserved.
0x0B: N = 12-bit ADC converter resolution.
0x0C to 0x0E: reserved.
0x0F: N = 16-bit ADC converter resolution.
0x10 to 0x1F: reserved.
Rev. A | Page 56 of 66
Data Sheet AD9625
Table 74. JESD204B Configuration Register, Address 0x073 (Default = 0x2F)
Bit No. Access Bit Description
[7:5] RW JESD204B device subclass version.
0x0: Subclass 0.
0x1: Subclass 1 (default).
0x2: Subclass 2 (not supported).
0x3: undefined.
[4:0] RW JESD204B total number of bits per sample (N' = Register 0x073[4:0] + 1).
0x0 to 0xA: unused.
0xB: N' = 12 (L must be equal to 6).
0xC to 0xE: unused.
0xF: N'=16 (L must be equal to 1, 2, 4, or 8).
Table 75. JESD204B Configuration Register, Address 0x074 (Default = 0x23)
Bit No. Access Bit Description
[7:5] RW JESD204B version.
0x0: JESD204A. SYNCINB± pins input are internally gated by the frame clock. SYNCINB± must be low for at
least two frame clock cycles to be interpreted as a synchronization request.
0x1: JESD204B. SYNCINB± pins input are internally gated by the local multiframe clock. SYNCINB± must be
low for at least four frame clock cycles to be interpreted as a synchronization request.
0x2 to 0x7: undefined.
[4:0] RO JESD204B samples per converter frame cycle (S = Register 0x074[4:0] + 1). These are read-only bits. For the
AD9625, S must be equal to 4 (Register 0x074[4:0] = 3).
Table 76. JESD204B Configuration Register, Address 0x075 (Default = 0x80)
Bit No. Access Bit Description
7 RO JESD204B high density (HD) format. This is a read-only bit.
0: HD format disabled.
1: HD format enabled. High density mode is automatically enabled based on the values of N' and L.
The values of HD for the AD9625 are as follows:
N' = 16, L = 1, HD = 0.
N' = 16, L = 2, HD = 0.
N' = 16, L = 4, HD = 0.
N' = 12, L = 6, HD = 1.
N' = 16, L = 8, HD = 1 (default).
[6:5] Unused.
[4:0] RO JESD204B Number of control words per frame clock cycle per link (CF). These are read-only bits. For the AD9625,
CF must equal 0 (Register 0x075[4:0] = 0).
Table 77. JESD204B Configuration Register, Address 0x076 (Default = 0x00)
Bit No.
Access
Bit Description
[7:0] RW JESD204B Serial Reserved Field 1.
Table 78. JESD204B Configuration Register, Address 0x077 (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW JESD204B Serial Reserved Field 2.
Table 79. JESD204B Configuration Register, Address 0x078 (Default = 0xC3)
Bit No. Access Bit Description
[7:0] RO JESD204B serial checksum value for Lane 0. This value is automatically calculated The value = (the sum of all link
configuration parameters for Lane 0) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.
Table 80. JESD204B Configuration Register, Address 0x079 (Default = 0xC4)
Bit No. Access Bit Description
[7:0] RO JESD204B serial checksum value for Lane 1. This value is automatically calculated. The value = (the sum of all link
configuration parameters for Lane 1) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.
Rev. A | Page 57 of 66
AD9625 Data Sheet
Rev. A | Page 58 of 66
Table 81. JESD204B Configuration Register, Address 0x07A (Default = 0xC5)
Bit No. Access Bit Description
[7:0] RO JESD204B serial checksum value for Lane 2. This value is automatically calculated. The value = (the sum of all link
configuration parameters for Lane 2) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.
Table 82. JESD204B Configuration Register, Address 0x07B (Default = 0xC6)
Bit No. Access Bit Description
[7:0] RO JESD204B serial checksum value for Lane 3. This value is automatically calculated. The value = (the sum of all link
configuration parameters for Lane 3) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.
Table 83. JESD204B Configuration Register, Address 0x07C (Default = 0xC7)
Bit No. Access Bit Description
[7:0] RO JESD204B serial checksum value for Lane 4. This value is automatically calculated. The value = (the sum of all link
configuration parameters for Lane 4) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.
Table 84. JESD204B Configuration Register, Address 0x07D (Default = 0xC8)
Bit No. Access Bit Description
[7:0] RO JESD204B serial checksum value for Lane 5. This value is automatically calculated. The value = (the sum of all link
configuration parameters for Lane 5) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.
Table 85. JESD204B Configuration Register, Address 0x07E (Default = 0xC9)
Bit No. Access Bit Description
[7:0] RO JESD204B serial checksum value for Lane 6. This value is automatically calculated. The value = (the sum of all link
configuration parameters for Lane 6) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.
Table 86. JESD204B Configuration Register, Address 0x07F (Default = 0xCA)
Bit No. Access Bit Description
[7:0] RO JESD204B serial checksum value for Lane 6. This value is automatically calculated. The value = (the sum of all link
configuration parameters for Lane 6) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.
Table 87. JESD204B Lane Power-Down Register, Address 0x080 (Default = 0x00)
Bit No. Access Bit Description
7 RW Physical Lane H power-down.
0: Lane H enabled.
1: Lane H powered down.
6 RW Physical Lane G power-down.
0: Lane G enabled.
1: Lane G powered down.
5 RW Physical Lane F power-down.
0: Lane F enabled.
1: Lane F powered down.
4 RW Physical Lane E power-down.
0: Lane E enabled.
1: Lane E powered down.
3 RW Physical Lane D power-down.
0: Lane D enabled.
1: Lane D powered down.
2 RW Physical Lane C power-down.
0: Lane C enabled.
1: Lane C powered down.
1 RW Physical Lane B power-down.
0: Lane B enabled.
1: Lane B powered down.
0 RW Physical Lane A power-down.
0: Lane A enabled.
1: Lane A powered down.
Data Sheet AD9625
Table 88. JESD204B Lane Control Register 1, Address 0x082 (Default = 0x10)
Bit No. Access Bit Description
7 Unused.
[6:4] RW Physical Lane B assignment.
000: Logical Lane 0.
001: Logical Lane 1 (default).
010: Logical Lane 2.
011: Logical Lane 3.
100: Logical Lane 4.
101: Logical Lane 5.
110: Logical Lane 6.
111: Logical Lane 7.
3 Unused.
[2:0] RW Physical Lane A assignment.
000: Logical Lane 0 (default).
001: Logical Lane 1.
010: Logical Lane 2.
011: Logical Lane 3.
100: Logical Lane 4.
101: Logical Lane 5.
110: Logical Lane 6.
111: Logical Lane 7.
Table 89. JESD204B Lane Control Register 2, Address 0x083 (Default = 0x32)
Bit No. Access Bit Description
7 Unused.
[6:4] RW Physical Lane D assignment.
000: Logical Lane 0.
001: Logical Lane 1.
010: Logical Lane 2.
011: Logical Lane 3 (default).
100: Logical Lane 4.
101: Logical Lane 5.
110: Logical Lane 6.
111: Logical Lane 7.
3 Unused.
[2:0] RW Physical Lane C assignment.
000: Logical Lane 0.
001: Logical Lane 1.
010: Logical Lane 2 (default).
011: Logical Lane 3.
100: Logical Lane 4.
101: Logical Lane 5.
110: Logical Lane 6.
111: Logical Lane 7.
Rev. A | Page 59 of 66
AD9625 Data Sheet
Table 90. JESD204B Lane Control Register 3, Address 0x084 (Default = 0x54)
Bit No. Access Bit Description
7 Unused.
[6:4] RW Physical Lane F assignment.
000: Logical Lane 0.
001: Logical Lane 1.
010: Logical Lane 2.
011: Logical Lane 3.
100: Logical Lane 4.
101: Logical Lane 5 (default).
110: Logical Lane 6.
111: Logical Lane 7.
3 Unused.
[2:0] RW
Physical Lane E assignment.
000: Logical Lane 0.
001: Logical Lane 1.
010: Logical Lane 2.
011: Logical Lane 3.
100: Logical Lane 4 (default).
101: Logical Lane 5.
110: Logical Lane 6.
111: Logical Lane 7.
Table 91. JESD204B Lane Control Register 4, Address 0x085 (Default = 0x76)
Bit No. Access Bit Description
7 Unused.
[6:4] RW Physical Lane H assignment.
000: Logical Lane 0.
001: Logical Lane 1.
010: Logical Lane 2.
011: Logical Lane 3.
100: Logical Lane 4.
101: Logical Lane 5.
110: Logical Lane 6.
111: Logical Lane 7 (default).
3 Unused.
[2:0] RW Physical Lane G assignment.
000: Logical Lane 0.
001: Logical Lane 1.
010: Logical Lane 2.
011: Logical Lane 3.
100: Logical Lane 4.
101: Logical Lane 5.
110: Logical Lane 6 (default).
111: Logical Lane 7.
Table 92. Unused, Address 0x088 (Default = 0x67)
Bit No. Access Bit Description
[7:0] RW Unused.
Table 93. Unused, Address 0x089 (Default = 0xF0)
Bit No. Access Bit Description
[7:0] RW Unused.
Rev. A | Page 60 of 66
Data Sheet AD9625
Table 94. Control Register, Address 0x08A (Default = 0x20)
Bit No. Access Bit Description
[7:6] Unused.
[5:4] RW Reserved; Bits[5:4] must be set to 10.
[3:2] Unused.
[1:0] RW Reserved; Bits[1:0] must be set to 00.
Table 95. JESD204B Local Multiframe Clock Offset Control Register, Address 0x08B (Default = 0x00)
Bit No. Access Bit Description
[7:5] Unused.
[4:0] RW Local multiframe clock (LMFC) phase offset value. These bits provide the reset value for LMFC phase counter when
SYSREF± pins are asserted; this is used for deterministic delay applications.
Table 96. JESD204B Local Frame Clock Offset Control Register, Address 0x08C (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW Local frame clock phase offset value. Reset value for frame clock phase counter when SYSREF± pins are asserted. For the
AD9625, only values from 0 to 7 are valid. This is used for deterministic delay applications.
Table 97. DIVCLK± Register, Address 0x0F8 (Default = 0x00)
Bit No. Access Bit Description
[7:1] RW Spare customer register.
0 RW Register control to set the ratio between ADC sampling clock and DIVCLK±.
0 = divide by 4.
1 = not used.
Table 98. Reserved Register, Address 0x0F9
Bit No. Access Bit Description
[7:0]
RW
Reserved
Table 99. Customer Spare Register, Address 0x0FF (Default = 0x00)
Bit No. Access Bit Description
[7:1] Unused.
0 RW Register map master/slave transfer bit. Self-clearing bit used to synchronize the transfer of data from the master to the
slave registers.
0: no effect.
1: transfers data from the master registers, written by the register maps, to the slave registers.
Table 100. Interrupt Request (IRQ) Status Register, Address 0x100 (Default = 0x00)
Bit No. Access Bit Description
7 RO Interrupt request PLL lock error.
1: the PLL is unlocked.
6 Unused.
5 RO Unused.
4 RO Unused.
3 RO Interrupt request SYSREF± hold error.
1: a hold error has occurred with the last SYSREF± signal received. To clear this error, set and clear Bit 6 in Register 0x03A.
2 RO Interrupt request SYSREF± setup error.
1: a setup error has occurred with the last SYSREF± signal received. To clear this error, set and clear Bit 6 in Register 0x03A.
1 Unused.
0 RO Interrupt request clock error.
Rev. A | Page 61 of 66
AD9625 Data Sheet
Table 101. Interrupt Request (IRQ) Mask Control Register, Address 0x101 (Default = 0xBC)
Bit No. Access Bit Description
7 RW Interrupt request PLL lock error masked.
1: PLL unlocked events are masked.
6 Unused.
5 RW Must be set to 1.
4 RW Must be set to 1.
3 RW Interrupt request SYSREF± hold error.
1: a hold error has occurred with the last SYSREF± signal received. To clear this error, set and clear Bit 6 in Register 0x03A.
2 RW Interrupt request SYSREF± setup error.
1: a setup error has occurred with the last SYSREF± signal received. To clear this error, set and clear Bit 6 in Register 0x03A.
1 Unused.
0 RW Interrupt request clock error mask.
1: clock error has occurred and the validity of the output data cannot be guaranteed. The only way to recover from this
error is to reset the device.
Table 102. Digital Control Register, Address 0x105 (Default = 0x00)
Bit No. Access Bit Description
[7:5] Unused.
4 RW Must be set to 0.
3
RW
Must be set to 0.
2 RW Must be set to 0.
1 RW Must be set to 0.
0
RW
Must be set to 0.
Table 103. Digital Calibration Threshold Control Register, Address 0x10A (Default = 0x10)
Bit No. Access Bit Description
[7:5] Unused.
4 RW Enable data set threshold logic for background gain.
[0:3] Unused.
Table 104. Digital Calibration Data Set Threshold Register, Address 0x10D (Default = 0x3D)
Bit No. Access Bit Description
[7:0] RW Data set threshold for background gain calibration.
Table 105. Digital Calibration Data Set Threshold Register, Address 0x10E (Default = 0x14)
Bit No.
Access
Bit Description
[7:0] RW Data set threshold for background gain calibration.
Table 106. DIVCLK± Output Control Register, Address 0x120 (Default = 0x11)
Bit No. Access Bit Description
[7:5] Unused.
4 RW DIVCLK± output disable. DIVCLK± is 1/4th of the sample clock frequency.
0: DIVCLK± output is disabled.
1: DIVCLK± output is enabled.
3 RW DIVCLK± output termination selection.
0: DIVCLK± output uses an external 100 Ω resistive termination.
1: DIVCLK± output uses no external resistive termination.
2 Unused.
[1:0] RW Control the differential swing for the DIVCLK± output.
00 = 100 mV p-p differential.
01 = 200 mV p-p differential.
10 = 300 mV p-p differential.
11 = 400 mV p-p differential.
Rev. A | Page 62 of 66
Data Sheet AD9625
Table 107. Trim Setting Control Register, Address 0x121 (Default = 0x00 for AD9625-2.5; Default = 0x03 for AD9625-2.0)
Bit No. Access Bit Description
[7:2] Reserved.
[1:0]
RW
Select trim setting, based on sample rate:
00 = Trim 0: for 2.5 GSPS encode rate (default for AD9625-2.5)
01 = Trim 1: for 2.4 GSPS to 2.5 GSPS encode rate
10 = Trim 2: for 2.2 GSPS to 2.4 GSPS encode rate
11 = Trim 3: for 330 MSPS to 2.2 GSPS encode rate (default for AD9625-2.0)
Table 108. Unused Register, Address 0x12A (Default = 0x05)
Bit No. Access Bit Description
[7:0] RW Reserved; maintain default setting of 0x05.
Table 109. DDC 0 Gain Control Register, Address 0x130 (Default = 0x00)
Bit No. Access Bit Description
[7:6]
Unused.
[5:4] RW DDC 0 polyphase (decimate by 2) gain in units of 6 dB.
00: 0 dB gain.
01: 6 dB gain.
10: 12 dB gain.
11: 18 dB gain.
[3:2] Unused.
[1:0] RW DDC 0 polyphase (decimate by 8) gain in units of 6 dB.
00: 0 dB gain.
01: 6 dB gain.
10: 12 dB gain.
11: 18 dB gain.
Table 110. DDC 0 Phase Increment Least Significant Bits Register, Address 0x131 (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW DDC 0 NCO phase increment value. Phase increment for the NCO within DDC 0. The output frequency =
(decimal(Register 0x132[1:0]; Register 0x131[7:0]) × fS)/1024.
Table 111. DDC 0 Phase Increment Most Significant Bits Register, Address 0x132 (Default = 0x00)
Bit No. Access Bit Description
[7:2] Unused.
[1:0] RW DDC 0 NCO phase increment value. Phase increment for the NCO within DDC 0.
Table 112. DDC 1 Gain Control Register, Address 0x138 (Default = 0x00)
Bit No.
Access
Bit Description
[7:6] Unused.
[5:4] RW DDC 1 polyphase (decimate by 2) gain in units of 6 dB.
00: 0 dB gain.
01: 6 dB gain.
10: 12 dB gain.
11: 18 dB gain.
[3:2] Unused.
[1:0] RW DDC 1 polyphase (decimate by 8) gain in units of 6 dB.
00: 0 dB gain.
01: 6 dB gain
10: 12 dB gain.
11: 18 dB gain.
Rev. A | Page 63 of 66
AD9625 Data Sheet
Table 113. DDC 1 Phase Increment Least Significant Bits Register, Address 0x139 (Default = 0x00)
Bit No. Access Bit Description
[7:0] RW DDC 1 NCO phase increment value. Phase increment for the NCO within DDC 1. The output frequency =
(decimal(Register 0x13A[1:0]; Register 0x139[7:0]) × fS)/1024.
Table 114. DDC 1 Phase Increment Most Significant Bits Register, Address 0x13A (Default = 0x00)
Bit No. Access Bit Description
[7:2] Unused.
[1:0] RW DDC1 NCO phase increment value.
Table 115. SYSREF±Hold Time Guardband Register, Address 0x13B (Default = 0x00)
Bit No.
Access
Bit Description
[7:5] RW These bits increase the SYSREF± hold time guardband that is used to assert the SYSREF± hold IRQ flag in register
0x100[3]. This time is informational only and does not change the actual hold time for SYSREF±.
000: No additional guardband hold time.
001: 35 ps of additional hold time guardband for 0x100[3].
010: 70 ps of additional hold time guardband for 0x100[3].
011: 105 ps of additional hold time guardband for 0x100[3].
100: 140 ps of additional hold time guardband for 0x100[3].
101: 175 ps of additional hold time guardband for 0x100[3].
110: 210 ps of additional hold time guardband for 0x100[3].
111: 245 ps of additional hold time guardband for 0x100[3].
[4:0] RW Reserved
Table 116. SYSREF± Setup Time Guardband Register, Address 0x13C (Default = 0x00)
Bit No. Access Bit Description
[7:5]
RW
These bits increase the SYSREF± setup time guardband that is used to assert the SYSREF± setup IRQ flag in register
0x100[2]. This time is informational only and does not change the actual setup time for SYSREF±.
000: No additional guardband setup time.
001: 35 ps of additional setup time guardband for 0x100[2].
010: 70 ps of additional setup time guardband for 0x100[2].
011: 105 ps of additional setup time guardband for 0x100[2].
100: 140 ps of additional setup time guardband for 0x100[2].
101: 175 ps of additional setup time guardband for 0x100[2].
110: 210 ps of additional setup time guardband for 0x100[2].
111: 245 ps of additional setup time guardband for 0x100[2].
[4:0] RW Reserved
Rev. A | Page 64 of 66
Data Sheet AD9625
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting system level design and layout of the AD9625, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD9625, it is recommended
that separate supplies are used: one supply for the analog output
(AVDD), and a separate supply for the digital outputs (DRVDD
and DVDD). The designer can use several different decoupling
capacitors to cover both high and low frequencies. Locate these
capacitors close to the point of entry at the printed circuit board
(PCB) level and close to the pins of the part with minimal trace
length.
When using the AD9625, a single PCB ground plane is
sufficient. With proper decoupling and smart partitioning of
the PCB analog, digital, and clock sections, optimum
performance is easily achieved
CLOCK STABILITY CONSIDERATIONS
When powered on, the AD9625 enters an initialization phase
during which an internal state machine sets up the biases and
the registers for proper operation. During the initialization
process, the AD9625 needs a stable clock. If the ADC clock
source is not present or not stable during ADC power-up, it
disrupts the state machine and causes the ADC to start up in
a less than optimum state. To correct this, an initialization
sequence must be invoked after the ADC clock is stable or any
change in the sampling clock frequency is made. By issuing a
digital reset via Register 0x00. The pseudo code sequence for a
digital reset is as follows:
#Stable Clock at the input to the AD9625
SPI_Write (0x00, 0x3C); # Reset
SPI_Write (0x080 0xFF) #SPI register transfer
#Write further configurations
SPI PORT
When the full dynamic performance of the converter is
required, do not activate the SPI port. Because the SCLK, CSB,
and SDIO signals are typically asynchronous to the ADC clock,
noise from these signals can degrade converter performance. If
the on-board SPI bus is used for other devices, it may be
necessary to provide buffers between this bus and the AD9625
to keep these signals from transitioning at the converter input
pins during critical sampling periods.
Rev. A | Page 65 of 66
AD9625 Data Sheet
Rev. A | Page 66 of 66
OUTLINE DIMENSIONS
Figure 87. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]
(BP-196-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9625BBPZ-2.5 −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-196-2
AD9625BBPZ-2.0 −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-196-2
AD9625BBP-2.5 −40°C to +85°C 196-Ball Ball Grid Array, PbSn, Thermally Enhanced [BGA_ED] BP-196-2
AD9625BBPZRL-2.5 −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED], 13” Tape and Reel BP-196-2
AD9625BBPZRL-2.0 −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED], 13” Tape and Reel BP-196-2
AD9625BBPRL-2.5 −40°C to +85°C 196-Ball BGA, PbSn, Thermally Enhanced [BGA_ED], 13” Tape and Reel BP-196-2
AD9625-2.5EBZ Evaluation Board with AD9625
AD9625-2.0EBZ Evaluation Board with AD9625
1 Z = RoHS Compliant Part.
COM P L IANT T O JE DEC S T A NDARDS MO -275- G G AA - 1.
07-20-2012-A
0.80
0.80 REF
0.51 REF
0.75
REF
A
B
C
D
E
F
G
91011121314 8 7 564231
BOTTOM VIEW
10.4 0 SQ
H
J
K
L
M
N
P
DETAIL A
TOP VI EW
DETAIL A
COPLANARITY
0.12
0.50
0.45
0.40
BALL DI A M ETER
SEATING
PLANE
12.10
12.00 SQ
11.90
A1 BALL
PAD CORNER
A1 BALL
PAD CO RN ER
1.70
1.59
1.50
11.2 0 SQ
8.20 SQ
1.33
1.26
1.19
0.38
0.33
0.28
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11814-0-9/14(A) www.analog.com/AD9625
