April 2004 AS7C251MFT18A (R) 2.5V 1M x 18 flowthrough burst synchronous SRAM Features * * * * * * * * * * * * * Organization: 1,048,576 words x18 bits Fast clock to data access: 8.5/10 ns Fast OE access time: 3.5/3.8 ns Fully synchronous flow-through operation Asynchronous output enable control Available 100-pin TQFP and 165-ball BGA packages Individual byte write and global write Multiple chip enables for easy expansion 2.5V core power supply Linear or interleaved burst control Snooze mode for reduced power-standby Boundary scan using IEEE 1149.1 JTAG function NTDTM1 flow-through mode architecture available (AS7C251MNTD18A, AS7C25512NTD32A/ AS7C25512NTD36A) 1 NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. LBO CLK ADV ADSC ADSP Logic block diagram CLK CS CLR 20 A[19:0] Burst logic Q D 20 1M x 18 Memory array 18 20 Address register CS CLK 18 18 GWE BWb D DQb Q Byte Write registers BWE CLK D DQa Q BWa Byte Write registers CE0 CE1 CE2 D 2 CLK OE EnableQ register CE CLK ZZ Power down Input registers Output buffers CLK D EnableQ delay register CLK 18 OE DQ[a,b] Selection guide -85 -10 Units Minimum cycle time 10 12 ns Maximum clock access time 8.5 10 ns Maximum operating current 250 230 mA Maximum standby current 85 75 mA Maximum CMOS standby current (DC) 40 40 mA 4/12/04, v. 1.0 Alliance Semiconductor 1 of 23 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C251MFT18A (R) Pin and ball designations NC NC NC TQFP 14 x 20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS NC VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 NC NC VSSQ VDDQ NC NC NC LBO A A A A A1 A0 NC NC VSS VDD A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDQ VSSQ NC NC DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 NC VDD NC VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A A Pin configuration for 100-pin TQFP 4/12/04, v. 1.0 Alliance Semiconductor 2 of 23 AS7C251MFT18A (R) Ball assignments for 165-ball BGA 1M X 18 1 2 3 4 5 6 7 8 9 10 11 A NC A CE0 BWb NC CE2 BWE ADSC ADV A A B NC A CE1 NC BWa CLK GWE OE ADSP A NC C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPa D NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa E NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa F NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa G NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa H NC NC NC VDD VSS VSS VSS VDD NC NC ZZ J DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC K DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC L DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC M DQb NC VDDQ VDD VSS VSS NC VDD VDDQ DQa NC N DQPb NC VDDQ VSS NC A VSS VSS VDDQ NC NC P NC NC A A TDI A11 TDO A A A A R LBO NC A A TMS A01 TCK A A A A 1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. 4/12/04, v. 1.0 Alliance Semiconductor 3 of 23 AS7C251MFT18A (R) Functional description The AS7C251MFT18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words x18 bits. Fast cycle times of 10/12 ns with clock access times (tCD) of 8.5/10 ns. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out buffers. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use an interleaved count sequence. With LBO driven LOW, the device uses a linear count sequence. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signals. BWn is ignored on the clock edge that samples ADSP LOW, but it is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW, regardless of OE. Data is clocked into the data input register when BWn is sampled LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow. * ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC. * WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH). * Master chip enable CE0 blocks ADSP, but not ADSC. The AS7C251MFT18A family operates from a core 2.5V power supply. These devices are available in a 100-pin TQFP and 165-ball BGA. TQFP and BGA capacitance Parameter Symbol Test conditions Min Max Unit Input capacitance CIN VIN = 0V - 5 pF I/O capacitance CI/O VIN = VOUT - 7 pF TQFP and BGA thermal resistance Description Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1 Symbol Typical Units Conditions 1 layer JA 40 C/W 4 layer JA 22 C/W JC 8 C/W Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 1 This parameter is sampled. 4/12/04, v. 1.0 Alliance Semiconductor 4 of 23 AS7C251MFT18A (R) Signal descriptions Signal I/O Properties Description CLK I CLOCK A,A0,A1 I SYNC Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and when OE is active. CE0 I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the "Synchronous truth table" for more information. CE1, CE2 I SYNC Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. ADSP I SYNC Address strobe processor. Asserted LOW to load a new bus address or to enter standby mode. ADSC I SYNC Address strobe controller. Asserted LOW to load a new address or to enter standby mode. ADV I SYNC Advance. Asserted LOW to continue burst read/write. GWE I SYNC Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and BW[a,b] control write enable. BWE I SYNC Byte write enable. Asserted LOW with GWE HIGH to enable effect of BW[a,b] inputs. BW[a,b] I SYNC Write enables. Used to control write of individual bytes when GWE is HIGH and BWE is LOW. If any of BW[a,b] is active with GWE HIGH and BWE LOW, the cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle. OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode. LBO I STATIC Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven LOW, device follows linear Burst order. This signal is internally pulled High. TDO O SYNC Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). TDI I SYNC Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only). TMS I SYNC This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA only). TCK O SYNC Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). ZZ I ASYNC NC - - Sleep. Places device in LOW power mode; data is retained. Connect to GND if unused. No connects Write enable truth table (per byte) Function Write all bytes (a, b) GWE BWE BWa BWb L X X X H L L L Write byte a H L L H Write byte b H L H L H H X X H L H H Read Key: X = don't care; L = low; H = high; BWE, BWn = internal write signal 4/12/04, v. 1.0 Alliance Semiconductor 5 of 23 AS7C251MFT18A (R) Burst sequence table Interleaved burst address Linear burst address A1 A0 A1 A0 A1 A0 A1 A0 1st Address nd 2 00 Address 01 01 rd 3 Address 00 10 th 4 Address 10 11 11 11 10 00 10 A1 A0 A1 A0 A1 A0 A1 A0 1st Address 11 2 01 01 00 nd 00 01 10 11 Address 01 10 11 00 rd 3 Address 10 11 00 01 th 11 10 01 10 4 Address Synchronous truth table CE01 CE1 CE2 ADSP ADSC H L L L L L L L L X X X X H H H H L X H X H X L L X X H H H H X X X X X X X X H X X X X X X X H H L L L L X X X X X X X X L X X X X X L H L H L L H H H H H H X X X X H H X H X L X L X L X X L L H H H H H H H H L H H H H ADV WRITE[2] X X X X X X X X X L L H H L L H H X L L H H X X X X X X X H H H H H H H H H H L L L L L OE Address accessed CLK Operation DQ X X X X X L H L H L H L H L H L H X X X X X NA NA NA NA NA External External External External Next Next Current Current Next Next Current Current External Next Next Current Current L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Continue read Continue read Suspend read Suspend read Continue read Continue read Suspend read Suspend read Begin write Continue write Continue write Suspend write Suspend write Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z D3 D D D D 1 X = don't care, L = low, H = high 2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 5 for more information. 3 For write operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold time 4/12/04, v. 1.0 Alliance Semiconductor 6 of 23 AS7C251MFT18A (R) Absolute maximum ratings Parameter Power supply voltage relative to GND Symbol Min Max Unit VDD, VDDQ -0.3 +3.6 V Input voltage relative to GND (input pins) VIN -0.3 VDD + 0.3 V Input voltage relative to GND (I/O pins) VIN -0.3 VDDQ + 0.3 V Power dissipation PD - 1.8 W DC output current IOUT - 20 mA mA Storage temperature (plastic) Tstg -65 +150 o Tbias -65 +135 o Temperature under bias C C Note: Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. Recommended operating conditions Parameter Symbol Min Nominal Max Unit Supply voltage for inputs VDD 2.375 2.5 2.625 V Supply voltage for I/O VDDQ 2.375 2.5 2.625 V Vss 0 0 0 V Ground supply 4/12/04, v. 1.0 Alliance Semiconductor 7 of 23 AS7C251MFT18A (R) DC electrical characteristics Parameter Sym Conditions Min Max Unit Input leakage current |ILI| VDD = Max, OV < VIN < VDD -2 2 A Output leakage current |ILO| OE VIH, VDD = Max, OV < VOUT < VDDQ -2 2 A Input high (logic 1) voltage VIH Address and control pins 1.7 VDD+0.3 V I/O pins 1.7 VDDQ+0.3 V Address and control pins * -0.3 0.7 V I/O pins -0.3* 0.7 V Input low (logic 0) voltage VIL Output high voltage VOH IOH = -4 mA, VDDQ = 2.375V 1.7 - V Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V - 0.7 V * VIL min = -1.5 for pulse width less than 0.2 X tCYC IDD operating conditions and maximum limits Parameter Operating power supply current1 Standby power supply current Sym Conditions -85 -10 Unit ICC CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax, IOUT = 0 mA 250 230 mA ISB Deselected, f = fMax, ZZ < VIL 85 75 ISB1 Deselected, f = 0, ZZ < 0.2V, all VIN 0.2V or VDD - 0.2V 40 40 ISB2 Deselected, f = fMax, ZZ ( VDD, VDDQ) - 0.2V, all VIN VIL or VIH 40 40 mA 1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading 4/12/04, v. 1.0 Alliance Semiconductor 8 of 23 AS7C251MFT18A (R) Timing characteristics over operating range -85 Parameter -10 Notes1 Sym Min Max Min Max Unit Cycle time tCYC 10 - 12 - ns Clock access time tCD - 8.5 - 10 ns Output enable low to data valid tOE - 3.5 - 3.8 ns Clock high to output low Z tLZC 0 - 0 - ns 2,3,4 Data output invalid from clock high tOH 3.0 - 3.0 - ns 2 Output enable low to output low Z tLZOE 0 - 0 - ns 2,3,4 Output enable high to output high Z tHZOE - 3.5 - 3.8 ns 2,3,4 Clock high to output high Z tHZC - 3.5 - 3.8 ns 2,3,4 tOHOE 0 - 0 - ns Clock high pulse width tCH 2.4 - 2.4 - ns 5 Clock low pulse width tCL 2.3 - 2.4 - ns 5 Address setup to clock high tAS 1.5 - 1.5 - ns 6 Data setup to clock high tDS 1.5 - 1.5 - ns 6 Write setup to clock high tWS 1.5 - 1.5 - ns 6,7 Chip select setup to clock high tCSS 1.5 - 1.5 - ns 6,8 Address hold from clock high tAH 0.5 - 0.5 - ns 6 Data hold from clock high tDH 0.5 - 0.5 - ns 6 Write hold from clock high tWH 0.5 - 0.5 - ns 6,7 Chip select hold from clock high tCSH 0.5 - 0.5 - ns 6,8 ADV setup to clock high tADVS 1.5 - 1.5 - ns 6 ADSP setup to clock high tADSPS 1.5 - 1.5 - ns 6 ADSC setup to clock high tADSCS 1.5 - 1.5 - ns 6 ADV hold from clock high tADVH 0.5 - 0.5 - ns 6 ADSP hold from clock high tADSPH 0.5 - 0.5 - ns 6 ADSC hold from clock high tADSCH 0.5 - 0.5 - ns 6 Output enable high to invalid output 1 See "Notes" on page 20. 4/12/04, v. 1.0 Alliance Semiconductor 9 of 23 AS7C251MFT18A (R) IEEE 1149.1 serial boundary scan (JTAG) The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. The inclusion of these functions would place an added delay in the critical speed path of the SRAM. The TAP controller functionality does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. It uses JEDEC-standard 2.5V I/O logic levels. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG feature If the JTAG function is not being implemented, TCK should be tied to VSS, TMS and TDI can be left unconnected, the device will come up in a reset state which will not interfere with the operation of the device. TDO should be left unconnected. TAP controller state diagram 1 TAP controller block diagram TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 0 Bypass Register 1 Selection Circuitry 0 TDI 1 1 CAPTURE-DR 0 1 EXIT1-IR 1 TCK 0 0 PAUSE-DR PAUSE-IR 0 1 0 TAP Controller TMS 0 1 EXIT2-DR 1 x = 53 for the x18 configuration, x = 72 for the x36 configuration. EXIT2-IR 1 1 UPDATE-DR 1 . . . 2 1 0 Boundary Scan Register1 0 1 EXIT1-DR 0 x . . SHIFT-IR 1 TDO Identification Register 0 SHIFT-DR Selection Circuitry 31 30 29 . . . 2 1 0 CAPTURE-IR 0 2 1 0 Instruction Register 0 UPDATE-IR 1 0 Note: The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK. Test access port (TAP) Test clock (TCK) The test clock is used with only the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test mode select (TMS) The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball unconnected if the TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level. 4/12/04, v. 1.0 Alliance Semiconductor 10 of 23 AS7C251MFT18A (R) Test data-in (TDI) The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See the TAP Controller Block Diagram.) Test data-out (TDO) The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP Controller State Diagram.) Performing a TAP RESET You can perform a RESET by forcing TMS high (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and can be performed while the SRAM is operating. TAP registers Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ball on the rising edge of TCK. Data is output on the TDO pin/ball on the falling edge of TCK. Instruction register You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO pins/balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at power up and also if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level series test data path. Bypass register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a singlebit register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set low (Vss) when the BYPASS instruction is executed. Boundary scan register The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has a 72-bit-long register and the x18 configuration has a 53-bit-long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/RELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO. Identification (ID) register The ID register has a vendor code and other information described in the Identification Register Definitions table. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. 4/12/04, v. 1.0 Alliance Semiconductor 11 of 23 AS7C251MFT18A (R) TAP instruction set Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are reserved and should not be used. Note that the TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/ PRELOAD. Instead, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST The EXTEST instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this SRAM TAP controller. The TAP controller, however, does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a high-Z state. EXTEST is a mandatory 1149.1 instruction. this device, therefore, is not compliant with 1149.1. IDCODE The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a high-Z state. SAMPLE/PRELOAD When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional pins/balls is captured in the boundary scan register. Note that the SAMPLE/PRELOAD is a 1149.1 mandatory instruction, but the PRELOAD portion of this instruction is not implemented in this device. The TAP controller, therefore, is not fully 1149.1 compliant. Be aware that the TAP controller clock can operate only at a frequency up to 10 Mhz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output can undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is possible to capture all other signals and ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. BYPASS The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between TDI and TDO. 4/12/04, v. 1.0 Alliance Semiconductor 12 of 23 AS7C251MFT18A (R) Reserved Do not use a reserved instruction.These instructions are not implemented but are reserved for future use. TAP timing diagram 1 2 3 4 5 6 Test Clock (TCK) tTHTL tTLTH tTHTH Test Mode Select (TMS) tMVTH tTHMX Test Data-In (TDI) tTLOV tTLOX tDVTH tTHDX Test Data-Out (TDO) Don't care Undefined TAP AC electrical characteristics For notes 1 and 2, +10oC < TJ < +110oC and +2.4V < VDD < +2.6V. Description Symbol Min Max Units Clock Clock cycle time t THTH 100 fTF Clock frequency ns 10 MHz Clock high time t THTL 40 ns Clock low time t TLTH 40 ns 0 ns Output Times TCK low to TDO unknown t TLOX TCK low to TDO valid t TLOV TDI valid to TCK high tDVTH 10 ns TCK high to TDI invalid t THDX 10 ns tMVTH 10 ns 10 ns 10 ns 10 ns 20 ns Setup Times TMS setup t Capture setup CS 1 Hold Times TMS hold Capture hold t THMX t CH 1 1 tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 2 Test conditions are specified using the load in the figure TAP AC output load equivalent. 4/12/04, v. 1.0 Alliance Semiconductor 13 of 23 AS7C251MFT18A (R) TAP AC test conditions TAP AC output load equivalent Input pulse levels. . . . . . . . . . . . . . . Vss to 2.5V 1.25V Input rise and fall times. . . . . . . . . . . . . . . 1 ns Input timing reference levels. . . . . . . . . . 1.25V 50 Output reference levels . . . . . . . . . . . . . . 1.25V TDO Test load termination supply voltage. . . . 1.25V 20pF ZO=50 TAP DC electrical characteristics and operating conditions (+10oC < TJ < +110oC and +2.4V < VDD < +2.6V unless otherwise noted) Description Conditions Symbol Min Max Units Notes Input high (logic 1) voltage VIH 1.7 VDD + 0.3 V 1, 2 Input low (logic 0) voltage VIL -0.3 0.7 V 1, 2 0V VIN VDD ILI -5.0 5.0 A Outputs disabled, 0V VIN VDDQ(DQx) ILO -5.0 5.0 A Output low voltage IOLC = 100A VOL1 0.2 V 1 Output low voltage IOLT = 2mA VOL2 0.7 V 1 Output high voltage IOHS = -100A VOH1 2.1 V 1 Output high voltage IOHT = -2mA VOH2 1.7 V 1 Input leakage current Output leakage current 1. All voltage referenced to VSS(GND). 2. Overshoot: VIH(AC) VDD + 1.5V for t tKHKH/2 Undershoot: VIL(AC) -0.5 for t tKHKH/2 Power-up: VIH +2.6V and VDD 2.4V and VDDQ 1.4V for t 200ms During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD, R/W, etc.) may not have pulsed widths less than tKHKL(Min) or operate at frequencies exceeding fKF(Max). 4/12/04, v. 1.0 Alliance Semiconductor 14 of 23 AS7C251MFT18A (R) Identification register definitions Instruction field 1M x 18 Description Revision number (31:28) xxxx Reserved for version number. Device depth (27:23) xxxxx Defines the depth of 1Mb words. Device width (22:18) xxxxx Defines the width of x18 bits. Device ID (17:12) xxxxxx Reserved for future use. JEDEC ID code (11:1) 00001010010 Allows unique identification of SRAM vendor. ID register presence indicator (0) 1 Indicates the presence of an ID register. Scan register sizes Register name Bit size Instruction 3 Bypass 1 ID 32 Boundary scan x18:53 x36:72 Instruction codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high-Z state. Reserved 011 Do not use. This instruction is reserved for future use. SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. Reserved 101 Do not use. This instruction is reserved for future use. Reserved 110 Do not use. This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 4/12/04, v. 1.0 Alliance Semiconductor 15 of 23 AS7C251MFT18A (R) 165-ball BGA boundary scan order (x18) Bit #s Signal Name Ball ID Bit #s Signal Name Ball ID 1 SA0 6R 28 OE 8B 2 SA1 6P 29 ADSC 8A 3 SA 4P 30 ADSP 9B 4 SA 4R 31 ADV 9A 5 SA 3R 32 SA 10B 6 SA 3P 33 SA 10A 7 LBO 1R 34 SA 11A 8 DQPb 1N 35 DQPa 11C 9 DQb 1M 36 DQa 11D 10 DQb 1L 37 DQa 11E 11 DQb 1K 38 DQa 11F 12 DQb 1J 39 DQa 11G 13 NC 1H 40 ZZ 11H 14 DQb 2G 41 DQa 10J 15 DQb 2F 42 DQa 10K 16 DQb 2E 43 DQa 10L 17 DQb 2D 44 DQa 10M 18 SA 2B 45 SA 11R 19 SA 2A 46 SA 10R 20 CE0 3A 47 SA 10P 21 CE1 3B 48 SA 9P 22 BWb 4A 49 SA 9R 23 BWa 5B 50 SA 8R 24 CE2 6A 51 SA 8P 25 CLK 6B 52 SA 6N 26 GWE 7B 53 SA 11P 27 BWE 7A Note: NC is don't care 4/12/04, v. 1.0 Alliance Semiconductor 16 of 23 AS7C251MFT18A (R) Key to switching waveforms Rising input Falling input Undefined/don't care Timing waveform of read cycle tCYC tCL tCH CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC LOAD NEW ADDRESS tAS tAH Address A1 A2 A3 tWS tWH GWE, BWE tCSS tCSH CE0, CE2 CE1 tADVS tADVH ADV ADV inserts wait states OE tOE tHZOE tLZOE DOUT tOH Q(A2Y01) Q(A1) Q(A2Y10) Q(A2Y11) tCD Read Q(A1) Suspend Read Q(A1) Read Q(A2) Q(A3) Q(A3Y01) Q(A3Y10) Q(A3Y11) tHZC Burst Burst Suspend Burst Read Burst Burst Burst Read Read Read Read Q(A3) Read Read Read 2Y01 2Y10 2Y10 2Y11 3Y01 3Y10 Q(A ) Q(A ) Q(A ) Q(A ) Q(A ) Q(A ) Q(A 3Y11) DSEL Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low. BW[a:b] is don't care. 4/12/04, v. 1.0 Alliance Semiconductor 17 of 23 AS7C251MFT18A (R) Timing waveform of write cycle tCH tCYC tCL CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC tAS tAH Address A1 ADSC loads new address A3 A2 tWS tWH BWE BW[a:d] tCSS tCSH CE0, CE2 CE1 tADVS tADVH ADV suspends burst ADV OE tDS tDH Data In D(A1) Read Q(A1) Suspend Write D(A1) D(A2) Read Q(A2) Suspend Write D(A 2) D(A2Y01) D(A2Y01) D(A2Y10) D(A2Y11) ADV Suspend ADV ADV Burst Write Burst Burst Write D(A 2Y01) Write Write D(A 2Y01) Q(A 2Y10) Q(A 2Y11) D(A3) D(A3Y01) D(A3Y10) Write D(A 3) Burst Write D(A 3Y01) ADV Burst Write D(A 3Y10) Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low. 4/12/04, v. 1.0 Alliance Semiconductor 18 of 23 AS7C251MFT18A (R) Timing waveform of read/write cycle tCYC tCL tCH CLK tADSPS tADSPH ADSP tAS tAH A2 A1 Address A3 tWS tWH GWE CE0, CE2 CE1 tADVS tADVH ADV OE tDS tDH DIN D(A2) tCD DOUT Q(A1) Q(A3Y01) tLZC DSEL Read Q(A1) tOH tOE tHZOE Q(A3Y10) Q(A3Y11) tLZOE Suspend Read Q(A1) Read Q(A2) Suspend Write D(A 2) Read Q(A3) ADV Burst Read D(A 3Y01) ADV Burst Read Q(A 3Y10) ADV Burst Read Q(A 3Y11) Suspend Read Q(A 3Y11) Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low. 4/12/04, v. 1.0 Alliance Semiconductor 19 of 23 AS7C251MFT18A (R) AC test conditions * Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B. * Input pulse level: GND to 2.5V. See Figure A. Thevenin equivalent: * Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A. +2.5V * Input and output timing reference levels: 1.25V. +2.5V 90% 10% GND 90% 10% Figure A: Input waveform DOUT Z0 = 50 50 VL = VDDQ/2 30 pF* Figure B: Output load (A) 319/1667 DOUT 353/1538 5 pF* GND *including scope and jig capacitance Figure C: Output load(B) Notes 1 2 3 4 5 6 7 8 For test conditions, see "AC Test Conditions", Figures A, B, and C. This parameter is measured with output load condition in Figure C. This parameter is sampled but not 100% tested. tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage. tCH is measured as high above VIH, and tCL is measured as low below VIL. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled. Write refers to GWE, BWE, and BW[a,b]. Chip select refers to CE0, CE1, and CE2. 4/12/04, v. 1.0 Alliance Semiconductor 20 of 23 AS7C251MFT18A (R) Package dimensions 100-pin TQFP (quad flat pack) TQFP Hd Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e D c L1 L e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 b A1 A2 He E 1.00 nominal 0 7 Dimensions in millimeters 165-ball BGA (ball grid array) A1 corner index area 15.00 12.90 13.00 10.00 F 0.26 0.30 0.35 0.40 0.45 A 10.00 13.000.10 0.20 Z 0.50 Alliance Semiconductor E D I G 0.12 Z F Side View 4/12/04, v. 1.0 1.00 1.00 D 1.20 0.40 14.00 C 13.000.10 0.50 I B 1.20 MAX H 13.10 A B C D E F G H J K L M N P R A 0.350.05 G 15.10 14.00 E 11 10 9 8 7 6 5 4 3 2 1 15.000.10 1.00 14.90 C D Max 0.26 B 1 2 3 4 5 6 7 8 9 10 11 15.000.10 A Typ Bottom View A B C D E F G H J K L M N P R All measurements are in mm. Min Top View H / 0.450.05 (165X) O 0.15 M Z X Y O 0.08 M Z Detail of Solder Ball 21 of 23 AS7C251MFT18A (R) Ordering information Package &Width TQFP x18 BGA x18 -85 -10 10AS7C251MFT18A-85TQC AS7C251MFT18A-10TQC AS7C251MFT18A-85TQI AS7C251MFT18A-10TQI AS7C251MFT18A-85BC AS7C251MFT18A-10BC AS7C251MFT18A-85BI AS7C251MFT18A-10BI Note: Add `N' to the above part numbers for Lead Free Parts (Ex. AS7C251MFT18A-85TQCN) Part numbering guide AS7C 25 1M FT 18 A -XX TQ or B C/I X 1 2 3 4 5 6 7 8 9 10 1. Alliance Semiconductor SRAM prefix 2. Operating voltage: 25 = 2.5V 3. Organization: 1M 4. Flow-through mode 5. Organization: 18 = x18 6. Production version: A = first production version 7. Clock speed 8. Package type: TQ = TQFP; B = BGA 9. Operating temperature: C = commercial (0 C to 70 C); I = industrial (-40 C to 85 C) 10. N = Lead Free Part 4/12/04, v. 1.0 Alliance Semiconductor 22 of 23 AS7C251MFT18A (R) (R) Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: AS7C251MFT18A Document Version: v. 1.0 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. 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