10AS7C251MFT18A-85TQC N - Alliance Semiconductor

April 2004

AS7C251MFT18A

4/12/04, v. 1.0 Alliance Semiconductor 1 of 23

2.5V 1M x 18 flowthrough burst synchronous SRAM

Features

• Organization: 1,048,576 words x18 bits

• Fast clock to data access: 8.5/10 ns

•Fast OE

access time: 3.5/3.8 ns

• Fully synchronous flow-through operation

• Asynchronous output enable control

• Available 100-pin TQFP and 165-ball BGA packages

•

Individual byte write and global write

• Multiple chip enables for easy expansion

• 2.5V core power supply

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

•

Boundary scan using IEEE 1149.1 JTAG function

•

NTD™

flow-through mode architecture available

(AS7C251MNTD18A, AS7C25512NTD32A/

AS7C25512NTD36A)

1 NTD™ is a trademark of Alliance Semiconductor Corporation. All

trademarks mentioned in this document are the property of their respective

owners.

Logic block diagram

Selection guide

-85 -10 Units

Minimum cycle time 10 12 ns

Maximum clock access time 8.5 10 ns

Maximum operating current 250 230 mA

Maximum standby current 85 75 mA

Maximum CMOS standby current (DC) 40 40 mA

Burst logic

ADV

ADSC

ADSP

CLK

LBO

CLK

CLR

A[19:0]

Address

CLK

Memory

array

DQb

CLK

Byte Write

registers

DQa

CLK

Byte Write

registers

Enable

CLK

Enable

CLK

delay

Output

buffers

Input

registers

Power

down

DQ[a,b]

CE0

CE1

CE2

BWb

BWa

CLK

BWE

GWE

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Pin and ball designations

Pin configuration for 100-pin TQFP

LBO

100

CE0

CE1

BWb

BWa

CE2

CLK

GWE

BWE

ADSC

ADSP

ADV

TQFP 14 x 20mm

DDQ

SSQ

DQb0

DQb1

SSQ

DDQ

DQb2

DQb3

DQb4

DQb5

DDQ

SSQ

DQb6

DQb7

DQPb

SSQ

DDQ

SSQ

DQPa

DQa7

DQa6

SSQ

DDQ

DQa5

DQa4

DQa3

DQa2

DDQ

SSQ

DQa1

DQa0

SSQ

DDQ

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AS7C251MFT18A

Ball assignments for 165-ball BGA 1M X 18

1 2 3 4 5 6 7 8 9 10 11

ANC A CE0

BWb

NC CE2 BWE ADSC ADV AA

BNC A CE1

BWa CLK GWE OE ADSP ANC

NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPa

DNC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa

ENC DQb VDDQ

VDD

VSS VSS VSS VDD VDDQ NC DQa

FNC DQb VDDQ

VDD

VSS VSS VSS VDD VDDQ NC DQa

GNC DQb VDDQ

VDD

VSS VSS VSS VDD VDDQ NC DQa

HNC NC NC

VDD

VSS VSS VSS VDD NC NC ZZ

JDQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC

KDQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC

LDQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC

MDQb NC VDDQ VDD VSS VSS NC VDD VDDQ DQa NC

NDQPb NC VDDQ VSS NC A VSS VSS VDDQ NC NC

PNC NC A A TDI A11

1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

TDOAAAA

RLBO NC

TMS

A01TCKAAAA

AS7C251MFT18A

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Functional description

The AS7C251MFT18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as

1,048,576 words x18 bits

Fast cycle times of 10/12 ns with clock access times (tCD) of 8.5/10 ns. Three chip enable (CE) inputs permit easy memory expansion. Burst

operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance

pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register

when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data

accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out buffers. ADV is

ignored on the clock edge that samples ADSP asserted, but it is sampled on all subsequent clock edges. Address is incremented internally for

the next access of the burst when ADV is sampled LOW and both address strobes are HIGH. Burst mode is selectable with the

LBO

input.

With

LBO

unconnected or driven HIGH, burst operations use an interleaved count sequence. With

LBO

driven LOW, the device uses a linear

count sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all

18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting

BWE and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP LOW, but it is sampled on all subsequent clock edges. Output buffers are disabled

when BWn is sampled LOW, regardless of OE. Data is clocked into the data input register when BWn is sampled LOW. Address is

incremented internally to the next burst address if BWn and ADV are sampled LOW.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP

follow.

•ADSP

must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

•WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).

•Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C251MFT18A family operates from a core 2.5V power supply. These devices are available in a 100-pin TQFP and 165-ball BGA.

TQFP and BGA capacitance

TQFP and BGA thermal resistance

Parameter Symbol Test conditions Min Max Unit

Input capacitance CIN VIN = 0V - 5 pF

I/O capacitance CI/O VIN = VOUT -7pF

Description Symbol Typical Units Conditions

Thermal resistance

(junction to ambient)1

1 This parameter is sampled.

1 layer θJA 40 °C/W Test conditions follow standard test

methods and procedures for

measuring thermal impedance, per

EIA/JESD51

4 layer θJA 22 °C/W

Thermal resistance

(junction to top of case)1θJC 8°C/W

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AS7C251MFT18A

Signal descriptions

Write enable truth table (per byte)

Key: X = don’t care; L = low; H = high; B

, B

= internal write signal

Signal I/O Properties Description

CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.

A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.

DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and when OE is active.

CE0 I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is

inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information.

CE1, CE2 I SYNC Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock

edges when ADSC is active or when CE0 and ADSP are active.

ADSP I SYNC Address strobe processor. Asserted LOW to load a new bus address or to enter standby

mode.

ADSC I SYNC Address strobe controller. Asserted LOW to load a new address or to enter standby mode.

ADV I SYNC Advance. Asserted LOW to continue burst read/write.

GWE I SYNC Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and BW[a,b]

control write enable.

BWE I SYNC Byte write enable. Asserted LOW with GWE HIGH to enable effect of BW[a,b] inputs.

BW[a,b] I SYNC

Write enables. Used to control write of individual bytes when GWE is HIGH and BWE is

LOW. If any of BW[a,b] is active with GWE HIGH and BWE LOW, the cycle is a write

cycle. If all BW[a,b] are inactive, the cycle is a read cycle.

OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read

mode.

LBO ISTATIC

Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When

driven LOW, device follows linear Burst order. This signal is internally pulled High.

TDO O SYNC Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).

TDI I SYNC Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).

TMS I SYNC This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK

(BGA only).

TCK O SYNC Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).

ZZ I ASYNC Sleep. Places device in LOW power mode; data is retained. Connect to GND if unused.

NC - - No connects

Function GWE BWE BWa BWb

Write all bytes (a, b) LXXX

HLLL

Write byte a H L L H

Write byte b H L H L

Read HHXX

HLHH

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Burst sequence table

Synchronous truth table

Interleaved burst address Linear burst address

A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0

1st Address 0 00 11 01 11

st Address 0 00 11 01 1

2nd Address 0 10 01 11 02

nd Address 0 11 01 10 0

3rd Address 1 01 10 00 13

rd Address 1 01 10 00 1

4th Address 1 11 00 10 04

th Address 1 11 00 11 0

CE01

1 X = don’t care, L = low, H = high

CE1 CE2 ADSP ADSC ADV

WRITE

[2]

2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx,

BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 5 for more information.

Address

accessed CLK Operation DQ

HXXXLX X X NA L to H DeselectHi−Z

L L X L X X X X NA L to H Deselect Hi−Z

L L X H L X X X NA L to H Deselect Hi−Z

L X H L X X X X NA L to H Deselect Hi−Z

L X H H L X X X NA L to H Deselect Hi−Z

L H L L X X X L External L to H Begin read Q

L H L L X X X H External L to H Begin read Hi−Z

L H L H L X H L External L to H Begin read Q

L H L H L X H H External L to H Begin read Hi−Z

XXXHHL H L Next L to HContinue readQ

XXXHHL H H Next L to HContinue readHi−Z

XXXHHH H L Current L to HSuspend readQ

XXXHHH H H Current L to HSuspend readHi−Z

HXXXHL H L Next L to HContinue readQ

HXXXHL H H Next L to HContinue readHi−Z

HXXXHH H L Current L to HSuspend readQ

HXXXHH H H Current L to HSuspend readHi−Z

L H L H L X L X External L to H Begin write D3

3 For write operation following a READ,

must be HIGH before the input data set up time and held HIGH throughout the input hold time

XXXHHL L X Next L to HContinue writeD

HXXXHL L X Next L to HContinue writeD

XXXHHH L X Current L to HSuspend writeD

HXXXHH L X Current L to HSuspend writeD

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AS7C251MFT18A

Absolute maximum ratings

Note: Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the

device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum

rating conditions may affect reliability.

Recommended operating conditions

Parameter Symbol Min Max Unit

Power supply voltage relative to GND VDD, VDDQ –0.3 +3.6 V

Input voltage relative to GND (input pins) VIN –0.3 VDD + 0.3 V

Input voltage relative to GND (I/O pins) VIN –0.3 VDDQ + 0.3 V

Power dissipation PD–1.8W

DC output current IOUT –20 mAmA

Storage temperature (plastic) Tstg –65 +150 oC

Temperature under bias Tbias –65 +135 oC

Parameter Symbol Min Nominal Max Unit

Supply voltage for inputs VDD 2.375 2.5 2.625 V

Supply voltage for I/O VDDQ 2.375 2.5 2.625 V

Ground supply Vss 0 0 0 V

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DC electrical characteristics

*VIL min = -1.5 for pulse width less than 0.2 X tCYC

IDD operating conditions and maximum limits

Parameter Sym Conditions Min Max Unit

Input leakage current |ILI|V

DD = Max, OV < VIN < VDD -2 2 µA

Output leakage current |ILO|OE ≥ VIH, VDD = Max, OV < VOUT < VDDQ -2 2 µA

Input high (logic 1) voltage VIH

Address and control pins 1.7 VDD+0.3 V

I/O pins 1.7 VDDQ+0.3 V

Input low (logic 0) voltage VIL

Address and control pins -0.3*0.7 V

I/O pins -0.3*0.7 V

Output high voltage VOH IOH = –4 mA, VDDQ = 2.375V 1.7 – V

Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V – 0.7 V

Parameter Sym Conditions -85 -10 Unit

Operating power supply current1

1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading

ICC CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax,

IOUT = 0 mA 250 230 mA

Standby power supply current

ISB Deselected, f = fMax, ZZ < VIL 85 75

ISB1 Deselected, f = 0, ZZ < 0.2V,

all VIN ≤ 0.2V or ≥ VDD – 0.2V 40 40

ISB2

Deselected, f = f

Max

, ZZ

≥(

DD,

DDQ

) – 0.2V,

all VIN ≤ VIL or ≥ VIH 40 40

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AS7C251MFT18A

Timing characteristics over operating range

Parameter Sym

–85 –10

Unit Notes1

1 See “Notes” on page 20.

Min Max Min Max

Cycle time tCYC 10–12– ns

Clock access time tCD –8.5–10ns

Output enable low to data valid tOE –3.5–3.8ns

Clock high to output low Z tLZC 0–0–ns2,3,4

Data output invalid from clock high tOH 3.0–3.0– ns 2

Output enable low to output low Z tLZOE 0–0–ns2,3,4

Output enable high to output high Z tHZOE – 3.5 - 3.8 ns 2,3,4

Clock high to output high Z tHZC – 3.5 - 3.8 ns 2,3,4

Output enable high to invalid output tOHOE 0–0–ns

Clock high pulse width tCH 2.4–2.4– ns 5

Clock low pulse width tCL 2.3–2.4– ns 5

Address setup to clock high tAS 1.5–1.5– ns 6

Data setup to clock high tDS 1.5–1.5– ns 6

Write setup to clock high tWS 1.5 – 1.5 – ns 6,7

Chip select setup to clock high tCSS 1.5 – 1.5 – ns 6,8

Address hold from clock high tAH 0.5–0.5– ns 6

Data hold from clock high tDH 0.5–0.5– ns 6

Write hold from clock high tWH 0.5 – 0.5 – ns 6,7

Chip select hold from clock high tCSH 0.5 – 0.5 – ns 6,8

ADV setup to clock high tADVS 1.5–1.5– ns 6

ADSP setup to clock high tADSPS 1.5–1.5– ns 6

ADSC setup to clock high tADSCS 1.5–1.5– ns 6

ADV hold from clock high tADVH 0.5–0.5– ns 6

ADSP hold from clock high tADSPH 0.5–0.5– ns 6

ADSC hold from clock high tADSCH 0.5–0.5– ns 6

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IEEE 1149.1 serial boundary scan (JTAG)

The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard 1149.1-1990 but

does not have the set of functions required for full 1149.1 compliance. The inclusion of these functions would place an added delay in the

critical speed path of the SRAM. The TAP controller functionality does not conflict with the operation of other devices using 1149.1 fully

compliant TAPs. It uses JEDEC-standard 2.5V I/O logic levels.

The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG feature

If the JTAG function is not being implemented, TCK should be tied to VSS, TMS and TDI can be left unconnected, the device will

come up in a reset state which will not interfere with the operation of the device. TDO should be left unconnected.

TAP controller state diagram TAP controller block diagram

Test access port (TAP)

Test clock (TCK)

The test clock is used with only the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling

edge of TCK.

Test mode select (TMS)

The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball unconnected if

the TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level.

UPDATE-IR

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

SELECT

IR-SCAN

UPDATE-DR

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

RUN-TEST/

IDLE

TEST-LOGIC

RESET

SELECT

DR-SCAN

11 1

Note: The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.

Selection

Circuitry

Selection

Circuitry

31 30 29 012

...

Boundary Scan Register1

Identification Register

Bypass Register

Instruction Register

x012

012

.. ...

TDI

TMS

TCK

TDO

TAP Controller

1 x = 53 for the x18 configuration, x = 72 for the x36 configuration.

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AS7C251MFT18A

Test data-in (TDI)

The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between

TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register,

see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) of any register. (See the TAP Controller Block Diagram.)

Test data-out (TDO)

The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state

machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP

Controller State Diagram.)

Performing a TAP RESET

You can perform a RESET by forcing TMS high (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM

and can be performed while the SRAM is operating.

TAP registers

Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test circuitry. Only

one register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ball on the rising edge of TCK.

Data is output on the TDO pin/ball on the falling edge of TCK.

Instruction register

You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO

pins/balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at power up and

also if the controller is placed in a reset state, as described in the previous section.

When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault

isolation of the board-level series test data path.

Bypass register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-

bit register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay.

The bypass register is set low (Vss) when the BYPASS instruction is executed.

Boundary scan register

The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has a 72-bit-long

The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then

placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/RELOAD, and

SAMPLE Z instructions can be used to capture the contents of the I/O ring.

The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM

package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO.

Identification (ID) register

The ID register has a vendor code and other information described in the Identification Register Definitions table. The ID register is loaded

with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The

IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state.

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TAP instruction set

Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes table. Three of

these instructions are reserved and should not be used.

Note that the TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot

preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/

PRELOAD. Instead, it performs a capture of the I/O ring when these instructions are executed.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During

this state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To execute the instruction once it is

shifted in, the TAP controller needs to be moved into the Update-IR state.

EXTEST

The EXTEST instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this SRAM TAP

controller. The TAP controller, however, does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction

EXTEST places the SRAM outputs in a high-Z state.

EXTEST is a mandatory 1149.1 instruction. this device, therefore, is not compliant with 1149.1.

IDCODE

The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register

between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR

state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the TAP controller

is in a Shift-DR state. It also places all SRAM outputs into a high-Z state.

SAMPLE/PRELOAD

When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a

snapshot of data on the inputs and bidirectional pins/balls is captured in the boundary scan register. Note that the SAMPLE/PRELOAD is a

1149.1 mandatory instruction, but the PRELOAD portion of this instruction is not implemented in this device. The TAP controller, therefore,

is not fully 1149.1 compliant.

Be aware that the TAP controller clock can operate only at a frequency up to 10 Mhz, while the SRAM clock operates more than an order of

magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or

output can undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device,

but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet

the TAP controller’s capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in

a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is possible to capture all other signals and

ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a

SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.

BYPASS

The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed

between TDI and TDO.

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AS7C251MFT18A

Reserved

Do not use a reserved instruction.These instructions are not implemented but are reserved for future use.

TAP timing diagram

TAP AC electrical characteristics

For notes 1 and 2, +10oC < TJ < +110oC and +2.4V < VDD < +2.6V.

Description Symbol Min Max Units

Clock

Clock cycle time tTHTH 100 ns

Clock frequency fTF 10 MHz

Clock high time tTHTL 40 ns

Clock low time tTLTH 40 ns

Output Times

TCK low to TDO unknown tTLOX 0 ns

TCK low to TDO valid tTLOV 20 ns

TDI valid to TCK high tDVTH 10 ns

TCK high to TDI invalid tTHDX 10 ns

Setup Times

TMS setup tMVTH 10 ns

Capture setup tCS1

1 tCS and tCH refer to the setup and hold time requirements of latching

data from the boundary scan register.

2 Test conditions are specified using the load in the figure TAP AC output

load equivalent.

10 ns

Hold Times

TMS hold tTHMX 10 ns

Capture hold tCH110 ns

1 23456

tTHTL tTLTH tTHTH

tMVTH tTHMX

tDVTH tTHDX tTLOX

tTLOV

Test Clock

(TCK)

Test Mode Select

(TMS)

Test D ata- In

(TDI)

Test D ata- Out

(TDO)

Don’t care Undefined

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TAP AC test conditions TAP AC output load equivalent

TAP DC electrical characteristics and operating conditions

(+10oC < TJ < +110oC and +2.4V < VDD < +2.6V unless otherwise noted)

1. All voltage referenced to VSS(GND).

2. Overshoot: VIH(AC) ≤ VDD + 1.5V for t ≤ tKHKH/2

Undershoot: VIL(AC) ≥ -0.5 for t ≤ tKHKH/2

Power-up: VIH ≤ +2.6V and VDD ≤ 2.4V and VDDQ ≤ 1.4V for t ≤ 200ms

During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD, R/W, etc.) may not have pulsed widths less than tKHKL(Min) or

operate at frequencies exceeding fKF(Max).

Description Conditions Symbol Min Max Units Notes

Input high (logic 1) voltage VIH 1.7 VDD + 0.3 V 1, 2

Input low (logic 0) voltage VIL -0.3 0.7 V 1, 2

Input leakage current 0V ≤ VIN ≤ VDD ILI-5.0 5.0 µA

Output leakage current Outputs disabled,

0V ≤ VIN ≤ VDDQ(DQx) ILO-5.0 5.0 µA

Output low voltage IOLC = 100µAV

OL1 0.2 V 1

Output low voltage IOLT = 2mA VOL2 0.7 V 1

Output high voltage IOHS = -100µAV

OH1 2.1 V 1

Output high voltage IOHT = -2mA VOH2 1.7 V 1

Input pulse levels. . . . . . . . . . . . . . . Vss to 2.5V

Input rise and fall times. . . . . . . . . . . . . . . 1 ns

Input timing reference levels. . . . . . . . . . 1.25V

Output reference levels . . . . . . . . . . . . . . 1.25V

Test load termination supply voltage. . . . 1.25V

TDO

50Ω

ZO=50Ω

1.25V

20pF

4/12/04, v. 1.0 Alliance Semiconductor 15 of 23

AS7C251MFT18A

Identification register definitions

Scan register sizes

Instruction codes

Instruction field 1M x 18 Description

Revision number (31:28) xxxx Reserved for version number.

Device depth (27:23) xxxxx Defines the depth of 1Mb words.

Device width (22:18) xxxxx Defines the width of x18 bits.

Device ID (17:12) xxxxxx Reserved for future use.

JEDEC ID code (11:1) 00001010010 Allows unique identification of SRAM vendor.

ID register presence indicator (0) 1 Indicates the presence of an ID register.

Instruction 3

Bypass 1

ID 32

Boundary scan x18:53 x36:72

Instruction Code Description

EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to high-Z state. This instruction is not 1149.1-compliant.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI

and TDO. This operation does not affect SRAM operations.

SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a high-Z state.

Reserved 011 Do not use. This instruction is reserved for future use.

SAMPLE/

PRELOAD 100

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation. This instruction does not implement 1149.1 preload

function and is therefore not 1149.1-compliant.

Reserved 101 Do not use. This instruction is reserved for future use.

Reserved 110 Do not use. This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect

SRAM operations.

AS7C251MFT18A

4/12/04, v. 1.0 Alliance Semiconductor 16 of 23

165-ball BGA boundary scan order (x18)

Bit #s Signal Name Ball ID

1SA0 6R

2SA1 6P

3SA 4P

4SA 4R

5SA 3R

6SA 3P

7LBO 1R

8DQPb 1N

9DQb 1M

10 DQb 1L

11 DQb 1K

12 DQb 1J

13 NC 1H

14 DQb 2G

15 DQb 2F

16 DQb 2E

17 DQb 2D

18 SA 2B

19 SA 2A

20 CE0 3A

21 CE1 3B

22 BWb 4A

23 BWa 5B

24 CE2 6A

25 CLK 6B

26 GWE 7B

27 BWE 7A

Bit #s Signal Name Ball ID

28 OE 8B

29 ADSC 8A

30 ADSP 9B

31 ADV 9A

32 SA 10B

33 SA 10A

34 SA 11A

35 DQPa 11C

36 DQa 11D

37 DQa 11E

38 DQa 11F

39 DQa 11G

40 ZZ 11H

41 DQa 10J

42 DQa 10K

43 DQa 10L

44 DQa 10M

45 SA 11R

46 SA 10R

47 SA 10P

48 SA 9P

49 SA 9R

50 SA 8R

51 SA 8P

52 SA 6N

53 SA 11P

Note: NC is don’t care

4/12/04, v. 1.0 Alliance Semiconductor 17 of 23

AS7C251MFT18A

Key to switching waveforms

Timing waveform of read cycle

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

BW[a:b] is don’t care.

Undefined/don’t careFalling inputRising input

CE1

CYC

ADSPS

ADSPH

ADVS

CLK

ADSP

ADSC

Address

GWE, BWE

CE0, CE2

ADV

CSS

ADVH

HZOE

ADSCS

ADSCH

LOAD NEW ADDRESS

ADV inserts wait states

A2A1 A3

OUT

Q(A2Ý10)

Q(A2Ý11)

Q(A3)

Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)

Q(A3Ý11)

Q(A1)

HZC

LZOE

CSH

Read

Q(A1)

Suspend

Read

Q(A1)

Read

Q(A2)

Burst

Read

Q(A 2Ý01

)

Read

Q(A3) DSEL

Burst

Read

Q(A 2Ý10

)

Suspend

Read

Q(A 2Ý10

)

Burst

Read

Q(A 2Ý11

)

Burst

Read

Q(A 3Ý01

)

Burst

Read

Q(A 3Ý10

)

Burst

Read

Q(A 3Ý11

)

AS7C251MFT18A

4/12/04, v. 1.0 Alliance Semiconductor 18 of 23

Timing waveform of write cycle

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

CYC

ADSPS

ADSPH

ADSCS

ADSCH

CSS

ADVS

CLK

ADSP

ADSC

Address

BWE

CE0, CE2

ADV

Data In

CSH

ADVH

D(A2Ý01) D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)

D(A1) D(A2Ý11)

ADV suspends burst

ADSC loads new address

A1 A2 A3

CE1

BW[a:d]

Read Q(A1) Suspend

Write

D(A1)

Read

Q(A2)

Suspend

Write

D(A 2

)

ADV

Burst

Write

D(A 2Ý01

)

Suspend

Write

D(A 2Ý01

)

ADV

Burst

Write

Q(A 2Ý10

)

Write

D(A 3

)

Burst

Write

D(A 3Ý01

)

ADV

Burst

Write

Q(A 2Ý11

)

ADV

Burst

Write

D(A 3Ý10

)

4/12/04, v. 1.0 Alliance Semiconductor 19 of 23

AS7C251MFT18A

Timing waveform of read/write cycle

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

DSEL Suspend

Read

Q(A1)

Read

Q(A1)

Suspend

Write

D(A 2

)

ADV

Burst

Read

D(A 3Ý01

)

Suspend

Read

Q(A 3Ý11

)

ADV

Burst

Read

Q(A 3Ý10

)

ADV

Burst

Read

Q(A 3Ý11

)

Read

Q(A2)

Read

Q(A3)

CYC

ADSPS

ADSPH

ADVS

CLK

ADSP

Address

GWE

CE0, CE2

ADV

LZC

ADVH

LZOE

D(A2)

A1 A2 A3

CE1

HZOE

OUT

Q(A1)

Q(A3Ý01) Q(A3Ý10)

Q(A3Ý11)

AS7C251MFT18A

4/12/04, v. 1.0 Alliance Semiconductor 20 of 23

AC test conditions

Notes

1 For test conditions, see “AC Test Conditions”, Figures A, B, and C.

2 This parameter is measured with output load condition in Figure C.

3 This parameter is sampled but not 100% tested.

HZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.

CH is measured as high above VIH, and tCL is measured as low below VIL.

6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must

meet the setup and hold times for all rising edges of CLK when chip is enabled.

7 Write refers to

GWE

BWE

, and

BW[a,b]

8 Chip select refers to

CE0

CE1

, and

CE2

= 50

Ω

OUT

Ω

Figure B: Output load (A)

30 pF*

Figure A: Input waveform

10%

90%

GND

90%

10%

+2.5V

• Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.

• Input pulse level: GND to 2.5V. See Figure A.

• Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.25V.

= V

DDQ

Thevenin equivalent:

353

Ω/1538Ω

5 pF*

319

Ω/1667Ω

OUT

GND

Figure C: Output load(B)

*including scope

and jig capacitance

+2.5V

4/12/04, v. 1.0 Alliance Semiconductor 21 of 23

AS7C251MFT18A

Package dimensions

100-pin TQFP (quad flat pack)

165-ball BGA (ball grid array)

He E

TQFP

Min Max

A1 0.05 0.15

A2 1.35 1.45

b0.22 0.38

c0.09 0.20

D13.90 14.10

E19.90 20.10

e0.65 nominal

Hd 15.85 16.15

He 21.80 22.20

L0.45 0.75

L1 1.00 nominal

α0° 7°

Dimensions in millimeters

A1 A2

/ 0.45±0.05 (165X)

Ø 0.08

Ø 0.15

67891011 123456543211110987

13.00±0.10

10.00

1.00

15.00±0.10

14.00

1.00

15.00±0.10

13.00±0.10

A1 corner index area

All measurements are in mm.

Min Typ Max

A1.00

B14.90 15.00 15.10

C14.00

D12.90 13.00 13.10

E10.00

F0.26

G0.30 0.35 0.40

H1.20

I0.40 0.45 0.50

ZXY

0.35±0.05

1.20 MAX

0.26

0.50

0.20 Z

Top View Bottom View

Side View Detail of Solder Ball

G I

0.12 Z

AS7C251MFT18A

4/12/04, v. 1.0 Alliance Semiconductor 22 of 23

Ordering information

Note:

Add ‘N’ to the above part numbers for Lead Free Parts (Ex.

AS7C251MFT18A-85TQCN)

Part numbering guide

1. Alliance Semiconductor SRAM prefix

2. Operating voltage: 25 = 2.5V

3. Organization:

4. Flow-through mode

5. Organization: 18 = x18

6. Production version: A = first production version

7. Clock speed

8. Package type: TQ = TQFP; B = BGA

9. Operating temperature: C = commercial (

C to 70

C); I = industrial (

-40

C to 85

10. N = Lead Free Part

Package &Width –85 –10

TQFP x18 10AS7C251MFT18A-85TQC AS7C251MFT18A-10TQC

AS7C251MFT18A-85TQI AS7C251MFT18A-10TQI

BGA x18 AS7C251MFT18A-85BC AS7C251MFT18A-10BC

AS7C251MFT18A-85BI AS7C251MFT18A-10BI

AS7C 25 1M FT 18 A –XX TQ or B C/I X

4567

8910

AS7C251MFT18A

Alliance Semiconductor Corporation

2575, Augustine Drive,

Santa Clara, CA 95054

Tel: 408 - 855 - 4900

Fax: 408 - 855 - 4999

www.alsc.com

Part Number: AS7C251MFT18A

Document Version: v. 1.0

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products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best

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