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Rev.2.00 May 20, 2005 page 1 of 21
HD49334ANP/AHNP
CDS/PGA & 10-bit A/D Converter REJ03F0106-0200
Rev.2.00
May 20, 2005
Description
The HD49334ANP/AHNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD
camera digital signal processing systems together with a 10 - bit A/D converter in a single chip.
Functions
• Correlated double sampling
• PGA
• Offset compensation
• Serial interface control
• 10-bit ADC
• Operates using only the 3 V voltage
• Corresponds to switching mode of power dissipation and operating frequency
Power dissipation: 120 mW (Typ), maximum frequency: 36 MHz (HD49334AHNP)
Power dissipation: 60 mW (Typ), maximum frequency: 25 MHz (HD49334ANP)
• ADC direct input mode
• QFN 36-pin package
Features
• Suppresses low-frequency noise output from CCD by the S/H type correlated double sampling.
• The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and
registers.
• High sensitivity is achieved due to the high S/N ratio and a wide coverage provided by a PG amplifier.
• Feedback is used to compensate and reduce the DC offsets including the output DC offset due to PGA gain change
and the CCD offset in the CDS (correlated double sampling) amplifier input.
• PGA, standby mode, etc., is achieved via a serial interface.
• High precision is provided by a 10-bit-resolution A/D converter.
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 2 of 21
Pin Arrangement
ADCIN
AV
SS
AV
DD
BIAS
BLKC
CDSIN
BLKFB
BLKSH
AV
DD
D1
D2
D3
D4
D5
D6
D7
D8
D9
27 26 25 24 23 22 21 20 19
123456789
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
(Top view)
AV
SS
SPSIG
SPBLK
OBP
PBLK
DV
DD
ADCLK
DV
SS
DRDV
DD
VRM
VRT
VRB
DV
DD
DV
SS
CS
SDATA
SCK
D0
Pin Description
Pin No.
Symbol
Description
I/O Analog(A) or
Digital(D)
1 to 9 D0 to D9 Digital output O D
10 DRDVDD Output buffer power supply (3 V) — D
11 DVSS Digital ground (0 V) — D
12 ADCLK ADC conversion clock input pin I D
13 DVDD Digital power supply (3 V) — D
14 PBLK Preblanking input pin I D
15 OBP Optical black pulse input pin I D
16 SPBLK Black level sampling clock input pin I D
17 SPSIG Signal level sampling clock input pin I D
18 AVSS Analog ground (0 V) — A
19 AVDD Analog power supply (3 V) — A
20 BLKSH Black level S/H pin — A
21 BLKFB Black level FB pin — A
22 CDSIN CDS input pin I A
23 BLKC Black level C pin — A
24 BIAS Internal bias pin
Connect a 33 kΩ resistor between BIAS and AVSS. — A
25 AVDD Analog power supply (3 V) — A
26 AVSS Analog ground (0 V) — A
27 ADCIN ADC input pin — A
28 VRM Reference voltage pin 1
Connect a 0.1 µF ceramic capacitor between VRM and AVSS. — A
29 VRT Reference voltage pin 3
Connect a 0.1 µF ceramic capacitor between VRT and AVSS. — A
30 VRB Reference voltage pin 2
Connect a 0.1 µF ceramic capacitor between VRB and AVSS. — A
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 3 of 21
Pin Description (cont.)
Pin No.
Symbol
Description
I/O Analog(A) or
Digital(D)
31 DVDD Digital power supply (3 V) — D
32 DVSS Digital ground (0 V) — D
33 CS Serial interface control input pin I D
34 SDATA Serial data input pin I D
35 SCK Serial clock input pin I D
36 D0 Digital output O D
Note: 1. With pull-down resistor.
Input/Output Equivalent Circuit
Pin Name Equivalent Circuit
Digital output D0 to D9
DIN DVDD
STBY
Digital
output
Digital input ADCLK, OBP,
SPBLK, SPSIG,
CS, SCK, SDATA,
PBLK
Digital
input
DV
DD
CDSIN
CDSIN
Internally
connected
to VRT
AVDD
ADCIN
A
DCIN
Internally
connected
to VRM
AVDD
BLKSH, BLKFB,
BLKC
BLKFB
AV
DD
BLKSH
BLKC
−
+
VRT, VRM, VRB
−
+
−
+
−
+
VRT VRB AVDD
VRM
Analog
BIAS
BIAS
AVDD
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 4 of 21
Block Diagram
33343243454417
27
26
28
29
35
2
3
4
5
6
7
8
42
9
191816
31
10bit
ADC
OEB
VRB
VRM
VRT
OBP
ADCIN
CDSIN CDS PGA
BLKSH
26PBLK
28BLKC
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BLKFB
CS
SDATA
SCK
BIAS
Timing
generator
1918
16
ADCLK
SPBLK
SPSIG
DVDD
DRDVDD
AVSS
AVDD
19
DVSS
DC offset
compensation
circuit
Serial
interface Bias
generator
Output latch circuit
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 5 of 21
Internal Functions
Functional Description
• CDS input
CCD low-frequency noise is suppressed by CDS (correlated double sampling).
The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *1
Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *2
• ADC in put
The center level of the input signal is clamped at 512 LSB (Typ).
Gain can be adjusted using 8 bits of register (0.01784 times steps) within the range from 0.57 times (–4.86 dB)
to 5.14 times (14.22 dB). *1
• Automatic offset calibration of PGA and ADC
• DC offset compensation feedback for CCD and CDS
• Pre-blanking
CDS input operation is protected by separating it from the large input signal.
Digital output is set at clamp level by resister.
• Digital output enable function
Notes: 1. It is not covered by warranty when 14LSB settings
2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Operating Description
Figure 1 shows CDS/PGA + ADC function block.
Gain setting
(register) Clamp data
(register)
D0 to D9
DAC
C3
CDS
AMP PG
AMP
CDSIN
BLKFB BLKSH
SH
AMP
ADCIN
C2
C1
VRT
10bit
ADC
BLKC
C4 OBP
Offset
calibration
logic
DC offset
feedback
logic
Current
DAC
Figure 1 HD49334ANP/AHNP Functional Block Diagram
1. CDS (Correlated Double Sampling) Circuit
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SPBLK pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SPSIG pulse, and provided to CDSAMP (see figure 1). The
difference between these two signal levels is extracted by the CDSAMP, which also operates as a programmable
gain amplifier at the previous stage. The CDS input is biased with VRT (2 V) during the SPBLK pulse validation
period. During the PBLK period, the above sampling and bias operation are paused.
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 6 of 21
2. PGA Circuit
The PGAMP is the programmable gain ampli fier for the latter stage. The PGAMP and the CDSAMP set the gain
using 8 bits of re gister.
The equation below shows how the gain changes when register value N is from 0 to 255.
In CDSIN mode: Gain = (–2.36 dB + 0.132 dB) × N (LOG linear).
In ADCIN mode: Gain = (0.57 times + 0.00446 times) × N (linear).
Full-scale digital output is defi ned as 0 dB (one time) when 1 V is input.
3. Automatic Offset Calib ration Function and B lack-Level Clamp Data Setting
The DAC DC voltage added to the output of the PGAMP is adjusted by automatic offset calibration.
The data, which cancels the output offset of the PGAMP and the input offset of the ADC, and the clamp data (14
LSB to 76 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts auto matically after the RESET mode set by register 1 is cancelled and
terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).
4. DC Offset Compen sation Feedback Function
Feedback is done to set the blac k si gnal level input during the OB p e riod to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC (see figure 1).
The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the follo wing equation. 1H is
the one cycle of the OBP.
∆Gain/∆H = 0.078/(fclk × C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)
Example: When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039
When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 4 times, 8 times, 16
times, or 32 times by changing the register settings (see table 1). Note that the open-loop differential gain
(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.
The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be
selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 32 LSB, the high-speed lead-in operation continues,
and when the offset error is 32 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4
H, or 8 H depending on the register settings. See table 2.
Table 1 Loop Gain Multiplication Factor during
High-Speed Lead-In Operation Table 2 High-Speed Lead-In Operation
Cancellation Time
HGain-Nsel
(register settings) Multiplication
Factor N
HGstop-Hsel
(register settings) Cancellation
Time
[0]
L
H
L
H
[1]
L
H
H
L4
32
16
8
[0]
L
H
L
H
[1]
L
H
H
L1 H
8 H
4 H
2 H
5. Pre-Blanking Function
During the PBLK input period, the CDS input operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp data (14 to 76 LSB).
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 7 of 21
6. ADC Digital Output Control Function
The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output f unctions and the c odes.
Table 3 ADC Digital Output Functions
Notes: 1. STBY, TEST, LINV, and MINV are set by register.
2. Mode setting for the PBLK is done by external input pins.
3. The polarity of the PBLK pin when the register setting is SPinv is low.
H
L
H
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
X
H
H
H
H
L
H
H
H
H
L
X
X
X
X
X
L
H
L
H
X
L
H
L
H
X
L
H
L
H
X
L
L
H
H
X
L
L
H
H
X
L
L
H
H
X
L
H
X
X
L
H
H
L
STBY
D9
TEST0
Operating Mode
ADC Digital Output D0D1D2D3D4D5D6D7D8
PBLK
MINV
TEST1
LINV
Hi-Z
Same as in table 4.
D9 is inverted in table 4.
D8 to D0 are inverted in table 4.
D9 to D0 are inverted in table 4.
Output code is set up to Clamp Level.
Same as in table 5.
D9 is inverted in table 5.
D8 to D0 are inverted in table 5.
D9 to D0 are inverted in table 5.
Output code is set up to Clamp Level.
Low-power wait state
Normal operation
Pre-blanking
Normal operation
Pre-blanking
Test mode
Table 4 ADC Output Code
Output Pin
Output
codes Steps D1
H
L
L
H
H
L
L
L
H
H
D0
H
L
H
L
H
L
L
H
L
H
D2
L
H
H
H
H
L
H
H
H
H
D7
L
L
L
L
H
L
H
H
H
H
D5
L
L
L
L
H
L
H
H
H
H
D4
L
L
L
L
H
L
H
H
H
H
D3
L
L
L
L
H
L
H
H
H
H
D6
L
L
L
L
H
L
H
H
H
H
D8
L
L
L
L
H
L
H
H
H
H
D9
L
L
L
L
L
H
H
H
H
H
3
4
5
6
511
512
1020
1021
1022
1023
Table 5 ADC Output Code (TEST1)
D8
L
L
L
L
H
H
L
L
L
L
D9
L
L
L
L
L
H
H
H
H
H
3
4
5
6
511
512
1020
1021
1022
1023
D1
H
H
H
L
L
L
H
H
L
L
D0
L
L
H
H
L
L
L
H
H
L
D2
L
H
H
H
L
L
L
L
L
L
D7
L
L
L
L
L
L
L
L
L
L
D5
L
L
L
L
L
L
L
L
L
L
D4
L
L
L
L
L
L
L
L
L
L
D3
L
L
L
L
L
L
L
L
L
L
D6
L
L
L
L
L
L
L
L
L
L
Output Pin
Output
codes Steps
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 8 of 21
7. Adjustment of Black-Level S/H Response Frequency Characteristics
The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the register
settings, as shown in table 6.
Table 6 SHSW CR Ti me Const ant Sett ing
L
[0]
2.20 nsec
(72 MHz) 2.30 nsec
(69 MHz)
L
[1]
L
[2]
L2.51 nsec
(63 MHz) 2.64 nsec
(60 MHz) 2.93 nsec
(54 MHz) 3.11 nsec
(51 MHz) 3.52 nsec
(45 MHz) 3.77 nsec
(42 MHz)
[3]
H
[0]
L
[1]
L
[2]
L
[3]
L
[0]
H
[1]
L
[2]
L
[3]
H
[0]
H
[1]
L
[2]
L
[3]
L
[0]
L
[1]
H
[2]
L
[3]
H
[0]
L
[1]
H
[2]
L
[3]
L
[0]
H
[1]
H
[2]
L
[3]
H
[0]
H
[1]
H
[2]
L
[3]
L
[0]
SHSW-fsel (Register setting)
4.40 nsec
(36 MHz) 4.80 nsec
(33 MHz)
L
[1]
L
[2]
H
CR Time Constant (Typ)
(cutoff frequency conversion)
5.87 nsec
(27 MHz) 6.60 nsec
(24 MHz) 8.80 nsec
(18 MHz) 10.6 nsec
(15 MHz) 17.6 nsec
(9 MHz) 26.4 nsec
(6 MHz)
[3]
H
[0]
L
[1]
L
[2]
H
[3]
L
[0]
H
[1]
L
[2]
H
[3]
H
[0]
H
[1]
L
[2]
H
[3]
L
[0]
L
[1]
H
[2]
H
[3]
H
[0]
L
[1]
H
[2]
H
[3]
L
[0]
H
[1]
H
[2]
H
[3]
H
[0]
H
[1]
H
[2]
H
[3]
BLKC
C4
23
The SHAMP frequency characteristics can be adjusted by changing the register settings
and the C4 value of the external 23rd pin.
The settings are shown in table 7.
Values other than those shown in the table 7 cannot be used.
8.
SHSW-fsel (Register setting)
CR Time Constant (Typ)
(cutoff frequency conversion)
Table 7 SHAMP Frequency Characteristics Setting
49 MHz
15000 pF
(620 pF)
24 MHz
27000 pF
(820 pF)
32 MHz
22000 pF
(750 pF)
SHA-fsel (Register setting)
LoPwr
(Register setting)
Note: Upper line
Middle line
Lower line
: SHAMP cutoff frequency (Typ)
: Standard value of C4 (maximum value is not defined)
: Minimum value of C4 (do not set below this value)
56 MHz
18000 pF
(360 pF)
116 MHz
10000 pF
(270 pF)
"Lo"
"Hi"
75 MHz
13000 pF
(300 pF)
H
[0] L
[1] L
[0] H
[1] H
[0] H
[1]
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 9 of 21
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
D0 to D9
D0 to D9
Note: The phases of SPBLK and SPSIG are those when the serial data SPinv bit is set to low.
012 91011
N+1 N+2 N+9 N+10 N+11N
N−9N−8N−1N
CDSIN
SPBLK
SPSIG
ADCLK
N+2 N+8 N+9 N+10 N+11
N−8N−9N−1
ADCIN
ADCLK
NN+1
NN+1
N−10
• When CDSIN input mode is used
• When ADCIN input mode is used
~
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used
• The ADC output (D0 to D9) is o ut put at the rising ed ge of t he ADCLK in both modes.
• Pipe-line delay is ten clock c ycles when CDSIN is used and nine when ADCIN is used.
• In ADCIN input mode, the input sig nal is sampled at the rising edge of the ADCLK.
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 10 of 21
Detailed Timing Specifications
Detailed Timing Specifications when CDSIN Input Mode is Used
Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.
Black
level Signal
level
D0 to D9
CDSIN
SPBLK Vth
(2) (3)
SPSIG
ADCLK (7)
Vth
Vth
(8)
(9)
(10)
(4)
(1)
(5)
(6)
Note: 1. When serial data Spinv bit is set to low. (When the Spinv bit is set to high,
the polarities of the SPBLK and the SPSIG are inverted.)
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used
Table 8 Timing Specifications when the CDSIN Input Mode is Used
No. Timing Symbol Min Typ Max Unit
(1) Black-level signal fetch time tCDS1 — (1.5) — ns
(2) SPBLK low period *1 t
CDS2 Typ × 0.8 1/4fCLK Typ × 1.2 ns
(3) Signal-level fetch time tCDS3 — (1.5) — ns
(4) SPSIG low period *1 t
CDS4 Typ × 0.8 1/4fCLK Typ × 1.2 ns
(5) SPBLK rising to SPSIG rising time *1 t
CDS5 Typ × 0.85 1/2fCLK Typ × 1.15 ns
(6) SPBLK rising to ADCLK rising inhibition time *1 t
CDS6 1 5 11 ns
(7), (8) ADCLK tWH min. /t WL min. tCDS7, 8 11 — — ns
(9) ADCLK rising to digital output hold time tCHLD9 3 7 — ns
(10) ADCLK rising to digital output delay time tCOD10 — 16 24 ns
Note: 1. SPBLK and SPSIG polarities when serial data Spinv bit is set to low.
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is input. The average of the black signal
level is taken for eight input cycles during the OB period and becomes the clamp level (DC standard).
CDSIN
OBP
Note:
OB pulse > 2 clock cycles
When serial data OBPinv bit is set to low
(When the OBPinv is set to high, the polarity of the OBP is inverted.)
OB period *1
1. Shifts ±1 clock cycle depending on the OBP input timing.
NN+1 N+5 N+12 N+13
This edge is used, when OBP pulse-width period is clamp-on.
Figure 4 OBP Detailed Timing Specifications
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 11 of 21
Detailed Timing Specifications at Pre-Blanking
Figure 5 shows the pre-blanking detailed timing specifications.
Digital output
(D0 to D9) ADC
data Clamp level ADC
data
PBLK
tPBLK
ADCLK × 2 clocks ADCLK × 10 clocks
(shifts one clock cycle depending
on the PBLK input timing)
When serial data SPinv bit is set to low
(When the SPinv is set to high, the PBLK polarity is inverted.)
Vth
VOL
VOH
Figure 5 Detailed Timing Specifications at Pre-Blanking
Detailed Timing Specifica tions when ADCIN Input Mode is Used
Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
A
DCIN (1)
A
DCLK
D0 to D9
(2) Vth
VDD/2
(3)
(5)
(4)
Figure 6 Detailed Timing C ha rt when ADCIN Input Mode is Used
Table 9 Timing Specifications when ADCIN Input Mode is Used
No. Timing Symbol Min Typ Max Unit
(1) Signal fetch time tADC1 — (6) — ns
(2), (3) ADCLK tWH min. /tWL min. tADC2, 3 Typ × 0.85 1/2fADCLK Typ × 1.15 ns
(4) ADCLK rising to digital output hold time tAHLD4 10 14.5 — ns
(5) ADCLK rising to digital output delay time tAOD5 — 23.5 31.5 ns
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 12 of 21
Serial Interface Specifications
Resister 0
Output mode setting (TEST1)
t
su
t
ho
t
INT
1, 2
f
SCK
50 ns
50 ns
Timing Specifications
50 ns
Min
5 MHz
Max
Latches SDATA
at SCK rising edge Data is determined
at CS rising edge
Table 10 Serial Data Function List
DI 00 (LSB)
DI 01
Low
Low
Low
Resister 4 to 7 *
7
Test Mode (can not be used)
High
Low
Low
Resister 1 Resister 2
Low
Low
High
Low to High
Low to High
High
Resister 3
High
Low
High
DI 02
DI 03
DI 04
DI 05
DI 06
DI 07
DI 08
DI 09
DI 10
DI 11
DI 12
DI 13
DI 14
DI 15 (MSB)
HGstop-Hsel [1]
HGain-Nsel [0]
SHA-fsel [0] (LSB)
SHA-fsel [1] (MSB)
SHSW-fsel [0] (LSB)
SHSW-fsel [1]
SHSW-fsel [2]
SHSW-fsel [3] (MSB)
Clamp-level [3]
Clamp-level [2]
Clamp-level [1]
Clamp-level [0] (LSB) C-Bias off
Clamp-level [4] (MSB)
HGstop-Hsel [0]
PGA gain setting (LSB)
PGA gain setting
PGA gain setting
PGA gain setting
PGA gain setting
PGA gain setting
Output mode setting (TEST0)
PGA gain setting
PGA gain setting (MSB)
HGain-Nsel [1]
SCK
CS
SDATA DI
00 DI
01 DI
02 DI
03 DI
04 DI
05 DI
06 DI
07 DI
08 DI
09 DI
10 DI
11 DI
12 DI
13 DI
14 DI
15
tINT1
t
ho
t
su
tINT2
f
SCK
Figure 7 Serial Interface Timing Specifications
Cannot be used.
Cannot be used.
0
0
0
0
0
0
1
1
0
Low_PWR
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
2 byte continuous communications.
SDATA is latched at SCK rising edge.
Insert 16 clocks of SCK while CS is low.
Data is invalid if data transmission is aborted during transmission.
The gain conversion table differs in the CDSIN input mode and the ADCIN input mode.
STBY: Reference voltage generator circuit is in the operating state.
SLP: All circuits are in the sleep state.
This bit is used for the IC testing, and cannot be used by the user.
The use of this address is prohibited.
Circuit current and the frequency characteristic are switched.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
Cannot be used.
All low
Cannot be used.
All low Cannot be used.
All low
Cannot be used.
All low
Low: CDSIN input mode
High: CIN input mode
CSEL
Low: Normal operation mode
High: Sleep mode
SLP
Low: Normal operation mode
High: Standby mode
STBY
Output mode setting (LINV)
Output mode setting (MINV)
SHAMP
frequency
character-
istics
switching
SHSW
frequency
character-
istics
switching
High-speed
lead-in
cancellation
time
High-speed
lead-in
gain
multiplication
SPinv,
SPSIG/SPBLK/PBLK inversion
OBPinv, OBP inversion
Low: Reset mode
High: Normal operation mode
RESET
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 13 of 21
Explanation of Serial Data of CDS Part
Serial data of CDS part has the following functions.
• PGA gain (D5 to D12 of register 0)
Details are referred to page 5 block diagram.
At CDS_in mode: –2.36 dB + 0.132 dB × N (Log linear)
At ADC_in mode: 0.57 times + 0.01784 times × N (Times linear)
∗: Full-scale digital output is defined as 0 dB when 1 V is input.
Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then
PGA outputs the 2 V full-range, and also ADC out puts the full code (1023).
This mean offset gain of PGA has 6 dB – 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add
on.
(1) Level dia explain
CDS PGA
0 dB when set N = 18 which correspond to 2.36 dB
ADC
(2) Level dia on the circuit
CDS PGA
3.64 dB + 0.132 dB × N
(CDS = 0 dB)
ADC
2 V 1023
(1.0 V)
(1.0 V) (2.0 V) (1023)
Figure 8 Level Dia of PGA
• CSEL (D15 of register 0)
Data = 0: Select CDSIN
Data = 1: Select ADCIN
Address STD1[7:0] (L) STD2[15:8] (H)
1 1 1 1 0 0 0 1 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
SHA_fseltest_I2 SHSW_fsel
test0
MINV
LINV
STBY
SLP
• SLP and STBY (D3, D4 of register 1)
SLP: Sto p the all circuit. Consumptio n current of CDS part is less than 10 µA.
Start up from offset calibration when recover is needed.
STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA.
Allow 50 H time for feedback clamp is stabilized until recover.
• Output mode (D5 to D7 of register 1 and D4 of register 3)
It is a test mode. Combination details are table 3 to 5. Normally set to all 0.
• SHA-fsel (D8 to D9 of register 1)
It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 9. To get rough idea, set the
double c ut off frequency point with using.
• SHSW-fsel (D10 to D13 of register 1)
It is a time constant which sa mpli ng the black level of SH amplifier. Frequency characteristics are referred to page
9. To get rough idea, set the double cut off frequency point with usin g. S/N change s by this da ta, so find t he
appropriate point with set data to up/down.
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 14 of 21
• Clamp (D3 to D7 of register 2)
Determine the OB part level with digital code o f ADC ou tp ut.
Clamp level = setting data × 2 + 14
Default data is 9 = 32 LSB.
• HGstop-Hsel, HGain-Nsel (D8 to D11 of register 2)
Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch
the high speed leading mode. T r ansfer the gain +1/–1 to p r evious field, its s witc h to high speed leading mode.
• Low_PWR (D12 of register 2)
Switch circuit current and fr equency chara cteristic.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
• SPinv (D13 of register 2)
SPSIG/SPBLK/PBLK input signal in verted switching.
Data = 1: Normal
Data = 0: Inverted
• Reset (D15 of register 2)
Software reset.
Data = 1: Normal
Data = 0: Reset
Offset calibration should be done when startin g up with using this bit. Details are referred to p age 18 .
• C_Bias_off (D3 of register 3)
Center bias is turned off in ADCIN mode.
Data = 0: Normally on
Data = 1: Off
• Ave_4H (D6 of register 3)
Clamp detection data is avera ged 4 H.
Data = 0: 1H
Data = 1: Averaged 4H
Differential Code and Gray Code (D4 to D5 and D7 to D9 of register 3)
• Gray code (D4 to D5 of register 3)
DC output code can be change to following type.
Gray Code [1] Gray Code [0] Output Code
0 0 Binary code
0 1 Gray code
1 0 Differential encoded binary
1 1 Differential encoded gray
• Serial data setting items (D7 to D9 of register 3)
Setting Bit Setting Contents
Gray_test[0]
Gray_test[1] Standard data output timing control signal
(Refer to the following table)
Gray_test[2] ADCLK polar with OBP. (Lo→Positive edge, HI→Negative edge)
• Standard data output timing
Gray_test[1] Gray_test[0] Standard Data Output Timing
Low Low Third and fourth
Low High Fourth and fifth
High Low Fifth and sixth
High High Sixth and seventh
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 15 of 21
Ripple (pseudo outline made b y quantized error) occurres on the point which swithing the ADC output multiple b it in
parallel. When switching the several of ADC output at the same time, ripple (pseudo o utline caused b y miss
quantization) occurs to the image.
Differential code and gray code are recommended for this countermeasure.
Figure 9 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital
output bit can be reduced and easily to reduce the ripple using this function.
This function is especial ly effective for longer the settings of sensor more than clk = 30 kHz, and ADC output.
Figure 10 indicates the timing specifications.
ADC 10 Differential SW(D5)
Carry bit
round
+
−
Gray SW(D4)
Standard data
control signal
(D9,D8,D7)
Standard
data
selector
10-bit
output
2clk_DL Gray→Binary
conversion
Figure 9 Differential Code, Gray Code Circuit
1
A
DCLK
OBP
Digital output
(Beginning edge of OBP and standard edge of ADCLK should be exept ±5 ns)
(In case of select the positive edge of ADCLK with D8)
(In case of select the positive polar)
Differential data Standard
data Differential data
234567891011
Figure 10 Differential Code Timing Specifications
To use differential code, complex circuit is necessary at DSP side.
(1) Differential coded
From ADC
Standard data
control signal
Carry bit
round
2clk_DL
Standard
data
selector
D9 D9
D8
D7
D0
D8
D7
D0
Gray →
Binary
(2) Gray → Binary conversion
Figure 11 Complex Circuit Example
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 16 of 21
Absolute Maximum Ratings
(Ta = 25°C)
Item Symbol Ratings Unit
Power supply voltage VDD(max) 4.1 V
Analog input voltage VIN(max) –0.3 to AVDD +0.3 V
Digital input voltage VI(max) –0.3 to DVDD +0.3 V
Operating temperature Topr –10 to +75 °C
Power dissipation Pt(max) 400 mW
Storage temperature Tstg –55 to +125 °C
Power supply voltage range Vopr 2.7 to 3.3 V
Notes: 1. VDD indicates AVDD and DVDD.
2. AVDD and DVDD must be commonly connected outside the IC. When they are separated by a noise filter, the
potential difference must be 0.3 V or less at power on, and 0.1 V or less during operation.
Electrical Characteristics
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
• Items Co mmon to CDSIN and ADCIN Input Modes
Item Symbol Min Typ Max Unit Test Conditions Remarks
Power supply volt age
range VDD 2.7 3.0 3.3 V
fCLK hi 20 — 36 MHz LoPwr = low HD49334AHNP Conversion frequency fCLK low 5. 5 — 25 MHz LoPwr = high HD49334ANP
VIH
DV
DD
3.0
2.0 ×
— DVDD V
VIL 0 —
DV
DD
3.0
0.8 ×
V
Digital i nput pins
other than CS,
SCK and SDATA
VIH2
DVDD
3.0
2.25 ×
— DVDD V
Digital i nput vol t age
VIL2 0 —
DV
DD
3.0
0.6 ×
V
CS, SCK , SD ATA
VOH DVDD –0.5 — — V IOH = –1 mA Digital output voltage VOL — — 0.5 V IOL = +1 mA
IIH — — 50 µA VIH = 3.0 V
IIH2 — — 250 µA VIH = 3.0 V
Digital i nput current
IIL –50 — — µA VIL = 0 V
IOZH — — 50 µA VOH = VDD Digital output current IOZL –50 — — µA VOL = 0 V
ADC resolution RES 10 10 10 bit
ADC integral lineari t y INL — 3 — LSBp-p fCLK = 25 MHz
ADC differenti al lineari ty+ DNL+ — 0.3 0. 9 LSB fCLK = 25 MHz *1
ADC differenti al li neari t y– DNL– –0.9 –0.3 — LSB fCLK = 25 MHz *1
Sleep current ISLP –100 0 100 µA Digital i nput pi n is
set to 0 V, output
pin is open
Standby current ISTBY — 3 5 mA Digital I/O pin is se t
to 0 V
Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes.
2. Values within parentheses ( ) are for reference.
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 17 of 21
Electrical Characteristics (cont.)
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
• Items for CDSIN Input Mode
Item Symbol Min Typ Max Unit Test Conditions Remarks
Consumpti on current (1) IDD1 — 45.0 54.5 mA fCLK = 36 MHz CDSIN mode
Lo Pwr = l ow
Consumpti on current (2) IDD2 — 23.5 31.0 mA fCLK = 25 MHz CDSIN mode
LoPwr = high
CCD offset tolerance range VCCD (–100) — (100) mV
Timing specifications (1) tCDS1 — (1.5) — ns
Timing specifications (2) tCDS2 Typ × 0.8 1/4fCLK Typ × 1.2 ns
Timing specifications (3) tCDS3 — (1.5) — ns
Timing specifications (4) tCDS4 Typ × 0.8 1/4fCLK Typ × 1.2 ns
Timing specifications (5) tCDS5 Typ × 0.85 1/2fCLK Typ × 1.15 ns
Timing specifications (6) tCDS6 1 5 9 ns
Timing specifications (7) tCDS7 11 — — ns
Timing specifications (8) tCDS8 11 — — ns
Timing specifications (9) tCHLD9 3 7 — ns
Timing specifications (10) tCOD10 — 16 24 ns
CL = 10 pF
See table 8
CLP(00) — (14) — LSB
CLP(09) — (32) — LSB
Clamp level
CLP(31) — (76) — LSB
PGA(0) –4.4 –2.4 –0.4 dB
PGA(63) 4.1 6.1 8.1 dB
PGA(127) 12.5 14.5 16.5 dB
PGA(191) 21.0 23.0 25.0 dB
PGA gain at CDS input
PGA(255) 29.4 31.4 33.4 dB
Note : Values within parentheses ( ) are for reference.
• Items for ADCIN Input Mode
Item Symbol Min Typ Max Unit Test Conditions Remarks
Consumpti on current (3) IDD3 — 30.0 38.0 mA fCLK = 36 MHz ADCI N mode
Lo Pwr = l ow
Consumpti on current (4) IDD4 — 17.0 21.5 mA fCLK = 25 MHz ADCI N mode
LoPwr = high
Timing specifications (11) tADC1 — (6) — ns
Timing specifications (12) tADC2 Typ × 0.85 1/2fADCLK Typ × 1.15 ns
Timing specifications (13) tADC3 Typ × 0.85 1/2fADCLK Typ × 1.15 ns
Timing specifications (14) tAHLD4 10 14.5 — ns
Timing specifications (15) tAOD5 — 23.5 31.5 ns
CL = 10 pF
See table 9
Input current at ADC input IINCIN –110 — 110 µA VIN = 1.0 V to 2.0 V
Clamp level at ADC input OF2 — (512) — LSB
GSL(0) 0.45 0.57 0.72 Times
GSL(63) 1.36 1.71 2.16 Times
GSL(127) 2.27 2.86 3.60 Times
GSL(191) 3.18 4.00 5.04 Times
PGA gain at ADC input
GSL(255) 4.08 5.14 6.47 Times
Note : Values within parentheses ( ) are for reference.
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 18 of 21
Operation Sequence at Power On
V
DD
HD49334ANP/AHNP
serial data transfer
RESET bit
RESET = "Low"
(RESET mode) RESET = "High"
(RESET cancellation)
Must be stable within the operating
power supply voltage range
SPBLK
SPSIG
ADCLK
OBP
etc.
Start control
of TG and
camera DSP
0 ms
or more
(1) Register 2 setting
(2) Register 2 setting
(3) Register 0, 1 and 3 settings
: Set all bits in register 2 to the usage condition, and set the RESET bit to low.
: Cancel the RESET mode by setting the register 2 RESET bit to high.
Do not change other register 2 settings. Offset calibration starts automatically.
: After the offset calibration is terminated, set registers 0, 1 and 3.
(1) Register 2 setting (2) Register 2 setting
(3) Registers 0, 1
and 3 settings
0 ms
or more
0 ms
or more
2 ms or more
2 ms or more
Ends after 40000 clock cycles
A
utomatic offset
calibration
The following describes the above serial data transfer. For details on registers 0, 1, 2, and 3, refer to table 10.
Offset calibration
(automatically starts
after RESET cancellation)
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 19 of 21
Notice for Use
1. Careful handling is necessary to prevent damage due to static electricity.
2. This product has been developed for consumer applications, and should not be used in non-consumer applications.
3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to
prevent latchup, a ceramic capacitor of 0.1 µF or more and an electrolytic capacitor of 10 µF or more should be
inserted between the ground and power supply.
4. Common connection of AVDD and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise filter,
the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation.
5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure
below.
HD49334ANP/AHNP
AV
SS
DV
SS
AV
DD
DV
DD
Noise filter
A
nalog
+3.0V
HD49334ANP/AHNP
DV
SS
AV
SS
DV
DD
AV
DD
100 µH
0.01 µF
Noise filter Example of noise filte
r
Digital
+3.0V
0.01 µF
6. Connect AVSS and DVSS off-chip using a common ground. If there are separate analog system and digital system
set grounds, connect to the analog system.
7. When VDD is specified in the data sheet, this indicates AVDD and DVDD.
8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be connected to power
supply or ground pins or left open to prevent crosstalk in adjacent analog pins.
9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is less tolerant of
bending than Fe-type lead material, careful handling is necessar y.
10. The infrared reflow soldering method should be used to mount the chip. Note that general heating methods such as
solder dipping cannot be used.
11. Serial communication should not be performed during the effective video period, since this will result in degraded
picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA signals used in the
HD49330AF. If ports are to be shared with another IC, picture quality should first be thoroughly checked.
12. At power-on, automatic adjustment of the offset voltage generated from PGA, ADC, etc., must be implemented in
accordance with the power-on operating sequence (see page 15).
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 20 of 21
Example of Recommended External Circuit
R11 100
R12 100
R13 100
R10 100
C18
0.1 C19
0.1
C17
0.1
L1
47 µ
• At CDS Input
Notes: 1. For C4, see table 5.
2. For C3, see page 8 "DC Offset Compensation Feedback Function".
Unit: R: Ω
C: F
17
19
20
21
22
23
24
25
26
C4*
1
C14 0.1
R15 33 k
C15 0.1
27
8
7
6
5
4
3
2
1
9
1011121314151618
29 34 35 363332313028
Serial data input
GND
from
Timing generator
from CCD out
Note: External circuit is same as above except for ADC input.
3.0 V
3.0 V
to
Camera
signal
processor
C22
0.1
C18
0.1 C19
0.1
C17
0.1 C22
0.1
C1
1 µC3
*
2
1 µ
C10
0.1
C10
0.1
C11
0.1
C11
0.1
R15 33 k
C16
47/6 C21
47/6
L2
47 µ
R14 100
HD49334ANP/AHNP
(CDS/PGA+ADC)
L1
47 µ
• At ADC Input
C15 0.1
Serial data input
GND
from
Timing generator
to
Camera
signal
processor
C14 0.1
C2 2.2/16
C16
47/6 C21
47/6
L2
47 µ
HD49334ANP/AHNP
(CDS/PGA+ADC)
+
−
AV
DD
BLKSH
BLKFB
CDSIN
BLKC
BIAS
AV
DD
AV
SS
ADCIN
D9
D8
D7
D6
D5
D4
D3
D2
D1
AV
SS
SPSIG
SPBLK
OBP
PBLK
DV
DD
ADCLK
DV
SS
DRDV
DD
VRM
VRT
VRB
DV
DD
DV
SS
CS
SDATA
SCK
D0
with ADC input
17
19
20
21
22
23
24
25
26
27
8
7
6
5
4
3
2
1
9
1011121314151618
29 34 35 363332313028
AV
DD
BLKSH
BLKFB
CDSIN
BLKC
BIAS
AV
DD
AV
SS
ADCIN
D9
D8
D7
D6
D5
D4
D3
D2
D1
AV
SS
SPSIG
SPBLK
OBP
PBLK
DV
DD
ADCLK
DV
SS
DRDV
DD
VRM
VRT
VRB
DV
DD
DV
SS
CS
SDATA
SCK
D0
HD49334ANP/AHNP
Rev.2.00 May 20, 2005 page 21 of 21
Package Dimensions
0.20
0.20
0.20
0.50 0.60 0.70
0.20
0.89
0.22
6.2
6.2H
c
H
c
D
E
1
0.17 0.25
0.05
0.5
0.17 0.22 0.27
0.95
0.05
Previous CodeJEITA Package Code RENESAS Code TNP-36/TNP-36V MASS[Typ.]
0.07gP-VQFN36-6x6-0.50 PVQN0036KA-A
e
e
A
MaxNomMin
Dimension in Millimeters
Symbol
Reference
D
E
A
A
b
b
x
y
Z
Z
L
2
1
1
D
E
p
y
1
t
6.0
6.0
0.040.020.005
1.0
1.0
1
c
2
1
p
b
1
y
y
1
x4 t
10
19
18
1927
36
28
E
D
E
D
A
A A
c
L
b
Z
Z
H
E
H
D
×
M
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits,
(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
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8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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