UT54ACS162245S RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Low Voltage Transceiver Datasheet March 12, 2003 FEATURES * Voltage translation - 3.3V bus to 2.5V bus - 2.5V bus to 3.3V bus * Cold sparing all pins LOGIC SYMBOL * 0.25 Commercial RadHard TM CMOS - Total dose: 300Krad(Si) and 1Mrad(Si) - Single Event Latchup immune * High speed, low power consumption * Schmitt trigger inputs to filter noisy signals * Cold and Warm Spare - all outputs * Available QML Q or V processes * Standard Microcircuit Drawing 5962-02543 * Package: - 48-lead flatpack, 25 mil pitch (.390 x .640) G1 G2 1A1 1A2 The 16-bit wide UT54ACS162245S MultiPurpose low voltage transceiver is built using Aeroflex UTMC's Commercial (47) (24) DIR2 (2) 11 12 (46) (3) (5) (43) 1A4 (41) 1A5 (40) 1A6 (38) 1A7 (37) 1A8 (36) 2A1 (6) 2A2 RadHard TM 2EN1 (BA) 2EN2 (AB) 1EN1 (BA) 1EN2 (AB) (44) 1A3 DESCRIPTION epitaxial CMOS technology and is ideal for space applications. This high speed, low power UT54ACS162245S low voltage transceiver is designed to perform multiple functions including: asynchronous two-way communication, Schmitt input buffering, voltage translation, warm and cold sparing. With VDD equal to zero volts, the UT54ACS162245S outputs and inputs present a minimum impedance of 1M making it ideal for "cold spare" applications. Balanced outputs and low "on" output impedance make the UT54ACS162245S well suited for driving high capacitance loads and low impedance backplanes. The UT54ACS162245S enables system designers to interface 2.5 volt CMOS compatible components with 3.3 volt CMOS components. For voltage translation, the A port interfaces with the 2.5 volt bus; the B port interfaces with the 3.3 volt bus. The direction control (DIRx) controls the direction of data flow. The output enable (OEx) overrides the direction control and disables both ports. These signals can be driven from either port A or B. The direction and output enable controls operate these devices as either two independent 8-bit transceivers or one 16-bit transceiver. O E1 (48) O E2 (25) (1) DIR1 (8) (9) 1B2 1B3 1B4 1B5 1B6 (11) 1B7 (12) 1B8 (13) 2B1 21 22 (35) (14) (33) (16) (32) 2A4 (30) 2A5 (29) 2A6 (27) 2A7 (26) 2A8 (17) 2A3 1B1 (19) (20) 2B2 2B3 2B4 2B5 2B6 (22) 2B7 (23) 2B8 PIN DESCRIPTION Pin Names 1 Description O Ex Output Enable Input (Active Low) DIRx Direction Control Inputs xAx Side A Inputs or 3-State Outputs (2.5V Port) xBx Side B Inputs or 3-State Outputs (3.3V Port) PINOUTS POWER TABLE 48-Lead Flatpack Top View DIR1 1 48 OE1 1B1 2 47 1A1 1B2 3 46 V SS 45 44 1A2 V SS 1B3 4 5 1B4 6 43 1A4 VDD1 7 42 VDD2 1B5 8 9 41 40 1A5 10 39 1A6 V SS 1B7 11 38 1A7 1B8 12 37 1A8 2B1 13 36 2A1 2B2 V SS 14 15 35 34 2A2 2B3 16 33 2A3 2B4 17 32 2A4 VDD1 2B5 18 19 20 21 31 30 29 28 VDD2 2A5 2A6 V SS 22 23 24 27 26 25 2A7 2A8 1B6 V SS 2B6 V SS 2B7 2B8 DIR2 1A3 V SS Port B Port A OPERATION 3.3 Volts 2.5 Volts Voltage Translator 3.3 Volts 3.3 Volts Non Translating 2.5 Volts 2.5 Volts Non Translating When V DD2 is at 2.5 volts, either 2.5 or 3.3 volts CMOS logic levels can be applied to all control inputs. For proper operation connect power to all V DD and ground all V SS pins (i.e., no floating V DD or VSS input pins). Tie unused inputs to VSS . Always insure V DD1 > V DD2 during operation of the part. FUNCTION TABLE ENABLE O Ex DIRECTION DIRx OPERATION L L B Data To A Bus L H A Data To B Bus H X Isolation COLD/WARM SPARE FUNCTION The device will place all outputs into a high-impedance state if either VDD supply is taken to zero volts (I WS , warm spare), or if both VDD supplies are set to zero volts (I CS, cold spare). DEVICE POWER UP FUNCTION The device will place all outputs into a high-impedance during power-up. The high impedance state is maintained for a time period approximately equal to the rise time of V DD1 . O E2 2 LOGIC DIAGRAM 2A1 2.5V PORT 1A4 (20) 2A7 (22) 2A8 (12) 3 2B7 (26) (23) 1B8 2B6 (27) 1B7 (37) 2B5 (29) 1B6 (38) 2B4 (30) (19) 2A6 (11) 1A8 (17) 2A5 2B3 (32) 1B5 (40) (9) 1A7 1B4 (41) (8) 1A6 (16) 2A4 2B2 (33) 1B3 (43) (6) 1A5 (14) 2A3 2B1 (35) 1B2 (44) OE 2 (36) (13) 2A2 (5) (25) 1B1 (46) (3) 1A3 (24) O E1 (47) (2) 1A2 DIR2 2.5V PORT 1A1 (48) 2B8 3.3 V PORT (1) 3.3 V PORT DIR1 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E5 rad(Si) SEL Latchup >113 MeV-cm2 /mg Neutron Fluence (Note 2) 1.0E14 n/cm 2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Not tested, inherent to CMOS technology. ABSOLUTE MAXIMUM RATINGS 1 SYMBOL PARAMETER LIMIT (Mil only) UNITS V I/O (Note 2) Voltage any pin -.3 to V DD1 +.3 V V DD1 Supply voltage -0.3 to 4.0 V V DD2 Supply voltage -0.3 to 4.0 V TSTG Storage Temperature range -65 to +150 C Maximum junction temperature +150 C JC Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W TJ (Note 3) Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maxim um rating conditions for extended periods may affect device reliability and performance . 2. For Cold Spare mode (V DD1 =VSS, V DD2 =VSS), V I/O may be -0.3V to the maximum recommended operating level of VDD1 +0.3V. 3. Maximum junction temperature may be increased to +175 oC during burn-in and life test. DUAL SUPPLY OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS V DD1 Supply voltage 2.3 to 3.6 V V DD2 Supply voltage 2.3 to 3.6 V VIN Input voltage any pin 0 to VDD1 V TC Temperature range -55 to + 125 C 4 DC ELECTRICAL CHARACTERISTICS ( -55C < TC < +125C) 1 SYMBOL PARAMETER CONDITION MIN MAX UNIT V T+ Schmitt Trigger, positive going threshold2 VDD from 2.3 to 3.6 .7VDD V VT - Schmitt Trigger, negative going threshold2 VDD from 2.3 to 3.6 .3V DD V VH1 Schmitt Trigger range of hysteresis9 VDD from 3.0 to 3.6 0.5 V VH2 Schmitt Trigger range of hysteresis9 VDD from 2.3 to 2.7 0.4 V I IN Input leakage current 9 VDD from 2.7 to 3.6 -1 3 A -1 3 A -5 5 A -5 5 A -200 200 mA -100 100 mA 0.4 V VIN = VDD or VSS IOZ Three-state output leakage current9 VDD from 2.7 to 3.6 VIN = VDD or VSS I CS Cold sparing input leakage current 3,11 VIN = 3.6 VDD = VSS IWS Warm sparing input leakage current3,11 VIN = VSS or VDD, V DD1 = 0, VDD2 = V DD or V DD1 = V DD, VDD2 = 0 I OS1 Short-circuit output current 5, 10 VO = V DD or V SS VDD from 3.0 to 3.6 I OS2 Short-circuit output current 5, 10 VO = V DD or V SS VDD from 2.3 to 2.7 V OL1 Low-level output voltage9 IOL= 8mA IOL= 100A 0.2 VDD = 3.0 V OL2 Low-level output voltage9 IOL= 8mA 0.4 IOL= 100A 0.2 VDD = 2.3 VOH1 High-level output voltage9 IOH = -8mA IOH = -100A VDD = 3.0 VOH2 High-level output voltage9 IOH = -8mA IOH = -100A VDD = 2.3 5 V VDD - 0.7 V VDD - 0.2 VDD - 0.7 VDD - 0.2 V DC ELECTRICAL CHARACTERISTICS 1 ( -55C < TC < +125C) SYMBOL P total1 CONDITION PARAMETER Power dissipation 4,6,7 CL = 40pF MIN MAX UNIT 6.2 mW/ MHz 3 MHz V DD from 3.0V to 3.6V P total2 Power dissipation 4,6,7 CL = 40pF V DD from 2.3V to 2.7V I DD CIN Standby Supply Current V DD1 or VDD2 V IN = VDD or VSS Pre-Rad 25 oC OE = VDD 10 A Pre-Rad -55oC to +125oC OE = VDD 475 A Post-Rad 25oC OE = VDD 15 mA Input Capacitance 8 f = 1MHz @ 0V 15 pF 15 pF VDD1 or V DD2 Zero Volt Offset 250 mV V DD1 and VDD2 Rise-Time 12 500 mS V DD = 3.6V V DD from 2.3V to 3.6V Cout Output Capacitance 8 f = 1MHz @ 0V V DD from 2.3V to 3.6V POR V DD1 & VDD2 Power-On4,13 Notes: 1. All specifications valid for radiation dose 1E5 rad (Si) per MIL-STD-883, Method 1019. 2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = V IH (min) + 20%, - 0%; V IL = V IL (max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 3. All combinations of OEx and DIRx 4. Guaranteed by characterization. 5. Not more than one output may be shorted at a time for maximum duration of one second. 6. Power does not include power contribution of any CMOS output sink current. 7. Power dissipation specified per switching output. 8.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 9.Guaranteed; tested on a sample of pins per device. 10. Supplied as a design limit, but not guaranteed or tested. 11. Zero Volts is defined as 0.0 Volts +/- 0.25Volts. 12. V DD1 and VDD2 Voltage rise is monotonic. 13. Rise time measured from V D D @ Zero Volts to V DD @ greater than 2.3 V. 6 AC ELECTRICAL CHARACTERISTICS1 (Port B = 3.3 Volt, Port A = 2.5 Volt) (V DD1 = 3.0V to 3.6V; V DD2 = 2.3V to 2.7V, -55C < T C < +125C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Propagation delay Data to Bus 2 10 ns tPHL Propagation delay Data to Bus 2 10 ns tPZL Output enable time OEx to Bus 2 12 ns tPZH Output enable time OEx to Bus 2 12 ns tPLZ Output disable time OEx to Bus high impedance 2 15 ns tPHZ Output disable time OEx to Bus high impedance 2 15 ns tPZL2 Output enable time DIRx to Bus 2 12 ns tPZH 2 Output enable time DIRx to Bus 2 12 ns tPLZ2 Output disable time DIRx to Bus high impedance 2 15 ns tPHZ 2 Output disable time DIRx to Bus high impedance 2 15 ns tSLH 3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps tSHL 3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested 3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-h igh Propagation Delay Input tPLH V DD V DD /2 0V tPHL V OH V DD /2 V OL Output Enable Disable Times Control Input 3.3V Output Normally Low 3.3V Output Normally High tPZL tPLZ V DD /2-0.2 tPZH tPHZ V DD /2+0.2 tPZL 2.5V Output Normally Low 2.5V Output Normally High .8VDD - .2V tPLZ V DD/2-0.2 tPZH .2VDD + .2V .2VDD + .2V tPHZ VDD /2+0.2 7 .7V DD - .2V V DD V DD /2 0V V DD /2 .2V DD .8V DD V DD /2 V DD/2 .2V DD .7V DD V DD/2 AC ELECTRICAL CHARACTERISTICS 1 (Port A = Port B, 3.3 Volt Operation) (V DD1 = 3.0 to 3.6V; V DD2 = 3.0V to 3.6V, -55C < TC < +125C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Propagation delay Data to Bus 2 7.5 ns tPHL Propagation delay Data to Bus 2 7.5 ns tPZL Output enable time OEx to Bus 2 10 ns tPZH Output enable time OEx to Bus 2 10 ns tPLZ Output disable time OEx to Bus high impedance 2 12 ns tPHZ Output disable time OEx to Bus high impedance 2 12 ns tPZL 2 Output enable time DIRx to Bus 2 10 ns tPZH2 Output enable time DIRx to Bus 2 10 ns tPLZ 2 Output disable time DIRx to Bus high impedance 2 12 ns tPHZ2 Output disable time DIRx to Bus high impedance 2 12 ns tSLH3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps tSHL3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested 3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-high Propagation Delay Input tPLH V DD V DD/2 0V tPHL V OH V DD/2 V OL Output Enable Disable Times Control Input 3.3V Output Normally Low 3.3V Output Normally High tPZL tPLZ V DD/2-0.2 .2VDD + .2V tPHZ tPZH V DD/2+0.2 8 .8VDD - .2V V DD V DD/2 0V V DD/2 .2V DD .8V DD V DD/2 AC ELECTRICAL CHARACTERISTICS1 (Port A = Port B, 2.5 Volt Operation) (V DD1 = 2.3V TO 2.7V; VDD2 = 2.3V to 2.7V, -55C < TC < +125C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Propagation delay Data to Bus 2 10 ns tPHL Propagation delay Data to Bus 2 10 ns tPZL Output enable time OEx to Bus 2 12 ns tPZH Output enable time OEx to Bus 2 12 ns tPLZ Output disable time OEx to Bus high impedance 2 15 ns tPHZ Output disable time OEx to Bus high impedance 2 15 ns tPZL2 Output enable time DIRx to Bus 2 12 ns tPZH 2 Output enable time DIRx to Bus 2 12 ns tPLZ2 Output disable time DIRx to Bus high impedance 2 15 ns tPHZ 2 Output disable time DIRx to Bus high impedance 2 15 ns tSLH 3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps tSHL 3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested 3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-h igh Propagation Delay Input tPLH V DD V DD/2 0V tPHL V OH V DD/2 V OL Output Enable Disable Times Control Input 2.5V Output Normally Low 2.5V Output Normally High tPZL tPLZ V DD/2-0.2 .2V DD + .2V tPHZ tPZH V DD/2+0.2 9 .7VDD - .2V V DD V DD/2 0V V DD/2 .2V DD .7VDD V DD/2 PACKAGE 5 6 4 6 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Lead position and colanarity are not measured. 5. ID mark symbol is vendor option. 6. With solder, increase maximum by 0.003. Figure 1. 48-Lead Flatpack 10 ORDERING INFORMATION UT54ACS162245S: SMD 5962 R 02543 01 * * * Lead Finish: (C) = Gold (A) = Solder Case Outline: (X) = 48 lead FP Class Designator: (Q) = Class Q (V) = Class V Device Type (01) = 16-bit MultiPurpose Low Voltage T ransceiver Drawing Number: 02543 Total Dose: (R) = 1E5 rad(Si) (F) = 3E5 rad(Si) (G) = 5E5 rad(Si) (H) = 1E6 rad(Si) Federal Stock Class Designator Notes: 1. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 11 UT54ACS162245S UT54 *** ****** * * * Lead Finish: (C) = (A) = Solder Gold Screening: (C) = Mil Temp (P) = Prototype Package Type: (U) = 48-lead FP Part Number: (16225SLV) = 16-bit MultiPurpose Low Voltage Transceiver I/O Type: (ACS)= CMOS compatible I/O Level UTMC Core Part Number Notes: 1. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested -55C, room temp, and 125C. Radiation n either tested nor guaranteed. 2. Prototype flow per UTMC Manufacturing Flows Document Tested at 25C only. Lead finish is gold only. 12