AR0330CM 1/3inch CMOS Digital Image Sensor Description The AR0330 from ON Semiconductor is a 1/3-inch CMOS digital image sensor with an active-pixel array of 2304 (H) x 1536 (V). It can support 3.15 Mp (2048 (H) x 1536 (V)) digital still image capture and a 1080p60 + 20% EIS (2304 (H) x 1296 (V)) digital video mode. It incorporates sophisticated on-chip camera functions such as windowing, mirroring, column and row sub-sampling modes, and snapshot modes. www.onsemi.com CLCC48 CASE 848AU Table 1. KEY PERFORMANCE PARAMETERS Parameter Typical Value ORDERING INFORMATION Optical Format 1/3-inch (6.0 mm) Entire Array: 6.09 mm Still Image: 5.63 mm (4:3) HD Image: 5.82 mm (16:9) Active Pixels 2304 (H) x 1536 (V): (Entire Array) 5.07mm (H) x 3.38mm (V) 2048 (H) x 1536 (V) (4:3, Still Mode) 2304 (H) x 1296 (V) (16:9, HD Mode) Pixel Size 2.2 x 2.2 mm Color Filter Array RGB Bayer Shutter Type ERS and GRR Input Clock Range 6-27 MHz Output Clock Maximum 196 Mp/s (4-lane HiSPi or MIPI) Output Video - 4-lane HiSPi 2304 x 1296 at 60 fps < 450 mW (VCM 0.2 V, 198 MP/s) 2304 x 1296 at 30 fps < 300 mW (VCM 0.2 V, 98 MP/s) Responsivity 2.0 V/lux-sec SNRMAX 39 dB Dynamic Range 69.5 dB Supply Voltage Digital Analog HiSPi PHY HiSPi I/O (SLVS) HiSPi I/O (HiVCM) I/O/Digital -30C to + 70C Package Options CLCC - 11.4 mm x 11.4mm CSP - 6.28 mm x 6.65 mm Bare Die (c) Semiconductor Components Industries, LLC, 2010 March, 2017 - Rev. 18 See detailed ordering and shipping information on page 2 of this data sheet. Features * 2.2 mm Pixel with A-Pixt Technology * Full HD support at 60 fps * * * * * * 1.7-1.9 V (1.8 V Nominal) 2.7-2.9 V 1.7-1.9 V (1.8 V Nominal) 0.3-0.9 V (0.4 or 0.8 V Nominal) 1.7-1.9 V (1.8 V Nominal) 1.7-1.9 V (1.8 V Nominal) or 2.4-3.1 V (2.8 V Nominal) Operating Temperature (Junction) -TJ ODCSP64 CASE 570BH * * * * (2304 (H) x 1296 (V)) for Maximum Video Performance Superior Low-light Performance 3.4 Mp (3:2) and 3.15 Mp (4:3) Still Images Support for External Mechanical Shutter Support for External LED or Xenon Flash Data Interfaces: Four-lane Serial High-speed Pixel Interface (HiSPi) Differential Signaling (SLVS), Four-lane Serial MIPI Interface, or Parallel On-chip Phase-locked Loop (PLL) Oscillator Simple Two-wire Serial Interface Auto Black Level Calibration 12-to-10 Bit Output A-Law Compression Slave Mode for Precise Frame-rate Control and for Synchronizing Two Sensors Applications * 1080p High-definition Digital Video Camcorder * Web Cameras and Video Conferencing Cameras * Security 1 Publication Order Number: AR0330CM/D AR0330CM ORDERING INFORMATION Table 2. AVAILABLE PART NUMBERS Product Description Part Number Orderable Product Attribute Description AR0330CM1C00SHAA0-DP 3 MP 1/3 CIS Dry Pack with Protective Film AR0330CM1C00SHAA0-DR 3 MP 1/3 CIS Dry Pack without Protective Film AR0330CM1C00SHAA0-TP 3 MP 1/3 CIS Tape & Reel with Protective Film AR0330CM1C00SHKA0-CP 3 MP 1/3 CIS Chip Tray with Protective Film AR0330CM1C00SHKA0-CR 3 MP 1/3 CIS Chip Tray without Protective Film AR0330CM1C12SHAA0-DP 3 MP 1/3 CIS Dry Pack with Protective Film AR0330CM1C12SHAA0-DR 3 MP 1/3 CIS Dry Pack without Protective Film AR0330CM1C12SHKA0-CP 3 MP 1/3 CIS Chip Tray with Protective Film AR0330CM1C12SHKA0-CR 3 MP 1/3 CIS Chip Tray without Protective Film AR0330CM1C21SHKA0-CP 3 MP 1/3 CIS Chip Tray with Protective Film AR0330CM1C21SHKA0-CR 3 MP 1/3 CIS Chip Tray without Protective Film FUNCTIONAL OVERVIEW GENERAL DESCRIPTION The AR0330 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 2304 x 1296 image at 60 frames per second (fps). The sensor outputs 10- or 12-bit raw data, using either the parallel or serial (HiSPi, MIPI) output ports. The AR0330 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can generate all internal clocks from a single master input clock running between 6 and 27 MHz. The maximum output pixel rate is 196 Mp/s using a 4-lane HiSPi or MIPI serial interface and 98 Mp/s using the parallel interface. Test Pattern Generator Ext Clock Analog Core Row Noise Correction Registers Row Drivers PLL Timing and Control 12-bit Digital Core Output Data-Path Compression (Optional) Black Level Correction Pixel Array Digital Gain Column Amplifiers Data Pedestal 12-bit 12-bit ADC 10- or 12-bit 8-, 10or 12-bit 12-bit Two-wire Serial I/F Parallel I/O: PIXCLK, FV, LV, DOUT[11:0] MIPI I/O: CLK P/N, DATA[11:0] P/N HiSPi I/O: SLVS C P/N, SLVS[3:0] P/N Figure 1. Block Diagram controlled by varying the time interval between reset and readout. Once a row has been read, the signal from the column is amplified in a column amplifier and then digitized in an analog-to-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 3.4 Mp active-pixel sensor array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is www.onsemi.com 2 AR0330CM WORKING MODES The AR0330 sensor working modes are specified from the following aspect ratios: Table 3. AVAILABLE ASPECT RATIOS IN THE AR0330 SENSOR Aspect Ratio Sensor Array Usage 3:2 Still Format #1 2256 (H) x 1504 (V) 4:3 Still Format #2 2048 (H) x 1536 (V) 16:10 Still Format #3 2256 (H) x 1440 (V) 16:9 HD Format 2304 (H) x 1296 (V) The AR0330 supports the following working modes. To operate the sensor at full speed (196 Mp/s) the sensor must use the 4-lane HiSPi or MIPI interface. The sensor will operate at half-speed (98 Mp/s) when using the parallel interface. Table 4. AVAILABLE WORKING MODES IN THE AR0330 SENSOR Mode Aspect Ratio Active Readout Window Sensor Output Resolution FPS (4-lane MIPI/ HiSPi Interface) FPS (Parallel Interface) Subsampling FOV 1080p + EIS 16:9 2304 x 1296 2304 x 1296 60 N/A - 100% 30 30 - 100% - 100% 3M Still 4:3 2048 x 1536 2048 x 1536 30 25 3:2 2256 x 1504 2256 x 1504 30 25 - 100% WVGA + EIS 16:9 2304 x 1296 1152 x 648 60 60 2x2 100% WVGA + EIS Slow-motion 16:9 2304 x 1296 1152 x 648 120 N/A 2x2 100% VGA Video 16:10 2256 x 1440 752 x 480 60 60 3x3 96% VGA Video Slow-motion 16:10 2256 x 1440 752 x 480 215 107 3x3 96% HiSPi POWER SUPPLY CONNECTIONS The HiSPi interface requires two power supplies. The VDD_HiSPi powers the digital logic while the VDD_HiSPi_TX powers the output drivers. The digital logic supply is a nominal 1.8 V and ranges from 1.7 to 1.9 V. The HiSPi drivers can receive a supply voltage of 0.4 to 0.8 V or 1.7 to 1.9 V. The common mode voltage is derived as half of the VDD_HiSPi _TX supply. Two settings are available for the output common mode voltage: 1. SLVS Mode: The VDD_HiSPi_Tx supply must be in the range of 0.4 to 0.8 V and the high_vcm register bit R0x306E[9] must be set to "0". The output common mode voltage will be in the range of 0.2 to 0.4 V. 2. HiVCM Mode: The VDD_HiSPi_Tx supply must be in the range of 1.7 to 1.9 V and the high_vcm register bit R0x306E[9] must be set to "1". The output common mode voltage will be in the range of 0.76 to 1.07 V. Two prior naming conventions have also been used with the VDD_HiSPi and VDD_HiSPi_TX pins: 1. Digital logic supply was named VDD_SLVS while the driver supply was named VDD_SLVS_TX. 2. Digital logic supply was named VDD_PHY while the driver supply was named VDD_SLVS. www.onsemi.com 3 AR0330CM TYPICAL CONFIGURATIONS Analog Analog Power1 Power1 VAA VDD_MIPI PLL Power1 VDD_PLL VDD_HiSPi_TX Master Clock (6-27 MHz) VDD HiSPi Power1 VDD_HiSPi VDD_IO 1.5 kW3, 4 1.5 kW3 Digital Digital Core I/O Power1 Power1 VAA_PIX SLVS0_P SLVS0_N SLVS1_P EXTCLK SLVS1_N SLVS2_P OE_BAR From Controller To Controller (HiSPi-serial Interface) SLVS2_N TRIGGER SLVS3_P SADDR SLVS3_N SCLK SLVSC_P SDATA SLVSC_N RESET_BAR SHUTTER FLASH TEST DGND GND_SLVS AGND Digital Ground VDD_HiSPi_TX 1.0 mF 0.1 mF 1.0 mF VDD_IO 0.1 mF 1.0 mF VDD 0.1 mF Analog Ground VDD_HiSPi 1.0 mF 0.1 mF 1.0 mF VDD_PLL 0.1 mF 1.0 mF VAA 0.1 mF VAA_PIX 1.0 mF 0.1 mF Notes: 1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0 mF and 0.1 mF decoupling capacitors for every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_IO, and VDD. Actual values and results may vary depending on layout and design considerations. 2. To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the pads as possible. In addition, place a 10 mF capacitor for each supply off-module but close to each supply. 3. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed. 4. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. TEST pin should be tied to DGND. 7. Set High_VCM (R0x306E[9]) to 0 (default) to use the VDD_HiSPi_TX in the range of 0.4-0.8 V. Set High_VCM to 1 to use a range of 1.7-1.9 V. 8. The package pins or die pads used for the MIPI data and clock as well as the parallel interface must be left floating. 9. The VDD_MIPI package pin and sensor die pad should be connected to a 2.8 V supply as VDD_MIPI is tied to the VDD_PLL supply both in the package routing and also within the sensor die itself. 10. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating. 11. If the TRIGGER pin or pad is not used then it should be tied to DGND. 12. The GND_SLVS pad must be tied to DGND. It is connected this way in the CLCC and CSP packages. Figure 2. Serial 4-lane HiSPi Interface www.onsemi.com 4 AR0330CM Master Clock (6-27 MHz) VDD Analog Analog Power1 Power1 VAA VDD_MIPI PLL Power1 VDD_PLL VDD_IO 1.5 kW3, 4 1.5 kW3 Digital Digital Core I/O Power1 Power1 VAA_PIX DATA1_P DATA1_N DATA2_P EXTCLK DATA2_N DATA3_P From Controller OE_BAR DATA3_N TRIGGER SADDR DATA4_N DATA4_P SCLK CLK_P SDATA CLK_N To Controller (MIPI-serial Interface) SHUTTER RESET_BAR FLASH TEST VDD_IO 1.0 mF 0.1 mF 1.0 mF DGND AGND Digital Ground Analog Ground VDD 0.1 mF VDD_PLL 1.0 mF 0.1 mF 1.0 mF VAA 0.1 mF VAA_PIX 1.0 mF 0.1 mF Notes: 1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0 mF and 0.1 mF decoupling capacitors for every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_MIPI, VDD_IO, and VDD. Actual values and results may vary depending on layout and design considerations. 2. To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the pads as possible. In addition, place a 10 mF capacitor for each supply off-module but close to each supply. 3. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed. 4. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. TEST pin must be tied to DGND for the MIPI configuration. 7. ON Semiconductor recommends that GND_MIPI be tied to DGND. 8. VDD_MIPI is tied to VDD_PLL in both the CLCC and the CSP package. ON Semiconductor strongly recommends that VDD_MIPI must be connected to a VDD_PLL in a module design since VDD_PLL and VDD_MIPI are tied together in the die. 9. The package pins or die pads used for the HiSPi data and clock as well as the parallel interface must be left floating. 10. HiSPi Power Supplies (VDD_HISPI and VDD_HISPI_TX) can be tied to ground. 11. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating. 12. If the TRIGGER pin or pad is not used then it should be tied to DGND. Figure 3. Serial MIPI www.onsemi.com 5 1.5 kW3, 4 1.5 kW3 AR0330CM Master Clock (6-27 MHz) Digital I/O Power1 Digital Core Power1 PLL Power1 Analog Power1 Analog Power1 VDD_IO VDD VDD_PLL VAA VAA_PIX EXTCLK DOUT[11:0] OE_BAR LINE_VALID PIXCLK TRIGGER From Controller To Controller FRAME_VALID SADDR SCLK SDATA FLASH SHUTTER RESET_BAR TEST VDD_IO 1.0 mF 0.1 mF 1.0 mF DGND AGND Digital Ground Analog Ground VDD 0.1 mF VDD_PLL 1.0 mF 0.1 mF 1.0 mF VAA 0.1 mF VAA_PIX 1.0 mF 0.1 mF Notes: 1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0 mF and 0.1 mF decoupling capacitors for every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_IO, and VDD. Actual values and results may vary depending on layout and design considerations. 2. To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the pads as possible. In addition, place a 10 mF capacitor for each supply off-module but close to each supply. 3. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed. 4. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. TEST pin should be tied to the ground. 7. The data and clock package pins or die pads used for the HiSPi and MIPI interface must be left floating. 8. The VDD_MIPI package pin and sensor die pad should be connected to a 2.8 V supply as it is tied to the VDD_PLL supply both in the package routing and also within the sensor die itself. HiSPi Power Supplies (VDD_HISPI and VDD_HISPI_TX) can be tied to ground. 9. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating. 10. If the TRIGGER pin or pad is not used then it should be tied to DGND. Figure 4. Parallel Pixel Data Interface www.onsemi.com 6 AR0330CM PIN DESCRIPTIONS Table 5. PIN DESCRIPTIONS Name Type RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default. EXTCLK Input Master input clock, range 6-27 MHz. Description OE_BAR Input Output enable (active LOW). Only available on bare die version. TRIGGER Input Receives slave mode VD signal for frame rate synchronization and trigger to start a GRR frame. SADDR Input Two-wire serial address select. SCLK Input Two-wire serial clock input. SDATA I/O PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock. DOUT[11:0] Output Parallel pixel data output. FLASH Output Flash output. Synchronization pulse for external light source. Can be left floating if not used. FRAME_VALID Output Asserted when DOUT data is valid. LINE_VALID Output Asserted when DOUT data is valid. VDD Power Digital power. VDD_IO Power IO supply power. VDD_PLL Power PLL power supply. The MIPI power supply (VDD_MIPI) is tied to VDD_PLL in both packages. DGND Power Digital GND. VAA Power Analog power. VAA_PIX Power Pixel power. AGND Power Analog GND. TEST Input SHUTTER Output Control for external mechanical shutter. Can be left floating if not used. SLVS0_P Output HiSPi serial data, lane 0, differential P. SLVS0_N Output HiSPi serial data, lane 0, differential N. SLVS1_P Output HiSPi serial data, lane 1, differential P. SLVS1_N Output HiSPi serial data, lane 1, differential N. SLVS2_P Output HiSPi serial data, lane 2, differential P. SLVS2_N Output HiSPi serial data, lane 2, differential N. SLVS3_P Output HiSPi serial data, lane 3, differential P. SLVS3_N Output HiSPi serial data, lane 3, differential N. SLVSC_P Output HiSPi serial DDR clock differential P. SLVSC_N Output HiSPi serial DDR clock differential N. DATA1_P Output MIPI serial data, lane 1, differential P. DATA1_N Output MIPI serial data, lane 1, differential N. Two-wire serial data I/O. Enable manufacturing test modes. Tie to DGND for normal sensor operation. DATA2_P Output MIPI serial data, lane 2, differential P. DATA2_N Output MIPI serial data, lane 2, differential N. DATA3_P Output MIPI serial data, lane 3, differential P. DATA3_N Output MIPI serial data, lane 3, differential N. DATA4_P Output MIPI serial data, lane 4, differential P. DATA4_N Output MIPI serial data, lane 4, differential N. www.onsemi.com 7 AR0330CM Table 5. PIN DESCRIPTIONS (continued) Name Type Description CLK_P Output Output MIPI serial clock, differential P. CLK_N Output Output MIPI serial clock, differential N. VDD_HiSPi Power 1.8 V power port to HiSPi digital logic. VDD_HiSPi_TX Power 0.4-0.8 V or 1.7-1.9 V. Refer to "HiSPi Power Supply Connections". VAA_HV_NPIX Power Power supply pin used to program the sensor OTPM (one-time programmable memory). This pin should be open if OTPM is not used. Table 6. CSP (HiSPi/MIPI) PACKAGE PINOUT 1 2 3 4 5 6 7 8 A VAA VAA_HV_NPIX AGND AGND VAA VDD TEST DGND B DGND NC VAA_PIX DGND VDD_IO TRIGGER RESET_BAR EXTCLK C VDD SHUTTER DGND SLVSC_P SLVS3_P SLVS3_N SLVS2_N SLVS2_P D SADDR SCLK SDATA FLASH SLVSC_N SLVS1_P VDD_HiSPi_TX VDD_HiSPi E VDD_IO VDD_IO CLK_N CLK_P DGND SLVS1_N SLVS0_N SLVS0_P F DGND VDD_IO DGND DGND DATA4_P DATA_N DATA_P VDD_PLL G VDD_IO VDD DGND VDD_IO DATA4_N DATA3_N DATA2_N VDD H DGND VDD_IO VDD_IO DGND VDD_PLL DATA3_P DATA2_P VDD_PLL 43 VAA_PIX 48 1 DGND SDATA FLASH VDD_IO VDD SADDR SCLK VAA_HV_NPIX NC DGND VDD DGND NOTE: NC = No Connection. 6 7 42 DATA4_N AGND DATA4_P VAA DATA3_N DGND DATA3_P EXTCLK CLK_N RESET_BAR CLK_P TRIGGER DATA2_N SHUTTER DATA2_P TEST DATA1_N VDD DATA1_P VDD_IO DGND VDD_PLL 18 31 SLVS1_P SLVS1_N SLVS0_P SLVS0_N SLVSC_P SLVSC_N VDD_HiSPi VDD_HiSPi_TX 19 SLVS3_P SLVS3_N SLVS2_P SLVS2_N 30 DGND NOTE: Pins labeled NC (Not Connected) should be tied to ground. Figure 5. CLCC Package Pin Descriptions www.onsemi.com 8 AR0330CM SENSOR INITIALIZATION Power-Up Sequence 6. Assert RESET_BAR for at least 1 ms. 7. Wait 150,000 EXTCLK periods (for internal initialization into software standby. 8. Write R0x3152 = 0xA114 to configure the internal register initialization process. 9. Write R0x304A = 0x0070 to start the internal register initialization process. 10. Wait 150,000 EXTCLK periods. 11. Configure PLL, output, and image settings to desired values. 12. Wait 1ms for the PLL to lock. 13. Set streaming mode (R0x301A[2] = 1). The recommended power-up sequence for the AR0330CS is shown in Figure 6. The available power supplies (VDD_IO, VDD_PLL, VDD_MIPI, VAA, VAA_PIX) must have the separation specified below. 1. Turn on VDD_PLL and VDD_MIPI power supplies. 2. After 100 ms, turn on VAA and VAA_PIX power supply. 3. After 100 ms, turn on VDD power supply. 4. After 100 ms, turn on VDD_IO power supply. 5. After the last power supply is stable, enable EXTCLK. VDD_PLL, VDD_MIPI (2.8) VAA_PIX VAA (2.8) t0 t1 VDD (1.8) t2 VDD_IO (1.8/2.8) t3 RESET_BAR t4 tX Hard Reset Internal Initialization t5 R0x3152 = 0xA114 R0x304A = 0x0070 Internal Initialization t6 Software Standby PLL Clock Streaming EXTCLK Notes: 1. A software reset (R0x301A[0] = 1) is not necessary after the procedure described above since a Hard Reset will automatically triggers a software reset. Independently executing a software reset, should be followed by steps seven through thirteen above. 2. The sensor must be receiving the external input clock (EXTCLK) before the reset pin is toggled. The sensor will begin an internal initialization sequence when the reset pin toggle from LOW to HIGH. This initialization sequence will run using the external input clock. Power on default state is software standby state, need to apply two-wire serial commands to start streaming. Above power up sequence is a general power up sequence. For different interface configurations, MIPI, and Parallel, some power rails are not needed. Those not needed power rails should be ignored in the general power up sequence. Figure 6. Power Up Table 7. POWER-UP SEQUENCE Symbol Definition Min Typ Max Unit t0 VDD_PLL, VDD_MIPI to VAA/VAA_PIX (Note 3) 0 100 - ms t1 VAA/VAA_PIX to VDD 0 100 - ms t2 VDD to VDD_IO 0 100 - ms tX External Clock Settling Time (Note 1) - 30 - ms t3 Hard Reset (Note 2) 1 - - ms t4 Internal Initialization 150000 - - EXTCLKs t5 Internal Initialization 150000 - - EXTCLKs t6 PLL Lock Time 1 - - ms 1. External clock settling time is component-dependent, usually taking about 10-100 ms. 2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the RC time must include the all power rail settle time and Xtal settle time. 3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the others. If the case happens that VDD_PLL is powered after other supplies then sensor may have functionality issues and will experience high current draw on this supply. 4. VDD_MIPI is tied to VDD_PLL in the both the CLCC and CSP packages and must be powered to 2.8 V. The VDD_HiSPi and VDD_HiSPi_TX supplies do not need to be turned on if the sensor is configured to use the MIPI or parallel interface. www.onsemi.com 9 AR0330CM Power-Down Sequence 2. The soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. Turn off VDD_HiSPi_TX. 4. Turn off VDD_IO. 5. Turn off VDD and VDD_HiSPi. 6. Turn off VAA/VAA_PIX. 7. Turn off VDD_PLL, VDD_MIPI. The recommended power-down sequence for the AR0330 is shown in Figure 7. The available power supplies (VDD_IO, VDD_HiSPi, VDD_HiSPi_TX, VDD_PLL, VDD_MIPI, VAA, VAA_PIX) must have the separation specified below. 1. Disable streaming if output is active by setting standby R0x301a[2] = 0. VDD_HiSPi_TX (0.4) t0 VDD_IO (1.8/2.8) t1 VDD, VDD_HiSPi (1.8) t2 VAA_PIX, VAA (2.8) t3 VDD_PLL, VDD_MIPI (2.8) EXTCLK t4 Power Down until Next Power Up Cycle Figure 7. Power Down Table 8. POWER-DOWN SEQUENCE Symbol Parameter Min Typ Max Unit t0 VDD_HiSPi_TX to VDD_IO 0 - - ms t1 VDD_IO to VDD and VDD_HiSPi 0 - - ms t2 VDD and VDD_HiSPi to VAA/VAA_PIX 0 - - ms t3 VAA/VAA_PIX to VDD_PLL 0 - - ms t4 PwrDn until Next PwrUp Time 100 - - ms NOTE: t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. www.onsemi.com 10 AR0330CM ELECTRICAL CHARACTERISTICS Table 9. DC ELECTRICAL DEFINITIONS AND CHARACTERISTICS (MIPI MODE) (fEXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; Output Load = 68.5 pF; TJ = 60C; Data Rate = 588 Mbps; 2304 x 1296 at 60 fps) Definition Min Typ Max Unit Core Digital Voltage 1.7 1.8 1.9 V I/O Digital Voltage 1.7 2.4 1.8 2.8 1.9 3.1 V Analog Voltage 2.7 2.8 2.9 V Symbol VDD VDD_IO VAA VAA_PIX Pixel Supply Voltage 2.7 2.8 2.9 V VDD_PLL PLL Supply Voltage 2.7 2.8 2.9 V VDD_MIPI MIPI Supply Voltage 2.7 2.8 2.9 V Digital Operating Current - 114 136 mA I/O Digital Operating Current - 0 0 mA Analog Operating Current - 41 53 mA I (VDD) I (VDD_IO) I (VAA) I (VAA_PIX) Pixel Supply Current - 9.9 12 mA I (VDD_PLL) PLL Supply Current - 15 27 mA I (VDD_MIPI) MIPI Digital Operating Current - 35 49 mA Table 10. DC ELECTRICAL DEFINITIONS AND CHARACTERISTICS (HiSPi MODE) (fEXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; VDD_HiSPi = 1.8 V, VDD_HiSPi_TX = 0.4 V; Output Load = 68.5 pF; TJ = 60C; Data Rate = 588 Mbps; DLL Set to 0; 2304 x 1296 at 60 fps) Min Typ Max Unit Core Digital Voltage Definition 1.7 1.8 1.9 V I/O Digital Voltage 1.7 2.4 1.8 2.8 1.9 3.1 V Analog Voltage 2.7 2.8 2.9 V VAA_PIX Pixel Supply Voltage 2.7 2.8 2.9 V VDD_PLL PLL Supply Voltage 2.7 2.8 2.9 V VDD_HiSPi HiSPi Digital Voltage 1.7 1.8 1.9 V VDD_HiSPi_TX HiSPi I/O Digital Voltage 0.3 1.7 0.4 1.8 0.9 1.9 V I (VDD) Digital Operating Current - 96.3 137 mA I/O Digital Operating Current - 0 0 mA Analog Operating Current - 45.1 53 mA I (VAA_PIX) Pixel Supply Current - 10.5 12 mA I (VDD_PLL) PLL Supply Current - 6.4 11 mA HiSPi Digital Operating Current - 21.8 36 mA HiSPi I/O Digital Operating Current - 22.3 40 mA Symbol VDD VDD_IO VAA I (VDD_IO) I (VAA) I (VDD_HiSPi) I (VDD_HiSPi_TX) www.onsemi.com 11 AR0330CM Table 11. DC ELECTRICAL DEFINITIONS AND CHARACTERISTICS (PARALLEL MODE) (fEXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; Output Load = 68.5 pF; TJ = 60C; 2304 x 1296 at 30 fps) Definition Min Typ Max Unit Core Digital Voltage 1.7 1.8 1.9 V I/O Digital Voltage 1.7 2.4 1.8 2.8 1.9 3.1 V Symbol VDD VDD_IO Analog Voltage 2.7 2.8 2.9 V VAA_PIX VAA Pixel Supply Voltage 2.7 2.8 2.9 V VDD_PLL PLL Supply Voltage 2.7 2.8 2.9 V Digital Operating Current - 66.5 75 mA I/O Digital Operating Current - 24 35 mA Analog Operating Current - 36 44 mA I (VAA_PIX) Pixel Supply Current - 10.5 18 mA I (VDD_PLL) PLL Supply Current - 6 11 mA I (VDD) I (VDD_IO) I (VAA) Table 12. STANDBY POWER (fEXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; Output Load = 68.5 pF; TJ = 60C) Hard Standby (CLK OFF) Soft Standby (CLK OFF) Soft Standby (CLK ON) Power Typ Max Unit Digital 19.8 35.8 mA Analog 5.8 7.0 mA Digital 23.5 39.7 mA Analog 5.4 5.9 mA Digital 15700 16900 mA Analog 5.5 5.7 mA CAUTION: Stresses greater than those listed in Table 13 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Table 13. ABSOLUTE MAXIMUM RATINGS Symbol Min Max Unit Core Digital Voltage -0.3 2.4 V I/O Digital Voltage -0.3 4 V VAA_MAX Analog Voltage -0.3 4 V VDD_MAX VDD_IO_MAX Definition VAA_PIX Pixel Supply Voltage -0.3 4 V VDD_PLL PLL Supply Voltage -0.3 4 V VDD_MIPI MIPI Supply Voltage -0.3 4 V VDD_HiSPi_MAX HiSPi Digital Voltage -0.3 2.4 V HiSPi I/O Digital Voltage -0.3 2.4 V Storage Temperature -40 85 C VDD_HiSPi_TX_MAX tST Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 12 AR0330CM Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 8 and Table 14. SDATA tLOW tf tSU;DAT tr tf tHD;STA tBUF tr SCLK tHD;STA S NOTE: tHD;DAT tSU;STA tHIGH tSU;STO Sr P S Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Figure 8. Two-Wire Serial Bus Timing Parameters Table 14. TWO-WIRE SERIAL BUS CHARACTERISTICS (fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; TA = 25C) Standard Mode Fast Mode Symbol Min Max Min Max Unit tSCL 0 100 0 400 kHz tHD;STA 4.0 - 0.6 - ms LOW Period of the SCLK Clock tLOW 4.7 - 1.3 - ms HIGH Period of the SCLK Clock tHIGH 4.0 - 0.6 - ms Set-up Time for a Repeated START Condition tSU;STA 4.7 - 0.6 - ms Data Hold Time tHD;DAT 0 (Note 4) 3.45 (Note 5) 0 (Note 6) 0.9 (Note 5) ms Data Set-up Time tSU;DAT 250 - 100 (Note 6) - ns Rise Time of both SDATA and SCLK Signals tr - 1000 20 + 0.1 Cb (Note 7) 300 ns Fall Time of both SDATA and SCLK Signals tf - 300 20 + 0.1 Cb (Note 7) 300 ns Set-up Time for STOP Condition tSU;STO 4.0 - 0.6 - ms tBUF 4.7 - 1.3 - ms Cb - 400 - 400 pF Parameter SCLK Clock Frequency Hold Time (Repeated) START Condition After this Period, the First Clock Pulse is Generated Bus Free Time between a STOP and START Condition Capacitive Load for Each Bus Line Serial Interface Input Pin Capacitance SDATA Max Load Capacitance SDATA Pull-up Resistor CIN_SI - 3.3 - 3.3 pF CLOAD_SD - 30 - 30 pF RSD 1.5 4.7 1.5 4.7 kW This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor. Two-wire control is I2C-compatible. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1 VDD levels. Sensor EXCLK = 27 MHz. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. 1. 2. 3. 4. 5. 6. www.onsemi.com 13 AR0330CM tR tF 90% tRP tFP 90% 10% 90% 10% 10% 90% 10% tEXTCLK EXTCLK tCP PIXCLK tPD Data[11:0] tPD Pxl_0 Pxl_1 Pxl_2 Pxl_n tPFL tPLL tPLH tPFH FRAME_VALID/ LINE_VALID FRAME_VALID Leads LINE_VALID by 609 PIXCLKs NOTE: FRAME_VALID Trails LINE_VALID by 16 PIXCLKs PLL disabled for tCP. Figure 9. I/O Timing Diagram Table 15. I/O PARAMETERS (fEXTCLK = 24 MHz; VDD = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; Output Load = 68.5 pF; TJ = 60C; CLK_OP = 98 Mp/s) Definition Symbol Condition Min Max Unit VIH Input HIGH Voltage VDD_IO = 1.8 V VDD_IO = 2.8 V 1.4 2.4 VDD_IO + 0.3 VDD_IO + 0.3 V VIL Input LOW Voltage VDD_IO = 1.8 V VDD_IO = 2.8 V GND - 0.3 GND - 0.3 0.4 0.8 mV IIN Input Leakage Current No Pull-up Resistor; VIN = VDD OR DGND -20 20 mA VOH Output HIGH Voltage At Specified IOH VDD_IO - 0.4 - V VOL Output LOW Voltage At Specified IOL - 0.4 V IOH Output HIGH Current At Specified VOH - -12 mA IOL Output LOW Current At Specified VOL - 9 mA IOZ Tri-state Output Leakage Current - 10 mA Table 16. I/O TIMING (fEXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; Output load = 68.5 pF; TJ = 60C; CLK_OP = 98 Mp/s) Definition Symbol Conditions Min Typ Max Unit 27 MHz fEXTCLK Input Clock Frequency PLL Enabled 6 24 tEXTCLK Input Clock Period PLL Enabled 166 41 20 ns tR Input Clock Rise Time 0.5 - Sine Wave Rise Time ns tF Input Clock Fall Time 0.5 - Sine Wave Fall Time ns Clock Duty Cycle 45 50 55 % tJITTER Output Pin Slew fPIXCLK Input Clock Jitter Fastest - - 0.3 ns CLOAD = 15 pF - 0.7 - V/ns PIXCLK frequency Default - 80 - MHz tPD PIXCLK to data valid Default - - 3 ns tPFH PIXCLK to FRAME_VALID HIGH Default - - 3 ns tPLH PIXCLK to LINE_VALID HIGH Default - - 3 ns tPFL PIXCLK to FRAME_VALID LOW Default - - 3 ns tPLL PIXCLK to LINE_VALID LOW Default - - 3 ns www.onsemi.com 14 AR0330CM Table 17. PARALLEL I/O RISE SLEW RATE (fEXTCLK = 24 MHz; VDD = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; Output Load = 68.5 pF; TJ = 60C; CLK_OP = 98 Mp/s) Parallel Slew Rate (R0x306E[15:13]) VDD_IO 0 1 2 3 4 5 6 7 Unit 1.70 V 0.069 0.115 0.172 0.239 0.325 0.43 0.558 0.836 V/ns 1.80 V 0.078 0.131 0.195 0.276 0.375 0.507 0.667 1.018 1.95 V 0.093 0.156 0.233 0.331 0.456 0.62 0.839 1.283 2.50 V 0.15 0.252 0.377 0.539 0.759 1.07 1.531 2.666 2.80 V 0.181 0.305 0.458 0.659 0.936 1.347 1.917 3.497 3.10 V 0.212 0.361 0.543 0.78 1.114 1.618 2.349 4.14 HiSPi TRANSMITTER NOTE: Refer to "High-Speed Serial Pixel Interface Physical Layer Specification v2.00.00" for further explanation of the HiSPi transmitter specification. SLVS Electrical Specifications Table 18. POWER SUPPLY AND OPERATING TEMPERATURE (fEXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; Output load = 68.5 pF; TJ = 60C; CLK_OP = 98 Mp/s) Symbol Parameter IDD_HiSPi_TX IDD_HiSPi TJ 1. 2. 3. 4. Min Typ Max Unit SLVS Current Consumption (Notes 1, 2) - - n x 18 mA HiSPi PHY Current Consumption (Notes 1, 2, 3) - - n x 45 mA -30 - 70 C Operating Temperature (Note 4) Where `n' is the number of PHYs. Temperature of 25C. Up to 700 Mbps. Specification values may be exceeded when outside this temperature range. Table 19. SLVS ELECTRICAL DC SPECIFICATION (TJ = 25C) Symbol Parameter Min Typ Max Unit VCM SLVS DC Mean Common Mode Voltage 0.45 * VDD_TX 0.5 * VDD_TX 0.55 * VDD_TX V |VOD| SLVS DC Mean Differential Output Voltage 0.36 * VDD_TX 0.5 * VDD_TX 0.64 * VDD_TX V DVCM Change in VCM between Logic 1 and 0 - - 25 mV |VOD| Change in |VOD| between Logic 1 and 0 - - 25 mV VOD Noise Margin - - 30 % |DVCM| Difference in VCM between any Two Channels - - 50 mV |DVOD| Difference in VOD between any Two Channels - - 100 mV VCM_AC Common-mode AC Voltage (pk) without VCM Cap Termination - - 50 mV VCM_AC Common-mode AC Voltage (pk) with VCM Cap Termination - - 30 mV VOD_AC Maximum Overshoot Peak |VOD| - - 1.3 * |VOD| V VDiff_pk-pk Maximum Overshoot VDiff_pk-pk - - 2.6 * VOD V RO Single-ended Output Impedance 35 50 70 W Output Impedance Mismatch - - 20 % NM DRO www.onsemi.com 15 AR0330CM Table 20. SLVS ELECTRICAL TIMING SPECIFICATION Symbol Min Max Unit 1/UI Data Rate (Note 1) 280 700 Mbps tPW Bitrate Period (Note 1) 1.43 3.57 ns tPRE Max Setup Time from Transmitter (Notes 1, 2) 0.3 - UI tPOST Max Hold Time from Transmitter (Notes 1, 2) 0.3 - UI tEYE Eye Width (Notes 1, 2) - 0.6 UI Data Total Jitter (pk-pk) @1e-9 (Notes 1, 2) - 0.2 UI tCKJIT Clock Period Jitter (RMS) (Note 2) - 50 ps tCYCJIT Clock Cycle-to-Cycle Jitter (RMS) (Note 2) - 100 ps tTOTALJIT Parameter tR Rise Time (20-80%) (Note 3) 150 ps 0.25 UI tF Fall Time (20-80%) (Note 3) 150 ps 0.25 UI 45 55 % DCYC Clock Duty Cycle (Note 2) tCHSKEW Mean Clock to Data Skew (Notes 1, 4) -0.1 0.1 UI tPHYSKEW PHY-to-PHY Skew (Notes 1, 5) - 2.1 UI tDIFFSKEW Mean Differential Skew (Note 6) -100 100 ps 1. One UI is defined as the normalized mean time between one edge and the following edge of the clock. 2. Taken from the 0 V crossing point with the DLL off. 3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3 UI. 4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges. 5. The absolute skew between any Clock in one PHY and any Data lane in any other PHY between any edges. 6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two complementary edges at mean VCM point. Note that differential skew also is related to the DVCM_AC spec which also must not be exceeded. HiVCM Electrical Specifications still scalable with VDD_HiSPi_TX, but with VDD_HiSPi_TX nominal set to 1.8 V the common-mode is elevated to around 0.9 V. The HiSPi 2.0 specification also defines an alternative signaling level mode called HiVCM. Both VOD and VCM are Table 21. HiVCM POWER SUPPLY AND OPERATING TEMPERATURES Symbol IDD_HiSPi_TX IDD_HiSPi TJ 1. 2. 3. 4. Parameter Min Typ Max Unit HiVCM Current Consumption (Notes 1, 2) - - n * 34 mA HiSPi PHY Current Consumption (Notes 1, 2, 3) - - n * 45 mA -30 - 70 C Operating Temperature (Note 4) Where `n' is the number of PHYs. Temperature of 25C. Up to 700 Mbps. Specification values may be exceeded when outside this temperature range. www.onsemi.com 16 AR0330CM Table 22. HiVCM ELECTRICAL VOLTAGE AND IMPEDANCE SPECIFICATION (TJ = 25C) Symbol Min Typ Max Unit VCM HiVCM DC Mean Common Mode Voltage 0.76 0.90 1.07 V |VOD| HiVCM DC Mean Differential Output Voltage 200 280 350 mV DVCM Change in VCM between Logic 1 and 0 - - 25 mV |VOD| Change in |VOD| between Logic 1 and 0 - - 25 mV VOD Noise Margin - - 30 % |DVCM| Difference in VCM between any Two Channels - - 50 mV |DVOD| Difference in VOD between any Two Channels - - 100 mV DVCM_AC Common-mode AC Voltage (pk) without VCM Cap Termination - - 50 mV DVCM_AC Common-mode AC Voltage (pk) with VCM Cap Termination - - 30 mV Maximum Overshoot Peak |VOD| - - 1.3 * |VOD| V Maximum Overshoot VDiff pk-pk - - 2.6 * VOD V Single-ended Output Impedance 40 70 100 W Output Impedance Mismatch - - 20 % NM VOD_AC VDiff_pk-pk RO DRO Parameter Table 23. HiVCM ELECTRICAL AC SPECIFICATION Symbol Parameter Min Max Unit 1/UI Data Rate (Note 1) 280 700 Mbps tPW Bitrate Period (Note 1) 1.43 3.57 ns tPRE Max Setup Time from Transmitter (Notes 1, 2) 0.3 - UI tPOST Max Gold Time from Transmitter (Notes 1, 2) 0.3 - UI tEYE Eye Width (Notes 1, 2) - 0.6 UI Data Total Jitter (pk-pk) @1e-9 (Notes 1, 2) - 0.2 UI tCKJIT Clock Period Jitter (RMS) (Note 2) - 50 ps tCYCJIT Clock Cycle-to-Cycle Jitter (RMS) (Note 2) - 100 ps tTOTALJIT tR Rise Time (20-80%) (Note 3) 150 ps 0.3 UI tF Fall Time (20-80%) (Note 3) 150 ps 0.3 UI 45 55 % DCYC Clock Duty Cycle (Note 2) tCHSKEW Clock to Data Skew (Notes 1, 4) -0.1 0.1 UI tPHYSKEW PHY-to-PHY Skew (Notes 1, 5) - 2.1 UI tDIFFSKEW Mean Differential Skew (Note 6) -100 100 ps 1. One UI is defined as the normalized mean time between one edge and the following edge of the clock. 2. Taken from the 0 V crossing point with the DLL off. 3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3 UI. 4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges. 5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges. 6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two complementary edges at mean VCM point. Note that differential skew also is related to the DVCM_AC spec which also must not be exceeded. www.onsemi.com 17 AR0330CM Electrical Definitions VCM use the DC test circuit shown in Figure 11 and set the HiSPi PHY to constant Logic 1 and Logic 0. Measure Voa, Vob and VCM with voltmeters for both Logic 1 and Logic 0. Figure 10 is the diagram defining differential amplitude VOD, VCM, and rise and fall times. To measure VOD and Single-Ended Signals Voa VOD_AC VOD V CM + V oa ) V ob 2 Vob Differential Signal 80% VDiff VOD = |Voa - Vob| tR 0V VOD = |Vob - Voa| tF Vdiff_pkpk 20% Figure 10. Single-Ended and Differential Signals 50 W Voa VCM V Vob 50 W V Figure 11. DC Test Circuit V OD(m) + V oa(m) * V ob(m) Both VOD and VCM are measured for all output channels. The worst case DVOD is defined as the largest difference in VOD between all channels regardless of logic level. And the worst case DVCM is similarly defined as the largest difference in VCM between all channels regardless of logic level. (eq. 1) Where m is either "1" for logic 1 or "0" for logic 0. V OD + V OD(1) ) V OD(0) 2 (eq. 2) V Diff + V OD(1) ) V OD(0) (eq. 3) DV OD + V OD(1) * V OD(0) (eq. 4) V CM + V CM(1) ) V CM(0) 2 DV CM + V CM(1) * V CM(0) (eq. 5) (eq. 6) www.onsemi.com 18 AR0330CM Timing Definitions edge, as shown in Figure 12. This time is compared with the ideal Data transition point of 0.5 UI with the difference being the Clock-to-Data Skew (see Equation 7). 1. Timing measurements are to be taken using the Square Wave test mode. 2. Rise and fall times are measured between 20% to 80% positions on the differential waveform, as shown in Figure 10. 3. Mean Clock-to-Data skew should be measured from the 0 V crossing point on Clock to the 0 V crossing point on any Data channel regardless of t CHSKEW(ps) + Dt * t CHSKEW(UI) + t pw 2 Dt * 0.5 t pw (eq. 7) (eq. 8) tpw 1 UI Clock 0.5 UI Dt tCHSKEW Data Figure 12. Clock-to-Data Skew Timing Diagram 4. The differential skew is measured on the two single-ended signals for any channel. The time is taken from a transition on Voa signal to corresponding transition on Vob signal at VCM crossing point. VCM tDIFFSKEW Common-mode AC Signal VCM_AC VCM VCM_AC Figure 13. Differential Skew Figure 13 also shows the corresponding AC VCM common-mode signal. Differential skew between the Voa and Vob signals can cause spikes in the common-mode, which the receiver needs to be able to reject. VCM_AC is measured as the absolute peak deviation from the mean DC VCM common-mode. www.onsemi.com 19 AR0330CM Transmitter Eye Mask 1.3 * VOD VOD Eye Width Eye Height Differential Amplitude 0.7 * VOD 0 -0.7 * VOD tPRE -VOD tPOST -1.3 * VOD 0 0.2 0.37 0.5 0.63 0.8 1 Normalized Time Figure 14. Transmitter Eye Mask Figure 14 defines the eye mask for the transmitter. 0.5 UI point is the instantaneous crossing point of the Clock. The area in white shows the area Data is prohibited from crossing into. The eye mask also defines the minimum eye height, the data tPRE and tPOST times, and the total jitter pk-pk +mean skew (tTJSKEW ) for Data. Clock Signal tHCLK is defined as the high clock period, and tLCLK is defined as the low clock period as shown in Figure 15. The clock duty cycle DCYC is defined as the percentage time the clock is either high (tHCLK) or low (tLCLK) compared with the clock period T. T 2 UI tHCLK Clock tLCLK Figure 15. Clock Duty Cycle D CYC(1) + D CYC(0) + t HCLK T t LCLK T t pw + (eq. 9) T 2 (i.e, 1 UI) (eq. 11) 1 t pw (eq. 12) Bitrate + (eq. 10) www.onsemi.com 20 AR0330CM Figure 16 shows the definition of clock jitter for both the period and the cycle-to-cycle jitter. tHCLK tLCLK tCKJIT (RMS) tpw Figure 16. Clock Jitter Period Jitter (tCKJIT) is defined as the deviation of the instantaneous clock tPW from an ideal 1 UI. This should be measured for both the clock high period variation DtHCLK, and the clock low period variation DtLCLK taking the RMS or 1-sigma standard deviation and quoting the worse case jitter between DtHCLK and DtLCLK. Cycle-to-cycle jitter (tCYCJIT) is defined as the difference in time between consecutive clock high and clock low periods tHCLK and tLCLK, quoting the RMS value of the variation D(tHCLK - tLCLK). If pk-pk jitter is also measured, this should be limited to 3-sigma. Table 24. HiVCM ELECTRICAL AC SPECIFICATION Symbol Parameter Min Max Unit 1/UI Data Rate (Note 1) 280 700 Mbps tPW Bitrate Period (Note 1) 1.43 3.57 ns tPRE Max Setup Time from Transmitter (Notes 1, 2) 0.3 - UI tPOST Max Gold Time from Transmitter (Notes 1, 2) 0.3 - UI tEYE Eye Width (Notes 1, 2) - 0.6 UI Data Total Jitter (pk-pk) @1e-9 (Notes 1, 2) - 0.2 UI tCKJIT Clock Period Jitter (RMS) (Note 2) - 50 ps tCYCJIT Clock Cycle-to-Cycle Jitter (RMS) (Note 2) - 100 ps tTOTALJIT tR Rise Time (20-80%) (Note 3) 150 ps 0.3 UI tF Fall Time (20-80%) (Note 3) 150 ps 0.3 UI 45 55 % DCYC Clock Duty Cycle (Note 2) tCHSKEW Clock to Data Skew (Notes 1, 4) -0.1 0.1 UI tPHYSKEW PHY-to-PHY Skew (Notes 1, 5) - 2.1 UI tDIFFSKEW Mean Differential Skew (Note 6) -100 100 ps 1. One UI is defined as the normalized mean time between one edge and the following edge of the clock. 2. Taken from the 0 V crossing point with the DLL off. 3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3 UI. 4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges. 5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges. 6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two complementary edges at mean VCM point. Note that differential skew also is related to the DVCM_AC spec which also must not be exceeded. www.onsemi.com 21 AR0330CM SENSOR PLL SEQUENCER The sequencer digital block determines the order and timing of operations required to sample pixel data from the array during each row period. It is controlled by an instruction set that is programmed into RAM from the sensor OTPM (One Time Programmable Memory). The OTPM is configured during production. The instruction set determines the length of the sequencer operation that determines the "ADC Readout Limitation" (Equation 5) listed in the Sensor Frame Rate section. The instruction set can be shortened through register writes in order to achieve faster frame rates. Instructions for shortening the sequencer can be found in the AR0330 Developer Guide. The sequencer digital block can be reprogrammed using the following instructions: Program a new sequencer. 1. Place the sensor in standby. 2. Write 0x8000 to R0x3088 ("seq_ctrl_port"). 3. Write each instruction incrementally to R0x3086. Each write must be 16-bit consisting of two bytes {Byte[N], Byte[N+1]}. 4. If the sequencer consists of an odd number of bytes, set the last byte to "0". VCO The sensor contains a phase-locked loop (PLL) that is used for timing generation and control. The required VCO clock frequency is attained through the use of a pre-PLL clock divider followed by a multiplier (see Figure 17). The multiplier is followed by set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces. Dual Readout Paths There are two readout paths within the sensor digital block (see Figure 18). The sensor row timing calculations refers to each data-path individually. For example, the sensor default configuration uses 1248 clocks per row (line_length_pck) to output 2304 active pixels per row. The aggregate clocks per row seen by the receiver will be 2496 clocks (1248 x 2 readout paths). Read the instructions stored in the sequencer. 1. Place the sensor in standby. 2. Write 0xC000 to R0x3088 ("seq_ctrl_port"). 3. Sequentially read one byte at a time from R0x3086 with 8-bit read command. pre_pll_clk_div 2(1-64) EXTCLK (6-27 MHz) pll_multiplier 58(32-384) FVCO Figure 17. Relationship between Readout Clock and Peak Pixel Rate All Digital Blocks CLK_PIX Serial Output (MIPI or HiSPi) Pixel Array Pixel Rate = 2 x CLK_PIX = # Data Lanes x CLK_OP (HiSPi or MIPI) = CLK_OP (Parallel) All Digital Blocks CLK_PIX Figure 18. Sensor Dual Readout Paths www.onsemi.com 22 AR0330CM Parallel PLL Configuration FVCO pre_pll_clk_div 2(1-64) EXTCLK (6-27 MHz) vt_sys_clk_div 1(1, 2, 4, 6, 8, 10, 12, 14, 16) pll_multiplier 58(32-384) vt_pix_clk_div 6(4-16) CLK_OP (Max 98 Mpixel/s) 1/2 CLK_PIX (Max 49 Mpixel/s) Figure 19. PLL for the Parallel Interface (The parallel interface has a maximum output data-rate of 98 Mpixel/s) The maximum output of the parallel interface is 98 Mpixel/s (CLK_OP). This will limit the readout clock (CLK_PIX) to 49 Mpixel/s. The sensor will not use the FSERIAL, FSERIAL_CLK, or CLK_OP when configured to use the parallel interface. Table 25. PLL PARAMETERS FOR THE PARALLEL INTERFACE Symbol Parameter EXTCLK External Clock FVCO VCO Clock Min Max Unit 6 27 MHz 384 768 MHz CLK_PIX Readout Clock 49 Mpixel/s CLK_OP Output Clock 98 Mpixel/s Table 26. EXAMPLE PLL CONFIGURATION FOR THE PARALLEL INTERFACE Parameter Value Output FVCO 588 MHz (Max) vt_sys_clk_div 1 vt_pix_clk_div 6 CLK_PIX 49 Mpixel/s (= 588 MHz/12) CLK_OP 98 Mpixel/s (= 588 MHz/6) Output Pixel Rate 98 Mpixel/s Serial PLL Configuration FVCO EXTCLK (6-27 MHz) pre_pll_clk_div 2(1-64) pll_multiplier 58(32-384) FVCO vt_sys_clk_div 1(1, 2, 4, 6, 8, 10, 12, 14, 16) vt_pix_clk_div 6(4-16) CLK_PIX op_sys_clk_div Constant - 1 op_pix_clk_div 12(8, 10, 12) CLK_OP FSERIAL 1/2 FSERIAL_CLK Figure 20. PLL for the Serial Interface The sensor will use op_sys_clk_div and op_pix_clk_div to configure the output clock per lane (CLK_OP). The configuration will depend on the number of active lanes (1, 2, or 4) configured. To configure the sensor protocol and number of lanes, refer to "Serial Configuration". www.onsemi.com 23 AR0330CM Table 27. PLL PARAMETERS FOR THE SERIAL INTERFACE Symbol EXTCLK FVCO Parameter External Clock VCO Clock Min Max Unit 6 27 MHz 384 768 MHz CLK_PIX Readout Clock - 98 Mpixel/s CLK_OP Output Clock - 98 Mpixel/s FSERIAL Output Serial Data Rate Per Lane HiSPi MIPI 300 384 700 768 Output Serial Clock Speed Per Lane HiSPIi MIPI 150 192 350 384 FSERIAL_CLK The serial output should be configured so that it adheres to the following rules: * The maximum data-rate per lane (FSERIAL) is 768 Mbps/lane (MIPI) and 700 Mbps/lane (HiSPi). * The output pixel rate per lane (CLK_OP) should be configured so that the sensor output pixel rate matches the peak pixel rate (2 x CLK_PIX): Mbps MHz 4-lane: 4 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 196 Mpixel/s) 2-lane: 2 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 98 Mpixel/s) 1-lane: 1 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 76 Mpixel/s) Table 28. EXAMPLE PLL CONFIGURATIONS FOR THE SERIAL INTERFACE 4-lane 2-lane 1-lane Parameter 12-bit 10-bit 12-bit 10-bit 12-bit 10-bit 8-bit Unit MHz FVCO 588 490 588 490 768 768 768 vt_sys_clk_div 1 1 2 2 4 4 4 vt_pix_clk_div 6 5 6 5 6 5 4 op_sys_clk_div 1 1 1 1 1 1 1 op_pix_clk_div 12 10 12 10 12 10 8 FSERIAL 588 490 588 490 768 768 768 FSERIAL_CLK 294 245 294 245 384 384 384 MHz CLK_PIX 98 98 49 49 32 38.4 48 Mpixel/s CLK_OP 49 49 49 49 64 76.8 96 Mpixel/s Pixel Rate 196 196 98 98 64 76.8 96 Mpixel/s www.onsemi.com 24 MHz AR0330CM PIXEL OUTPUT INTERFACES Parallel Interface When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. Set reset_register[12] to disable the serializer while in parallel output mode. The parallel pixel data interface uses these output-only signals: * FV * LV * PIXCLK * DOUT[11:0] Output Enable Control When the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and High-Z under pin or register control, as shown in Table 29. OE_BAR pin is only available on the bare die version. The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. Table 30 shows the recommended settings. Table 29. OUTPUT ENABLE CONTROL OE_BAR Pin Drive Signals R0x301A-B[6] Description Disabled 0 Interface High-Z Disabled 1 Interface Driven 1 0 Interface High-Z X 1 Interface Driven 0 X Interface Driven Configuration of the Pixel Data Interface Fields in R0x301A are used to configure the operation of the pixel data interface. The supported combinations are shown in Table 30. Table 30. CONFIGURATION OF THE PIXEL DATA INTERFACE Serializer Disable R0x301A-B[12] Parallel Enable R0x301A-B[7] Standby End-of-Frame R0x301A-B[7] 0 0 1 Power up default. Serial pixel data interface and its clocks are enabled. Transitions to soft standby are synchronized to the end of frames on the serial pixel data interface. 1 1 0 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its clocks disabled to save power. Transitions to soft standby are synchronized to the end of the current row readout on the parallel pixel data interface. 1 1 1 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its clocks disabled to save power. Transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface. Description High Speed Serial Pixel Data Interface The HiSPi interface supports three protocols, Streaming S, Streaming SP, and Packetized SP. The streaming protocols conform to a standard video application where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. The Packetized SP protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. These protocols are further described in the High-Speed Serial Pixel (HiSPi) Interface Protocol Specification V1.00.00. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. Figure 21 shows the configuration between the HiSPi transmitter and the receiver. The High Speed Serial Pixel (HiSPi) interface uses four data and one clock low voltage differential signaling (LVDS) outputs. * SLVSC_P * SLVSC_N * SLVS0_P * SLVS0_N * SLVS1_P * SLVS1_N * SLVS2_P * SLVS2_N * SLVS3_P * SLVS3_N www.onsemi.com 25 AR0330CM A Camera Containing the HiSPi Transmitter Tx PHY0 A Host (DSP) Containing the HiSPi Receiver Dp0 Dp0 Dn0 Dn0 Dp1 Dp1 Dn1 Dn1 Dp2 Dp2 Dn2 Dn2 Dp3 Dp3 Dn3 Dn3 Cp0 Cp0 Cn0 Cn0 Rx PHY0 Figure 21. HiSPi Transmitter and Receiver Interface Block Diagram The PHY will serialize a 10-, 12-, 14- or 16-bit data word and transmit each bit of data centered on a rising edge of the clock, the second on the falling edge of clock. Figure 22 shows bit transmission. In this example, the word is transmitted in order of MSB to LSB. The receiver latches data at the rising and falling edge of the clock. HiSPi Physical Layer The HiSPi physical layer is partitioned into blocks of four data lanes and an associated clock lane. Any reference to the PHY in the remainder of this document is referring to this minimum building block. TxPost cp .... cn TxPre dp MSB .... LSB dn 1 UI Figure 22. Timing Diagram DLL Timing Adjustment The specification includes a DLL to compensate for differences in group delay for each data lane. The DLL is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. Once the DLL has gained phase lock, each lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in PCB design. If the DLL timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation. www.onsemi.com 26 del3[2:0] del2[2:0] delclock[2:0] del1[2:0] del0[2:0] AR0330CM Delay Delay Delay Delay Delay data_lane0 data_lane1 clock_lane0 data_lane2 data_lane3 Figure 23. Block Diagram of DLL Timing Adjustment 1 UI dataN (delN = 000) cp (delclock = 000) cp (delclock = 001) cp (delclock = 010) cp (delclock = 011) cp (delclock = 100) cp (delclock = 101) cp (delclock = 110) cp (delclock =111) increasing delclock_[2:0] increases clock delay Figure 24. Delaying the Clock_lane with Respect to the Data_lane cp (delclock = 000) dataN (delN = 000) dataN (delN = 001) dataN (delN = 010) dataN (delN = 011) dataN (delN = 100) dataN (delN = 101) dataN (delN = 110) dataN (delN = 111) tDLLSTEP increasing delN_[2:0] increases data delay 1 UI Figure 25. Delaying the Data_lane with Respect to the Clock_lane www.onsemi.com 27 AR0330CM Serial Configuration HiSPi Streaming Mode Protocol Layer The HiSPi protocol is described HiSPi Protocol V1.00.00 A. The serial format should be configured using R0x31AC. This register should be programmed to 0x0C0C when using the parallel interface. The R0x0112-3 register can be programmed to any of the following data format settings that are supported: * 0x0C0C - Sensor supports RAW12 uncompressed data format * 0x0C0A - The sensor supports RAW12 compressed format (10-bit words) using 12-10 bit A-LAW Compression. See "Compression" section * 0x0A0A - Sensor supports RAW10 uncompressed data format. This mode is supported by discarding all but the upper 10 bits of a pixel value * 0x0808 - Sensor supports RAW8 uncompressed data format. This mode is supported by discarding all but the upper 8 bits of a pixel value (MIPI only). MIPI Interface The serial pixel data interface uses the following output-only signal pairs: * DATA1_P * DATA1_N * DATA2_P * DATA2_N * DATA3_P * DATA3_N * DATA4_P * DATA4_N * CLK_P * CLK_N The serial_format register (R0x31AE) register controls which serial interface is in use when the serial interface is enabled (reset_register[12] = 0). The following serial formats are supported: * 0x0201 - Sensor supports single-lane MIPI operation * 0x0202 - Sensor supports dual-lane MIPI operation * 0x0204 - Sensor supports quad-lane MIPI operation * 0x0304 - Sensor supports quad-lane HiSPi operation The signal pairs use both single-ended and differential signaling, in accordance with the the MIPI Alliance Specification for D-PHY v1.00.00. The serial pixel data interface is enabled by default at power up and after reset. The DATA0_P, DATA0_N, DATA1_P, DATA1_N, CLK_P and CLK_N pads are set to the Ultra Low Power State (ULPS) if the serial disable bit is asserted (R0x301A-B[12] = 1) or when the sensor is in the hardware standby or soft standby system states. When the serial pixel data interface is used, the LINE_VALID, FRAME_VALID, PIXCLK and DOUT[11:0] signals (if present) can be left unconnected. The MIPI timing registers must be configured differently for 10-bit or 12-bit modes. These modes should be configured when the sensor streaming is disabled. See Table 31. Table 31. RECOMMENDED MIPI TIMING CONFIGURATION Configuration 10-bit, 490 Mbps/Lane 12-bit, 588 Mbps/Lane Clocking: Continuous Register Description 0x31B0 40 36 Frame Preamble 0x31B2 14 12 Line Preamble 0x31B4 0x2743 0x2643 MIPI Timing 0 0x31B6 0x114E 0x114E MIPI Timing 1 0x31B8 0x2049 0x2048 MIPI Timing 2 0x31BA 0x0186 0x0186 MIPI Timing 3 0x31BC 0x8005 0x8005 MIPI Timing 4 0x31BE 0x2003 0x2003 MIPI Config Status www.onsemi.com 28 AR0330CM PIXEL SENSITIVITY Row Integration (tINTEGRATION) Row Reset (Start of Integration) Row Readout Figure 26. Integration Control in ERS Readout A pixel's integration time is defined by the number of clock periods between a row's reset and read operation. Both the read followed by the reset operations occur within a row period (TROW) where the read and reset may be applied to different rows. The read and reset operations will be applied to the rows of the pixel array in a consecutive order. The integration time in an ERS frame is defined as: T INTEGRATION + T COARSE * T FINE (eq. 13) The coarse integration time is defined by the number of row periods (TROW) between a row's reset and the row read. The row period is the defined as the time between row read operations (see Sensor Frame Rate section). T COARSE + T ROW coarse_integration_time (eq. 14) TCOARSE = coarse_integration_time x TROW 8.33 ms = 654 Rows x 12.7 ms/Row Read Reset Horizontal Blanking Vertical Blanking Image TFRAME = frame_length_lines x TROW 16.6 ms = 1308 Rows x 12.7 ms/Row Time Vertical Blanking Figure 27. Example of 8.33 ms Integration in 16.6 ms Frame The fine integration is then defined by the number of pixel clock periods between the row reset and row read operation within TROW. This period fine_integration_time register. Start of Read Row N and Reset Row K is defined by the Start of Read Row N+1 and Reset Row K+1 Read Row N Reset Row K TFINE = fine_integration_time x (1 / CLK_PIX) TROW = line_length_pck x (1 / CLK_PIX) Figure 28. Row Read and Row Reset Showing Fine Integration T FINE + fine_integration_time clk_pix ON Semiconductor recommends that fine_integration_time in the AR0330 be left at zero. (eq. 15) The maximum allowed value for fine_integration_time is line_length_pck - 1204. www.onsemi.com 29 the AR0330CM Read Pointer TCOARSE = coarse_integration_time x TROW 20.7 ms = 1634 Rows x 12.7 ms/Row Horizontal Blanking Vertical Blanking Image TFRAME = frame_length_lines x TROW 16.6 ms = 1308 Rows x 12.7 ms/Row Vertical Blanking Extended Vertical Blanking Shutter Pointer Horizontal Blanking Time 4.1 ms Image Figure 29. The Row Integration Time is Greater than the Frame Readout Time The minimum frame-time is defined by the number of row periods per frame and the row period. The sensor frame-time will increase if the coarse_integration_time is set to a value equal to or greater than the frame_length_lines. The maximum integration time can be limited to the frame time by setting R0x30CE[5] to 1. www.onsemi.com 30 AR0330CM GAIN STAGES The analog gain stages of the AR0330 sensor are shown in Figure 30. The sensor analog gain stage consists of column amplifiers and a variable ADC reference. The sensor will apply the same analog gain to each color channel. Digital gain can be configured to separate levels for each color channel. ADC Reference Digital Gain with Dithering Coarse Gain: 1x, 2x, 4x, 8x Fine Gain: 1-2x: 16 Steps 2-4x: 8 Steps 4-8x: 4 Steps 1x to 15.992x (128 Steps per 6 dB) "xxxx.yyyy" xxxx(15-0) yyyyyyy(127/128 to 0) Figure 30. Gain Stages in AR0330 Sensor The level of analog gain applied is controlled by the coarse_gain and fine_gain registers. The analog readout can be configured differently for each gain level. The recommended gain tables are listed in Table 32. It is recommended that these registers are configured before streaming images. Table 32. RECOMMENDED SENSOR ANALOG GAIN TABLES COARSE_GAIN FINE_GAIN Total Gain COARSE_GAIN FINE_GAIN Total Gain R0x3060[5:4] Gain (x) R0x3060[3:0] Gain (x) (x) (dB) R0x3060[5:4] Gain (x) R0x3060[3:0] Gain (x) (x) (dB) 0 1 0 1.00 1.00 0.00 0 1x 15 1.88 1.88 5.49 0 1 1 1.03 1.03 0.26 1 2x 0 1.00 2.00 6.00 0 1 2 1.07 1.07 0.56 1 2x 2 1.07 2.13 6.58 0 1 3 1.10 1.10 0.86 1 2x 4 1.14 2.29 7.18 0 1 4 1.14 1.14 1.16 1 2x 6 1.23 2.46 7.82 0 1 5 1.19 1.19 1.46 1 2x 8 1.33 2.67 8.52 0 1 6 1.23 1.23 1.80 1 2x 10 1.45 2.91 9.28 0 1 7 1.28 1.28 2.14 1 2x 12 1.60 3.20 10.10 0 1 8 1.33 1.33 2.50 1 2x 14 1.78 3.56 11.02 0 1 9 1.39 1.39 2.87 2 4x 0 1.00 4.00 12.00 0 1 10 1.45 1.45 3.25 2 4x 4 1.14 4.57 13.20 0 1 11 1.52 1.52 3.66 2 4x 8 1.33 5.33 14.54 0 1 12 1.60 1.60 4.08 2 4x 12 1.60 6.40 16.12 0 1 13 1.68 1.68 4.53 3 8x 0 1.00 8.00 18.00 0 1 14 1.78 1.78 5.00 Each digital gain can be configured from a gain of 0 to 15.875. The digital gain supports 128 gain steps per 6 dB of gain. The format of each digital gain register is "xxxx.yyyyyyy" where "xxxx" refers an integer gain of 1 to 15 and "yyyyyyy" is a fractional gain ranging from 0/128 to 127/128. The sensor includes a digital dithering feature to reduce quantization resulting from using digital gain can be implemented by setting R0x30BA[5] to 1. The default value is 0. Refer to "Real-Time Context Switching" for the analog and digital gain registers in both context A and context B modes. www.onsemi.com 31 AR0330CM DATA PEDESTAL The data pedestal is a constant offset that is added to pixel values at the end of datapath. The default offset is 168 and is a 12-bit offset. This offset matches the maximum range used by the corrections in the digital readout path. The data pedestal value can be changed if the lock register bit (R0x301A[3]) is set to "0". This bit is set to "1" by default. * SENSOR READOUT Image Acquisition Modes The AR0330 supports two image acquisition modes: * Electronic Rolling Shutter (ERS) Mode: This is the normal mode of operation. When the AR0330 is streaming; it generates frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When the ERS is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. The integration (exposure) time is controlled by varying the time between row reset and row readout. For each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. When the integration time is changed (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the AR0330 switches cleanly from the old integration time to the new while only generating frames with uniform integration. See "Changes to Integration Time" in the AR0330 Register Reference. Global Reset Mode: This mode can be used to acquire a single image at the current resolution. In this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the AR0330 provides control signals to interface to that shutter. The benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particularly at low frame rates, because an ERS image effectively integrates each row of the pixel array at a different point in time. Window Control The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_addr_end, and y_addr_end registers. The x_addr_start equal to 6 is the minimum setting value. The y_addr_start equal to 6 is the minimum setting value. Please refer to Table 33 and Table 34 for details. Table 33. PIXEL COLUMN CONFIGURATION Column Address Number Type 0-5 6 Active Border columns 6-2309 2304 Active Active columns 2310-2315 6 Active Border columns Notes Table 34. PIXEL ROW CONFIGURATION Row Address Number Type 2-5 4 Active Not used in case of "edge effects" 6-1549 1544 Active Active rows 1550-1555 6 Active Not used in case of "edge effects" Notes Readout Modes Horizontal Mirror When the horizontal_mirror bit (R0x3040[14]) is set in the image_orientation register, the order of pixel readout within a row is reversed, so that readout starts from x_addr_end + 1and ends at x_addr_start. Figure 31 shows a sequence of 6 pixels being read out with R0x3040[14] = 0 and R0x3040[14] = 1. Changing R0x3040[14] causes the Bayer order of the output image to change; the new Bayer order is reflected in the value of the pixel_order register. www.onsemi.com 32 AR0330CM LINE_VALID Horizontal_mirror = 0 DOUT[11:0] G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0] Horizontal_mirror = 1 DOUT[11:0] G3[11:0] R2[11:0] G2[11:0] R1[11:0] G1[11:0] R0[11:0] Figure 31. Effect of Horizontal Mirror on Readout Order Vertical Flip When the vertical_flip bit (R0x3040[15]) is set in the image_orientation register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. Figure 32 shows a sequence of 6 rows being read out with R0x3040[15] = 0 and R0x3040[15] = 1. Changing this bit causes the Bayer order of the output image to change; the new Bayer order is reflected in the value of the pixel_order register. FRAME_VALID Vertical_flip = 0 DOUT[11:0] Row0[11:0] Row1[11:0] Row2[11:0] Row3[11:0] Row4[11:0] Row5[11:0] Vertical_flip = 1 DOUT[11:0] Row6[11:0] Row5[11:0] Row4[11:0] Row3[11:0] Row2[11:0] Row1[11:0] Figure 32. Effect of Vertical Flip on Readout Order www.onsemi.com 33 AR0330CM SUBSAMPLING The AR0330 supports subsampling. Subsampling allows the sensor to read out a smaller set of active pixels by either skipping or binning pixels within the readout window. The Isb working modes described in the data sheet that use subsampling are configured to use either 2x2 or 3x3 subsampling. Isb Isb Isb Isb Isb Figure 33. Horizontal Binning in the AR0330 Sensor Horizontal binning is achieved either in the pixel readout or the digital readout. The sensor will sample the combined 2x or 3x adjacent pixels within the same color plane. e- e- e- e- Figure 34. Vertical Row Binning in the AR0330 Sensor read together. As well, that the sensor will read a Gr-R row first followed by a B-Gb row. Vertical row binning is applied in the pixel readout. Row binning can be configured of 2x or 3x rows within the same color plane. ON Semiconductor recommends not to use 3x binning in AR0330 as it may introduce some image artifacts. Pixel skipping can be configured up to 2x and 3x in both the x-direction and y-direction. Skipping pixels in the x-direction will not reduce the row time. Skipping pixels in the y-direction will reduce the number of rows from the sensor effectively reducing the frame time. Skipping will introduce image artifacts from aliasing. The sensor increments its x and y address based on the x_odd_inc and y_odd_inc value. The value indicates the addresses that are skipped after each pair of pixels or rows has been read. The sensor will increment x and y addresses in multiples of 2. This indicates that a GreenR and Red pixel pair will be x subsampling factor + y subsampling factor + 1 ) x_odd_inc 2 1 ) y_odd_inc 2 (eq. 16) (eq. 17) A value of 1 is used for x_odd_inc and y_odd_inc when no pixel subsampling is indicated. In this case, the sensor is incrementing x and y addresses by 1 + 1 so that it reads consecutive pixel and row pairs. To implement a 2x skip in the x direction, the x_odd_inc is set to 3 so that the x address increment is 1 + 3, meaning that sensor will skip every other Gr-R pair. www.onsemi.com 34 AR0330CM Table 35. CONFIGURATION FOR HORIZONTAL SUBSAMPLING x_odd_inc Restrictions No Subsampling x_odd_inc = 1 Skip = (1+1) * 0.5 = 1x The horizontal FOV must be programmed to meet the following rule: Skip 2x x_odd_inc = 3 Skip = (1+3) * 0.5 = 2x Skip 3x x_odd_inc = 5 Skip = (1+5) * 0.5 = 3x Analog Bin 2x x_odd_inc = 3 Skip = (1+3) * 0.5 = 2x col_sf_bin_en = 1 Analog Bin 3x x_odd_inc = 5 Skip = (1+5) * 0.5 = 3x col_sf_bin_en = 1 Digital Bin 2x x_odd_inc = 3 Skip = (1+3) * 0.5 =2x col_bin =1 Digital Bin 3x x_odd_inc = 5 Skip = (1+5) * 0.5 = 3x col_bin = 1 x_addr_end * x_addr_start ) 1 + even number x_odd_inc 2 Table 36. CONFIGURATION FOR VERTICAL SUBSAMPLING No Subsampling Skip 2x y_odd_inc Restrictions y_odd_inc = 1 Skip = (1+1) * 0.5 = 1x row_bin = 0 The horizontal FOV must be programmed to meet the following rule: y_addr_end * y_addr_start ) 1 y_odd_inc y_odd_inc = 3 skip = (1+3) * 0.5 = 2x row_bin = 0 Skip 3x y_odd_inc = 5 skip = (1+5) * 0.5 = 3x row_bin = 0 Analog Bin 2x y_odd_inc = 3 skip = (1+3) * 0.5 = 2x row_bin = 1 Analog Bin 3x y_odd_inc = 5 skip = (1+5) * 0.5 = 3x row_bin = 1 2 www.onsemi.com 35 + even number AR0330CM SENSOR FRAME RATE The time required to read out an image frame (TFRAME) can be derived from the number of clocks required to output each image and the pixel clock. The frame-rate is the inverse of the frame period. fps + 1 T FRAME Row Period (TROW) The line_length_pck will determine the number of clock periods per row and the row period (TROW) when combined with the sensor readout clock. The line_length_pck includes both the active pixels and the horizontal blanking time per row. The sensor utilizes two readout paths, as seen in Figure 18, allowing the sensor to output two pixels during each pixel clock. The minimum line_length_pck is defined as the maximum of the following three equations: ADC Readout Limitation: (eq. 18) The number of clocks can be simplified further into the following parameters: * The number of clocks required for each sensor row (line_length_pck) This parameter also determines the sensor row period when referenced to the sensor readout clock. (TROW = line_length_pck x 1/CLK_PIX) * The number of row periods per frame (frame_length_lines) * An extra delay between frames used to achieve a specific output frame period (extra_delay) 1 CLK_PIX or Options to modify this limit, as mentioned in the "Sequencer" section, can be found in the AR0330 Developer Guide. Digital Readout Limitation: 1 3 (eq. 19) (frame_length_lines line_length_pck ) extra_delay) Vertical Blanking (VB) Active Rows Active Columns Horizontal Blanking (HB) (eq. 20) 1116 (ADC_HIGH_SPEED) + 1(0) * x_addr_start x_addr_end (x_odd_inc ) 1) 0.5 (eq. 21) Output Interface Limitations: 1 2 frame_length_lines = Active Rows + VB T FRAME + 1024 (ADC_HIGH_SPEED) + 0 * x_addr_start x_addr_end ) 96 (x_odd_inc ) 1) 0.5 (eq. 22) Row Periods per Frame The frame_length_lines determines the number of row periods (TROW) per frame. This includes both the active and blanking rows. The minimum_vertical_blanking value is defined by the number of OB rows read per frame, two embedded data rows, and two blank rows. Minimum frame_length_lines + extra_delay y_addr_end * y_addr_start y_odd_inc)1 2 ) (eq. 23) ) minimum_vertical_blanking line_length_pck = Active Columns + HB The sensor is configured to output frame information in two embedded data rows by setting R0x3064[8] to 1 (default). If R0x3064[8] is set to 0, the sensor will instead output two blank rows. The data configured in the two embedded rows is defined in MIPI CSI-2 Specification V1.00. Figure 35. Frame Period Measured in Clocks Table 37. MINIMUM VERTICAL BLANKING CONFIGURATION R0x3180[0x00F0] OB Rows minimum_vertical_blanking 0x8 (Default) 8 OB Rows 8 OB + 4 = 12 0x4 4 OB Rows 4 OB + 4 = 8 0x2 2 OB Rows 2 OB + 4 = 6 The locations of the OB rows, embedded rows, and blank rows within the frame readout are identified in Figure 36. www.onsemi.com 36 AR0330CM SLAVE MODE The slave mode feature of the AR0330 supports triggering the start of a frame readout from a VD signal that is supplied from an external ASIC. The slave mode signal allows for precise control of frame rate and register change updates. VD Signal Start of frame N Time Frame Valid The VD signal is input to the trigger pin. Both the GPI_EN (R0x301A[8]) and the SLAVE_MODE (R0x30CE[4]) bits must be set to "1" to enable the slave mode. OB Rows (2, 4, or 8 rows) Embedded Data Row (2 rows) Active Data Rows Blank Rows (2 rows) Extra Vertical Blanking (frame_length_lines - min_frame_length_lines) Extra Delay (clocks) The period between the rising edge of the VD signal and the slave mode ready state is TFRAME = 16 clocks. Slave Mode Active State End of frame N Start of frame N + 1 Figure 36. Slave Mode Active State and Vertical Blanking slave mode will remain inactive for the period of one frame time minus 16 clock periods (TFRAME - (16 / CLK_PIX)). After this period, the slave mode will re-enter the active state and will respond to the VD signal. If the slave mode is disabled, the new frame will begin after the extra delay period is finished. The slave mode will react to the rising edge of the input VD signal if it is in an active state. When the VD signal is received, the sensor will begin the frame readout and the www.onsemi.com 37 AR0330CM Frame Valid Rising Edge Rising Edge Rising Edge VD Signal Slave Mode Trigger Inactive Active Inactive Active Row reset and read operations begin after the rising edge of the VD signal. Rising edge of VD signal triggers the start of the frame readout. Row Reset (start of integration) Row Readout Programmed Integration Row 0 Integration due to Slave Mode Delay Row N The Slave Mode will become "Active" after the last row period. Both the row reset and row read operations will wait until the rising edge of the VD signal. Figure 37. Slave Mode Example with Equal Integration and Frame Readout Periods (The integration of the last row is therefore started before the end of the programmed integration for the first row) 2. If the sensor integration time is configured to be less than the frame period, then the sensor will not have reset all of the sensor rows before it begins waiting for the input VD signal. This error can be minimized by configuring the frame period to be as close as possible to the desired frame rate (period between VD signals). The row shutter and read operations will stop when the slave mode becomes active and is waiting for the VD signal. The following should be considered when configuring the sensor to use the slave mode: 1. The frame period (TFRAME) should be configured to be less than the period of the input VD signal. The sensor will disregard the input VD signal if it appears before the frame readout is finished. Frame Valid Rising Edge Rising Edge Rising Edge VD Signal Slave Mode Trigger Inactive 8.33 ms 8.33 ms Row0 Active Inactive Active Row reset and read operations begin after the rising edge of the Vd signal. Row Reset (start of integration) Row Readout Programmed Integration Integration due to Slave Mode Delay Row N Reset operation is held during slave mode "Active" state. Figure 38. Slave Mode Example where the Integration Period is Half of the Frame Readout Period (The sensor read pointer will have paused at row 0 while the shutter pointer pauses at row N/2. The extra integration caused by the slave mode delay will only be seen by rows 0 to N/2. The example below is for a frame readout period of 16.6ms while the integration time is configured to 8.33 ms) www.onsemi.com 38 AR0330CM To avoid uneven exposure, programmed integration time cannot be larger than VD period. To increase integration time more than current VD period, the AR0330 must be configured to work at a lower frame rate and read out image with new VD to match the new timing. The period between slave mode pulses must also be greater than the frame period. If the rising edge of the VD pulse arrives while the slave mode is inactive, the VD pulse will be ignored and will wait until the next VD pulse has arrived. When the slave mode becomes active, the sensor will pause both row read and row reset operations. NOTE: The row integration period is defined as the period from row reset to row read. When the AR0330 is working in slave mode, the external trigger signal VD must have accurately controlled timing to avoid uneven exposure in the output image. The VD timing control should make the slave mode "wait period" less than 32 pixel clocks. www.onsemi.com 39 AR0330CM FRAME READOUT The sensor readout begins with vertical blanking rows followed by the active rows. The frame readout period can be defined by the number of row periods within a frame (frame_length_lines) and the row period (line_length_pck). 1/60s 1/60s Row Reset The sensor will read the first vertical blanking row at the beginning of the frame period and the last active row at the end of the row period. Row Read Row Reset Row Read Vertical Blanking Active Rows Time Row Reset Row Read Row Reset Row Read End of Frame Readout VB (12 Rows) Serial SYNC Codes Start of Vertical Blanking Start of Frame Start of Active Row End of Line HB (192 Pixels/Column) 2304 x 1296 VB (12 Rows) End of Frame Readout HB (192 Pixels/Column) 2304 x 1296 End of Frame Frame Valid Line Valid Figure 39. Example of the Sensor Output of a 2304 y 1296 Frame at 60 fps (The frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. The SYNC codes represented in this diagram represent the HiSPi Streaming SP protocol) Frame 39 aligns the frame integration and readout operation to the sensor output. It also shows the sensor output using the HiSPi Streaming SP protocol. Different sensor protocols will list different SYNC codes. Table 38. SERIAL SYNC CODES INCLUDED WITH EACH PROTOCOL INCLUDED WITH THE AR0330 SENSOR Interface/Protocol Parallel Start of Vertical Blanking Row (SOV) Start of Frame (SOF) Start of Active Line (SOA) End of Line (EOL) End of Frame (EOF) Parallel Interface Uses FRAME VALID (FV) and LINE VALID (LV) Outputs to Denote Start and End of Line and Frame. HiSPi Streaming S Yes Send SOV Yes No SYNC Code No SYNC Code HiSPi Streaming SP Yes Yes Yes Yes Yes HiSPi Packetized SP No SYNC Code Yes Yes Yes Yes MIPI No SYNC Code Yes Yes Yes Yes 2304 x 1296 frame rate from 60 fps to 30 fps without increasing the delay between the readout of the first and last active row. Figure 40 illustrates how the sensor active readout time can be minimized while reducing the frame rate. 1308 VB rows were added to the output frame to reduce the www.onsemi.com 40 AR0330CM 1/30s 1/30s Row Reset Row Read Row Reset Row Read Vertical Blanking Active Rows Row Reset Time Row Read Row Reset Row Read End of Frame Readout End of Frame Readout Serial SYNC Codes Start of Vertical Blanking Start of Frame Start of Active Row End of Line VB (1320 Rows) 2304 x 1296 HB (192 Pixels) End of Frame VB (1320 Rows) 2304 x 1296 HB (192 Pixels) Frame Valid Line Valid Figure 40. Example of the Sensor Output of a 2304 y 1296 Frame at 30 fps (The frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. The SYNC codes represented in this diagram represent the HiSPi Streaming SP protocol) www.onsemi.com 41 AR0330CM CHANGING SENSOR MODES Register Changes bit in R0x30B0[13]. When the context switch is configured to context A the sensor will reference the "Context A Registers". If the context switch is changed from A to B during the readout of frame n, the sensor will then reference the context B coarse_integration_time registers in frame n+1 and all other context B registers at the beginning of reading frame n+2. The sensor will show the same behavior when changing from context B to context A. All register writes are delayed by 1x frame. A register that is written to during the readout of frame n will not be updated to the new value until the readout of frame n+2. This includes writes to the sensor gain and integration registers. Real-Time Context Switching In the AR0330, the user may switch between two full register sets A and B by writing to a context switch change Table 39. LIST OF CONFIGURABLE REGISTERS FOR CONTEXT A AND CONTEXT B Context A Register Description Coarse_integration_time Context B Address Register Description Address 0x3012 Coarse_integration_time_CB 0x3016 Fine_integration_time 0x3014 Fine_integration_time_CB 0x3018 Line_length_pck 0x300C Line_length_pck_CB 0x303E Frame_length_lines 0x300A Frame_length_lines_CB 0x30AA COL_SF_BIN_EN 0x3040[9] COL_SF_BIN_EN_CB 0x3040[8] ROW_BIN 0x3040[12] ROW_BIN_CB 0x3040[10] COL_BIN 0x3040[13] COL_BIN_CB 0x3040[11] FINE_GAIN 0x3060[3:0] FINE_GAIN_CB COARSE_GAIN 0x3060[5:4] COARSE_GAIN_CB 0x3060[11:8] 0x3060[13:12] x_addr_start 0x3004 x_addr_start_CB 0x308A y_addr_start 0x3002 y_addr_start_CB 0x308C x_addr_end 0x3008 x_addr_end_CB 0x308E y_addr_end 0x3006 y_addr_end_CB 0x3090 Y_odd_inc 0x30A6 Y_odd_inc_CB 0x30A8 0x30A2 X_odd_inc_CB X_odd_inc ADC_HIGH_SPEED 0x30BA[6] ADC_HIGH_SPEED_CB 0x30AE 0x30BA[7] GREEN1_GAIN 0x3056 GREEN1_GAIN_CB 0x30BC BLUE_GAIN 0x3058 BLUE_GAIN_CB 0x30BE RED_GAIN 0x305A RED_GAIN_CB 0x30C0 GREEN2_GAIN 0x305C GREEN2_GAIN_CB 0x30C2 GLOBAL_GAIN 0x305E GLOBAL_GAIN_CB 0x30C4 NOTE: ON Semiconductor recommends leaving fine_integration_time at 0. www.onsemi.com 42 AR0330CM 1/60s 1/60s 1/54s Vertical Blanking Active Rows Start of Frame Start of Active Row End of Line End of Frame HB (192 Pixels/Column) 2304 x 1296 Frame N VB (12 Rows) Serial SYNC Codes Start of Vertical Blanking VB (12 Rows) End of Frame Readout HB (192 Pixels/Column) 2304 x 1296 Frame N+1 Integration time of context B mode implemented during readout of frame N+1 Write context A to B during readout of Frame N End of Frame Readout VB (12 Rows) Time HB (192 Pixels/Column) 2048 x 1536 Frame N+2 Context B mode is implemented in frame N+2 Figure 41. Example of Changing the Sensor from Context A to Context B www.onsemi.com 43 End of Frame Readout AR0330CM COMPRESSION The sensor can optionally compress 12-bit data to 10-bit using A-law compression. The compression is applied after the data pedestal has been added to the data. See Figure 1. The A-law compression is disabled by default and can be enabled by setting R0x31D0 from "0" to "1". Table 40. A-LAW COMPRESSION TABLE FOR 12-10 BITS Input Values Compressed Codeword Input Range 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 0 to 127 0 0 0 0 0 a b c d e f g 0 0 0 a b c d e f g 128 to 255 0 0 0 0 1 a b c d e f g 0 0 1 a b c d e f g 256 to 511 0 0 0 1 a b c d e f g X 0 1 0 a b c d e f g 512 to 1023 0 0 1 a b c d e f g X X 0 1 1 a b c d e f g 1024 to 2047 0 1 a b c d e f g h X X 1 0 a b c d e f g h 2048 to 4095 1 a b c d e f g h X X X 1 1 a b c d e f g h TEST PATTERNS The AR0330 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. With one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns are selected by Test_Pattern_Mode register (R0x3070). Only one of the test patterns can be enabled at a given point in time by setting the Test_Pattern_Mode register according to Table 41. When test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in Test_Pattern_Green (R0x3074 and R0x3078) for green pixels, Test_Pattern_Blue (R0x3076) for blue pixels, and Test_Pattern_Red (R0x3072) for red pixels. Table 41. TEST PATTERN MODES Test_Pattern_Mode Test Pattern Output 0 No Test Pattern (Normal Operation) 1 Solid Color 2 100% Vertical Color Bars 3 Fade-to-Gray Vertical Color Bars 256 Walking 1s Test Pattern (12-bit) Solid Color When the color field mode is selected, the value for each pixel is determined by its color. Green pixels will receive the value in Test_Pattern_Green, red pixels will receive the value in Test_Pattern_Red, and blue pixels will receive the value in Test_Pattern_Blue. Vertical Color Bars When the vertical color bars mode is selected, a typical color bar pattern will be sent through the digital pipeline. Walking 1s When the walking 1s mode is selected, a walking 1s pattern will be sent through the digital pipeline. The first value in each row is 1. www.onsemi.com 44 AR0330CM TWO-WIRE SERIAL REGISTER INTERFACE The two-wire serial interface bus enables read/write access to control and status registers within the AR0330. This interface is designed to be compatible with the electrical characteristics and transfer protocols of the I2C specification. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5 kW resistor. Either the slave or master device can drive SDATA LOW - the interface protocol determines which device is allowed to drive SDATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the AR0330 uses SCLK as an input only and therefore never drives it LOW. [0] indicates a WRITE, and a "1" indicates a READ. The default slave addresses used by the AR0330 sensor are 0x20 (write address) and 0x21 (read address). Alternate slave addresses of 0x30 (WRITE address) and 0x31 (READ address) can be selected by asserting the SADDR signal (tie HIGH). Alternate slave addresses can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the SCLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Protocol No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA LOW during the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no-) acknowledge bit 4. a message byte 5. a stop condition Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a "0" indicates a write and a "1" indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave's internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit. The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a "repeated start" or "restart" condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for both the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A "0" in bit www.onsemi.com 45 AR0330CM Single READ From Random Location This sequence (Figure 42) starts with a dummy WRITE to the 16-bit address that is to be used for the READ. The master terminates the WRITE by generating a restart condition. The master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. Figure 42 shows how the internal register address maintained by the AR0330 is loaded and incremented as the sequence proceeds. Previous Reg Address, N S Slave Address 0 A S = Start Condition P = Stop Condition Sr = Restart Condition A = Acknowledge A = No-acknowledge Reg Address[15:8] Reg Address, M Reg Address[7:0] A A Sr 1 A Slave Address M+1 A Read Data P Slave to Master Master to Slave Figure 42. Single READ from Random Location Single READ From Current Location The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent READ sequences. This sequence (Figure 43) performs a read using the current value of the AR0330 internal register address. Previous Reg Address, N S Slave Address 1 A Reg Address, N+1 A P Read Data S Slave Address 1 A N+2 Read Data A P Figure 43. Single READ from Current Location Sequential READ, Start From Random Location This sequence (Figure 44) starts in the same way as the single READ from random location (Figure 42). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until "L" bytes have been read. Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Read Data A Reg Address[7:0] M+2 A Read Data Reg Address, M M+3 A Sr Slave Address M+L-2 A Read Data 1 A M+L-1 A Read Data Figure 44. Sequential READ, Start from Random Location www.onsemi.com 46 M+1 Read Data M+L A P A AR0330CM Sequential READ, Start From Current Location This sequence (Figure 45) starts in the same way as the single READ from current location (Figure 43). Instead of generating a no-acknowledge bit after the first byte of data Previous Reg Address, N S Slave Address 1 A has been transferred, the master generates an acknowledge bit and continues to perform byte READs until "L" bytes have been read. N+1 Read Data A N+2 Read Data A N+L-1 Read Data A N+L Read Data A P Figure 45. Sequential READ, Start from Current Location Single WRITE to Random Location then LOW bytes of the register address that is to be written. The master follows this with the byte of write data. The WRITE is terminated by the master generating a stop condition. This sequence (Figure 46) begins with the master generating a start condition. The slave address/data direction byte signals a WRITE and is followed by the HIGH Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] Reg Address, M A A Reg Address[7:0] M+1 A A Write Data P Figure 46. Single WRITE to Random Location Sequential WRITE, Start at Random Location This sequence (Figure 47) starts in the same way as the single WRITE to random location (Figure 46). Instead of generating a stop condition after the first byte of data has been transferred, the master continues to perform byte WRITEs until "L" bytes have been written. The WRITE is terminated by the master generating a stop condition. Previous Reg Address, N S Slave Address 0 A M+1 Write Data Reg Address[15:8] A M+2 A Write Data Reg Address, M Reg Address[7:0] M+3 A Write Data M+L-2 A Write Data 47 A M+L-1 A Figure 47. Sequential WRITE, Start at Random Location www.onsemi.com M+1 Write Data M+L A A P AR0330CM SPECTRAL CHARACTERISTICS 70 Red Green Blue 60 Quantum Efficiency (%) 50 40 30 20 10 0 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 Wavelength (nm) Figure 48. Bare Die Quantum Efficiency CRA vs. Image Height Plot 0 0 0 5 0.152 0.80 19 10 0.305 1.66 18 15 0.457 2.54 20 0.609 3.42 15 25 0.761 4.28 14 30 0.914 5.11 13 35 1.066 5.94 11 40 1.218 6.75 10 45 1.371 7.57 9 50 1.523 8.37 7 55 1.675 9.16 6 60 1.828 9.90 5 65 1.980 10.58 70 2.132 11.15 2 75 2.284 11.57 1 80 2.437 11.80 0 85 2.589 11.78 90 2.741 11.48 95 2.894 10.88 100 3.046 9.96 17 16 Chief Ray Angle (Degrees) CRA (deg) (mm) 20 AR0330 CRA Characteristic 12 8 4 3 0 10 20 30 40 50 60 70 80 90 100 Image Height (%) NOTE: Image Height (%) 110 The CRA listed in the advanced data sheet described the 2048 x 1536 field of view (2.908 mm image height). This information was sufficient for configuring the sensor to read both the 4:3 (2048 x 1536) and 16:9 (2304 x 1296) aspect ratios. The CRA information listed in the data sheet has now been updated to represent the entire pixel array (2304 x 1536). Figure 49. Chief Ray Angle (CRA) - 125 www.onsemi.com 48 AR0330CM CRA vs. Image Height Plot 0 0 0 5 0.152 1.10 28 10 0.305 2.20 26 15 0.457 3.30 20 0.609 4.40 25 0.761 5.50 30 0.914 6.60 35 1.066 7.70 40 1.218 8.80 45 1.371 9.90 50 1.523 11.00 55 1.675 12.10 60 1.828 13.20 65 1.980 14.30 70 2.132 15.40 75 2.284 16.50 80 2.437 17.60 85 2.589 18.70 90 2.741 19.80 95 2.894 20.90 100 3.046 22.00 24 Chief Ray Angle (Degrees) CRA (deg) (mm) 30 AR0330 CRA Characteristic 22 20 18 16 14 12 10 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 Image Height (%) NOTE: Image Height (%) The CRA listed in the advanced data sheet described the 2048 x 1536 field of view (2.908 mm image height). This information was sufficient for configuring the sensor to read both the 4:3 (2048 x 1536) and 16:9 (2304 x 1296) aspect ratios. The CRA information listed in the data sheet has now been updated to represent the entire pixel array (2304 x 1536). Figure 50. Chief Ray Angle (CRA) - 215 CRA vs. Image Height Plot 0 0 0 5 0.152 2.24 28 10 0.305 4.50 26 15 0.457 6.75 20 0.609 8.95 25 0.761 11.11 30 0.914 13.19 35 1.066 15.20 40 1.218 17.10 45 1.371 18.88 50 1.523 20.50 55 1.675 21.95 60 1.828 23.18 65 1.980 24.17 70 2.132 24.89 75 2.284 25.35 80 2.437 25.54 85 2.589 25.51 90 2.741 25.33 95 2.894 25.11 100 3.046 25.01 24 Chief Ray Angle (Degrees) CRA (deg) (mm) 30 AR0330 CRA Characteristic 22 20 18 16 14 12 10 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 Image Height (%) NOTE: Image Height (%) 110 The CRA listed in the advanced data sheet described the 2048 x 1536 field of view (2.908 mm image height). This information was sufficient for configuring the sensor to read both the 4:3 (2048 x 1536) and 16:9 (2304 x 1296) aspect ratios. The CRA information listed in the data sheet has now been updated to represent the entire pixel array (2304 x 1536). Figure 51. Chief Ray Angle (CRA) - 255 www.onsemi.com 49 AR0330CM Read the Sensor CRA Follow the steps below to obtain the CRA value of the Image Sensor: 1. Set the register bit field R0x301A[5] = 1. 2. Read the register bit fields R0x31FA[11:9]. 3. Determine the CRA value according to Table 42. Table 42. CRA VALUE Binary Value of R0x31FA[11:9] CRA Value 000 0 001 21 010 25 011 12 www.onsemi.com 50 AR0330CM PACKAGES The AR0330 comes in two packages: * CLCC Package * CSP HiSPi/MIPI Package PACKAGE DIMENSIONS CLCC48 CASE 848AU ISSUE O www.onsemi.com 51 AR0330CM PACKAGE DIMENSIONS ODCSP64 CASE 570BH ISSUE O 2 3 4 A 5 6 7 S1 8 8 J1 7 65 4 3 21 S2 1 First clear pixel(-1987.5,2776.5) A J2 A B B C C Package Center=Die Center(0,0) D B D Package Center=Die Center(0,0) Optical center(-290,230) E Optical center(290,230) F E E E F G G Last clear pixel(1407.5,-2316.5) H H Notch Bottom View (BGA side) Unit:um Package Size:6278.15*6648.15 Ball diameter:250 Ball pitch:650 C C3 C2 C1 C4 Top View (Image side) Cross-section View (E-E) Table 43. CSP (MIPI/HISPI) PACKAGE DIMENSIONS Nom Parameter Min Max Nom Millimeters Symbol Min Max Inches Package Body Dimension X A 6.278 6.253 6.303 0.247 0.246 0.248 Package Body Dimension Y B 6.648 6.623 6.673 0.262 0.261 0.263 Package Height C 0.700 0.645 0.745 0.028 0.025 0.029 Cavity Height (Glass to Pixel Distance) C4 0.041 0.037 0.045 0.002 0.001 0.002 Glass Thickness C3 0.400 0.390 0.410 0.016 0.015 0.016 Package Body Thickness C2 0.570 0.535 0.605 0.022 0.021 0.024 Ball Height C1 0.130 0.100 0.160 0.005 0.004 0.006 Ball Diameter D 0.250 0.220 0.280 0.010 0.009 0.011 Total Ball Count N 64 Ball Count X Axis N1 8 Ball Count Y Axis N2 8 UBM U 0.280 0.270 0.290 0.011 0.011 0.011 Pins Pitch X Axis J1 0.650 0.026 Pins Pitch Y Axis J2 0.650 0.026 BGA Ball Center to Package Center Offset in X-direction X 0.000 -0.025 0.025 0.000 -0.001 0.001 BGA Ball Center to Package Center Offset in Y-direction Y 0.000 -0.025 0.025 0.000 -0.001 0.001 BGA Ball Center to Chip Center Offset in X-direction X1 0.000 -0.014 0.014 0.000 -0.001 0.001 BGA Ball Center to Chip Center Offset in Y-direction Y1 0.000 -0.014 0.014 0.000 -0.001 0.001 Edge to Ball Center Distance along X S1 0.864 0.834 0.894 0.034 0.033 0.035 Edge to Ball Center Distance along Y S2 1.049 1.019 1.079 0.041 0.040 0.042 www.onsemi.com 52 AR0330CM PACKAGE ORIENTATION IN CAMERA DESIGN In a camera design, the package should be placed in a PCB so that the first clear pixel is located at the bottom left of the package (look at the package). This orientation will ensure that the image captured using a lens will be oriented correctly. Lens The package is oriented so that the first clear pixel is located in bottom left. Figure 52. Image Orientation with Relation to Camera Lens The package pin locations after the sensor has been oriented correctly can be shown below. CSP Package CLCC Package 1------------8 (0,0) (2304,1536) (2304,1536) Pixel Array First Clear Pixel First Clear Pixel (0,0) A ---------------H 48 1 Pin Orientation Figure 53. First Clear Pixel and Pin Location (Looking Down on Cover Glass) A-Pix is a trademark trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. All other brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. 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