D1912HKPC 20121130-S00003/71112HK 20120628-S00001/62012HKPC No.A2048-1/11
http://onsemi.com
Semiconductor Components Industries, LLC, 2013
August, 2013 Ver1.0.1
LC717A00AR
Overview
The LC717A00AR is a high-performance, low-cost capacitance-digital-converter LSI for electrostatic capacitive
touch sensor, especially focused on usability. It has 8 channels capacitance-sensor input. The built-in logic circuit can
detect the state (ON/OFF) of each input and output the result. This makes it ideal for various switch applications.
The calibration function is automatically performed by the built-in logic circuit during power activation or whenever
there are environmental changes. In addition, since initial settings of parameters, such as gain, are configured,
LC717A00AR can operate as stand-alone when the recommended switch pattern is applied.
Also, since LC717A00AR has a serial interface compatible with I2C and SPI bus, parameters can be adjusted using
external devices whenever necessary. Moreover, outputs of the 8-input capacitance data can be detected and measured
as 8-bit data.
Features
• Detection system: Differential capacitance detection (Mutual capacitance type)
• Input capacitance resolution: Can detect capacitance changes in the femto Farad order
• Measurement interval (8 differential inputs): 18ms (Typ) (at initial configuration),
3ms (Typ) (at minimum interval configuration)
• External components for measurement: Not required
• Current consumption: 320μA (Typ) (VDD = 2.8V), 740μA (Typ) (VDD = 5.5V)
• Supply voltage: 2.6V to 5.5V
• Detection operations: Switch
• Packages: VCT28
• Interface: I2C * compatible bus or SPI selectable.
Ordering number : ENA2048B
CMOS LSI
Capacitance-Digital-Converter LSI
for Electrostatic Capacitive Touch
Sensors
* I2C Bus is a trademark of Philips Corporation.
LC717A00AR
No.A2048-2/11
Specifications
Absolute Maximum Ratings at Ta = +25°C
Parameter Symbol Ratings (VSS = 0V) Unit Remarks
Supply voltage VDD -0.3 to +6.5 V
Input voltage VIN -0.3 to VDD+0.3 V *1
Output voltage VOUT -0.3 to VDD+0.3 V *2
Power dissipation Pd max 160 mW Ta = +105°C,
Mounted on a substrate *3
Peak output current IOP ±8 mA per terminal,
50% Duty ratio *2
Total output current IOA ±40 mA Output total value of LSI,
25% Duty ratio
Storage temperature Tstg -55 to +125 °C
*1) Apply to Cin0 to 7, Cref, nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN
*2) Apply to Cdrv, Pout0 to 7, SDA, SO, ERROR, INTOUT
*3) 4-layer glass epoxy board (40×50×0.8t mm)
Recommended Operating Conditions
Parameter Symbol Conditions min typ max Unit Remarks
Operating supply voltage VDD 2.6 5.5 V
Supply ripple + noise Vpp ±20 mV *1
Operating temperature Topr -40 25 105 °C
*1) Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended.
In this case, the small-valued capacitor should be at least 0.1μF, and is mounted near the LSI.
Electrical Characteristics at VSS = 0V, VDD = 2.6 to 5.5V, Ta = -40 to +105°C
* Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143kHz.
* Not tested at low temperature before shipment.
Parameter Symbol Conditions min typ max Unit Remarks
Capacitance detection resolution N 8 bit
Output nois e RM S NRMS minimum gain setting ±1.0 LSB *1 *3
Input offset capacitance
adjustment range CoffRANGE ±8.0 pF *1 *3
Input offset capacitance
adjustment resolution CoffRESO 8 bit
Cin offset drift CinDRIFT minimum gain setting ±8 LSB *1
Cin detection sensitivity CinSENSE minimum gain setting 0.04 0.12 LSB/fF *2
Cin pin leak current ICin Cin = Hi-Z ±25 ±500 nA
Cin allowable parasitic input
capacitance CinSUB Cin against VSS 30 pF *1 *3
Cdrv drive frequency fCDRV 100 143 186 kHz
Cdrv pin leak current ICDRV Cdrv = Hi-Z ±25 ±500 nA
nRST minimum pulse width tNRST 1 μs *1
Power-on reset time tPOR 20 ms *1
Power-on reset operation
condition: Hold time tPOROP 10 ms *1
Power-on reset operation
condition: Input voltage VPOROP 0.1 V *1
Power-on reset operation
condition: Power supply rise rate tVDD 0V to VDD 1 V/ms *1
VIH High input 0.8VDD Pin input voltage
VIL Low input 0.2VDD V *1 *4
VOH High output
(IOH = +3mA ) 0.8VDD
Pin output voltage
VOL Low output
(IOL = -3mA) 0.2VDD V *5
Continued to the next page.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
C onditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
LC717A00AR
No.A2048-3/11
Continued from the previous page.
Parameter Symbol Conditions min typ max Unit Remarks
SDA pin leak current VOL I2C SDA Low output
(IOL = -3mA) 0.4 V
Pin leak current ILEAK ±1 μA *6
When stand-alone
configuration and
non-touch
VDD = 2.8V
320 390
IDD
when stand-alone
configuration and
non-touch
VDD = 5.5V
740 900
μA *1 *3
Current consumption
ISTBY During Sleep process 1 μA *3
*1) Design-guaranteed values (not tested before shipment)
*2) Measurements conducted using the test mode in the LSI
*3) Ta = +25°C
*4) Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN
*5) Apply to Cdrv, Pout0 to 7, SO, ERROR, INTOUT
*6) Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN
LC717A00AR
No.A2048-4/11
I2C Compatible Bus Timing Characteristics at VSS = 0, VDD = 2.6 to 5.5V, Ta = -40 to +105°C
*Not tested at low temperature before shipment
Parameter Symbol Pin Name Conditions min typ max Unit Remarks
SCL clock frequency fSCL SCL 400 kHz
START condition hold time tHD;STA SCL
SDA 0.6 μs
SCL clock low period tLOW SCL 1.3 μs
SCL clock high period tHIGH SCL 0.6 μs
Repeated START condition
setup time tSU;STA SCL
SDA 0.6 μs *1
Data hold time tHD;DAT SCL
SDA 00.9 μs
Data setup time tSU;DAT SCL
SDA 100 μs *1
SDA, SCL rise/fall time tr / tf SCL
SDA 300 μs *1
STOP condition setup time tSU;STO SCL
SDA 0.6 μs
STOP-to-START bus release
time tBUF SCL
SDA 1.3 μs *1
*1) Design-guaranteed values (not tested before shipment)
SPI Bus Timing Characteristics at VSS = 0, VDD = 2.6 to 5.5V, Ta = -40 to +105°C
*Not tested at low temperature before shipment
Parameter Symbol Pin Name Conditions min typ max Unit Remarks
SCK clock frequency fSCK SCK 5 MHz
SCK clock Low time tLOW SCK 90 ns *1
SCK clock High time tHIGH SCK 90 ns *1
Input signal rise/fall time tr / tf nCS
SCK
SI
300 ns *1
nCS setup time tSU;NCS nCS
SCK 90 ns *1
SCK clock setup time tSU;SCK nCS
SCK 90 ns *1
Data setup time tSU;SI SCK
SI 20 ns *1
Data hold time tHD;SI SCK
SI 30 ns *1
nCS hold time tHD;NCS nCS
SCK 90 ns *1
SCK clock hold time tHD;SCK nCS
SCK 90 ns *1
nCS standby pulse width tCPH nCS 90 ns *1
Output high impedance time
from nCS tCHZ nCS
SO 80 ns *1
Output data determination time tv SCK
SO 80 ns *1
Output data hold time tHD;SO SCK
SO 0 ns *1
Output low impedance time
from SCK clock tCLZ SCK
SO 0 ns *1
*1) Design-guaranteed values (not tested before shipment)
LC717A00AR
No.A2048-5/11
Power-on Reset (POR)
When power is turned on, power-on reset is enabled inside the LSI and its state is released after a certain power-on reset
time, tPOR. Power-on reset operation condition: Power supply rise rate tVDD must be at least 1V/ms.
Since INTOUT pin changes from “High” to “Low” at the same time as the released of power-on reset state, it is
possible to verify the tPOR externally.
During power-on reset state, Cin, Cref and Pout are unknown.
fig.1
I2C Compatible Bus Data Timing
fig.2
I2C Compatible Bus Communication Formats
• Write format (data can be written into sequentially incremented addresses)
START Slave Addres s
Write=L
Register Ad dres s ( N )ACK ACK
Data written to Register Address (N)
ACK
Data written to Register Address (N+1)
ACK STOP
Slave Slave Slave Slave
fig.3
• Read format (data can be read from sequentially incremented addresses)
START Slave Address
Write=L
Register A ddr ess ( N)ACK ACK
Data read from Register Address (N)
ACK
RESTART
Slave Address
Read=H
ACK
Data read from Regi ster Address (N+1)
ACK
Data read from Register Address (N+2)
NACK
STOP
Slave
Slave
Slave
Master Master
Master
fig.4
SDA
SCL
START
condition
tHD;STA
tLOW
tHI
G
H
tr
repeated START
condition STOP
condition
10%
tf
90% 10% 10%
90% 90%
tHD;DTA tSU;DTA
10% 10%
10%
90%
tSU;STA
90% 90%
tHD;STA
90%
10%
90%
10%
90%
10%
tSU;STO tBUF
START
condition
90%
POR
(LSI internal signal) RELEASE
tP
O
R
VDD
RESET
tVDD
INTOUT
VP
O
R
O
P
Cin,
Cref,
Pout UNKNOWN
VALID
tP
O
R
O
P
UNKNOWN
UNKNOWN
UNKNOWN RESET RELEASE
tP
O
R
VALID
LC717A00AR
No.A2048-6/11
I2C Compatible Bus Slave Address
Selection of two kinds of addresses is possible through the SA terminal.
SA pin input 7bit Slave Address Binary Notation 8bit Slave Address
00101100b (Write) 0x2C Low 0x16
00101101b (Read) 0x2D
00101110b (Write) 0x2E High 0x17
00101111b (Read) 0x2F
SPI Data Timing (SPI Mode 0 / Mode 3)
fig.5
SPI Communication Formats (Example of Mode 0)
• Write format (data can be written into sequentially incremented addresses while holding nCS = L)
nCS
SCK
SI
SO
76543210
Hi-Z Register Address(N)
Data written to Register Address(N) Data written to Register Address(N+1)
Write=L 7654321076543210
fig.6
• Read format (data can be read from sequentially incremented addresses while holding nCS = L)
Register Address(N)
Data read from Register Address(N) Data read from Register Address(N+1)
7
Read=H
76543210
Hi-Z
nCS
SCK
SI
SO 7654321076543210
fig.7
nCS
SCK
SI
SO
tSU;SI
VALID
Hi-Z
tr
tHD;SI
tSU;SCK tSU;NCS tHIGH t
LOW tf
tCPH
tHD;NCS tHD;SCK
tCLZ tHD;SO tCHZ
VALID
tV
LC717A00AR
No.A2048-7/11
Package Dimensions [LC717A00AR]
unit : mm (typ)
3357
Pin Assignment
Pin No. Pin Name Pin No. Pin Name
1 Cin0 15 Pout4
2 Cin1 16 Pout5
3 Cin2 17 Pout6
4 Cin3 18 Pout7
5 VDD 19 Cref
6 VSS 20 ERROR
7 Cin4 21 Cdrv
8 Cin5 22 INTOUT
9 Cin6 23 GAIN
10 Cin7 24 SCL/SCK
11 Pout0 25 SDA/SI
12 Pout1 26 SA/SO
13 Pout2 27 nCS
14 Pout3 28 nRST
SANYO : VCT28(3.5X3.5)
3.5
0.19
3.5
0.4
0.8
(0.035)
12
28
0.4 (0.55)
TOP VIEW SIDE VIEW
SIDE VIEW
BOTTOM VIEW
(0.125)
(C0.09)
(0.09)
LC717A00AR
No.A2048-8/11
Block Diagram
Cin0
SCL/SCK
SDA/SI VDD
VSS
INTOUT
Cin1
Cin2
Cin3
Cin4
Cin5
Cin6
Cin7
Pout0
Pout1
Pout6
Pout7
Pout5
Pout4
Pout3
Pout2
nCS
SA/SO
Cdrv
GAIN
nRST
ERROR
Cref
MUX
1st
AMP A/D
CONVERTER
2nd
AMP
POR
CONTROL
LOGIC
OSCILLATOR
I
2
C/SPI
LC717A00AR is capacitance-digital-converter LSI capable of detecting changes in capacitance in the femto Farad order.
It consists of an oscillation circuit that generates the system clock, a power-on reset circuit that resets the system when
the power is turned on, a multiplexer that selects the input channels, a two-stage amplifier that detects the changes in the
capacitance and outputs analog-amplitude values, a A/D converter that converts the analog-amplitude values into digital
data, and a control logic that controls the entire chip. Also, it has an I2C compatible bus or SPI that enables serial
communication with external devices as necessary.
LC717A00AR
No.A2048-9/11
Pin Functions
Pin Name I/O Pin Functions Pin Type
Cin0 I/O Capacitance sensor input
Cin1 I/O Capacitance sensor input
Cin2 I/O Capacitance sensor input
Cin3 I/O Capacitance sensor input
Cin4 I/O Capacitance sensor input
Cin5 I/O Capacitance sensor input
Cin6 I/O Capacitance sensor input
Cin7 I/O Capacitance sensor input
Cref I/O Reference capacitance input
RAMP
VDD
VSS Buffer
Pout0 O Cin0 judgment result output
Pout1 O Cin1 judgment result output
Pout2 O Cin2 judgment result output
Pout3 O Cin3 judgment result output
Pout4 O Cin4 judgment result output
Pout5 O Cin5 judgment result output
Pout6 O Cin6 judgment result output
Pout7 O Cin7 judgment result output
ERROR O Error occurrence status output
Cdrv O Output for capacitance sen sors driv e
INTOUT O Interrupt output
VDD
VSS
Buffer
SCL/SCK I Clock input (I2C)
/ Clock input (SPI)
GAIN I Selection pin of the initial value of gain of the
2nd-amplifier
nCS I Interf ace selection
/ Chip select inverting input (SPI)
nRST I External reset signal inverting input
VDD
VSS
R
SDA/SI I/O Data input and output (I2C)
/ Data input (SPI)
VDD
VSS
R
SA/SO I/O Slave address selection (I2C)
/ Data output (SPI)
VDD
VSS
R
Buffer
VDD Power supply (2.6V to 5.5V) *1
VSS Ground (Earth) *1 *2
*1) Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended.
In this case, the small-valued capacitor should be at least 0.1μF, and is mounted near the LSI.
*2) When VSS terminal is not grounded in battery-powered mobile equipment, detection sensitivity may be degraded.
LC717A00AR
No.A2048-10/11
Details of Pin Functions
●Cin0 to Cin7
These are the capacitance-sensor-input pins. These pins are used by connecting them to the touch switch pattern. Cin
and the Cdrv wire patterns should be close to each other. By doing so, Cdrv and Cin patterns are capacitively coupled.
Therefore, LSI can detect capacitance change near each pattern as 8bit digital data.
However, if the shape of each pattern or the capacitively coupled value of Cdrv is not appropriate, it may not be able
to detect the capacitance change correctly.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. Cin0 to Cin7 are connected to the inverting input of the 1st amplifier in the LSI.
During measurement process, channels other than the one being measured are all in “Low” condition.
Leave the unused terminals open.
●Cref
It is the reference-capacitance-input pin. It is used by connecting to the wire pattern like Cin pins or is used by
connecting any capacitance between this pin and Cdrv pin.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. Cref is connected to the non-inverting input of the 1st amplifier in the LSI.
Due to the parasitic capacitance generated in the wire connections of Cin pins and their patterns, as well as the one
generated between the wire patterns of Cin and Cdrv pins, Cref may not detect capacitance change of each Cin pin
accurately. In this case, connect an appropriate capacitance between Cref and Cdrv to detect capacitance change
accurately.
However, if the difference between the parasitic capacitance of each Cin pin is extremely large, it may not detect
capacitance change in each Cin pin correctly.
●Pout0 to Pout7
These are the detection-result-output pins. The capacitance detection results of Cin0 to Cin7 are compared with the
threshold of the LSI. The pin outputs a “High” or a “Low” depending on the result.
●ERROR
It is the error-occurrence-status-output pin.
It outputs “Low” during normal operation. If there is a calibration error or a system error, it outputs “High” to indicate
that an error occurred.
●Cdrv
It is the output pin for capacitance sensors drive. It outputs the pulse voltage which is needed to detect capacitance at
Cin0 to Cin7.
Cdrv and Cin wire patterns should be close to each other so that they are capacitively coupled.
●INTOUT
It is the interrupt-output pin. It outputs “High” when a measurement process is completed.
Connect to a main microcomputer if necessary, and use as interrupt signal.
Leave the terminal open if not in used.
●SCL/SCK
Clock input (I2C) / Clock input (SPI)
It is the clock input pin of the I2C compatible bus or the SPI depending on the mode of operation.
If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a
communication terminal on board is still recommended.
●GAIN
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. It is the selection pin of the initial value of gain of the 2nd amplifier.
Even if this LSI is used alone, gain setting can still be selected through this terminal. At initialization of the LSI, it is
set to 7-times higher than the minimum setting when GAIN pin is “Low”, and is set to 14-times higher than the
minimum setting when GAIN pin is “High”.
LC717A00AR
No.A2048-11/11
●nCS
Interface selection / Chip-select-inverting input (SPI)
Selection of I2C compatible bus mode or SPI mode is through this terminal. After initialization, the LSI is
automatically in I2C compatible bus mode. To continually use I2C compatible bus mode, fix nCS pin to “High”. To
switch to SPI mode after LSI initialization, change the nCS input “High” → “Low”. The nCS pin is used as the chip-
select-inverting input pin of SPI, and SPI mode is kept until LSI is again initialized.
If interface is not to be used, fix the pin to “High”.
●nRST
It is the external-reset-signal-inverting-input pin. When nRST pin is “Low”, LSI is in the reset state.
Each pin (Cin0 to 7, Cref, Pout,0 to 7, ERROR) is “Hi-Z” during reset state.
●SDA/SI
Data input and output (I2C) / Data input (SPI)
It is the data input and output pin of the I2C compatible bus or the data input pin of the SPI depending on the mode of
operation.
If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a
communication terminal on board is still recommended.
●SA/SO
Slave address selection (I2C) / Data output (SPI)
It is the slave address selection pin of the I2C compatible bus or the data output pin of the SPI depending on the mode
of operation.
If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a
communication terminal on board is still recommended.
PS
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