Low Profile, 500 mA, 6 MHz, Synchronous, Step-Down, DC-to-DC Converter ADP2125 FEATURES GENERAL DESCRIPTION 1.26 V fixed output voltage Clock signal enable 6 MHz (maximum) operating frequency 500 mA continuous output current Input voltage: 2.1 V to 5.5 V 0.3 A (typical) shutdown supply current Compatible with tiny multilayer inductors Internal synchronous rectifier Internal compensation Internal soft start Output-to-ground short-circuit protection Current-limit protection Undervoltage lockout Thermal shutdown protection Ultrasmall, 0.405 mm height (maximum), 6-ball BUMPED_CHIP The ADP2125 is a high frequency, step-down, dc-to-dc converter optimized for portable applications in which board area and battery life are critical constraints. Fixed frequency operation at 6 MHz enables the use of tiny ceramic inductors and capacitors. Additionally, the synchronous rectification improves efficiency and results in fewer external components. Over all load currents, the device uses a voltage regulating pulse-width modulation (PWM) mode that maintains a constant frequency with excellent stability and transient response. The ADP2125 is enabled by a 6 MHz to 27 MHz external clock signal applied to the EXTCLK pin. When the external clock is not switching and in a low state (EXTCLK 0.5 V), the input is disconnected from the output and draws less than 0.3 A (typical) from the source. The ADP2125 has an input voltage range of 2.1 V to 5.5 V, allowing the use of single Li+/Li polymer cell, three-cell alkaline, NiMH cell, and other standard power sources. The ADP2125 is internally compensated to minimize external components and can source up to 500 mA. Other key features such as cycle-by-cycle peak current limit, soft start, undervoltage lockout (UVLO), output-to-ground short-circuit protection, and thermal shutdown provide protection for internal and external circuit components. APPLICATIONS Mobile phones Digital still/video cameras Digital audio Portable equipment Camera modules Image stabilization systems TYPICAL APPLICATION CIRCUIT ADP2125 A2 VIN L 1.5H OUTPUT VOLTAGE 1.26V SW B1 CIN 2.2F C2 GND FB C1 EXTCLK NC B2 A1 OFF ON COUT 4.7F NC = NO CONNECT 08774-002 INPUT VOLTAGE 2.1V TO 5.5V Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010-2011 Analog Devices, Inc. All rights reserved. ADP2125 TABLE OF CONTENTS Features .............................................................................................. 1 Overview ..................................................................................... 10 Applications....................................................................................... 1 External Clock (EXTCLK) Enable ........................................... 10 General Description ......................................................................... 1 Internal Control Features .......................................................... 10 Typical Application Circuit ............................................................. 1 Protection Features .................................................................... 11 Revision History ............................................................................... 2 Timing Constraints .................................................................... 11 Specifications..................................................................................... 3 Applications Information .............................................................. 12 Timing Diagram ........................................................................... 4 Inductor Selection ...................................................................... 12 Absolute Maximum Ratings............................................................ 5 Input Capacitor Selection.......................................................... 12 Thermal Considerations.............................................................. 5 Output Capacitor Selection....................................................... 13 Thermal Resistance ...................................................................... 5 Thermal Limit Calculations...................................................... 13 ESD Caution.................................................................................. 5 PCB Layout Guidelines.................................................................. 14 Pin Configuration and Function Descriptions............................. 6 Outline Dimensions ....................................................................... 15 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 15 Theory of Operation ...................................................................... 10 REVISION HISTORY 5/11--Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 15 9/10--Revision 0: Initial Version Rev. A | Page 2 of 16 ADP2125 SPECIFICATIONS VIN = 3.6 V, VOUT = 1.26 V, TA = 25C for typical specifications, and TA = TJ = -40C to +85C for minimum and maximum specifications, unless otherwise noted. All specifications at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Typical specifications are not guaranteed. Table 1. Parameter SUPPLY Operating Input Voltage Range Quiescent Current Shutdown Current UNDERVOLTAGE LOCKOUT Rising VIN Threshold Falling VIN Threshold OUTPUT Continuous Output Current 1 Output Accuracy 2 FB Bias Current FB Pull-Down Resistance SWITCHING CHARACTERISTICS PMOS On Resistance NMOS On Resistance SW Leakage Current PMOS Switch Current Limit Oscillator Frequency SHORT-CIRCUIT PROTECTION Rising VOUT Threshold Falling VOUT Threshold EXTCLK INPUT High Threshold Voltage Low Threshold Voltage Leakage Current Duty Cycle Operating Range Frequency Operating Range THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis TIMING VIN High to EXTCLK On1 EXTCLK On to VOUT Rising 1 2 Symbol Test Conditions/Comments VIN Min 2.1 No load VEXTCLK = 0 V, open-loop 8 0.3 1.5 ILOAD VOUT RDSCHG Typ VIN = 2.1 V to 5.5 V VIN = 2.3 V to 4.8 V VFB = 1.2 V VEXTCLK = 0 V, IFB = 10 mA 1.9 1.8 500 VOUT - 2% 4 110 180 250 VSW = 0 V, VIN = 5.5 V Open-loop fSW VEXTCLK(H) VEXTCLK(L) VIN = 2.5 V to 4.4 V VIN = 2.5 V to 4.4 V VIN = 5.5 V, VEXTCLK = 2.1 V to 5.5 V DEXTCLK fEXTCLK 770 4.83 1000 5.52 0.4 0.55 0.52 Max Unit 5.5 V mA A 1.5 2.1 mA VOUT + 2% V 9 A 180 340 10 1291 6 0.7 1.4 0.01 40 6 0.5 1 60 27 146 13 t1 t2 VOUT Power-Up Time (Soft Start)1 EXTCLK Off to VOUT Falling VOUT Power-Down Time t3 t5 t6 Minimum Shutdown Time1 Minimum Power-Off Time1 t 5 + t6 t7 See Figure 2 VIN = 2.1 V to 5.5 V DEXTCLK = 40% to 60%, fEXTCLK = 6 MHz DEXTCLK = 40% to 60%, fEXTCLK = 27 MHz COUT = 4.7 F, RLOAD = 3.6 DEXTCLK = 40% to 60%, fEXTCLK = 6 MHz to 27 MHz COUT = 4.7 F, RLOAD = 3.6 COUT = 4.7 F, no load COUT = 4.7 F, no load Guaranteed by design. Transients not included in voltage accuracy specifications. Rev. A | Page 3 of 16 200 17 16 1400 500 23 21 105 4.1 36 1070 V V m m A mA MHz V V V V A % MHz C C 32 28 200 11 s s s s s s s s s ADP2125 TIMING DIAGRAM VIN x 90% VIN t7 VIN x 10% t6 t3 VOUT VOUT(NOM) x 10% t2 t5 08774-003 EXTCLK t1 Figure 2. I/O Timing Diagram Rev. A | Page 4 of 16 ADP2125 ABSOLUTE MAXIMUM RATINGS ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. Table 2. Parameter VIN to GND EXTCLK to GND SW, NC to GND FB (VIN 3.6 V) to GND FB (VIN < 3.6 V) to GND Operating Ambient Temperature (TA) Operating Junction Temperature (TJ) at ILOAD = 500 mA Soldering Conditions 1 Rating -0.3 V to +6 V -0.3 V to +6 V -0.3 V to VIN -0.3 V to +3.6 V -0.3 V to VIN -40C to +85C1 -40C to +125C The operating junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (JA). TJ is calculated using the following formula: TJ = TA + (PD x JA) (1) See the Applications Information section for further information on calculating the operating junction temperature for a specific application. JEDEC J-STD-020 THERMAL RESISTANCE The maximum operating junction temperature (TJ(MAX)) supersedes the maximum operating ambient temperature (TA(MAX)). See the Thermal Considerations section for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. JA of the package is based on modeling and calculation using a 4-layer board. JA is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. JA is specified for worst-case conditions, that is, a device soldered on a circuit board for surface-mount packages. JA is determined according to JEDEC Standard JESD51-9 on a 4-layer printed circuit board (PCB). Table 3. Thermal Resistance THERMAL CONSIDERATIONS The maximum operating junction temperature (TJ(MAX)) supersedes the maximum operating ambient temperature (TA(MAX)) because the ADP2125 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. Package Type 6-Ball Bumped Bare Die, 4-Layer Board ESD CAUTION In applications with high power dissipation and poor PCB thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and good PCB thermal resistance, the maximum Rev. A | Page 5 of 16 JA 120 Unit C/W ADP2125 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 1 2 NC VIN A SW EXTCLK B FB GND TOP VIEW BALL SIDE DOWN BUMPS ON OPPOSITE SIDE (Not to Scale) 08774-005 C Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. A1 Mnemonic NC B1 C1 SW FB A2 B2 C2 VIN EXTCLK GND Description No Connection. Any voltage applied to this pin must be between GND and VIN. Voltages above VIN or below GND exceed the absolute maximum ratings and may cause damage to the part. Switch Node. Feedback Divider Input. Connect the output capacitor from FB to GND to set the output voltage ripple and to complete the control loop. Power Supply Input. External Clock Enable Signal. The ADP2125 powers up when a clock signal (6 MHz to 27 MHz) is detected on this pin. Ground. Rev. A | Page 6 of 16 ADP2125 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.6 V, fEXTCLK = 10 MHz, VOUT = 1.26 V, L = 1.8 H (700 mA, 0603 package, LQM18PN1R8NC0), CIN = 2.2 F (6.3 V, 0402 package, X5R, GRM155R60J225ME15), COUT = 4.7 F (4 V, 0402 package, X5R, GRM155R60G475ME47), and TA = 25C, unless otherwise noted. 1.263 100 90 1.262 60 50 40 30 VIN = 2.1V VIN = 2.7V VIN = 3.6V VIN = 4.8V VIN = 5.5V 10 1 10 100 1000 LOAD CURRENT (mA) 1.259 VIN = 2.1V VIN = 2.7V VIN = 3.6V VIN = 4.8V VIN = 5.5V 1.257 1 10 1.262 90 1.261 OUTPUT VOLTAGE (V) 80 75 70 ILOAD = 100mA ILOAD = 250mA ILOAD = 500mA 2.6 3.1 1.260 1.259 1.258 1.257 TA = -40C TA = +25C TA = +85C 1.256 3.6 4.1 4.6 5.1 INPUT VOLTAGE (V) 1.255 08774-105 EFFICIENCY (%) 85 60 2.1 1 0.9 0.8 SHUTDOWN CURRENT (A) 10 9 8 7 6 TA = -40C TA = +25C TA = +85C 2.6 3.1 3.6 4.1 1000 4.6 INPUT VOLTAGE (V) 5.1 TA = -40C TA = +25C TA = +85C 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.1 08774-106 5 100 Figure 8. Output Voltage Accuracy over Temperature 11 QUIESCENT CURRENT (mA) 10 LOAD CURRENT (mA) Figure 5. Efficiency vs. Input Voltage 4 2.1 1000 Figure 7. Output Voltage Accuracy Figure 4. Efficiency vs. Load Current 65 100 LOAD CURRENT (mA) 08774-108 0 1.260 1.258 08774-104 20 1.261 SW = OPEN 2.6 3.1 3.6 4.1 4.6 INPUT VOLTAGE (V) Figure 6. Quiescent Current vs. Input Voltage Figure 9. Shutdown Current vs. Input Voltage Rev. A | Page 7 of 16 5.1 08774-109 EFFICIENCY (%) 70 08774-107 OUTPUT VOLTAGE (V) 80 ADP2125 350 TA = -40C TA = +25C TA = +85C ISW = 500mA OUTPUT VOLTAGE (20mV/DIV) 1.26V OFFSET P-CHANNEL R DSON (m) 300 1 250 200 LOAD CURRENT (200mA/DIV) 100 2.1 2.6 3.1 3.6 4.1 4.6 5.1 INPUT VOLTAGE (V) TIME (20s/DIV) Figure 10. PMOS Drain-to-Source On Resistance 450 Figure 13. Load Transient Response, 250 mA to 420 mA, VIN = 2.1 V TA = -40C TA = +25C TA = +85C ISW = 500mA 400 N-CHANNEL R DSON (m) VIN = 2.1V VOUT = 1.26V 08774-110 2 08774-113 150 OUTPUT VOLTAGE (50mV/DIV) 1.26V OFFSET 1 350 300 LOAD CURRENT (200mA/DIV) 250 150 2.1 2.6 3.1 3.6 4.1 4.6 5.1 INPUT VOLTAGE (V) TIME (20s/DIV) Figure 14. Load Transient Response, 250 mA to 420 mA, VIN = 3.6 V Figure 11. NMOS Drain-to-Source On Resistance 6.0 VIN = 3.6V VOUT = 1.26V 08774-111 2 08774-114 200 TA = -40C TA = +25C TA = +85C OUTPUT VOLTAGE (50mV/DIV) 1.26V OFFSET 5.8 5.6 5.4 LOAD CURRENT (200mA/DIV) 2 5.0 2.1 2.6 3.1 3.6 4.1 4.6 5.1 INPUT VOLTAGE (V) VIN = 5.5V VOUT = 1.26V TIME (20s/DIV) 08774-115 5.2 08774-112 FREQUENCY (MHz) 1 Figure 15. Load Transient Response, 250 mA to 420 mA, VIN = 5.5 V Figure 12. Switching Frequency vs. Input Voltage Rev. A | Page 8 of 16 ADP2125 VIN = 3.6V VOUT = 1.26V NO LOAD OUTPUT VOLTAGE (500mV/DIV) OUTPUT VOLTAGE (200mV/DIV) 1 1 INDUCTOR CURRENT (200mA/DIV) INDUCTOR CURRENT (1A/DIV) 2 2 TIME (20s/DIV) TIME (200s/DIV) Figure 16. Startup, No Load VIN = 3.6V VOUT = 1.26V RLOAD = 3.6 08774-118 EXTCLK (5V/DIV) 08774-116 3 Figure 18. Output Short-Circuit Response VIN = 3.6V OUTPUT VOLTAGE (500mV/DIV) OUTPUT VOLTAGE (10mV/DIV) 1.26V OFFSET 1 1 INDUCTOR CURRENT (200mA/DIV) INDUCTOR CURRENT (200mA/DIV) 2 2 SWITCH PIN VOLTAGE (5V/DIV) 3 TIME (100ns/DIV) Figure 17. Startup, RLOAD = 3.6 Figure 19. Standard Operation Rev. A | Page 9 of 16 08774-119 TIME (20s/DIV) 3 08774-117 EXTCLK (5V/DIV) ADP2125 THEORY OF OPERATION VIN 2.1V TO 5.5V CIN 2.2F A2 VIN PVIN VOUT FB AVIN C1 PDRIVE R1 PWM COMP EAMP R2 AGND BG RAMP COMPENSATION 6MHz OSCILLATOR RDSCHG 110 FB B1 NDRIVE V(VIN) SW C2 PILIM PREF SOFT START SHORT-CIRCUIT PROTECTION VOUT DISCHARGE ZXCOMP LOGIC AND PWM CONTROL L 1.5H VOUT 1.26V COUT 4.7F PGND THERMAL SHUTDOWN AGND FB SHOOTTHROUGH CONTROL GND AGND NREF AGND CLK DETECT BG THRESHOLD DETECT B2 OFF A1 EXTCLK NC ON GND TO VIN 08774-006 BANDGAP Figure 20. Internal Block Diagram OVERVIEW The ADP2125 is a high efficiency, synchronous, step-down, dc-to-dc converter that operates from a 2.1 V to 5.5 V input voltage. It provides up to 500 mA of continuous output current at a fixed output voltage. The 6 MHz operating frequency enables the use of tiny external components. The internal control schemes of the ADP2125 give excellent stability and transient response. Other internal features such as cycle-bycycle peak current limiting, soft start, undervoltage lockout, output-to-ground short-circuit protection, and thermal shutdown provide protection for internal and external circuit components. EXTERNAL CLOCK (EXTCLK) ENABLE The ADP2125 is enabled by a 6 MHz to 27 MHz clock signal applied to the EXTCLK pin (see Figure 2 and Figure 20). The ADP2125 internally detects the clock signal and allows the converter to power up and the output voltage to rise to its nominal value. The ADP2125 can detect a nonswitching state and disable the part whether the EXTCLK gates low or high. If the EXTCLK signal gates low, the part is shut down, reducing the current consumption to 0.3 A (typical). INTERNAL CONTROL FEATURES Pulse-Width Modulation (PWM) PWM forces the part to maintain a fixed frequency of 6 MHz (maximum) over all load conditions. The ADP2125 uses a hybrid proprietary voltage mode control scheme to control the duty cycle over load current and line voltage variation. This control provides excellent stability, transient response, and output regulation. Synchronous Rectification In addition to the P-channel MOSFET switch, the ADP2125 includes an N-channel MOSFET switch to build the synchronous rectifier. The synchronous rectifier improves efficiency, especially for small load currents, and reduces cost and board space by eliminating the need for an external rectifier. Soft Start To prevent excessive input inrush current at startup, the ADP2125 operates with an internal soft start. When EXTCLK begins to oscillate, or when the part recovers from a fault (UVLO, TSD, or SCP), a soft start timer begins. During this time, the peak current limit is gradually increased to its maximum. The output Rev. A | Page 10 of 16 ADP2125 PROTECTION FEATURES Overcurrent Protection To ensure that excessively high currents do not damage the inductor, the ADP2125 incorporates cycle-by-cycle overcurrent protection. This function is accomplished by monitoring the instantaneous peak current on the power PMOS switch. If this current exceeds the PMOS switch current limit (1 A typical), then the PMOS is immediately turned off. This minimizes the potential for damage to power components during certain faults and transient events. Output Short-Circuit Protection (SCP) If the output voltage is shorted to GND, a standard dc-to-dc controller delivers maximum power into that short. This may result in a potentially catastrophic failure. To prevent this, the ADP2125 senses when the output voltage is below the SCP threshold (typically 0.55 V). At this point, the controller turns off for approximately 450 s and then automatically initiates a soft start sequence. This cycle repeats until the short is removed or the part is disabled. Figure 18 shows this operating behavior of the ADP2125 during a short-circuit fault. The SCP dramatically reduces the power delivered into the short circuit, yet still allows the converter to recover if the fault is removed. Thermal Shutdown (TSD) Protection The ADP2125 also includes TSD protection. If the die temperature exceeds 146C (typical), the TSD protection activates and turns off the power devices. They remain off until the die temperature falls 13C (typical), at which point the converter restarts. Undervoltage Lockout (UVLO) If the input voltage is below the UVLO threshold, the ADP2125 automatically turns off the power switches and places the part in a low power consumption mode. This prevents potentially erratic operation at low input voltages. The UVLO levels have approximately 100 mV of hysteresis to ensure glitch-free startup. TIMING CONSTRAINTS Shutdown Time When the ADP2125 enters shutdown mode after the EXTCLK signal is removed, the ADP2125 must remain in shutdown for a minimum of 1400 s, if no load is applied, before the EXTCLK signal can be reapplied. This allows all internal nodes to discharge to an off state. Power-Off Time When VIN drops, thereby triggering UVLO, the ADP2125 has a minimum power-off time (t7) of 500 s that must elapse before VIN can be reapplied. This allows all supplies to discharge enough power so that all internal devices are in an off state. t7 VIN x 10% Figure 21. Power-Off Time Rev. A | Page 11 of 16 08774-021 voltage increases in stages to ensure that the converter is able to start up effectively and in proper sequence. After the soft start period expires, the peak PMOS switch current limit remains at 1 A (typical) and the part is able to operate. ADP2125 APPLICATIONS INFORMATION It is important that the inductor be capable of handling the maximum peak inductor current, IPK, determined by the following equation: The ADP2125 is designed to be compatible with chip inductors and multilayer ceramic capacitors that are ideal for their small footprint and low height. The recommended components for this application may change as this technology advances. Table 5, Table 6, and Table 7 list compatible inductors and capacitors. IPK = ILOAD(MAX) + IL/2 The dc current rating of the inductor should be greater than the calculated IPK to prevent core saturation. This section describes the selection of external components. The component value ranges are limited to optimize efficiency and transient performance while maintaining stability over the full operating range. INPUT CAPACITOR SELECTION INDUCTOR SELECTION The high switching frequency of the ADP2125 allows for minimal output voltage ripple, even with small inductors. Inductor sizing is a trade-off between efficiency and transient response. A small value inductor leads to a larger inductor current ripple that provides excellent transient response, but degrades efficiency. A small footprint and low height chip inductor can be used for an overall smaller solution size but has a higher dc resistance (DCR) value and lower current rating that can degrade performance. Shielded ferrite core inductors are recommended for their low core losses and low electromagnetic interference (EMI). The recommended inductor for the ADP2125 is 1.5 H. The inductor peak-to-peak current ripple, IL, can be calculated as follows: I L = VOUT x (V IN - VOUT ) (2) V IN x L x f SW (3) The input capacitor must be rated to support the maximum input operating voltage. Higher value input capacitors reduce the input voltage ripple caused by the switch currents on the VIN pin. Maximum rms input current for the application can be calculated using the following equation: I RMS _ MAX (CIN ) = I LOAD ( MAX ) x VOUT x (V IN - VOUT ) V IN (4) Place the input capacitor as close as possible to the VIN pin to minimize supply noise. In principle, different types of capacitors can be considered, but for battery-powered applications, the best choice is the multilayer ceramic capacitor, due to its small size, low equivalent series resistance (ESR), and low equivalent series inductance (ESL). It is recommended that the VIN pin be bypassed with a 2.2 F input capacitor. The input capacitor can be increased without any limit for better input voltage filtering. X5R or X7R dielectrics with a voltage rating of 6.3 V or higher are recommended. Table 5. Inductor Selection Manufacturer Murata Taiyo Yuden Series LQM18PN1R8NC0L LQM18PN1R5NB0L CKP1608L1R5M Inductance (H) 1.80 1.50 1.50 DCR (m) (typ) 240 350 220 Current Rating (mA) 700 600 700 Size (L x W x H) (mm) 1.60 x 0.80 x 0.55 1.60 x 0.80 x 0.40 1.60 x 0.80 x 0.55 Package 0603 0603 0603 Table 6. Input Capacitor Selection Manufacturer Murata Taiyo Yuden TDK Part Number GRM155R60J225ME95 JMK105BJ225MV-F C1005X5R0J225M Capacitance (F) 2.2 2.2 2.2 Voltage Rating (V) 6.3 6.3 6.3 Temperature Coefficient X5R X5R X5R Size (L x W x H) (mm) 1.0 x 0.5 x 0.5 1.0 x 0.5 x 0.5 1.0 x 0.5 x 0.5 Package 0402 0402 0402 Capacitance (F) 4.7 4.7 4.7 4.7 Voltage Rating (V) 6.3 4 4 6.3 Temperature Coefficient X5R X5R X5R X5R Size (L x W x H) (mm) 1.0 x 0.5 x 0.5 1.0 x 0.5 x 0.5 1.0 x 0.5 x 0.5 1.0 x 0.5 x 0.5 Package 0402 0402 0402 0402 Table 7. Output Capacitor Selection Manufacturer Murata Taiyo Yuden TDK Part Numbers GRM155R60J475ME87 GRM155R60G475ME47 AMK105BJ475MV-F C1005X5R0J475M Rev. A | Page 12 of 16 ADP2125 OUTPUT CAPACITOR SELECTION The output capacitor selection affects both the output voltage ripple and the loop dynamics of the converter. For a given loop crossover frequency (the frequency at which the loop gain drops to 0 dB), the maximum voltage transient excursion (overshoot) is inversely proportional to the value of the output capacitor. When choosing output capacitors, it is also important to account for the loss of capacitance due to output voltage dc bias. This may result in using a capacitor with a higher rated voltage to achieve the desired capacitance value. Additionally, if ceramic output capacitors are used, the capacitor rms ripple current rating should always meet the application requirements. The rms ripple current is calculated as follows: I RMS (COUT ) = 1 2 3 x ( VOUT x V IN ( MAX ) - VOUT ) (5) L x f SW x V IN ( MAX ) At nominal load currents, the converter operates in forced PWM mode, and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor. VOUT = IL x (ESR + 1/(8 x COUT x fSW)) (6) The power dissipation (PD) of the ADP2125 is only a portion of the power loss of the overall application. For a given application with known operating conditions, the application power loss can be calculated by combining the following equations for power loss (PLOSS) and efficiency (): PLOSS = PIN - POUT = THERMAL LIMIT CALCULATIONS The operating junction temperature (TJ) of the device is dependent on the ambient operating temperature (TA) of the application, the power dissipation of the ADP2125 (PD), and the junction-to-ambient thermal resistance of the package (JA). The operating junction temperature (TJ) is calculated using the following equation: 100 PLOSS = POUT - 1 (9) (10) The power loss calculated using this approach is the combined loss of the ADP2125 device (PD), the inductor (PL), input capacitor (PCIN), and the output capacitor (PCOUT), as shown in the following equation: PLOSS = PD + PL + PCIN + PCOUT (11) The power loss for the inductor, input capacitor, and output capacitor can be calculated as follows: (12) 2 I PCIN = RMS x ESR CIN 2 (13) PCOUT = (IOUT)2 x ESRCOUT (14) If multilayer chip capacitors with low ESR are used, the power loss in the input and output capacitors is negligible and PD + PL >> PCIN + PCOUT (15) PLOSS PD + PL (16) The final equation for calculating PD can be used in Equation 7 to ensure that the operating junction temperature is not exceeded. (7) where JA is 120C/W, as provided in Table 3. The ADP2125 can be damaged when the operating junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature (TJ) is within the specified temperature limits. * x 100 PL = IRMS2 x DCR The ADP2125 is designed to operate with small 4.7 F ceramic capacitors that have low ESR and ESL. These components are therefore able to meet tight output voltage ripple specifications. X5R or X7R dielectrics with a voltage rating of 4 V or higher are recommended. * PIN The resulting equation uses the output power and the efficiency to determine the PLOSS. The largest voltage ripple occurs at the highest input voltage. TJ = TA + (PD x JA) POUT (8) In applications with high PD and poor PCB thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate PD and good PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. Rev. A | Page 13 of 16 100 PD PLOSS - PL POUT - 1 - PL (17) ADP2125 PCB LAYOUT GUIDELINES To ensure package reliability, consider the following guidelines when designing the footprint for the ADP2125. The BUMPED_CHIP device footprint must ultimately be determined according to application and customer specific reliability requirements, PCB fabrication quality, and PCB assembly capabilities. * 08774-022 * Figure 22. ADP2125 Recommended Top Layer Layout * * * * 08774-023 * Figure 23. ADP2125 Recommended Bottom Layer Layout For high efficiency, good regulation, and stability, a welldesigned and manufactured PCB is required. Use the following guidelines when designing PCBs: * * * * Keep the low ESR input capacitor, CIN, close to VIN and GND. Keep high current traces as short and as wide as possible. Avoid routing high impedance traces near any node connected to SW or near the inductor to prevent radiated noise injection. Keep the low ESR output capacitor, COUT, close to the FB and GND pins of the ADP2125. Long trace lengths from the part to the output capacitor add series inductance that may cause instability or increased ripple. Rev. A | Page 14 of 16 The Cu pad on the PCB for each solder bump should be 80% to 100% of the width of the solder bump. A smaller pad opening favors solder joint reliability (SJR) performance, whereas a larger pad opening favors drop test performance. The maximum pad size, including tolerance, should not exceed 180 m. Electroplated nickel, immersion gold (ENIG) and organic solderability preservative (OSP) were used for internal reliability testing and are recommended. Nonsolder mask defined (NSMD) Cu pads are recommended for BUMPED_CHIP packages. The solder mask opening should be approximately 100 m larger than the pad opening. The trace width should be less than two-thirds the size of the pad opening. The routing of traces from the Cu pads should be symmetrical in X and Y directions. Symmetrical routing of the traces prevents part rotation due to uneven solder wetting/surface tension forces. Stencil design is important for proper transfer of paste onto the Cu pads. Area ratio (AR), the relationship between the surface area of the stencil aperture and the inside surface area of the aperture walls, is critically important. Stencil thickness has the greatest impact on this ratio. AR values from 0.66 to 0.8 provide the best paste transfer efficiency and repeatability. The AR is calculated using the following equation: Ap AR = Aw where: Ap is the area of the aperture opening. Aw is the wall area. ADP2125 OUTLINE DIMENSIONS 0.405 0.390 0.375 0.940 0.900 0.860 SEATING PLANE 2 1 A BALL A1 IDENTIFIER 1.340 1.300 1.260 0.170 TYP 0.80 BSC B 0.40 BSC C 0.05 NOM COPLANARITY 0.40 BSC BOTTOM VIEW 0.115 TYP (BALL SIDE UP) 082409-A TOP VIEW (BALL SIDE DOWN) DIRECTION OF FEED 08774-008 Figure 24. 6-Ball Bumped Bare Die Sales [BUMPED_CHIP] (CD-6-2) Dimensions shown in millimeters Figure 25. Tape and Reel Orientation for ADP2125 ORDERING GUIDE Model 1 ADP2125BCDZ-1.26R7 ADP2125B-1.26EVALZ 1 2 Output Voltage 1.26 V 1.26 V Pin A1 Function NC NC Temperature Range -40C to +85C Package Description 6-Ball Bumped Bare Die [BUMPED_CHIP] Evaluation Board Z = RoHS Compliant Part. This package option is halide free. Rev. A | Page 15 of 16 Package Option 2 CD-6-2 Branding LEP ADP2125 NOTES (c)2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08774-0-5/11(A) Rev. A | Page 16 of 16