Low Profile, 500 mA, 6 MHz, Synchronous,
Step-Down, DC-to-DC Converter
ADP2125
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.
FEATURES
1.26 V fixed output voltage
Clock signal enable
6 MHz (maximum) operating frequency
500 mA continuous output current
Input voltage: 2.1 V to 5.5 V
0.3 µA (typical) shutdown supply current
Compatible with tiny multilayer inductors
Internal synchronous rectifier
Internal compensation
Internal soft start
Output-to-ground short-circuit protection
Current-limit protection
Undervoltage lockout
Thermal shutdown protection
Ultrasmall, 0.405 mm height (maximum), 6-ball BUMPED_CHIP
APPLICATIONS
Mobile phones
Digital still/video cameras
Digital audio
Portable equipment
Camera modules
Image stabilization systems
GENERAL DESCRIPTION
The ADP2125 is a high frequency, step-down, dc-to-dc
converter optimized for portable applications in which board
area and battery life are critical constraints. Fixed frequency
operation at 6 MHz enables the use of tiny ceramic inductors
and capacitors. Additionally, the synchronous rectification
improves efficiency and results in fewer external components.
Over all load currents, the device uses a voltage regulating
pulse-width modulation (PWM) mode that maintains a
constant frequency with excellent stability and transient
response. The ADP2125 is enabled by a 6 MHz to 27 MHz
external clock signal applied to the EXTCLK pin. When the
external clock is not switching and in a low state (EXTCLK ≤
0.5 V), the input is disconnected from the output and draws less
than 0.3 A (typical) from the source.
The ADP2125 has an input voltage range of 2.1 V to 5.5 V,
allowing the use of single Li+/Li polymer cell, three-cell
alkaline, NiMH cell, and other standard power sources. The
ADP2125 is internally compensated to minimize external
components and can source up to 500 mA. Other key features
such as cycle-by-cycle peak current limit, soft start, undervoltage
lockout (UVLO), output-to-ground short-circuit protection, and
thermal shutdown provide protection for internal and external
circuit components.
TYPICAL APPLICATION CIRCUIT
A2
C2
B2 A1
B1
C1
VIN
GND FB
SW
EXTCLK NC
NC = NO CONNECT
OFF ON
C
IN
2.2µF C
OUT
4.7µF
INPUT
VOLTAGE
2.1V TO 5.5V
L
1.5µH
ADP2125
OUTPUT
VOLTAGE
1.26V
08774-002
Figure 1.
ADP2125
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagram ........................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Considerations.............................................................. 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Overview ..................................................................................... 10
External Clock (EXTCLK) Enable........................................... 10
Internal Control Features.......................................................... 10
Protection Features .................................................................... 11
Timing Constraints .................................................................... 11
Applications Information.............................................................. 12
Inductor Selection...................................................................... 12
Input Capacitor Selection.......................................................... 12
Output Capacitor Selection....................................................... 13
Thermal Limit Calculations...................................................... 13
PCB Layout Guidelines.................................................................. 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
5/11—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 15
9/10—Revision 0: Initial Version
ADP2125
Rev. A | Page 3 of 16
SPECIFICATIONS
VIN = 3.6 V, VOUT = 1.26 V, TA = 25°C for typical specifications, and TA = TJ = −40°C to +85°C for minimum and maximum specifications,
unless otherwise noted. All specifications at temperature extremes are guaranteed via correlation using standard statistical quality control
(SQC) methods. Typical specifications are not guaranteed.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY
Operating Input Voltage Range VIN 2.1 5.5 V
Quiescent Current No load 8 mA
Shutdown Current VEXTCLK = 0 V, open-loop 0.3 1.5 µA
UNDERVOLTAGE LOCKOUT
Rising VIN Threshold 1.9 2.1 V
Falling VIN Threshold 1.5 1.8 V
OUTPUT
Continuous Output Current1 I
LOAD V
IN = 2.1 V to 5.5 V 500 mA
Output Accuracy2 VOUT V
IN = 2.3 V to 4.8 V VOUT − 2% VOUT + 2% V
FB Bias Current VFB = 1.2 V 4 9 µA
FB Pull-Down Resistance RDSCHG V
EXTCLK = 0 V, IFB = 10 mA 110 180 Ω
SWITCHING CHARACTERISTICS
PMOS On Resistance 180 340 mΩ
NMOS On Resistance 250 mΩ
SW Leakage Current VSW = 0 V, VIN = 5.5 V 10 µA
PMOS Switch Current Limit Open-loop 770 1000 1291 mA
Oscillator Frequency fSW 4.83 5.52 6 MHz
SHORT-CIRCUIT PROTECTION
Rising VOUT Threshold 0.55 0.7 V
Falling VOUT Threshold 0.4 0.52 V
EXTCLK INPUT
High Threshold Voltage VEXTCLK(H) V
IN = 2.5 V to 4.4 V 1.4 V
Low Threshold Voltage VEXTCLK(L) V
IN = 2.5 V to 4.4 V 0.5 V
Leakage Current VIN = 5.5 V, VEXTCLK = 2.1 V to 5.5 V 0.01 1 µA
Duty Cycle Operating Range DEXTCLK 40 60 %
Frequency Operating Range fEXTCLK 6 27 MHz
THERMAL SHUTDOWN
Thermal Shutdown Threshold 146 °C
Thermal Shutdown Hysteresis 13 °C
TIMING See Figure 2
VIN High to EXTCLK On1 t
1 V
IN = 2.1 V to 5.5 V 200 s
EXTCLK On to VOUT Rising t2 D
EXTCLK = 40% to 60%, fEXTCLK = 6 MHz 17 23 32 s
D
EXTCLK = 40% to 60%, fEXTCLK = 27 MHz 16 21 28 s
VOUT Power-Up Time (Soft Start)1 t
3 C
OUT = 4.7 µF, RLOAD = 3.6 Ω 105 200 s
EXTCLK Off to VOUT Falling t5 D
EXTCLK = 40% to 60%, fEXTCLK = 6 MHz to 27 MHz 4.1 11 s
VOUT Power-Down Time t6 C
OUT = 4.7 µF, RLOAD = 3.6 Ω 36 s
C
OUT = 4.7 µF, no load 1070 s
Minimum Shutdown Time1 t
5 + t6 C
OUT = 4.7 µF, no load 1400 s
Minimum Power-Off Time1 t
7 500 s
1 Guaranteed by design.
2 Transients not included in voltage accuracy specifications.
ADP2125
Rev. A | Page 4 of 16
TIMING DIAGRAM
t
6
t
7
t
5
t
3
t
2
t
1
V
OUT(NOM)
× 10%
V
IN
× 10%
V
IN
× 90%
VIN
V
OUT
EXTCLK
08774-003
Figure 2. I/O Timing Diagram
ADP2125
Rev. A | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VIN to GND −0.3 V to +6 V
EXTCLK to GND −0.3 V to +6 V
SW, NC to GND −0.3 V to VIN
FB (VIN ≥ 3.6 V) to GND −0.3 V to +3.6 V
FB (VIN < 3.6 V) to GND −0.3 V to VIN
Operating Ambient Temperature (TA) –40°C to +85°C1
Operating Junction Temperature (TJ)
at ILOAD = 500 mA
–40°C to +125°C
Soldering Conditions JEDEC J-STD-020
1 The maximum operating junction temperature (TJ(MAX)) supersedes the
maximum operating ambient temperature (TA(MAX)). See the Thermal
Considerations section for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination.
THERMAL CONSIDERATIONS
The maximum operating junction temperature (TJ(MAX))
supersedes the maximum operating ambient temperature
(TA(MAX)) because the ADP2125 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits.
In applications with high power dissipation and poor PCB
thermal resistance, the maximum ambient temperature may
need to be derated. In applications with moderate power
dissipation and good PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits.
The operating junction temperature (TJ) of the device is dependent
on the ambient temperature (TA), the power dissipation of the
device (PD), and the junction-to-ambient thermal resistance of
the package (θJA). TJ is calculated using the following formula:
TJ = TA + (PD × θJA) (1)
See the Applications Information section for further infor-
mation on calculating the operating junction temperature
for a specific application.
THERMAL RESISTANCE
θJA of the package is based on modeling and calculation using a
4-layer board. θJA is highly dependent on the application and
board layout. In applications where high maximum power dissi-
pation exists, attention to thermal board design is required. The
value of θJA may vary, depending on PCB material, layout, and
environmental conditions.
θJA is specified for worst-case conditions, that is, a device
soldered on a circuit board for surface-mount packages. θJA
is determined according to JEDEC Standard JESD51-9 on a
4-layer printed circuit board (PCB).
Table 3. Thermal Resistance
Package Type θJA Unit
6-Ball Bumped Bare Die, 4-Layer Board 120 °C/W
ESD CAUTION
ADP2125
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC VIN
SW
FB GND
08774-005
1
A
B
C
2
BALL
A
1
INDICATOR
EXTCLK
TOP VIEW
BALL SIDE DOWN
BUMPS ON OPPOSITE SIDE
(Not to Scale)
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
A1 NC No Connection. Any voltage applied to this pin must be between GND and VIN. Voltages above VIN or below GND
exceed the absolute maximum ratings and may cause damage to the part.
B1 SW Switch Node.
C1 FB Feedback Divider Input. Connect the output capacitor from FB to GND to set the output voltage ripple and to
complete the control loop.
A2 VIN Power Supply Input.
B2 EXTCLK External Clock Enable Signal. The ADP2125 powers up when a clock signal (6 MHz to 27 MHz) is detected on this pin.
C2 GND Ground.
ADP2125
Rev. A | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.6 V, fEXTCLK = 10 MHz, VOUT = 1.26 V, L = 1.8 µH (700 mA, 0603 package, LQM18PN1R8NC0), CIN = 2.2 µF (6.3 V, 0402 package,
X5R, GRM155R60J225ME15), COUT = 4.7 µF (4 V, 0402 package, X5R, GRM155R60G475ME47), and TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
1 10 100 1000
EFFICIENCY (%)
LOAD CURRENT (mA)
VIN = 2.1V
VIN = 2.7V
VIN = 3.6V
VIN = 4.8V
VIN = 5.5V
08774-104
Figure 4. Efficiency vs. Load Current
90
85
80
75
70
65
60
2.1 5.14.64.13.63.12.6
EFFICIENCY (%)
INPUT VOLTAGE (V)
I
LOAD
= 100mA
I
LOAD
= 250mA
I
LOAD
= 500mA
08774-105
Figure 5. Efficiency vs. Input Voltage
11
10
9
8
7
6
5
4
2.1 5.14.64.13.63.12.6
QUIESCENT CURRENT (mA)
INPUT VOLTAGE (V)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08774-106
Figure 6. Quiescent Current vs. Input Voltage
1.263
1.262
1.261
1.260
1.259
1.258
1.257
1 10 100 1000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
V
IN
= 2.1V
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.8V
V
IN
= 5.5V
08774-107
Figure 7. Output Voltage Accuracy
1.262
1.261
1.260
1.259
1.258
1.257
1.256
1.255
1 10 100 1000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08774-108
Figure 8. Output Voltage Accuracy over Temperature
2.1 5.14.64.13.63.12.6
0.9
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
SHUTDOWN CURRENT (µA)
INPUT VOLTAGE (V)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
SW = OPEN
08774-109
Figure 9. Shutdown Current vs. Input Voltage
ADP2125
Rev. A | Page 8 of 16
2.1 5.14.64.13.63.12.6
350
300
250
200
150
100
P-CHANNEL
R
DSON
(mΩ)
INPUT VOLTAGE (V)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
I
SW
= 500mA
08774-110
Figure 10. PMOS Drain-to-Source On Resistance
2.1 5.14.64.13.63.12.6
450
400
350
300
250
200
150
N-CHANNEL R
DSON
(mΩ)
INPUT VOLTAGE (V)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
I
SW
= 500mA
08774-111
Figure 11. NMOS Drain-to-Source On Resistance
2.1 5.14.64.13.63.12.6
6.0
5.8
5.6
5.4
5.2
5.0
FREQUENCY (MHz)
INPUT VOLTAGE (V)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08774-112
Figure 12. Switching Frequency vs. Input Voltage
1
2
LOAD CURRENT (200mA/DIV)
TIME (20µs/DIV)
OUTPUT VOLTAGE (20mV/DIV)
1.26V OFFSET
VIN = 2.1V
VOUT = 1.26V
08774-113
Figure 13. Load Transient Response, 250 mA to 420 mA, VIN = 2.1 V
1
2
LOAD CURRENT (200mA/DIV)
TIME (20µs/DIV)
OUTPUT VOLTAGE (50mV/DIV)
1.26V OFFSET
VIN = 3.6V
VOUT = 1.26V
08774-114
Figure 14. Load Transient Response, 250 mA to 420 mA, VIN = 3.6 V
1
2
LOAD CURRENT (200mA/DIV)
TIME (20µs/DIV)
OUTPUT VOLTAGE (50mV/DIV)
1.26V OFFSET
VIN = 5.5V
VOUT = 1.26V
08774-115
Figure 15. Load Transient Response, 250 mA to 420 mA, VIN = 5.5 V
ADP2125
Rev. A | Page 9 of 16
1
2
3
INDUCTOR CURRENT (200mA/DIV)
EXTCLK (5V/DIV)
TIME (20µs/DIV)
OUTPUT VOLTAGE (500mV/DIV)
VIN = 3.6V
VOUT = 1.26V
NO LOAD
08774-116
Figure 16. Startup, No Load
1
2
3
INDUCTOR CURRENT (200mA/DIV)
EXTCLK (5V/DIV)
TIME (20µs/DIV)
OUTPUT VOLTAGE (500mV/DIV)
VIN = 3.6V
VOUT = 1.26V
RLOAD = 3.6Ω
08774-117
Figure 17. Startup, RLOAD = 3.6 Ω
1
2
INDUCTOR CURRENT (1A/DIV)
TIME (200µs/DIV)
OUTPUT VOLTAGE (200mV/DIV)
08774-118
Figure 18. Output Short-Circuit Response
1
2
3
TIME (100ns/DIV)
OUTPUT VOLTAGE (10mV/DIV)
1.26V OFFSET
INDUCTOR CURRENT (200mA/DIV)
SWITCH PIN VOLTAGE (5V/DIV)
08774-119
V
IN
= 3.6V
Figure 19. Standard Operation
ADP2125
Rev. A | Page 10 of 16
THEORY OF OPERATION
SHOOT-
THROUGH
CONTROL
LOGIC
AND
PWM
CONTROL
THERMAL
SHUTDOWN
SOFT START
BANDGAP
BG
FB
BG
AGND
R1
FB
R2
V
OUT
AGND
AGND
FB
6MHz
OSCILLATOR
B2
THRESHOLD
DETECT
V
OUT
DISCHARGE
CLK
DETECT
SHORT-CIRCUIT
PROTECTION
COMPENSATION
EAMP
R
DSCHG
110Ω
RAMP
V(V
IN
)
ZXCOMP
PILIM
PDRIVE
PWM
COMP
PV
IN
C
IN
2.2µF
V
IN
2.1V TO 5.5V
AV
IN
NDRIVE
PREF
C
OUT
4.7µF
V
OUT
1.26
V
L
1.5µH
PGND
VIN
GND
SW
AGND
NREF
EXTCLK
ONOFF
C2
B1
A2
C1
GND TO V
IN
A1
NC
08774-006
Figure 20. Internal Block Diagram
OVERVIEW
The ADP2125 is a high efficiency, synchronous, step-down,
dc-to-dc converter that operates from a 2.1 V to 5.5 V input
voltage. It provides up to 500 mA of continuous output current
at a fixed output voltage. The 6 MHz operating frequency
enables the use of tiny external components. The internal
control schemes of the ADP2125 give excellent stability and
transient response. Other internal features such as cycle-by-
cycle peak current limiting, soft start, undervoltage lockout,
output-to-ground short-circuit protection, and thermal
shutdown provide protection for internal and external circuit
components.
EXTERNAL CLOCK (EXTCLK) ENABLE
The ADP2125 is enabled by a 6 MHz to 27 MHz clock signal
applied to the EXTCLK pin (see Figure 2 and Figure 20). The
ADP2125 internally detects the clock signal and allows the
converter to power up and the output voltage to rise to its
nominal value.
The ADP2125 can detect a nonswitching state and disable the
part whether the EXTCLK gates low or high. If the EXTCLK
signal gates low, the part is shut down, reducing the current
consumption to 0.3 µA (typical).
INTERNAL CONTROL FEATURES
Pulse-Width Modulation (PWM)
PWM forces the part to maintain a fixed frequency of 6 MHz
(maximum) over all load conditions. The ADP2125 uses a
hybrid proprietary voltage mode control scheme to control the
duty cycle over load current and line voltage variation. This
control provides excellent stability, transient response, and
output regulation.
Synchronous Rectification
In addition to the P-channel MOSFET switch, the ADP2125
includes an N-channel MOSFET switch to build the synchron-
ous rectifier. The synchronous rectifier improves efficiency,
especially for small load currents, and reduces cost and board
space by eliminating the need for an external rectifier.
Soft Start
To prevent excessive input inrush current at startup, the ADP2125
operates with an internal soft start. When EXTCLK begins to
oscillate, or when the part recovers from a fault (UVLO, TSD,
or SCP), a soft start timer begins. During this time, the peak
current limit is gradually increased to its maximum. The output
ADP2125
Rev. A | Page 11 of 16
t limit remains at
to operate.
ES
nt
power components during certain faults
e
et still
allows the converter to recover if the fault is removed.
voltage increases in stages to ensure that the converter is able to
start up effectively and in proper sequence. After the soft start
period expires, the peak PMOS switch curren
1 A (typical) and the part is able
PROTECTION FEATUR
Overcurrent Protection
To ensure that excessively high currents do not damage the
inductor, the ADP2125 incorporates cycle-by-cycle overcurre
protection. This function is accomplished by monitoring the
instantaneous peak current on the power PMOS switch. If this
current exceeds the PMOS switch current limit (1 A typical),
then the PMOS is immediately turned off. This minimizes the
potential for damage to
and transient events.
Output Short-Circuit Protection (SCP)
If the output voltage is shorted to GND, a standard dc-to-dc
controller delivers maximum power into that short. This may
result in a potentially catastrophic failure. To prevent this, th
ADP2125 senses when the output voltage is below the SCP
threshold (typically 0.55 V). At this point, the controller turns
off for approximately 450 µs and then automatically initiates a
soft start sequence. This cycle repeats until the short is removed
or the part is disabled. Figure 18 shows this operating behavior
of the ADP2125 during a short-circuit fault. The SCP dramati-
cally reduces the power delivered into the short circuit, y
Thermal Shutdown (TSD) Protection
The ADP2125 also includes TSD protection. If the die tempera-
ture exceeds 146°C (typical), the TSD protection activates and
turns off the power devices. They remain off until the die
temperature falls 13°C (typical), at which point the converter
restarts.
Undervoltage Lockout (UVLO)
If the input voltage is below the UVLO threshold, the ADP2125
automatically turns off the power switches and places the part
in a low power consumption mode. This prevents potentially
erratic operation at low input voltages. The UVLO levels have
approximately 100 mV of hysteresis to ensure glitch-free startup.
TIMING CONSTRAINTS
Shutdown Time
When the ADP2125 enters shutdown mode after the EXTCLK
signal is removed, the ADP2125 must remain in shutdown for a
minimum of 1400 µs, if no load is applied, before the EXTCLK
signal can be reapplied. This allows all internal nodes to
discharge to an off state.
Power-Off Time
When VIN drops, thereby triggering UVLO, the ADP2125 has a
minimum power-off time (t7) of 500 µs that must elapse before
VIN can be reapplied. This allows all supplies to discharge
enough power so that all internal devices are in an off state.
t
7
VIN × 10%
08774-021
Figure 21. Power-Off Time
ADP2125
Rev. A | Page 12 of 16
APPLICATIONS INFORMATION
The ADP2125 is designed to be compatible with chip inductors
and multilayer ceramic capacitors that are ideal for their small
footprint and low height. The recommended components for
this application may change as this technology advances. Table 5,
Table 6, and Table 7 list compatible inductors and capacitors.
This section describes the selection of external components.
The component value ranges are limited to optimize efficiency
and transient performance while maintaining stability over the
full operating range.
INDUCTOR SELECTION
The high switching frequency of the ADP2125 allows for minimal
output voltage ripple, even with small inductors. Inductor sizing
is a trade-off between efficiency and transient response. A small
value inductor leads to a larger inductor current ripple that
provides excellent transient response, but degrades efficiency. A
small footprint and low height chip inductor can be used for an
overall smaller solution size but has a higher dc resistance (DCR)
value and lower current rating that can degrade performance.
Shielded ferrite core inductors are recommended for their low
core losses and low electromagnetic interference (EMI). The
recommended inductor for the ADP2125 is 1.5 µH.
The inductor peak-to-peak current ripple, IL, can be calculated as
follows:
(
)
SW
IN
OUT
IN
OUT
LfLV
VVV
I××
−×
=Δ (2)
It is important that the inductor be capable of handling the
maximum peak inductor current, IPK, determined by the
following equation:
IPK = ILOAD(MAX) + IL/2 (3)
The dc current rating of the inductor should be greater than the
calculated IPK to prevent core saturation.
INPUT CAPACITOR SELECTION
The input capacitor must be rated to support the maximum
input operating voltage. Higher value input capacitors reduce
the input voltage ripple caused by the switch currents on the
VIN pin. Maximum rms input current for the application can
be calculated using the following equation:
()
IN
OUT
IN
OUT
MAXLOADCINMAXRMS V
VVV
II −×
×= )()(_ (4)
Place the input capacitor as close as possible to the VIN pin to
minimize supply noise.
In principle, different types of capacitors can be considered, but
for battery-powered applications, the best choice is the multi-
layer ceramic capacitor, due to its small size, low equivalent
series resistance (ESR), and low equivalent series inductance (ESL).
It is recommended that the VIN pin be bypassed with a 2.2 µF
input capacitor. The input capacitor can be increased without any
limit for better input voltage filtering. X5R or X7R dielectrics with
a voltage rating of 6.3 V or higher are recommended.
Table 5. Inductor Selection
Manufacturer Series Inductance (µH) DCR (mΩ) (typ) Current Rating (mA) Size (L × W × H) (mm) Package
Murata LQM18PN1R8NC0L 1.80 240 700 1.60 × 0.80 × 0.55 0603
LQM18PN1R5NB0L 1.50 350 600 1.60 × 0.80 × 0.40 0603
Taiyo Yuden CKP1608L1R5M 1.50 220 700 1.60 × 0.80 × 0.55 0603
Table 6. Input Capacitor Selection
Manufacturer Part Number Capacitance (F) Voltage Rating (V)
Temperature
Coefficient Size (L × W × H) (mm) Package
Murata GRM155R60J225ME95 2.2 6.3 X5R 1.0 × 0.5 × 0.5 0402
Taiyo Yuden JMK105BJ225MV-F 2.2 6.3 X5R 1.0 × 0.5 × 0.5 0402
TDK C1005X5R0J225M 2.2 6.3 X5R 1.0 × 0.5 × 0.5 0402
Table 7. Output Capacitor Selection
Manufacturer Part Numbers Capacitance (F) Voltage Rating (V)
Temperature
Coefficient Size (L × W × H) (mm) Package
Murata GRM155R60J475ME87 4.7 6.3 X5R 1.0 × 0.5 × 0.5 0402
GRM155R60G475ME47 4.7 4 X5R 1.0 × 0.5 × 0.5 0402
Taiyo Yuden AMK105BJ475MV-F 4.7 4 X5R 1.0 × 0.5 × 0.5 0402
TDK C1005X5R0J475M 4.7 6.3 X5R 1.0 × 0.5 × 0.5 0402
ADP2125
Rev. A | Page 13 of 16
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the converter. For a given loop
crossover frequency (the frequency at which the loop gain drops
to 0 dB), the maximum voltage transient excursion (overshoot)
is inversely proportional to the value of the output capacitor.
When choosing output capacitors, it is also important to account
for the loss of capacitance due to output voltage dc bias. This
may result in using a capacitor with a higher rated voltage to
achieve the desired capacitance value. Additionally, if ceramic
output capacitors are used, the capacitor rms ripple current
rating should always meet the application requirements. The
rms ripple current is calculated as follows:
()
(
)
)(
)(
32
1
MAXIN
SW
OUT
MAXIN
OUT
COUTRMS VfL
VVV
I××
−×
×= (5)
At nominal load currents, the converter operates in forced
PWM mode, and the overall output voltage ripple is the sum of the
voltage spike caused by the output capacitor ESR plus the voltage
ripple caused by charging and discharging the output capacitor.
VOUT = IL × (ESR + 1/(8 × COUT × fSW)) (6)
The largest voltage ripple occurs at the highest input voltage.
The ADP2125 is designed to operate with small 4.7 µF ceramic
capacitors that have low ESR and ESL. These components are
therefore able to meet tight output voltage ripple specifications.
X5R or X7R dielectrics with a voltage rating of 4 V or higher are
recommended.
THERMAL LIMIT CALCULATIONS
The operating junction temperature (TJ) of the device is
dependent on the ambient operating temperature (TA) of the
application, the power dissipation of the ADP2125 (PD), and the
junction-to-ambient thermal resistance of the package (θJA).
The operating junction temperature (TJ) is calculated using the
following equation:
TJ = TA + (PD × θJA) (7)
where θJA is 120°C/W, as provided in Table 3.
The ADP2125 can be damaged when the operating junction
temperature limits are exceeded. Monitoring ambient tempera-
ture does not guarantee that the junction temperature (TJ) is
within the specified temperature limits.
• In applications with high PD and poor PCB thermal
resistance, the maximum ambient temperature may need
to be derated.
• In applications with moderate PD and good PCB thermal
resistance, the maximum ambient temperature can exceed
the maximum limit as long as the junction temperature is
within specification limits.
The power dissipation (PD) of the ADP2125 is only a portion of
the power loss of the overall application. For a given application
with known operating conditions, the application power loss
can be calculated by combining the following equations for
power loss (PLOSS) and efficiency (η):
PLOSS = PIN − POUT (8)
100×=
IN
OUT
P
P
η
(9)
The resulting equation uses the output power and the efficiency
to determine the PLOSS.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−= 1
100
η
OUT
LOSS PP (10)
The power loss calculated using this approach is the combined
loss of the ADP2125 device (PD), the inductor (PL), input
capacitor (PCIN), and the output capacitor (PCOUT), as shown in
the following equation:
PLOSS = PD + PL + PCIN + PCOUT (11)
The power loss for the inductor, input capacitor, and output
capacitor can be calculated as follows:
PL = IRMS2 × DCR (12)
CIN
RMS
CIN ESR
I
P×
⎟
⎠
⎞
⎜
⎝
⎛
=
2
2 (13)
PCOUT = (∆IOUT)2 × ESRCOUT (14)
If multilayer chip capacitors with low ESR are used, the power
loss in the input and output capacitors is negligible and
PD + PL >> PCIN + PCOUT (15)
PLOSS ≈ PD + PL (16)
The final equation for calculating PD can be used in Equation 7
to ensure that the operating junction temperature is not
exceeded.
L
OUT
L
LOSS
DPPPPP −
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−≈−≈ 1
100
η
(17)
ADP2125
Rev. A | Page 14 of 16
PCB LAYOUT GUIDELINES
08774-022
Figure 22. ADP2125 Recommended Top Layer Layout
08774-023
Figure 23. ADP2125 Recommended Bottom Layer Layout
For high efficiency, good regulation, and stability, a well-
designed and manufactured PCB is required.
Use the following guidelines when designing PCBs:
• Keep the low ESR input capacitor, CIN, close to VIN
and GND.
• Keep high current traces as short and as wide as possible.
• Avoid routing high impedance traces near any node con-
nected to SW or near the inductor to prevent radiated
noise injection.
• Keep the low ESR output capacitor, COUT, close to the FB
and GND pins of the ADP2125. Long trace lengths from
the part to the output capacitor add series inductance that
may cause instability or increased ripple.
To ensure package reliability, consider the following guidelines
when designing the footprint for the ADP2125. The
BUMPED_CHIP device footprint must ultimately be
determined according to application and customer specific
reliability requirements, PCB fabrication quality, and PCB
assembly capabilities.
• The Cu pad on the PCB for each solder bump should be
80% to 100% of the width of the solder bump. A smaller
pad opening favors solder joint reliability (SJR) perfor-
mance, whereas a larger pad opening favors drop test
performance. The maximum pad size, including tolerance,
should not exceed 180 µm.
• Electroplated nickel, immersion gold (ENIG) and organic
solderability preservative (OSP) were used for internal
reliability testing and are recommended.
• Nonsolder mask defined (NSMD) Cu pads are recom-
mended for BUMPED_CHIP packages.
• The solder mask opening should be approximately 100 µm
larger than the pad opening.
• The trace width should be less than two-thirds the size of
the pad opening.
• The routing of traces from the Cu pads should be symmet-
rical in X and Y directions. Symmetrical routing of the
traces prevents part rotation due to uneven solder
wetting/surface tension forces.
• Stencil design is important for proper transfer of paste onto
the Cu pads. Area ratio (AR), the relationship between the
surface area of the stencil aperture and the inside surface
area of the aperture walls, is critically important. Stencil
thickness has the greatest impact on this ratio. AR values
from 0.66 to 0.8 provide the best paste transfer efficiency
and repeatability. The AR is calculated using the following
equation:
A
w
Ap
AR =
where:
Ap is the area of the aperture opening.
Aw is the wall area.
ADP2125
Rev. A | Page 15 of 16
OUTLINE DIMENSIONS
082409-A
0.40 BSC
0.115 TYP
0.170
TYP 0.80
BSC
1.340
1.300
1.260
0.940
0.900
0.860 SEATING
PLANE
0.405
0.390
0.375
0.40
BSC
A
12
B
C
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
BALL A1
IDENTIFIER
0.05 NOM
COPLANARITY
Figure 24. 6-Ball Bumped Bare Die Sales [BUMPED_CHIP]
(CD-6-2)
Dimensions shown in millimeters
08774-008
DIRECTION OF FEED
Figure 25. Tape and Reel Orientation for ADP2125
ORDERING GUIDE
Model1
Output
Voltage
Pin A1
Function
Temperature
Range Package Description
Package
Option2 Branding
ADP2125BCDZ-1.26R7 1.26 V NC −40°C to +85°C 6-Ball Bumped Bare Die [BUMPED_CHIP] CD-6-2 LEP
ADP2125B-1.26EVALZ 1.26 V NC Evaluation Board
1 Z = RoHS Compliant Part.
2 This package option is halide free.
ADP2125
Rev. A | Page 16 of 16
NOTES
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08774-0-5/11(A)
