MB90F867APFV - Fujitsu Quantum Devices Limited

DS07-13732-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90860A Series

MB90F867A (S) , MB90867A (S)

■DESCRIPTION

The MB90860A-series is Fujitsu 16-bit general-purpose microcontroller which enhances each kind of timers and

communication macros . With the new 0.35 µm CMOS technolog y, Fujitsu now off ers 128 Kbytes on-chip FLASH-

ROM program memory. An internal voltage booster removes the necessity for a second programming voltage.

The power supply (3 V) is supplied to the inter nal MCU core from an internal regulator circuit. This creates a

major advantage in terms of EMI and power consumption.

The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external

4 MHz clock.

The unit f eatures an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free

running timers. 4 UARTs constitute additional functionality for communication purposes.

Note : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

■PACKAGES

100-pin Plastic QFP 100-pin Plastic LQFP

(FPT-100P-M06) (FPT-100P-M05)

MB90860A Series

■FEATURES

•

••

• Clock

• Built-in PLL clock frequency multiplication circuit

• Selection of machine clocks (PLL cloc ks) is allow ed among frequency division by two on oscillation cloc k, and

multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).

• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without

S-suffix only)

• Minimum ex ecution time of instruction : 42 ns (when operating with 4-MHz oscillation cloc k, and 6-time m ulti-

plied PLL clock).

•

••

• 16 Mbyte CPU memory space

• 24-bit internal addressing

•

••

• Instruction system best suited to controller

• Wide choice of data types (bit, byte, word, and long word)

• Wide choice of addressing modes (23 types)

• Enhanced multiply-divide instructions and RETI instructions

• Enhanced high-precision computing with 32-bit accumulator

•

••

• Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Enhanced various pointer indirect instructions

• Barrel shift instructions

•

••

• Increased processing speed

• 4-byte instruction queue

•

••

• Powerful interrupt function

• Powerful 8-level, 34-condition interrupt feature

• Up to 16 external interrupts are supported

•

••

• Automatic data transfer function independent of CPU

• Extended intelligent I/O service function (EI2OS) : up to 16 channels

• DMA : up to 16 channels

•

••

• Low power consumption (standby) mode

• Sleep mode (a mode that halts CPU operating clock)

• Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only)

• Watch mode (a mode that operates sub clock and clock timer only)

• Stop mode (a mode that stops oscillation clock and sub clock)

• CPU blocking operation mode

•

••

• Pr ocess

•CMOS technology

•

••

• I/O port

• General-purpose input/output port (CMOS output)

- 80 ports (devices without S-suffix)

- 82 ports (devices with S-suffix)

(Continued)

MB90860A Series

(Continued)

•

••

• Timer

• Time-base timer, clock timer, watchdog timer : 1 channel

• 8/16-bit PPG timer : 8-bit X 16 channels, or 16-bit X 8 channels

• 16-bit reload timer : 4 channels

• 16- bit input/output timer

- 16-bit free run timer : 2 channel (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)

- 16- bit input capture: (ICU) : 8 channels

- 16-bit output compare : (OCU) : 8 channels

•

••

• UART (LIN/SCI) : 4 channels

• Equipped with full-duplex double buffer

• Clock-asynchronous or clock-synchronous serial transmission is available

•

••

• I2C interface* : 2 channels

• Up to 400 kbit/s transfer rate

•

••

• DTP/External interrupt : 16 channels, CAN wakeup : 2 channels

• Module for activation of extended intelligent I/O service (EI2OS), DMA, and generation of external interrupt.

•

••

• Delay interrupt generator module

• Generates interrupt request for task switching.

•

••

• 8/10-bit A/D converter : 24 channels

• Resolution is selectable between 8-bit and 10-bit.

• Activation by external trigger input is allowed.

• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)

•

••

• Program patch function

• Address matching detection for 6 address pointers.

•

••

• Internal voltage regulator

• Supports 3 V MCU core, offering low EMI and low power consumption figures

•

••

• Programmable input levels

• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)

• TTL level (initial level for External bus mode)

•

••

• ROM security function

• Protects the content of ROM (MASK ROM device only)

•

••

• Flash security function

• Protects the content of Flash (Flash device only)

•

••

• External bus interface

•

••

• Clock monitor function

* : I2C license :

Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these com-

ponents in an I2C system provided that the system conforms to the I2C standard Specification as defined by

Philips.

MB90860A Series

■PRODUCT LINEUP

(Continued)

Part Number

Parameter MB90F867A (S) , MB90867A (S) MB90V340(S)

CPU F2MC-16LX CPU

System clock On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)

ROM Boot-block,Flash memory

128 Kbytes External

RAM 6 Kbytes 30 Kbytes

Emulator-specific

power supply*1Yes

Technology 0.35 µm CMOS with on-chip voltage regulator for internal

power supply + Flash memory with

On-chip charge pump for programming voltage

0.35 µm CMOS with

on-chip voltage regulator

for internal power supply

Operating

voltage range

3.5 V to 5.5 V : at normal operating (not using A/D converter)

4.0 V to 5.5 V : at using A/D converter/Flash programming

4.5 V to 5.5 V : at using external bus 5 V ± 10%

Temperature range −40 °C to +105 °C

Package QFP-100, LQFP-100 PGA-299

UART

4 channels 5 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

I2C (400 Kbit/s) 2 channel

A/D

Converter

24 input channels

10-bit or 8-bit resolution

Conversion time : Min 3 µs include sample time (per one channel)

16-bit Reload Timer

(4 channels) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)

Supports External Event Count function

16-bit

I/O Timer

(2 channels)

Signals an interrupt when overflowing

Supports Timer Clear when a match with Output Compare (Channel 0, 4)

Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27

(fsys = Machine clock freq.)

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3

I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7

16-bit Output

Compare

(8 channels (16-bit) /

16 channels (8-bit) )

Signals an interrupt when 16-bit I/O Timer match output compare registers.

A pair of compare registers can be used to generate an output signal.

16-bit Input Capture

(8 channels) Rising edge, falling edge or rising & falling edge sensitive

Signals an interrupt upon external event

MB90860A Series

(Continued)

*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

Part Number

Parameter MB90F867A (S) , MB90867A (S) MB90V340(S)

8/16-bit

Programmable Pulse

Generator

(8 channels)

Supports 8-bit and 16-bit operation modes

Sixteen 8-bit reload counters

Sixteen 8-bit reload registers for L pulse width

Sixteen 8-bit reload registers for H pulse width

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler plus 8-bit reload counter

Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz

(fsys = Machine clock frequency, fosc = Oscillation clock frequency)

CAN Interface 3 channels

External Interrupt

(16 channels) Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

expanded inteligent I/O services (EI2OS) and DMA

D/A converter 2 channels

Up to100 kHz

Subclock for low

power operation

devices with ‘S’-suffix : without subclock

devices without ‘S’-suffix : with subclock

I/O Ports

Virtually all external pins can be used as general purpose I/O port

All push-pull outputs

Bit-wise settable as input/output or peripheral signal

Settable in pin-wise of 8 as CMOS schmitt trigger/ automotive inputs (default)

TTL input level settable for external bus (32-pin only for external bus)

Flash

Memory

Supports automatic programming, Embedded AlgorithmTM*2

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of erase cycles : 10,000 times

Data retention time : 10 years

Boot block configuration

Erase can be performed on each block

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash



ROM Security Protects the content of ROM (MASK ROM device only) 

MB90860A Series

■PIN ASSIGNMENTS

•MB90F867A (S) , MB90867A (S)

(Continued)

(TOP VIEW)

(FPT-100P-M06)

100

50P04/AD04/INT12

P23/A19/PPGF(E)

P22/A18/PPGD(C)

P21/A17/PPGB(A)

P20/A16/PPG9(8)

P17/AD15

P16/AD14

P15/AD13

Vss

Vcc

P14/AD12/SCK3

P13/AD11/SOT3

P12/AD10/SIN3/NT11R

P11/AD09/TOT1

P10/AD08/TIN1

P07/AD07/INT15

P06/AD06/INT14

P05/AD05/INT13

P75/AN21/INT5

P03/AD03/INT11

P02/AD02/INT10

P01/AD01/INT9

P00/AD00/INT8

PA1

PA0/INT8R

P97/OUT3

P96/OUT2

P95/OUT1

P94/OUT0

P93/PPG7(6)

P92/PPG5(4)

P91/PPG3(2)

P90/PPG1(0)

Vss

Vcc

P87/SCK1

P86/SOT1

P85/SIN1

P84/SCK0/INT15R

P83/SOT0/TOT2

P82/SIN0/TIN2/INT14R

P81/TOT0/CKOT/INT13R

P80/TIN0/ADTG/INT12R

P77/AN23/INT7

P76/AN22/INT6

MD0

MD1

MD2

P24/A20/IN0

P25/A21/IN1

P26/A22/IN2

P27/A23/IN3

P30/ALE/IN4

P34/HRQ/OUT4

P56/AN14

P55/AN13

P54/AN12/TOT3

P53/AN11/TIN3

P52/AN10/SCK2

P51/AN9/SOT2

P50/AN8/SIN2

P47/SCL1

P46/SDA1

P45/SCL0/FRCK1

P44/SDA0/FRCK0

P43/IN7

P42/IN6/INT9R

Vss

Vcc

P41/X1 A*

P40/X0 A*

P37/CLK/OUT7

P36/RDY/OUT6

QFP - 100

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

P74/AN20/INT4

P73/AN19/INT3

P72/AN18/INT2

P71/AN17/INT1

P70/AN16/INT0

P67/AN7/PPGE(F)

P66/AN6/PPGC(D)

P65/AN5/PPGA(B)

P64/AN4/PPG8(9)

P61/AN1/PPG2(3)

AVss

P57/AN15

AVcc

P60/AN0/PPG0(1)

AVRL

AVRH

Vss

P62/AN2/PPG4(5)

P63/AN3/PPG6(7)

RST

P31/RD/IN5

P33/WRH

P35/HAK/OUT5

P32/WRL/WR/INT10R

* : MB90F867A, MB90867A : X0A, X1A

MB90F867AS, MB90867AS : P40, P41

MB90860A Series

(Continued)

(TOP VIEW)

(FPT-100P-M05)

P04/AD04/INT12

P23/A19/PPGF(E)

P22/A18/PPGD(C)

P21/A17/PPGB(A)

P20/A16/PPG9(8)

P17/AD15

P16/AD14

P15/AD13

Vss

Vcc

P14/AD12/SCK3

P13/AD11/SOT3

P12/AD10/SIN3/NT11R

P11/AD09/TOT1

P10/AD08/TIN1

P07/AD07/INT15

P06/AD06/INT14

P05/AD05/INT13

P00/AD00/INT8

PA1

PA0/INT8R

P97/OUT3

P96/OUT2

P95/OUT1

P94/OUT0

P93/PPG7(6)

P92/PPG5(4)

P91/PPG3(2)

P90/PPG1(0)

Vss

Vcc

P87/SCK1

P86/SOT1

P85/SIN1

P84/SCK0/INT15R

P83/SOT0/TOT2

P82/SIN0/TIN2/INT14R

P81/TOT0/CKOT/INT13R

P80/TIN0/ADTG/INT12R

P77/AN23/INT7

P76/AN22/INT6

MD0

P26/A22/IN2

P27/A23/IN3

P30/ALE/IN4

P34/HRQ/OUT4

P53/AN11/TIN3

P52/AN10/SCK2

P51/AN9/SOT2

P50/AN8/SIN2

P47/SCL1

P46/SDA1

P45/SCL0/FRCK1

P44/SDA0/FRCK0

P43/IN7

P42/IN6//INT9R

Vss

Vcc

P41/X1A*

P40/X0A*

P37/CLK/OUT7

P36/RDY/OUT6

99P24/A20/IN0 100P25/A21/IN1

28 P56/AN14

27 P55/AN13

26 P54/AN12/TOT3

49 MD2

50 MD1

78P03/AD03/INT11 77P02/AD02/INT10 76P01/AD01/INT9

LQFP - 100

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

12345678910111213141516171819202122232425

P75/AN21/INT5

P74/AN20/INT4

P73/AN19/INT3

P72/AN18/INT2

P71/AN17/INT1

P70/AN16/INT0

Vss

P67/AN7/PPGE(F)

P66/AN6/PPGC(D)

P65/AN5/PPGA(B)

P64/AN4/PPG8(9)

P63/AN3/PPG6(7)

P62/AN2/PPG4(5)

P61/AN1/PPG2(3)

P60/AN0/PPG0(1)

AVss

AVRL

AVRH

AVcc

P57/AN15

RST

P31/RD/IN5

P33/WRH

P35/HAK/OUT5

P32/WRL/WR/INT10R

* : MB90F867A, MB90867A : X0A, X1A

MB90F867AS, MB90867AS : P40, P41

MB90860A Series

■PIN DESCRIPTION

(Continued)

Pin No. Pin name Circuit

type Function

LQFP100*2QFP100*1

90 92 X1 AOscillation output

91 93 X0 Oscillation input

52 54 RST E Reset input

75 to 82 77 to 84

P00 to P07

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

AD00 to AD07 I/O pins for 8 lower bits of the external address/data bus.

This function is enabled when the external bus is enabled.

INT8 to INT15 External interrupt request input pins for INT8 to INT15.

83 85

P10

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

AD08 I/O pin for bit 8 of the external address/data bus.

This function is enabled when the external bus is enabled.

TIN1 Event input pin for the reload timer 1

84 86

P11

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

AD09 I/O pin for bit 9 of the external address/data bus.

This function is enabled when the external bus is enabled.

TOT1 Output pin for the reload timer 1

85 87

P12

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

AD10 I/O pin for bit 10 of the external address/data bus.

This function is enabled when the external bus is enabled.

SIN3 Serial data input pin for UART3

INT11R Sub external interrupt request input pin for INT11

86 88

P13

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

AD11 I/O pin for bit 11 of the external address/data bus.

This function is enabled when the external bus is enabled.

SOT3 Serial data output pin for UART3

87 89

P14

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

AD12 I/O pin for bit 12 of the external address/data bus.

This function is enabled when the external bus is enabled.

SCK3 Clock I/O pin for UART3

MB90860A Series

(Continued)

Pin No. Pin name Circuit

type Function

LQFP100*2QFP100*1

92 94

P15

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

AD13 I/O pin for bit 13 of the external address/data bus.

This function is enabled when the external bus is enabled.

SIN4 Serial data input pin for UART4 (MB90V340 only)

93 95

P16

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

AD14 I/O pin for bit 14 of the external address/data bus.

This function is enabled when the external bus is enabled.

SOT4 Serial data output pin for UART4 (MB90V340 only)

94 96

P17

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

AD15 I/O pin for bit 15 of the external address/data bus. This function

is enabled when the external bus is enabled.

SCK4 Clock I/O pin for UART4 (MB90V340 only)

95 to 98 97 to 100

P20 to P23

General purpose I/O. The register can be set to select whether

to use a pull-up resistor.In external bus mode, the pin is

enabled as a general-purpose I/O port when the corresponding

bit in the external address output control register (HACR) is 1.

A16 to A19

Output pins for A16 to A19 of the external address bus. When

the corresponding bit in the external address output control

output pins (A16 to A19).

PPG9,PPGB,

PPGD,PPGF Output pins for PPGs

99 to 2 1 to 4

P24 to P27

General purpose I/O. The register can be set to select whether

to use a pull-up resistor.In external bus mode, the pin is

enabled as a general-purpose I/O port when the corresponding

bit in the external address output control register (HACR) is 1.

A20 to A23

Output pins for A20 to A23 of the external address bus. When

the corresponding bit in the external address output control

output pins (A20 to A23).

IN0 to IN3 Data sample input pins for input captures ICU0 to ICU3

P30

General purpose I/O.The register can be set to select whether

to use a pull-up resistor.This function is enabled in single-chip

mode.

ALE Address latch enable output pin. This function is enabled when

the external bus is enabled.

IN4 Data sample input pin for input capture ICU4

MB90860A Series

(Continued)

Pin No. Pin name Cir cuit

type Function

LQFP100*2QFP100*1

P31

General purpose I/O.The register can be set to select whether to

use a pull-up resistor.This function is enabled in single-chip

mode.

RD Read strobe output pin for the data bus. This function is enabled

when the external bus is enabled.

IN5 Data sample input pin for input capture ICU5

P32

General purpose I/O. The register can be set to select whether to

use a pull-up resistor. This function is enabled either in single-chip

mode or with the WR/WRL pin output disabled.

WRL / WR

Write strobe output pin for the data bus. This function is enabled

when both the external bus and the WR/WRL pin output are en-

abled. WRL is used to write-strobe 8 lower bits of the data bus in

16-bit access while WR is used to write-strobe 8 bits of the data

bus in 8-bit access.

RX2 RX input pin for CAN2 Interface (MB90V340 only)

INT10R Sub external interrupt request input pin for INT10

P33

General purpose I/O. The register can be set to select whether to

use a pull-up resistor.This function is enabled either in single-chip

mode or with the WRH pin output disabled.

WRH

Write strobe output pin for the 8 higher bits of the data bus. This

function is enabled when the external bus is enabled, when the

external bus 16-bit mode is selected, and when the WRH output

pin is enabled.

TX2 TX Output pin for CAN2 (MB90V340 only)

P34

General purpose I/O. The register can be set to select whether to

use a pull-up resistor. This function is enabled either in single-chip

mode or with the hold function disabled.

HRQ Hold request input pin. This function is enabled when both the ex-

ternal bus and the hold function are enabled.

OUT4 Waveform output pin for output compare OCU4

810

P35

General purpose I/O. The register can be set to select whether to

use a pull-up resistor. This function is enabled either in single-chip

mode or with the hold function disabled.

HAK Hold acknowledge output pin. This function is enabled when both

the external bus and the hold function are enabled.

OUT5 Waveform output pin for output compare OCU5

911

P36

General purpose I/O. The register can be set to select whether to

use a pull-up resistor. This function is enabled either in single-chip

mode or with the external ready function disabled.

RDY Ready input pin. This function is enabled when both the

external bus and the external ready function are enabled.

OUT6 Waveform output pin for output compare OCU6

MB90860A Series

(Continued)

Pin No. Pin name Circuit

type Function

LQFP100*2QFP100*1

10 12

P37

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled either in

single-chip mode or with the CLK output disabled.

CLK CLK output pin. This function is enabled when both the

external bus and CLK output are enabled.

OUT7 Waveform output pin for output compare OCU7

11 to 12 13 to 14 P40 , P41 F General purpose I/O (devices with S-suffix)

X0A , X1A B Oscillator input pins for sub-clock (devices without S-suffix)

16 18

P42

General purpose I/O

IN6 Data sample input pin for input capture ICU6

RX1 RX input pin for CAN1 (MB90V340 (S) only)

INT9R Sub external interrupt request input pin for INT10

17 19 P43 FGeneral purpose I/O

IN7 Data sample input pin for input capture ICU7

TX1 TX Output pin for CAN1 (MB90V340 (S) only)

18 20 P44 HGeneral purpose I/O

SDA0 Serial data I/O pin for I 2C 0

FRCK0 Input for the 16-bit I/O Timer 0

19 21 P45 HGeneral purpose I/O

SCL0 Serial clock I/O pin for I2C 0

FRCK1 Input for the 16-bit I/O Timer 1

20 22 P46 HGeneral purpose I/O

SDA1 Serial data I/O pin for I 2C 1

21 23 P47 HGeneral purpose I/O

SCL1 Serial clock I/O pin for I2C 1

22 24 P50 OGeneral purpose I/O

AN8 Analog input pin for the A/D converter

SIN2 Serial data input pin for UART2

23 25 P51 IGeneral purpose I/O

AN9 Analog input pin for the A/D converter

SOT2 Serial data output pin for UART2

24 26 P52 IGeneral purpose I/O

AN10 Analog input pin for the A/D converter

SCK2 Clock I/O pin for UART2

25 27 P53 IGeneral purpose I/O

AN11 Analog input pin for the A/D converter

TIN3 Event input pin for the reload timer 3

MB90860A Series

(Continued)

Pin No. Pin name Circuit

type Function

LQFP100*2QFP100*1

26 28 P54 IGeneral purpose I/O

AN12 Analog input pin for the A/D converter

TOT3 Output pin for the reload timer 3

27 29 P55 IGeneral purpose I/O

AN13 Analog input pin for the A/D converter

28, 29 30, 31 P56 to P57 JGeneral purpose I/O

AN14 to AN15 Analog input pin for the A/D converter

DA00 to DA01 D/A converter analog output pins (MB90V340 only)

34 to 41 36 to 43

P60 to P67

General purpose I/O

AN0 to AN7 Analog input pins for the A/D converter

PPG0, 2, 4, 6,

8, A, C, E Output pins for PPGs

43 to 48,

53, 54 45 to 50,

55, 56

P70 to P77 IGeneral purpose I/O

AN16 to AN23 Analog input pins for the A/D converter (devices with C-suffix)

INT0 to INT7 External interrupt request input pins for INT0 to INT7

55 57

P80

General purpose I/O

TIN0 Event input pin for the reload timers 0

ADTG Trigger input pin for the A/D converter

INT12R Sub external interrupt request input pin for INT12

56 58

P81

General purpose I/O

TOT0 Output pin for the reload timer 0

CKOT Output pin for the clock monitor

INT13R Sub external interrupt request input pin for INT13

57 59

P82

General purpose I/O

SIN0 Serial data input pin for UART0

TIN2 Event input pin for the reload timers 2

INT14R Sub external interrupt request input pin for INT14

58 60 P83 FGeneral purpose I/O

SOT0 Serial data output pin for UART0

TOT2 Output pin for the reload timer 2

59 61 P84 FGeneral purpose I/O

SCK0 Clock I/O pin for UART0

INT15R Sub external interrupt request input pin for INT15

60 62 P85 MGeneral purpose I/O

SIN1 Serial data input pin for UART1

61 63 P86 FGeneral purpose I/O

SOT1 Serial data output pin for UART1

MB90860A Series

(Continued)

*1 : FPT-100P-M06

*2 : FPT-100P-M05

Pin No. Pin name Circuit

type Function

LQFP100*2QFP100*1

62 64 P87 FGeneral purpose I/O

SCK1 Clock I/O pin for UART1

65 to 68 67 to 70 P90 to P93 FGeneral purpose I/O

PPG1, 3, 5, 7 Output pins for PPGs

69 to 72 71 to 74

P94 to P97

General purpose I/O

OUT0 to

OUT3

Waveform output pins for output compares OCU0 to OCU3.

This function is enabled when the OCU enables waveform

output.

73 75 PA0 FGeneral purpose I/O

RX0 RX input pin for CAN0 (MB90V340 (s) only)

INT8R Sub external interrupt request input pin for INT8

74 76 PA1 FGeneral purpose I/O

TX0 TX Output pin for CAN0 (MB90V340 (s) only)

30 32 AVCC K Vcc power input pin for analog circuits

31 33 AVRH L Reference voltage input for the A/D Converter. This power

supply must be turned on or off while a voltage higher than or

equal to AVRH is applied to AVCC.

32 34 AVRL K Lower reference voltage input for the A/D Converter

33 35 AVSS K Vss power input pin for analog circuits

50, 51 52, 53 MD1, MD0 C Input pins for specifying the operating mode. The pins must be

directly connected to Vcc or Vss

49 51 MD2 D Input pin for specifying the operating mode. The pins must be

directly connected to Vcc or Vss.

90 VCC Power (3.5 V to 5.5 V) input pins

VSS Power (0V) input pins

15 17 C K This is the power supply stabilization capacitor pin. It should be

connected to a higher than or equal to 0.1 µF ceramic capaci-

tor.

MB90860A Series

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

Oscillation circuit

• High-speed oscillation feedback

resistor = approx. 1 MΩ

Oscillation circuit

• Low-speed oscillation feedback

resistor = approx. 10 MΩ

Mask ROM and EVA device:

• CMOS Hysteresis input pin

Flash device:

• CMOS input pin

Mask ROM and EVA device:

• CMOS Hysteresis input pin

• Pull-down resistor v alule: approx. 50 kΩ

Flash device:

• CMOS input pin

• No Pull-down

CMOS Hysteresis input pin

• Pull-up resistor valule: approx. 50 kΩ

Standby control signal

Xout

Standby control signal

X1A

X0A

Xout

Hysteresis

inputs

Pull-down

Resistor

Hysteresis

inputs

Pull-up

Resistor

Hysteresis

inputs

MB90860A Series

(Continued)

Type Circuit Remarks

• CMOS level output(IOL = 4 mA, IOH = −4 mA)

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

• CMOS level output(IOL = 4 mA, IOH = −4 mA)

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

• TTL input (With the standby-time input

shutdown function)

• Programmalble pullup resistor: 50 kΩ

approx.

• CMOS level output(IOL = 3 mA, IOH = −3 mA)

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

Hysteresis inputs

Automotive inputs

Standby control for

input shutdown

Pout

Nout

pull-up control

Hysteresis inputs

Automotive inputs

TTL input

Standby control for

input shutdown

Pout

Nout

Hysteresis inputs

Automotive inputs

Standby control for

input shutdown

Pout

Nout

MB90860A Series

(Continued)

Type Circuit Remarks

• CMOS level output(IOL = 4 mA, IOH = −4 mA)

• CMOS hysteresis inputs (With the standby-

time input shutdown function)

• Automotive input (With the standby-time in-

put shutdown function)

• A/D analog input

• CMOS level output(IOL = 4 mA, IOH = −4 mA)

• D/A analg output

• CMOS hysteresis inputs (With the standby-

time input shutdown function)

• Automotive input (With the standby-time in-

put shutdown function)

• A/D analog input

• Power supply input protection circuit

• A/D converter reference voltage power

supply input pin, with the protection circuit

• Flash de vices do not ha v e a protection cir-

cuit against VCC for pin AVRH

Hysteresis inputs

Automotive inputs

Standby control for

input shutdown

Analog input

Pout

Nout

Hysteresis inputs

Automotive inputs

Standby control for

input shutdown

Analog input

Analog output

Pout

Nout

ANE

AVR

ANE

MB90860A Series

(Continued)

Type Circuit Remarks

• CMOS level output(IOL = 4 mA, IOH = −4 mA)

• CMOS inputs (With the standby-time

input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

• CMOS level output(IOL = 4 mA, IOH = −4 mA)

• CMOS inputs (With the standby-time

input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

• TTL input (With the standby-time input

shutdown function)

Programmable pullup registor:50 kΩ

approx.

• CMOS level output(IOL = 4 mA, IOH = −4 mA)

• CMOS inputs (With the standby-time

input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

• A/D analog input

CMOS inputs

Automotive inputs

Standby control for

input shutdown

Pout

Nout

pull-up control

CMOS inputs

Automotive inputs

TTL input

Standby control for

input shutdown

Pout

Nout

CMOS inputs

Automotive inputs

Standby control for

input shutdown

Analog input

Pout

Nout

MB90860A Series

■HANDLING DEVICES

Special care is required for the following when handling the device :

• Preventing latch-up

• Treatment of unused pins

• Using external clock

• Precautions for when not using a sub clock signal

• Notes on during operation of PLL clock mode

• Power supply pins (VCC/VSS)

• Pull-up/down resistors

• Crystal Oscillator Circuit

• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

• Connection of Unused Pins of A/D Converter

• Notes on Energization

• Stabilization of power supply voltage

• Initialization

• Port0 to port3 output during Power-on(External-bus mode)

• Flash security Function

1. Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than VCC or lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between VCC and VSS.

•The AVCC power supply is applied before the VCC voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

F or the same reason, also be careful not to let the analog power-supply v oltage (AVCC, AVRH) e xceed the digital

power-supply voltage.

2. Treatment of unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the

device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should

be more than 2 kΩ .

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above

described connection.

3. Using external clock

To use external clock, drive the X0 pin and leave X1 pin open.

4. Precautions for when not using a sub clock signal

If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the

X1A pin open.

MB90860A Series

Open

MB90860A Series

5. Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be w orking with the self-oscillating circuit e ven

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

6. Power supply pins (VCC/VSS)

• If there are multiple VCC and VSS pins, from the point of vie w of device design, pins to be of the same potential

are connected the inside of the device to prevent such malfunctioning as latch up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,

and observe the standard f or total output current, be sure to connect the VCC and VSS pins to the po wer supply

and ground externally.

• Connect VCC and VSS to the device from the current supply source at a low impedance.

• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between

VCC and VSS in the vicinity of VCC and VSS pins of the device

7. Pull-up/down resistors

The MB90860A Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).

Use external components where needed.

8. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and

make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground

area for stabilizing the operation.

9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D conver ter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23)

after turning-on the digital power supply (VCC) .

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure

that the v oltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously

is acceptable) .

10. Connection of Unused Pins of A/D Converter if A/D Converter is used

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.

Vcc

Vss

Vcc

Vss

Vcc

MB90860A

Series

Vcc Vss

Vcc

Vss

MB90860A Series

11. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at

50 µs or more (0.2 V to 2.7 V)

12. Stabilization of power supply voltage

A sudden change in the supply voltage may cause the de vice to malfunction ev en within the specified VCC supply

voltage operating range. Therefore, the VCC supply voltage should be stabilized.

For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at

commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient

of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.

13. Initialization

In the device, there are internal registers which are initialized only by a power-on reset. T o initialize these registers,

turn on the power again.

14. Port 0 to port 3 output during Power-on (External-bus mode)

As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of

Port 0 to Port 3 might be unstable.

15. Flash security Function

The security byte is located in the area of the flash memory.

If protection code 01H is written in the security byte, the flash memory is in the protected state by security.

Therefore please do not write 01H in this address if you do not use the security function.

Please refer to following table for the address of the security byte.

Flash memory size Address for security byte

MB90F867A (S) Embedded 1 Mbit Flash Memory FE0001H

V 5

V 3

Port0 to Port3

Port0 to 3 outputs

might be unstable Port0 to 3 outputs = Hi-Z

MB90860A Series

■BLOCK DIAGRAMS

MB90V340(S)

RAM 30 K

UART

Prescaler

10-bit ADC

24 ch

16-bit Reload

Timer 4 ch

IO Timer 0

Clock

Controller

Input

Capture

8 ch

Output

Compare

8 ch

CAN

Controller

External

Interrupt

16LX

CPU

FMC-16 Bus

X0,X1

RST

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

AVCC

AVSS

AN23 to AN0

AVRH

AVRL

ADTG

TIN3 to TIN0

TOT3 to TOT0

IN7 to IN0

OUT7 to OUT0

RX2 to RX0

TX2 to TX0

INT15 to INT8

External

Bus

Interface

AD15 to AD00

A23 to A16

ALE

WRL

WRH

HRQ

HAK

RDY

CLK

X0A,X1A*

5 ch

10-bit

DAC

2 ch

DA01, DA00

IO Timer 1

FRCK0

FRCK1

8/16-bit

PPG

16 ch

PPGF to PPG0

I2C

Interface

SDA1, SDA0

SCL1, SCL0

3 ch

5 ch

2 ch

DMAC

* : Only for MB90V340 ( without ‘S’ Suffix )

Clock

Monitor CKOT

(INT15R to INT8R)

INT7 to INT0

MB90860A Series

MB90F867A (S) , MB90867A (S)

RAM

ROM/Flash

UART

Prescaler

10-bit ADC

16/24 ch

IO Timer 0

Clock

Controller

Input

Capture

8 ch

Output

Compare

8 ch

External

Interrupt

16LX

CPU

FMC-16 Bus

X0,X1

RST

SOT3 to SOT0

SCK3 to SCK0

SIN3 to SIN0

AVCC

AVSS

AN15 to AN0

AVRH

AVRL

ADTG

IN7 to IN0

OUT7 to OUT0

INT15 to INT8

External

Bus

Interface

AD15 to AD00

A23 to A16

ALE

WRL

WRH

HRQ

HAK

RDY

CLK

X0A,X1A*

128 K

4 ch

IO Timer 1

FRCK0

FRCK1

8/16-bit

PPG

16 ch

PPGF to PPG0

4 ch

I2C

Interface

SDA1, SDA0

SCL1, SCL0

2 ch

AN23 to AN16

6 K

DMAC

* : Only for devices without ‘S’ Suffix

Clock

Monitor CKOT

(INT15R to INT8R)

INT7 to INT0

16-bit Reload

Timer 4 ch TIN3 to TIN0

TOT3 to TOT0

MB90860A Series

■MEMORY MAP

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C

compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without

using the far specification in the pointer declaration.

For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.

The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.

The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and

FF7FFFH is visible only in bank FF.

MB90V340 (S)

FFFFFFH

FF0000H

FEFFFFH

FE0000H

FDFFFFH

FD0000H

FCFFFFH

FC0000H

FBFFFFH

FB0000H

FAFFFFH

FA0000H

F9FFFFH

F90000H

F8FFFFH

F80000H

00FFFFH

008000H

007FFFH

007900H

0078FFH

000100H

0000EFH

000000H

ROM(FF bank)

ROM(FE bank)

ROM

(Image of FF bank)

Peripheral

RAM 30 K

FFFFFFH

FF0000H

FEFFFFH

FE0000H

00FFFFH

008000H

007FFFH

007900H

0018FFH

000100H

0000EFH

000000HPeripheral

RAM 6 K

Peripheral

ROM

(Image of FF bank)

ROM(FE bank)

ROM(FF bank)

MB90867A (S)

MB90F867A (S)

: No access

MB90860A Series

■I/O MAP

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial va lue

00HPort 0 Data Register PDR0 R/W Port 0 XXXXXXXX

01HPort 1 Data Register PDR1 R/W Port 1 XXXXXXXX

02HPort 2 Data Register PDR2 R/W Port 2 XXXXXXXX

03HPort 3 Data Register PDR3 R/W Port 3 XXXXXXXX

04HPort 4 Data Register PDR4 R/W Port 4 XXXXXXXX

05HPort 5 Data Register PDR5 R/W Port 5 XXXXXXXX

06HPort 6 Data Register PDR6 R/W Port 6 XXXXXXXX

07HPort 7 Data Register PDR7 R/W Port 7 XXXXXXXX

08HPort 8 Data Register PDR8 R/W Port 8 XXXXXXXX

09HPort 9 Data Register PDR9 R/W Port 9 XXXXXXXX

0AHPort A Data Register PDRA R/W Port A XXXXXXXX

0BHPort 5 Analog Input Enable Register ADER5 R/W Port 5, A/D 11111111

0CHPort 6 Analog Input Enable Register ADER6 R/W Port 6, A/D 11111111

0DHPort 7 Analog Input Enable Register ADER7 R/W Port 7, A/D 11111111

0EHInput Level Select Register 0 ILSR0 R/W Ports 00000000

0FHInput Level Select Register 1 ILSR1 R/W Ports 00000000

10HPort 0 Direction Register DDR0 R/W Port 0 00000000

11HPort 1 Direction Register DDR1 R/W Port 1 00000000

12HPort 2 Direction Register DDR2 R/W Port 2 00000000

13HPort 3 Direction Register DDR3 R/W Port 3 00000000

14HPort 4 Direction Register DDR4 R/W Port 4 00000000

15HPort 5 Direction Register DDR5 R/W Port 5 00000000

16HPort 6 Direction Register DDR6 R/W Port 6 00000000

17HPort 7 Direction Register DDR7 R/W Port 7 00000000

18HPort 8 Direction Register DDR8 R/W Port 8 00000000

19HPort 9 Direction Register DDR9 R/W Port 9 00000000

1AHPort A Direction Register DDRA R/W Port A 00000100

1BHReserved

1CHPort 0 Pullup Control Register PUCR0 R/W Port 0 00000000

1DHPort 1 Pullup Control Register PUCR1 R/W Port 1 00000000

1EHPort 2 Pullup Control Register PUCR2 R/W Port 2 00000000

1FHPort 3 Pullup Control Register PUCR3 R/W Port 3 00000000

MB90860A Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

20HSerial Mode Register 0 SMR0 W,R/W

UART0

00000000

21HSerial Control Register 0 SCR0 W,R/W 00000000

22HReception/Transmission Data Register 0 RDR0/

TDR0 R/W 00000000

23HSerial Status Register 0 SSR0 R,R/W 00001000

24HExtended Communication Control Reg. 0 ECCR0 R,W,R/

W000000XX

25HExtended Status/Control Register 0 ESCR0 R/W 00000100

26HBaud Rate Generator Register 00 BGR00 R/W 00000000

27HBaud Rate Generator Register 01 BGR01 R/W 00000000

28HSerial Mode Register 1 SMR1 W,R/W

UART1

00000000

29HSerial Control Register 1 SCR1 W,R/W 00000000

2AHReception/Transmission Data Register 1 RDR1/

TDR1 R/W 00000000

2BHSerial Status Register 1 SSR1 R,R/W 00001000

2CHExtended Communication Control Reg. 1 ECCR1 R,W,

R/W 000000XX

2DHExtended Status Control Register 1 ESCR1 R/W 00000100

2EHBaud Rate Generator Register 10 BGR10 R/W 00000000

2FHBaud Rate Generator Register 11 BGR11 R/W 00000000

30HPPG 0 Operation Mode Control Register PPGC0 W,R/W 16-bit PPG 0/1 0X000XX1

31HPPG 1 Operation Mode Control Register PPGC1 W,R/W 0X000001

32HPPG 01 Clock Select Register PPG01 R/W 000000X0

33HReserved

34HPPG 2 Operation Mode Control Register PPGC2 W,R/W 16-bit PPG 2/3 0X000XX1

35HPPG 3 Operation Mode Control Register PPGC3 W,R/W 0X000001

36HPPG 23 Clock Select Register PPG23 R/W 000000X0

37HReserved

38HPPG 4 Operation Mode Control Register PPGC4 W,R/W 16-bit PPG 4/5 0X000XX1

39HPPG 5 Operation Mode Control Register PPGC5 W,R/W 0X000001

3AHPPG 4 and PPG 5 Clock Select Register PPG45 R/W 000000X0

3BHProgram Address Detection Control

Status Register 1 PACSR1 R/W Address Match

Detection 1 00000000

3CHPPG 6 Operation Mode Control Register PPGC6 W,R/W 16-bit PPG 6/7 0X000XX1

3DHPPG 7 Operation Mode Control Register PPGC7 W,R/W 0X000001

3EHPPG 67 Clock Select Register PPG67 R/W 000000X0

3FHReserved

MB90860A Series

(Continued)

Address Register Abbrevi-

ation Access Resource name Initial value

40HPPG 8 Operation Mode Control Register PPGC8 W,R/W

16-bit PPG 8/9

0X000XX1

41HPPG 9 Operation Mode Control Register PPGC9 W,R/W 0X000001

42HPPG 89 Clock Select Register PPG89 R/W 000000X0

43HReserved

44HPPG A Operation Mode Control Register PPGCA W,R/W

16-bit PPG A/B

0X000XX1

45HPPG B Operation Mode Control Register PPGCB W,R/W 0X000001

46HPPG AB Clock Select Register PPGAB R/W 000000X0

47HReserved

48HPPG C Operation Mode Control Register PPGCC W,R/W

16-bit PPG C/D

0X000XX1

49HPPG D Operation Mode Control Register PPGCD W,R/W 0X000001

4AHPPG CD Clock Select Register PPGCD R/W 000000X0

4BHReserved

4CHPPG E Operation Mode Control Register PPGCE W,R/W

16-bit PPG E/F

0X000XX1

4DHPPG F Operation Mode Control Register PPGCF W,R/W 0X000001

4EHPPG EF Clock Select Register PPGEF R/W 000000X0

4FHReserved

50HInput Capture Control Status Register 0/1 ICS01 R/W Input Capture 0/1 00000000

51HInput Capture Edge Register 0/1 ICE01 R/W, R XXX0X0XX

52HInput Capture Control Status Register 2/3 ICS23 R/W Input Capture 2/3 00000000

53HInput Capture Edge Register 2/3 ICE23 R XXXXXXXX

54HInput Capture Control Status Register 4/5 ICS45 R/W Input Capture 4/5 00000000

55HInput Capture Edge Register 4/5 ICE45 R XXXXXXXX

56HInput Capture Control Status Register 6/7 ICS67 R/W Input Capture 6/7 00000000

57HInput Capture Edge Register 6/7 ICE67 R/W, R XXX000XX

58HOutput Compare Control Status Register 0 OCS0 R/W Output Compare 0/1 0000XX00

59HOutput Compare Control Status Register 1 OCS1 R/W 0XX00000

5AHOutput Compare Control Status Register 2 OCS2 R/W Output Compare 2/3 0000XX00

5BHOutput Compare Control Status Register 3 OCS3 R/W 0XX00000

5CHOutput Compare Control Status Register 4 OCS4 R/W Output Compare 4/5 0000XX00

5DHOutput Compare Control Status Register 5 OCS5 R/W 0XX00000

5EHOutput Compare Control Status Register 6 OCS6 R/W Output Compare 6/7 0000XX00

5FHOutput Compare Control Status Register 7 OCS7 R/W 0XX00000

MB90860A Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

60HTimer Control Status Register 0 TMCSR0 R/W 16-bit Reload Timer 0 00000000

61HTimer Control Status Register 0 TMCSR0 R/W XXXX0000

62HTimer Control Status Register 1 TMCSR1 R/W 16-bit Reload Timer 1 00000000

63HTimer Control Status Register 1 TMCSR1 R/W XXXX0000

64HTimer Control Status Register 2 TMCSR2 R/W 16-bit Reload Timer 2 00000000

65HTimer Control Status Register 2 TMCSR2 R/W XXXX0000

66HTimer Control Status Register 3 TMCSR3 R/W 16-bit Reload Timer 3 00000000

67HTimer Control Status Register 3 TMCSR3 R/W XXXX0000

68HA/D Control Status Register 0 ADCS0 R/W

A/D Converter

000XXXX0

69HA/D Control Status Register 1 ADCS1 R/W 0000000X

6AHA/D Data Register 0 ADCR0 R 00000000

6BHA/D Data Register 1 ADCR1 R XXXXXX00

6CHADC Setting Register 0 ADSR0 R/W 00000000

6DHADC Setting Register 1 ADSR1 R/W 00000000

6EHReserved

6FHROM Mirroring Register ROMM W ROM Mirror XXXXXXX1

70H to 8FHReserved

90H to 9AHReserved

9BHDMA Descriptor Channel Specification

DMA

00000000

9CHDMA Status Register L DSRL R/W 00000000

9DHDMA Status Register H DSRH R/W 00000000

9EHProgram Address Detection Control

Status Register 0 PACSR0 R/W Address Match

Detection 0 00000000

9FHDelayed Interrupt/Release DIRR R/W Delayed Interrupt XXXXXXX0

A0HLow-power Mode Control Register LPMCR W,R/W Low Power

Controller 00011000

A1HClock Selection Register CKSCR R,R/W Low Power

Controller 11111100

A2H, A3HReserved

A4HDMA Stop Status Register DSSR R/W DMA 00000000

A5HAutomatic Ready Function Select Reg. ARSR W External Memory

Access

0011XX00

A6HExternal Address Output Control Reg. HACR W 00000000

A7HBus Control Signal Selection Register ECSR W 0000000X

A8HWatchdog Control Register WDTC R,W Watchdog Timer XXXXX111

A9HTimebase Timer Control Register TBTC W,R/W Time Base Timer 1XX00100

MB90860A Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

AAHWatch Timer Control Register WTC R,R/W Watch Timer 1X001000

ABHReserved

ACHDMA Enable Register L DERL R/W DMA 00000000

ADHDMA Enable Register H DERH R/W 00000000

AEHFlash Control Status Register

(FlashDevices only.

Otherwise reserved) FMCS R,R/W Flash Memory 000X0000

AFHReserved

B0HInterrupt Control Register 00 ICR00 W,R/W

Interrupt Controller

00000111

B1HInterrupt Control Register 01 ICR01 W,R/W 00000111

B2HInterrupt Control Register 02 ICR02 W,R/W 00000111

B3HInterrupt Control Register 03 ICR03 W,R/W 00000111

B4HInterrupt Control Register 04 ICR04 W,R/W 00000111

B5HInterrupt Control Register 05 ICR05 W,R/W 00000111

B6HInterrupt Control Register 06 ICR06 W,R/W 00000111

B7HInterrupt Control Register 07 ICR07 W,R/W 00000111

B8HInterrupt Control Register 08 ICR08 W,R/W 00000111

B9HInterrupt Control Register 09 ICR09 W,R/W 00000111

BAHInterrupt Control Register 10 ICR10 W,R/W 00000111

BBHInterrupt Control Register 11 ICR11 W,R/W 00000111

BCHInterrupt Control Register 12 ICR12 W,R/W 00000111

BDHInterrupt Control Register 13 ICR13 W,R/W 00000111

BEHInterrupt Control Register 14 ICR14 W,R/W 00000111

BFHInterrupt Control Register 15 ICR15 W,R/W 00000111

C0HD/A Converter Data 0 DAT0 R/W

D/A Converter

XXXXXXXX

C1HD/A Converter Data 1 DAT1 R/W XXXXXXXX

C2HD/A Control 0 DACR0 R/W XXXXXXX0

C3HD/A Control 1 DACR1 R/W XXXXXXX0

C4H, C5HReserved

C6HExternal Interrupt Request Enable

External Interrupt 0

00000000

C7HExternal Interrupt Request Register 0 EIRR0 R/W XXXXXXXX

C8HExternal Interrupt Level Register 0 ELVR0 R/W 00000000

C9HExternal Interrupt Level Register 0 ELVR0 R/W 00000000

MB90860A Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

CAHExternal Interrupt Request Enable

External Interrupt 1

00000000

CBHExternal Interrupt Request Register 1 EIRR1 R/W XXXXXXXX

CCHExternal Interrupt Level Register 1 ELVR1 R/W 00000000

CDHExternal Interrupt Level Register 1 ELVR1 R/W 00000000

CEHExternal Interrupt Source Select

CFHPLL/Subclock Control Register PSCCR W PLL XXXX0000

D0HDMA Buffer Address Pointer L BAPL R/W

DMA

XXXXXXXX

D1HDMA Buffer Address Pointer M BAPM R/W XXXXXXXX

D2HDMA Buffer Address Pointer H BAPH R/W XXXXXXXX

D3HDMA Control Register DMACS R/W XXXXXXXX

D4HI/O Register Address Pointer L IOAL R/W XXXXXXXX

D5HI/O Register Address Pointer H IOAH R/W XXXXXXXX

D6HData Counter L DCTL R/W XXXXXXXX

D7HData Counter H DCTH R/W XXXXXXXX

D8HSerial Mode Register 2 SMR2 W,R/W

UART2

00000000

D9HSerial Control Register 2 SCR2 W,R/W 00000000

DAHReception/Transmission Data

TDR2 R/W 00000000

DBHSerial Status Register 2 SSR2 R,R/W 00001000

DCHExtended Communication Control

R/W 000000XX

DDHExtended Status/Control Register 2 ESCR2 R/W 00000100

DEHBaud Rate Reload Register 20 BGR20 R/W 00000000

DFHBaud Rate Reload Register 21 BGR21 R/W 00000000

E0H to EFHReserved

F0H to FFHExternal

MB90860A Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

7900HReload Register L0 PRLL0 R/W

16-bit PPG 0/1

XXXXXXXX

7901HReload Register H0 PRLH0 R/W XXXXXXXX

7902HReload Register L1 PRLL1 R/W XXXXXXXX

7903HReload Register H1 PRLH1 R/W XXXXXXXX

7904HReload Register L2 PRLL2 R/W

16-bit PPG 2/3

XXXXXXXX

7905HReload Register H2 PRLH2 R/W XXXXXXXX

7906HReload Register L3 PRLL3 R/W XXXXXXXX

7907HReload Register H3 PRLH3 R/W XXXXXXXX

7908HReload Register L4 PRLL4 R/W

16-bit PPG 4/5

XXXXXXXX

7909HReload Register H4 PRLH4 R/W XXXXXXXX

790AHReload Register L5 PRLL5 R/W XXXXXXXX

790BHReload Register H5 PRLH5 R/W XXXXXXXX

790CHReload Register L6 PRLL6 R/W

16-bit PPG 6/7

XXXXXXXX

790DHReload Register H6 PRLH6 R/W XXXXXXXX

790EHReload Register L7 PRLL7 R/W XXXXXXXX

790FHReload Register H7 PRLH7 R/W XXXXXXXX

7910HReload Register L8 PRLL8 R/W

16-bit PPG 8/9

XXXXXXXX

7911HReload Register H8 PRLH8 R/W XXXXXXXX

7912HReload Register L9 PRLL9 R/W XXXXXXXX

7913HReload Register H9 PRLH9 R/W XXXXXXXX

7914HReload Register LA PRLLA R/W

16-bit PPG A/B

XXXXXXXX

7915HReload Register HA PRLHA R/W XXXXXXXX

7916HReload Register LB PRLLB R/W XXXXXXXX

7917HReload Register HB PRLHB R/W XXXXXXXX

7918HReload Register LC PRLLC R/W

16-bit PPG C/D

XXXXXXXX

7919HReload Register HC PRLHC R/W XXXXXXXX

791AHReload Register LD PRLLD R/W XXXXXXXX

791BHReload Register HD PRLHD R/W XXXXXXXX

791CHReload Register LE PRLLE R/W

16-bit PPG E/F

XXXXXXXX

791DHReload Register HE PRLHE R/W XXXXXXXX

791EHReload Register LF PRLLF R/W XXXXXXXX

791FHReload Register HF PRLHF R/W XXXXXXXX

7920HInput Capture Data Register 0 IPCP0 R

Input Capture 0/1

XXXXXXXX

7921HInput Capture Data Register 0 IPCP0 R XXXXXXXX

7922HInput Capture Data Register 1 IPCP1 R XXXXXXXX

7923HInput Capture Data Register 1 IPCP1 R XXXXXXXX

MB90860A Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

7924HInput Capture Data Register 2 IPCP2 R

Input Capture 2/3

XXXXXXXX

7925HInput Capture Data Register 2 IPCP2 R XXXXXXXX

7926HInput Capture Data Register 3 IPCP3 R XXXXXXXX

7927HInput Capture Data Register 3 IPCP3 R XXXXXXXX

7928HInput Capture Data Register 4 IPCP4 R

Input Capture 4/5

XXXXXXXX

7929HInput Capture Data Register 4 IPCP4 R XXXXXXXX

792AHInput Capture Data Register 5 IPCP5 R XXXXXXXX

792BHInput Capture Data Register 5 IPCP5 R XXXXXXXX

792CHInput Capture Data Register 6 IPCP6 R

Input Capture 6/7

XXXXXXXX

792DHInput Capture Data Register 6 IPCP6 R XXXXXXXX

792EHInput Capture Data Register 7 IPCP7 R XXXXXXXX

792FHInput Capture Data Register 7 IPCP7 R XXXXXXXX

7930HOutput Compare Register 0 OCCP0 R/W

Output Compare 0/1

XXXXXXXX

7931HOutput Compare Register 0 OCCP0 R/W XXXXXXXX

7932HOutput Compare Register 1 OCCP1 R/W XXXXXXXX

7933HOutput Compare Register 1 OCCP1 R/W XXXXXXXX

7934HOutput Compare Register 2 OCCP2 R/W

Output Compare 2/3

XXXXXXXX

7935HOutput Compare Register 2 OCCP2 R/W XXXXXXXX

7936HOutput Compare Register 3 OCCP3 R/W XXXXXXXX

7937HOutput Compare Register 3 OCCP3 R/W XXXXXXXX

7938HOutput Compare Register 4 OCCP4 R/W

Output Compare 4/5

XXXXXXXX

7939HOutput Compare Register 4 OCCP4 R/W XXXXXXXX

793AHOutput Compare Register 5 OCCP5 R/W XXXXXXXX

793BHOutput Compare Register 5 OCCP5 R/W XXXXXXXX

793CHOutput Compare Register 6 OCCP6 R/W

Output Compare 6/7

XXXXXXXX

793DHOutput Compare Register 6 OCCP6 R/W XXXXXXXX

793EHOutput Compare Register 7 OCCP7 R/W XXXXXXXX

793FHOutput Compare Register 7 OCCP7 R/W XXXXXXXX

7940HData Register 0 TCDT0 R/W

I/O Timer 0

00000000

7941HData Register 0 TCDT0 R/W 00000000

7942HControl Status Register 0 TCCSL0 R/W 00000000

7943HControl Status Register 0 TCCSH0 R/W 0XXXXXXX

7944HData Register 1 TCDT1 R/W

I/O Timer 1

00000000

7945HData Register 1 TCDT1 R/W 00000000

7946HControl Status Register 1 TCCSL1 R/W 00000000

7947HControl Status Register 1 TCCSH1 R/W 0XXXXXXX

MB90860A Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

7948HTimer Register 0/Reload Register 0 TMR0/

TMRLR0 R/W 16-bit Reload

Timer 0 XXXXXXXX

7949HR/W XXXXXXXX

794AHTimer Register 1/Reload Register 1 TMR1/

TMRLR1 R/W 16-bit Reload

Timer 1 XXXXXXXX

794BHR/W XXXXXXXX

794CHTimer Register 2/Reload Register 2 TMR2/

TMRLR2 R/W 16-bit Reload

Timer 2 XXXXXXXX

794DHR/W XXXXXXXX

794EHTimer Register 3/Reload Register 3 TMR3/

TMRLR3 R/W 16-bit Reload

Timer 3 XXXXXXXX

794FHR/W XXXXXXXX

7950HSerial Mode Register 3 SMR3 W,R/W

UART3

00000000

7951HSerial Control Register 3 SCR3 W,R/W 00000000

7952HReception/Transmission Data Register 3 RDR3/

TDR3 R/W 00000000

7953HSerial Status Register 3 SSR3 R,R/W 00001000

7954HExtended Communication Control Reg. 3 ECCR3 R,W,

R/W 000000XX

7955HExtended Status/Control Register 3 ESCR3 R/W 00000100

7956HBaud Rate Reload Register 30 BGR30 R/W 00000000

7957HBaud Rate Reload Register 31 BGR31 R/W 00000000

7958HSerial Mode Register 4 SMR4 W,R/W

UART4

00000000

7959HSerial Control Register 4 SCR4 W,R/W 00000000

795AHReception/Transmission Data Register 4 RDR4/

TDR4 R/W 00000000

795BHSerial Status Register 4 SSR4 R,R/W 00001000

795CHExtended Communication Control Reg. 4 ECCR4 R,W,

R/W 000000XX

795DHExtended Status/Control Register 4 ESCR4 R/W 00000100

795EHBaud Rate Reload Register 40 BGR40 R/W 00000000

795FHBaud Rate Reload Register 41 BGR41 R/W 00000000

7960H to

796BHReserved

796CHClock Output Enable Register CLKR R/W Clock Monitor XXXX0000

796DH to

796FHReserved

MB90860A Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

7970HI2C Bus Status Register 0 IBSR0 R

I2C Interface 0

00000000

7971HI2C Bus Control Register 0 IBCR0 W,R/W 00000000

7972HI2C 10-bit Slave Address Register 0 ITBAL0 R/W 00000000

7973HITBAH0 R/W 00000000

7974HI2C 10-bit Slave Address Mask Register 0 ITMKL0 R/W 11111111

7975HITMKH0 R/W 00111111

7976HI2C 7-bit Slave Address Register 0 ISBA0 R/W 00000000

7977HI2C 7-bit Slave Address Mask Register 0 ISMK0 R/W 01111111

7978HI2C Data Register 0 IDAR0 R/W 00000000

7979H,

797AHReserved

797BHI2C Clock Control Register 0 ICCR0 R/W I2C Interface 0 00011111

797CH to

797FHReserved

7980HI2C Bus Status Register 1 IBSR1 R

I2C Interface 1

00000000

7981HI2C Bus Control Register 1 IBCR1 W,R/W 00000000

7982HI2C 10-bit Slave Address Register 1 ITBAL1 R/W 00000000

7983HITBAH1 R/W 00000000

7984HI2C 10-bit Slave Address Mask Register 1 ITMKL1 R/W 11111111

7985HITMKH1 R/W 00111111

7986HI2C 7-bit Slave Address Register 1 ISBA1 R/W 00000000

7987HI2C 7-bit Slave Address Mask Register 1 ISMK1 R/W 01111111

7988HI2C Data Register 1 IDAR1 R/W 00000000

7989H,

798AHReserved

798BHI2C Clock Control Register 1 ICCR1 R/W I2C Interface 1 00011111

798CH to

79C1HReserved

79C2HClock Modulator Control Register CMCR R,R/W Clock Modulator 0001X000

79C3H to

79DFHReserved

MB90860A Series

(Continued)

Notes : • Initial value of “X” represents unknown value.

• Addresses in the range 0000H to 00BFH, which are not listed in the table, are reserved for the primary

functions of the MCU. A read access to these reserved addresses results reading “X” and any write

access should not be performed.

Address Register Abbrevia-

tion Access Resource name Initial value

79E0HProgram Address Detection Register 0 PADR0 R/W

Address Match

Detection 0

XXXXXXXX

79E1HProgram Address Detection Register 0 PADR0 R/W XXXXXXXX

79E2HProgram Address Detection Register 0 PADR0 R/W XXXXXXXX

79E3HProgram Address Detection Register 1 PADR1 R/W XXXXXXXX

79E4HProgram Address Detection Register 1 PADR1 R/W XXXXXXXX

79E5HProgram Address Detection Register 1 PADR1 R/W XXXXXXXX

79E6HProgram Address Detection Register 2 PADR2 R/W XXXXXXXX

79E7HProgram Address Detection Register 2 PADR2 R/W XXXXXXXX

79E8HProgram Address Detection Register 2 PADR2 R/W XXXXXXXX

79E9H to

79EFHReserved

79F0HProgram Address Detection Register 3 PADR3 R/W

Address Match

Detection 1

XXXXXXXX

79F1HProgram Address Detection Register 3 PADR3 R/W XXXXXXXX

79F2HProgram Address Detection Register 3 PADR3 R/W XXXXXXXX

79F3HProgram Address Detection Register 4 PADR4 R/W XXXXXXXX

79F4HProgram Address Detection Register 4 PADR4 R/W XXXXXXXX

79F5HProgram Address Detection Register 4 PADR4 R/W XXXXXXXX

79F6HProgram Address Detection Register 5 PADR5 R/W XXXXXXXX

79F7HProgram Address Detection Register 5 PADR5 R/W XXXXXXXX

79F8HProgram Address Detection Register 5 PADR5 R/W XXXXXXXX

79F9H to

7FFFHReserved

MB90860A Series

■INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

(Continued)

Interrupt cause EI2OS

clear DMA ch

number Interrupt vector Interrupt control

Number Address Number Address

Reset N #08 FFFFDCH

INT9 instruction N #09 FFFFD8H

Exception N #10 FFFFD4H

(Reserved) N #11 FFFFD0HICR00 0000B0H

(Reserved) N #12 FFFFCCH

Input Capture 6 Y1 #13 FFFFC8HICR01 0000B1H

Input Capture 7 Y1 #14 FFFFC4H

I2C0 N #15 FFFFC0HICR02 0000B2H

(Reserved) N #16 FFFFBCH

16-bit Reload Timer 0 Y1 0 #17 FFFFB8HICR03 0000B3H

16-bit Reload Timer 1 Y1 1 #18 FFFFB4H

16-bit Reload Timer 2 Y1 2 #19 FFFFB0HICR04 0000B4H

16-bit Reload Timer 3 Y1 #20 FFFFACH

PPG 0/1/4/5 N #21 FFFFA8HICR05 0000B5H

PPG 2/3/6/7 N #22 FFFFA4H

PPG 8/9/C/D N #23 FFFFA0HICR06 0000B6H

PPG A/B/E/F N #24 FFFF9CH

Time Base Timer N #25 FFFF98HICR07 0000B7H

External Interrupt 0 to 3, 8 to 11 Y1 3 #26 FFFF94H

Watch Timer N #27 FFFF90HICR08 0000B8H

External Interrupt 4 to 7, 12 to 15 Y1 4 #28 FFFF8CH

A/D Converter Y1 5 #29 FFFF88HICR09 0000B9H

I/O Timer 0 / I/O Timer 1 N #30 FFFF84H

Input Capture 4/5 / I2C1 Y1 6 #31 FFFF80HICR10 0000BAH

Output Compare 0/1/4/5 Y1 7 #32 FFFF7CH

Input Capture 0 to 3 Y1 8 #33 FFFF78HICR11 0000BBH

Output Compare 2/3/6/7 Y1 9 #34 FFFF74H

UART 0 RX Y2 10 #35 FFFF70HICR12 0000BCH

UART 0 TX Y1 11 #36 FFFF6CH

UART 1 RX / UART 3 RX Y2 12 #37 FFFF68HICR13 0000BDH

UART 1 TX / UART 3 TX Y1 13 #38 FFFF64H

MB90860A Series

(Continued)

Y1 : Usab le

Y2 : Usable, with EI2OS stop function

N : Unusable

Notes : •The peripheral resources sharing the ICR register have the same interrupt level.

•When two peripheral resources share the ICR register , only one can use Extended Intelligent I/O Service

at a time.

•When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O

Service, the other one cannot use interrupts.

Interrupt cause EI2OS

clear DMA ch

number Interrupt vector Interrupt control

Number Address Number Address

UART 2 RX / UART 4 RX Y2 14 #39 FFFF60HICR14 0000BEH

UART 2 TX / UART 4 TX Y1 15 #40 FFFF5CH

Flash Memory N #41 FFFF58HICR15 0000BFH

Delayed interrupt N #42 FFFF54H

MB90860A Series

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximu m Ratings (VSS = AVSS = 0 V)

(Continued)

Parameter Symbol Rating Unit Remarks

Min Max

Power supply voltage

VCC VSS − 0.3 VSS + 6.0 V

AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC *1

AVRH,

AVRL VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH, AVCC ≥ AVRL,

AVRH ≥ AVRL

Input voltage VIVSS − 0.3 VSS + 6.0 V *2

Output voltage VOVSS − 0.3 VSS + 6.0 V *2

Maximum Clamp Current ICLAMP −4.0 +4.0 mA *4

Total Maximum Clamp Current Σ|ICLAMP|40 mA *4

“L” level maximum output current IOL 15 mA *3

“L” level average output current IOLAV 4mA*3

“L” level maximum overall output current ΣIOL 100 mA *3

“L” level average overall output current ΣIOLAV 50 mA *3

“H” level maximum output current IOH −15 mA *3

“H” level average output current IOHAV −4mA*3

“H” level maximum overall output current ΣIOH −100 mA *3

“H” level average overall output current ΣIOHAV −50 mA *3

Power consumption PD340 mW MB90F867A

Operating temperature TA−40 +105 °C

Storage temperature TSTG −55 +150 °C

MB90860A Series

(Continued)

*1:Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the

analog inputs does not exceed AVCC when the power is switched on.

*2:VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun

current to/from an input is limited by some means with e xternal components, the ICLAMP rating supercedes the VI

rating.

*3:Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,

P70 to P77, P80 to P87, P90 to P97, PA0 to PA1

*4: • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67

P70 to P77, P80 to P87, P90 to P97, PA0 to PA1

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting

supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Sample recommended circuits:

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

P-ch

N-ch

VCC

• Input/output equivalent circuits

+B input (0 V to 16 V)

Limiting

resistance

Protective diode

MB90860A Series

2. Recommended Conditions (VSS = AVSS = 0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Parameter Symbol Value Unit Remarks

Min Typ Max

Power supply voltage VCC,

AVCC

4.0 5.0 5.5 V Under normal operation

3.5 5.0 5.5 V Under normal operation, when not

using the A/D converter and not

Flash programming.

4.5 5.0 5.5 V When External bus is used.

3.0 5.5 V Maintains RAM data in stop mode

Smooth capacitor CS0.1 1.0 µF

Use a ceramic capacitor or capac-

itor of better AC characteristics.

Capacitor at the VCC should be

greater than this capacitor.

Operating temperature TA−40 +105 °C

C Pin Connection Diagram

MB90860A Series

3. DC Characteristics (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

(Continued)

Parameter Sym-

bol Pin Condition Value Unit Remarks

Min Typ Max

Input H

voltage

(At VCC =

5 V ± 10%)

VIHS 0.8 VCC VCC + 0.3 V

Port inputs if CMOS

hysteresis input levels

are selected (except

UART SIN input pins

and I2C input pins)

VIHA 0.8 VCC VCC + 0.3 V Port inputs if

AUTOMOTIVE input

levels are selected

VIHT 2.0 VCC + 0.3 V Port inputs if TTL input

levels are selected

VIHS 0.7 VCC VCC + 0.3 V UART SIN inputs if

CMOS input levels are

selected

VIHI 0.7 VCC VCC + 0.3 V I2C Port inputs if CMOS

hysteresis input levels

are selected

VIHR 0.8 VCC VCC + 0.3 V RST input pin (CMOS

hysteresis)

VIHM VCC − 0.3 VCC + 0.3 V MD input pin

Input L

voltage

(At VCC =

5 V ± 10%)

VILS VSS − 0.3 0.2 VCC V

Port inputs if CMOS

hysteresis input levels

are selected (except

UART SIN input pins

and I2C input pins)

VILA VSS − 0.3 0.5 VCC VPort inputs if

AUTOMOTIVE input

levels are selected

VILT VSS − 0.3 0.8 V Port inputs if TTL

input levels are selected

VILS VSS − 0.3 0.3 VCC VUART SIN inputs if

CMOS input levels are

selected

VILI VSS − 0.3 0.3 VCC VI2C Port inputs if CMOS

hysteresis input levels

are selected

VILR VSS − 0.3 0.2 VCC VRST input pin (CMOS

hysteresis)

VILM VSS − 0.3 VSS + 0.3 V MD input pin

Output H

voltage VOH Normal

outputs VCC = 4.5 V,

IOH = −4.0 mA VCC − 0.5 V

Output H

voltage VOHI I2C current

outputs VCC = 4.5 V,

IOH = −3.0 mA VCC − 0.5 V

Output L

voltage VOL Normal

outputs VCC = 4.5 V,

IOL = 4.0 mA 0.4 V

Output L

voltage VOLI I2C current

outputs VCC = 4.5 V,

IOL = 3.0 mA 0.4 V

MB90860A Series

(Continued)

(TA = −40 °C to +105, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

* : Current values are tentative. They are subject to change without notice according to improvements in the

characteristics. The power supply current is measured with an external clock.

Parameter Sym-

bol Pin Condition Value Unit Remarks

Min Typ Max

Input leak current IIL VCC = 5.5 V, VSS < VI < VCC −11µA

Pull-up

resistance RUP

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

RST

25 50 100 kΩ

Pull-down

resistance RDOWN MD2 25 50 100 kΩExcept Flash

devices

Power supply

current*

ICC

VCC

VCC = 5.0 V,

Internal frequency : 24 MHz,

At normal operation. 55 70 mA MB90F867A

VCC = 5.0 V,

Internal frequency : 24 MHz,

At writing FLASH memory. 70 85 mA MB90F867A

VCC = 5.0 V,

Internal frequency : 24 MHz,

At erasing FLASH memory. 75 90 mA MB90F867A

ICCS VCC = 5.0 V,

Internal frequency : 24 MHz,

At Sleep mode. 25 35 mA MB90F867A

ICTS VCC = 5.0 V,

Internal frequency : 2 MHz,

At Main Timer mode 0.3 0.8 mA MB90F867A

ICTSPLL6

VCC = 5.0 V,

Internal frequency : 24 MHz,

At PLL Timer mode,

external frequency = 4 MHz 4 7 mA MB90F867A

ICCL

VCC = 5.0V

Internal frequency: 8 kHz,

At sub operation

TA = +25°C170 360 µA MB90F867A

ICCLS

VCC = 5.0V

Internal frequency: 8 kHz,

At sub sleep

TA = +25°C20 50 µA MB90F867A

ICCT

VCC = 5.0V

Internal frequency: 8 kHz,

At watch mode

TA = +25°C10 35 µA MB90F867A

ICCH VCC = 5.0 V,

At Stop mode,

TA = +25°C725µA MB90F867A

Input capacity CIN Other than C, AVCC, AVSS,

AVRH, AVRL, VCC, VSS, 515pF

MB90860A Series

4. AC Characteristics

(1) Clock Timing (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

* : Whem selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as

mentioned in “Relation among external clock frequency and machine clock frequency”.

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Clock frequency fC

X0, X1 3 16 MHz When using an oscillation

circuit

X0 3 24 MHz When using an external

clock*

fCL X0A, X1A — 32.768 100 kHz

Clock cycle time tCYL

X0, X1 62.5 333 ns When using an oscillation

circuit

X0 41.67 333 ns When using an external

clock

tCYLL X0A, X1A 1 0 30.5 — µs

Input clock pulse width PWH, PWL X0 10 ns Duty ratio is about 30% to

70%.

PWHL, PWLL X0A 5 15.2 µs

Input clock rise and fall time tCR, tCF X0  5 ns When using external clock

Internal operating clock

frequency (machine clock) fCP 1.5 24 MHz When using main clock

fCPL 8.192 50 kHz When using sub clock

Internal operating clock

cycle time (machine clock) tCP 41.67 666 ns When using main clock

tCPL 20 122.1 µs When using sub clock

tCYL

tCF tCR

0.8 VCC

0.2 VCC

PWH PWL

X0A

tCYLL

tCF tCR

0.8 VCC

0.2 VCC

PWHL PWLL

Clock Timing

MB90860A Series

• Guaranteed PLL operation range

Guaranteed operation range of MB90860A Series

*1 : PLL × 1 guaranteed operation range is from 4.0 MHz to 20 MHz.

*2 : When using a crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz.

External clock frequency and Machine clock frequency

5.5

3.5

41.5 24

4.5

8 20

Guaranteed operation range

Guaranteed PLLL operation range (CS2=1)

Guaranteed PLL operation range (CS=0)

Guaranteed A/D converter

operation range

Machine clock fCP (MHz)

Power supply voltage VCC (V)

4.0

1.5

34 8 24

×1/2

(PLL off)

16 20

Guaranteed operation frequency range*2

×4

(CS=11) ×3

(CS=10) ×2

(CS=01) ×1

(CS=00)

Machine clock fCP (MHz)

External clock fC (MHz) 1

CS2 (bit0 in PSCCR reigster) = 0

4.0

1.5

34 8 24

×1/2

(PLL off)

Guaranteed operation frequency range*2

×6

(CS=10) ×4

(CS=01) ×2

(CS=00)

Machine clock fCP (MHz)

External clock fC (MHz) 1

CS2 (bit0 in PSCCR reigster) = 1

MB90860A Series

(2) Reset Standby Input (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)

* : Oscillation time of oscillator is the time that the amplitude reaches 90%.

In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In F AR / ceramic oscillators,

the oscillation time is between hundreds of µs to se v eral ms . With an e xternal clock, the oscillation time is 0 ms.

Parameter Symbol Pin Value Unit Remarks

Min Max

Reset input

time tRSTL RST

500 ns Under normal operation

Oscillation time of oscillator*

+ 100 µsns In Stop mode, Sub Clock

mode, Sub Sleep mode

and Watch mode

100 µs In Time Timer mode

tRSTL

0.2 VCC 0.2 VCC

100

RST

90% of

amplitude

Instruction execution

Oscillation stabilization

waiting time

Oscillation time

of oscillator

Internal operation

clock

Internal reset

0.2 VCC

RST

tRSTL

0.2 VCC

Under normal operation:

In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:

MB90860A Series

(3) Power On Reset (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Power on rise time tRVCC 0.05 30 ms

Power off time tOFF VCC 1ms Due to repetitive operation

VCC

VSS

3 V

tOFF

2.7 V

0.2 V 0.2 V0.2 V

Holds RAM data

If you change the power supply voltage too rapidly, a power on reset may occur.

We recommend that you startup smoothly by restraining voltages when changing

the power supply voltage during operation, as shown in the figure below. Perform

while not using the PLL clock. However, if voltage drops are within 1 V/s, you can

operate while using the PLL clock.

We recommend a rise of

50 mV/ms maximum.

MB90860A Series

(4) Bus Timing (Read) (TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)

Parameter Sym-

bol Pin Condition Value Unit Remarks

Min Max

ALE pulse width tLHLL ALE



tCP/2 − 10 ns

Valid address ⇒ ALE ↓ time tAVLL ALE, A23 to

A16, AD15

to AD00 tCP/2 − 15 ns

ALE ↓ ⇒ Address valid time tLLAX ALE, AD15

to AD00 tCP/2 − 15 ns

Valid address ⇒ RD ↓ time tAVRL A23 toA16,

AD15 to

AD00, RD tCP − 15 ns

Valid address ⇒ Valid data

input tAVDV A23 to A16,

AD15 to

AD00 5 tCP/2 − 40 ns

RD pulse width tRLRH RD 3 tCP/2 − 20 ns

RD ↓ ⇒ Valid data input tRLDV RD, AD15 to

AD00 3 tCP/2 − 50 ns

RD ↑ ⇒ Data hold time tRHDX RD, AD15 to

AD00 0ns

RD ↓ ⇒ ALE ↑ time tRHLH RD, ALE tCP/2 − 15 ns

RD ↑ ⇒ Address valid time tRHAX RD, A23 to

A16 tCP/2 − 10 ns

Valid address ⇒ CLK ↑ time tAVCH A23 to A16,

AD15 to

AD00, CLK tCP/2 − 15 ns

RD ↓ ⇒ CLK ↑ time tRLCH RD, CLK tCP/2 − 15 ns

ALE ↓ ⇒ RD ↓ time tLLRL ALE, RD tCP/2 − 15 ns

MB90860A Series

A23 to A16 0.8 V 2.4 V

2.4 V

0.8 V

tRHAX

AD15 to AD00 0.8 V

2.4 V 2.4 V

0.8 V Address VIL

VIH VIH

VIL Read data

tRHDX

tRLDV

tAVDV

CLK

tAVCH

2.4 V

tRLCH

2.4 V

ALE 2.4 V

tLHLL

2.4 V

tRHLH

0.8 V

tLLAX

2.4 V

tAVLL

tLLRL

tRLRH

0.8 V 2.4 V

tAVRL

MB90860A Series

(5) Bus Timing (Write) (TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Valid address ⇒ WR ↓ time tAVWL A23 to A16,

AD15 to AD00,



tCP−15 ns

WR pulse width tWLWH WR 3 tCP/2 − 20 ns

Valid data output ⇒ WR ↑

time tDVWH AD15 to AD00,

WR 3 tCP/2 − 20 ns

WR ↑ ⇒ Data hold time tWHDX AD15 to AD00,

WR 15 ns

WR ↑ ⇒ Address valid time tWHAX A23 to A16,

WR tCP/2 − 10 ns

WR ↑ ⇒ ALE ↑ time tWHLH WR, ALE tCP/2 − 15 ns

WR ↓ ⇒ CLK ↑ time tWLCH WR, CLK tCP/2 − 15 ns

CLK

tWLCH

2.4 V

ALE

tWHLH

2.4 V

WR (WRL, WRH)

tWLWH

0.8 V 2.4 V

tAVWL

A23 to A16 0.8 V 2.4 V

2.4 V

0.8 V

tWHAX

AD15 to AD00 2.4 V

0.8 V Address 0.8 V

2.4 V

Write data

tDVWH

0.8 V

2.4 V

tWHDX

MB90860A Series

(6) Ready Input Timing (TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)

Note : If the RDY setup time is insufficient, use the auto-ready function.

Parameter Sym-

bol Pin Test

Condition Value Units Remarks

Min Max

RDY setup time tRYHS RDY 45 ns

RDY hold time tRYHH RDY 0 ns

CLK 2.4 V

ALE

RD/WR

RDY

When WAIT is not used.

VIH VIH

tRYHH

RDY

When WAIT is used.

tRYHS

VIL

MB90860A Series

(7) Hold Timing (TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)

Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.

Parameter Symbol Pin Condition Value Units Remarks

Min Max

Pin floating ⇒ HAK ↓

time tXHAL HAK 30 tCP ns

HAK ↑ time ⇒ Pin v alid

time tHAHV HAK tCP 2 tCP ns

HAK

Each pin High-Z

tHAHV

tXHAL

2.4V

0.8V

2.4V 2.4V

0.8V 0.8V

MB90860A Series

(8) UART0/1/2/3/4 (TA = −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)

* : Refer to “ (1) Clock timing” rating for tCP (internal operating clock cycle time).

Notes : •AC characteristic in CLK synchronized mode.

•CL is load capacity value of pins when testing.

•tCP is the machine cycle (Unit : ns)

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK0 to SCK4

Internal clock

operation output

pins are

CL = 80 pF + 1 TTL.

8 tCP*ns

SCK ↓ → SOT delay time tSLOV SCK0 to SCK4,

SOT0 to SOT4 −80 +80 ns

Valid SIN → SCK ↑tIVSH SCK0 to SCK4,

SIN0 to SIN4 100 ns

SCK ↑ → Valid SIN hold time tSHIX SCK0 to SCK4,

SIN0 to SIN4 60 ns

Serial clock “H” pulse width tSHSL SCK0 to SCK4

External clock

operation output

pins are

CL = 80 pF + 1 TTL.

4 tCP*ns

Serial clock “L” pulse width tSLSH SCK0 to SCK4 4 tCP*ns

SCK ↓ → SOT delay time tSLOV SCK0 to SCK4,

SOT0 to SOT4 150 ns

Valid SIN → SCK ↑tIVSH SCK0 to SCK4,

SIN0 to SIN4 60 ns

SCK ↑ → Valid SIN hold time tSHIX SCK0 to SCK4,

SIN0 to SIN4 60 ns

Internal Shift Clock Mode

SCK 2.4 V

tSCYC

0.8 V

SOT 0.8 V

2.4 V

0.8 V

tSLOV

SIN VIL

VIH

tIVSH

VIL

VIH

tSHIX

MB90860A Series

(9) Trigger Input Timing (TA =

= −

−−

−40 °

°°

°C to +

+105 °

°°

°C, VCC =

= 4.5 V to 5.5 V, VSS =

= 0 V)

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Input pulse width tTRGH

tTRGL

INT0 to INT15,

INT0R to INT15R,

ADTG 5 tCP ns

External Shift Clock Mode

SCK VIH

tSLSH

VIL

SOT 0.8 V

2.4 V

tSLOV

SIN VIL

VIH

tIVSH

VIL

VIH

tSHIX

VIH

VIL

tSHSL

VIL

VIH

tTRGH

VIL

VIH

tTRGL

INT0 to INT15,

INT0R to INT15R,

ADTG

MB90860A Series

(10) Timer Related Resource Input Timing (TA = −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)

(11) Timer Related Resource Output Timing (TA = –40° to +105°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V)

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Input pulse width tTIWH TIN0 to TIN3

IN0 to IN7 4 tCP ns

tTIWL

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

CLK ↑ ⇒ TOUT change time tTO TOT0 to TOT3,

PPG0 to PPGF 30 ns

VIL

VIH

tTIWH

VIL

VIH

tTIWL

TIN0 to TIN3,

IN0 to IN7

CLK 2.4 V

0.8 V

2.4 V

tTO

TOT0 to TOT3,

PPG0 to PPGF

MB90860A Series

5. A/D Converter

(TA = −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

* : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) .

Note : The accuracy gets worse as AVRH − AVRL becomes smaller.

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Resolution    10 bit

Total error    ±3.0 LSB

Nonlinearity error    ±2.5 LSB

Differential

nonlinearity error    ±1.9 LSB

Zero reading

voltage VOT AN0 to AN23 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB

Full scale reading

voltage VFST AN0 to AN23 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB

Compare time  1.0 16,500 µs4.5 V ≤ AVCC ≤ 5.5 V

2.0 4.0 V ≤ AVCC < 4.5 V

Sampling time  0.5 ∞µs4.5 V ≤ AVCC ≤ 5.5 V

1.2 4.0 V ≤ AVCC < 4.5 V

Analog port input

current IAIN AN0 to AN23 −0.3 +0.3 µA

Analog input

voltage range VAIN AN0 to AN23 AVRL AVRH V

Reference

voltage range AVRH AVRL + 2.7 AVCC V

AVRL 0 AVRH − 2.7 V

Power supply

current IAAVCC 3.5 7.5 mA

IAH AVCC  5µA*

Reference

voltage current IRAVRH 600 900 µA

IRH AVRH  5µA*

Offset between

input channels AN0 to AN23  4LSB

MB90860A Series

6. Definition of A/D Converter Terms

(Continued)

Resolution : Analog variation that is recognized by an A/D converter.

Non linearity

error : De viation between a line across z ero-tr ansition line ( “00 0000 0000” ← → “00 0000 0001” )

and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion

characteristics.

Differential

linearity error : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal

value.

Total error : Difference between an actual value and an ideal value . A total error includes zero transition

error, full-scale transition error, and linear error.

Zero reading

voltage : Input voltage which results in the minimum conversion value.

Full scale

reading voltage : Input voltage which results in the maximum conversion value.

3FF

3FE

3FD

004

003

002

001

AVRL AVRH

VNT

1.5 LSB

0.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

Actual conversion

characteristics

(Actually-measured value)

Actual conversion

characteristics

Ideal characteristics

Digital output

Analog input

Total error

Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB}

1 LSB [LSB]

1 LSB = (Ideal value) AVRH − AVRL

1024 [V]

VOT (Ideal value) = AVRL + 0.5 LSB [V]

VFST (Ideal value) = AVRH − 1.5 LSB [V]

VNT : A voltage at which digital output transitions from (N − 1) to N.

MB90860A Series

(Continued)

3FF

3FE

3FD

004

003

002

001

AVRL AVRH AVRL AVRH

N + 1

N − 1

N − 2

VOT (actual measurement value)

{1 LSB × (N − 1)

+ VOT }

Actual conversion

characteristics

VFST (actual

measurement

value)

VNT (actual

measurement value)

Actual conversion

characteristics

Ideal characteristics

Actual conversion

characteristics

Actual conversion

characteristics

Ideal

characteristics

Digital output

Analog inputAnalog input

VNT

(actual measurement value)

V (N + 1) T

(actual measurement

value)

Non linearity error Differential linearity error

Non linearity error of digital output N =VNT − {1 LSB × (N − 1) + VOT}

1 LSB [LSB]

Differential linearity error of digital output N =V (N+1) T − VNT

1 LSB −1 LSB [LSB]

VFST − VOT

1022 [V]

1 LSB =

VOT : Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

MB90860A Series

7. Notes on A/D Converter Section

Use the device with external circuits of the following output impedance for analog inputs :

Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,

sampling period ≤ 0.5 µs)

if the output inpedance exceeds 1.5 kΩ, set a longer sampling time or add an external capacitor compensate

the output inpedance. About setting of sampling time, please refer to hardware manual of MB90860A series.

If an e x ternal capacitor is used, in consideration of the eff ect by tap capacitance caused by external capacitors

and on-chip capacitors, capacitance of the e xternal one is recommended to be several thousand times as high

as internal capacitor.

If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient.

8. Flash Memory Program/Erase Characteristics

Parameter Conditions Value Unit Remarks

Min Typ Max

Sector erase time

TA = +25 °C

VCC = 5.0 V

115s

Excludes programming

prior to erasure

Chip erase time 9sExcludes programming

prior to erasure

Word (16 bit width)

programming time 16 3,600 µsExcept for the over head

time of the system

Programs/Erase cycle 10,000 cycle

Comparator

Analog input R

4.5 V ≤ AVCC ≤ 5.5 V : R := 2.52 kΩ, C := 10.7 pF

4.0 V ≤ AVCC < 4.5 V : R := 13.6 kΩ, C := 10.7 pF

• Analog input circuit model

Note : Use the values in the figure only as a guideline.

MB90860A Series

■ORDERING INFORMATION

Part number Package Remarks

MB90F867APF

100-pin Plastic QFP

(FPT-100P-M06)

MB90F867ASPF

MB90867APF

MB90867ASPF

MB90F867APFV

100-pin Plastic LQFP

(FPT-100P-M05)

MB90F867ASPFV

MB90867APFV

MB90867ASPFV

MB90V340

MB90V340S 299-pin Ceramic PGA

(PGA-299C-A01) For evaluation

MB90860A Series

■PACKAGE DIMENSIONS

(Continued)

100-pin Plastic QFP

(FPT-100P-M06)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness including plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

2002 FUJITSU LIMITED F100008S-c-5-5

1 30

5180

100

20.00±0.20(.787±.008)

23.90±0.40(.941±.016)

14.00±0.20

(.551±.008)

17.90±0.40

(.705±.016)

INDEX

0.65(.026) 0.32±0.05

(.013±.002) M

0.13(.005)

"A"

0.17±0.06

(.007±.002)

0.10(.004)

Details of "A" part

(.035±.006)

0.88±0.15

(.031±.008)

0.80±0.20

0.25(.010)

3.00 +0.35

–0.20

+.014

–.008

.118

(Mounting height)

0.25±0.20

(.010±.008)

(Stand off)

0~8˚

MB90860A Series

(Continued)

100-pin Plastic LQFP

(FPT-100P-M05)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

2003 FUJITSU LIMITED F100007S-c-4-6

14.00±0.10(.551±.004)SQ

16.00±0.20(.630±.008)SQ

125

76 50

100

0.50(.020) 0.20±0.05

(.008±.002) M

0.08(.003) 0.145±0.055

(.0057±.0022)

0.08(.003)

"A"

INDEX .059 –.004

+.008

–0.10

+0.20

1.50

(Mounting height)

0˚~8˚

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.25(.010)

0.10±0.10

(.004±.004)

Details of "A" part

(Stand off)

MB90860A Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0309

 FUJITSU LIMITED Printed in Japan