M48Z128Y70PM1 - STMICROELECTRONICS

Not recommended for new design

This is information on a product still in production but not recommended for new designs.

September 2011 Doc ID 2426 Rev 6 1/20

M48Z128

M48Z128Y

5.0 V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM

Features

■Integrated, ultra low power SRAM, power-fail

control circuit, and battery

■Conventional SRAM operation; unlimited

WRITE cycles

■10 years of data retention in the absence of

power

■Battery internally isolated until power is first

applied

■Automatic power-fail chip deselect and WRITE

protection

■WRITE protect voltages:

(VPFD = power-fail deselect voltage)

–M48Z128: V

CC = 4.75 to 5.5 V;

4.5 V ≤ VPFD ≤ 4.75 V

–M48Z128Y: V

CC = 4.5 to 5.5 V;

4.2 V ≤ VPFD ≤ 4.5 V

■Pin and function compatible with JEDEC

standard 128 K x 8 SRAMs

■RoHS compliant

– Lead-free second level interconnect

PMDIP32 module

www.st.com

Contents M48Z128, M48Z128Y

2/20 Doc ID 2426 Rev 6

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

M48Z128, M48Z128Y List of tables
Doc ID 2426 Rev 6 3/20
List of tables
Table 1. Signal names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Operating modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ mode AC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE mode AC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Capacitance  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. Power down/up trip points DC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. PMDIP32 – 32-pin plastic DIP module, package mechanical data. . . . . . . . . . . . . . . . . . . 16
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

List of figures M48Z128, M48Z128Y

4/20 Doc ID 2426 Rev 6

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8

Figure 5. Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. WRITE enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 8. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11. PMDIP32 – 32-pin plastic DIP module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

M48Z128, M48Z128Y Description

Doc ID 2426 Rev 6 5/20

1 Description

The M48Z128/Y ZEROPOWER® RAM is a 128 Kbit x 8 non-volatile static RAM organized

as131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM

and a control circuit in a plastic, 32-pin DIP module to provide a highly integrated battery-

backed memory solution.

The M48Z128/Y is a non-volatile pin and function equivalent to any JEDEC standard

128 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets,

providing the non-volatility of PROMs without any requirement for special WRITE timing or

limitations on the number of WRITEs that can be performed. The 32-pin, 600 mil DIP

module houses the M48Z128/Y silicon with a long-life lithium button cell in a single package.

Figure 1. Logic diagram

Table 1. Signal names

A0-A16 Address inputs

DQ0-DQ7 Data inputs / outputs

EChip enable input

GOutput enable input

WWRITE enable input

VCC Supply voltage

VSS Ground

NC Not connected internally

AI01194

A0-A16

DQ0-DQ7

VCC

M48Z128

M48Z128Y

VSS

Description M48Z128, M48Z128Y

6/20 Doc ID 2426 Rev 6

Figure 2. DIP connections

Figure 3. Block diagram

DQ0

A13

A10

DQ7

A15

A11

DQ5DQ1

DQ2

DQ3VSS

DQ4

DQ6

A16

NC VCC

AI01195

M48Z128

M48Z128Y

A12

A14

AI01196

INTERNAL

BATTERY

VCC

VSS

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

131,072 x 8

SRAM ARRAY

A0-A16

DQ0-DQ7

POWER

M48Z128, M48Z128Y Operating modes

Doc ID 2426 Rev 6 7/20

2 Operating modes

The M48Z128/Y also has its own power-fail detect circuit. The control circuitry constantly

monitors the single VCC supply for an out of tolerance condition. When VCC is out of

tolerance, the circuit write protects the SRAM, providing a high degree of data security in the

midst of unpredictable system operation brought on by low VCC. As VCC falls below the

switchover voltage (VSO), the control circuitry connects the battery which maintains data

until valid power returns.

Table 2. Operating modes

Note: X = VIH or VIL; VSO = battery backup switchover voltage.

2.1 READ mode

The M48Z128/Y is in the READ mode whenever W (WRITE enable) is high and E (chip

enable) is low. The device architecture allows ripple-through access of data from eight of

1,048,576 locations in the static storage array. Thus, the unique address specified by the 17

address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data

will be available at the data I/O pins within address access time (tAVQV) after the last

address input signal is stable, providing that the E and G (output enable) access times are

also satisfied. If the E and G access times are not met, valid data will be available after the

later of chip enable access time (tELQV) or output enable access time (tGLQV). The state of

the eight three-state data I/O signals is controlled by E and G. If the outputs are activated

before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address

inputs are changed while E and G remain low, output data will remain valid for output data

hold time (tAXQX) but will go indeterminate until the next address access.

Mode VCC E G W DQ0-DQ7 Power

Deselect

4.75 to 5.5 V

4.5 to 5.5 V

VIH X X High Z Standby

WRITE VIL XV

IL DIN Active

READ VIL VIL VIH DOUT Active

READ VIL VIH VIH High Z Active

Deselect VSO to VPFD (min)(1)

1. See Table 10 on page 15 for details.

X X X High Z CMOS standby

Deselect ≤ VSO(1) X X X High Z Battery backup mode

Operating modes M48Z128, M48Z128Y

8/20 Doc ID 2426 Rev 6

Figure 4. Chip enable or output enable controlled, READ mode AC waveforms

Note: WRITE enable (W) = high.

Figure 5. Address controlled, READ mode AC waveforms

Note: Chip enable (E) and output enable (G) = low, WRITE enable (W) = high.

AI01197

tAVAV

tAVQV tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

DATA OUT

A0-A16

DQ0-DQ7

VALID

AI01078

tAVAV

tAVQV tAXQX

A0-A16

DQ0-DQ7

VALID

DATA VALID

Table 3. READ mode AC characteristics

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where

noted).

M48Z128/Y M48Z128/Y M48Z128/Y

Unit–70 –85 –120

Min Max Min Max Min Max

tAVAV READ cycle time 70 85 120 ns

tAVQV Address valid to output valid 70 85 120 ns

tELQV Chip enable low to output valid 70 85 120 ns

tGLQV Output enable low to output valid 354560ns

tELQX(2)

2. CL = 5 pF.

Chip enable low to output transition 5 5 5 ns

tGLQX(2) Output enable low to output

transition 33 3ns

tEHQZ(2) Chip enable high to output Hi-Z 303545ns

tGHQZ(2) Output enable high to output Hi-Z 20 25 35ns

tAXQX

Address transition to output

transition 5 5 10 ns

M48Z128, M48Z128Y Operating modes

Doc ID 2426 Rev 6 9/20

2.2 WRITE mode

The M48Z128/Y is in the WRITE mode whenever W and E are active. The start of a WRITE

is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the

earlier rising edge of W or E.

The addresses must be held valid throughout the cycle. E or W must return high for

minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE

cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX or

tEHDX afterward. G should be kept high during WRITE cycles to avoid bus contention;

although, if the output bus has been activated by a low on E and G, a low on W will disable

the outputs tWLQZ after W falls.

Figure 6. WRITE enable controlled, WRITE AC waveforms

Note: Output enable (G) = high.

Figure 7. Chip enable controlled, WRITE AC waveforms

Note: Output enable (G) = high.

AI01198

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A16

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI01199

tAVAV

tEHAX

tDVEH

A0-A16

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

Operating modes M48Z128, M48Z128Y

10/20 Doc ID 2426 Rev 6

Table 4. WRITE mode AC characteristics

2.3 Data retention mode

With valid VCC applied, the M48Z128/Y operates as a conventional BYTEWIDE™ static

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write

protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all

inputs are treated as “Don't care.”

If power fail detection occurs during a valid access, the memory cycle continues to

completion. If the memory cycle fails to terminate within the time tWP

, write protection takes

place. When VCC drops below VSO, the control circuit switches power to the internal energy

source which preserves data.

The internal coin cell will maintain data in the M48Z128/Y after the initial application of VCC

for an accumulated period of at least 10 years when VCC is less than VSO. As system power

returns and VCC rises above VSO, the battery is disconnected, and the power supply is

switched to external VCC. Write protection continues for tER after VCC reaches VPFD to allow

for processor stabilization. After tER, normal RAM operation can resume.

For more information on battery storage life refer to the application note AN1012.

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).

M48Z128/Y M48Z128/Y M48Z128/Y

Unit–70 –85 –120

Min Max Min Max Min Max

tAVAV WRITE cycle time 70 85 120 ns

tAVWL Address valid to WRITE enable Low 0 0 0 ns

tAVEL Address valid to chip enable low 0 0 0 ns

tWLWH WRITE enable pulse width 55 65 85 ns

tELEH Chip enable low to chip enable high 55 75 100 ns

tWHAX WRITE enable high to address transition 5 5 5 ns

tEHAX Chip enable high to address transition 15 15 15 ns

tDVWH Input valid to WRITE enable high 303545ns

tDVEH Input valid to chip enable high 303545ns

tWHDX WRITE enable high to input transition 0 0 0 ns

tEHDX Chip enable high to input transition 10 10 10 ns

tWLQZ(2)(3)

2. CL = 5 pF.

3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

WRITE enable low to output Hi-Z 25 3040ns

tAVWH Address valid to WRITE enable high 65 75 100 ns

tAVEH Address valid to chip enable high 65 75 100 ns

tWHQX(2)(3)WRITE enable high to output transition 5 5 5 ns

M48Z128, M48Z128Y Operating modes

Doc ID 2426 Rev 6 11/20

2.4 VCC noise and negative going transients

ICC transients, including those produced by output switching, can produce voltage

fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if

capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the

bypass capacitors will be released as low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (see Figure 8)

is recommended in order to provide the needed filtering.

In addition to transients that are caused by normal SRAM operation, power cycling can

generate negative voltage spikes on VCC that drive it to values below VSS by as much as

one volt. These negative spikes can cause data corruption in the SRAM while in battery

backup mode. To protect from these voltage spikes, ST recommends connecting a schottky

diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817

is recommended for through hole and MBRS120T3 is recommended for surface-mount).

Figure 8. Supply voltage protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

Maximum ratings M48Z128, M48Z128Y

12/20 Doc ID 2426 Rev 6

3 Maximum ratings

Stressing the device above the rating listed in the absolute maximum ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Table 5. Absolute maximum ratings

Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup

mode.

Symbol Parameter Value Unit

TAAmbient operating temperature 0 to 70 °C

TSTG Storage temperature (VCC off, oscillator off) –40 to 85 °C

TBIAS Temperature under bias –10 to 70 °C

TSLD(1)

1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices

shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST

recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.

Lead solder temperature for 10 seconds 260 °C

VIO Input or output voltages –0.3 to 7 V

VCC Supply voltage –0.3 to 7.0 V

IOOutput current 20 mA

PDPower dissipation 1 W

M48Z128, M48Z128Y DC and AC parameters

Doc ID 2426 Rev 6 13/20

4 DC and AC parameters

This section summarizes the operating and measurement conditions, as well as the DC and

AC characteristics of the device. The parameters in the following DC and AC characteristic

tables are derived from tests performed under the measurement conditions listed in the

relevant tables. Designers should check that the operating conditions in their projects match

the measurement conditions when using the quoted parameters.

Table 6. Operating and AC measurement conditions

Note: Output Hi-Z is defined as the point where data is no longer driven.

Figure 9. AC measurement load circuit

Table 7. Capacitance

Parameter M48Z128/Y Unit

Supply voltage (VCC) 4.75 to 5.5 V or 4.5 to 5.5 V

Ambient operating temperature (TA)0 to 70°C

Load capacitance (CL) 100 pF

Input rise and fall times ≤ 5ns

Input pulse voltages 0 to 3V

Input and output timing ref. voltages 1.5 V

Symbol Parameter(1)(2)

1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.

2. At 25 °C, f = 1 MHz.

Min Max Unit

CIN Input capacitance - 10 pF

CIO(3)

3. Outputs deselected.

Input / output capacitance - 10 pF

AI03630

CL = 100pF

CL includes JIG capacitance

650Ω

DEVICE

UNDER

TEST

1.75V

DC and AC parameters M48Z128, M48Z128Y

14/20 Doc ID 2426 Rev 6

Table 8. DC characteristics

Sym Parameter Test condition(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).

M48Z128/Y

Unit–70 / –85 / –120

Min Max

ILI Input leakage current 0 V ≤ VIN ≤ VCC ±1 µA

ILO(2)

2. Outputs deselected.

Output leakage current 0 V ≤ VOUT ≤ VCC ±1 µA

ICC Supply current E = VIL

Outputs open 105 mA

ICC1 Supply current (standby) TTL E = VIH 7mA

ICC2 Supply current (standby) CMOS E = VCC – 0.2 V 4 mA

VIL Input low voltage –0.30.8 V

VIH Input high voltage 2.2 VCC + 0.3V

VOL Output low voltage IOL = 2.1 mA 0.4 V

VOH Output high voltage IOH = –1 mA 2.4 V

M48Z128, M48Z128Y DC and AC parameters

Doc ID 2426 Rev 6 15/20

Figure 10. Power down/up mode AC waveforms

Table 9. Power down/up AC characteristics

Table 10. Power down/up trip points DC characteristics

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where

noted).

Min Max Unit

tF(2)

2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring

until 200 µs after VCC passes VPFD (min).

VPFD (max) to VPFD (min) VCC fall time 300 µs

tFB(3)

3.V

PFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.

VPFD (min) to VSS VCC fall time 10 µs

tRVPFD (min) to VPFD (max) VCC rise time 10 µs

tRB VSS to VPFD (min) VCC rise time 1 µs

tWP Write protect time 40 150 µs

tER E recovery time 40 120 ms

Symbol Parameter(1)(2)

1. All voltages referenced to VSS.

2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where

noted).

Min Typ Max Unit

VPFD Power-fail deselect voltage M48Z128 4.5 4.6 4.75 V

M48Z128Y 4.2 4.34.5 V

VSO Battery backup switchover voltage M48Z128/Y 3.0 V

tDR(3)

3. At 25 °C; VCC = 0 V.

Expected data retention time 10 YEARS

AI01031

VCC

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tFB

tRB

tWP

tDR

VALID VALID

(PER CONTROL INPUT)

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

tER

Package mechanical data M48Z128, M48Z128Y

16/20 Doc ID 2426 Rev 6

5 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Figure 11. PMDIP32 – 32-pin plastic DIP module, package outline

Note: Drawing is not to scale.

Table 11. PMDIP32 – 32-pin plastic DIP module, package mechanical data

PMDIP

Be1

Symb

mm inches

Typ Min Max Typ Min Max

A9.279.520.365 0.375

A1 0.38 – 0.015 –

B0.430.59 0.017 0.023

C0.200.33 0.008 0.013

D 42.42 43.18 1.670 1.700

E 18.0318.80 0.710 0.740

e1 2.29 2.79 0.090 0.110

e338.1 1.5

eA 14.99 16.00 0.590 0.630

L3.05 3.81 0.120 0.150

S 1.91 2.79 0.075 0.110

N3232

M48Z128, M48Z128Y Part numbering

Doc ID 2426 Rev 6 17/20

6 Part numbering

Table 12. Ordering information scheme

For other options, or for more information on any aspect of this device, please contact the

ST sales office nearest you.

Example: M48Z 128Y –70 PM 1

Device type

M48Z

Supply voltage and write protect voltage

128(1) = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V

1. Device is not recommended for new design. Contact local ST sales office for availability.

128Y(1) = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V

Speed

–70 = 70 ns

–85 = 85 ns

–120(2) = 120 ns

2. Contact local ST sales office for availability.

Package

PM = PMDIP32

Temperature range

1 = 0 to 70 °C

Shipping method

blank = ECOPACK® package, tubes

Environmental information M48Z128, M48Z128Y

18/20 Doc ID 2426 Rev 6

7 Environmental information

Figure 12. Recycling symbols

This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)

button cell battery fully encapsulated in the final product.

Recycle or dispose of batteries in accordance with the battery manufacturer's instructions

and local/national disposal and recycling regulations.

M48Z128, M48Z128Y Revision history
Doc ID 2426 Rev 6 19/20
8 Revision history
Table 13. Revision history
         
Date Revision Changes
May-1999 1 First issue
13-Apr-2000 2 Document layout changed; surface-mount chip set solution added
20-Jun-2000 2.1 tGLQX changed (Ta bl e 3 )
19-Jul-2000 2.2 M48Z128V added
14-Sep-2001 3Reformatted; added temperature information (Ta b l e 7 , 8, 3, 4, 9, 10)
07-Nov-2001 3.1 Remove chipset option from ordering Information (Ta b l e 1 2 )
20-May-2002 3.2 Modify reflow time and temperature footnotes (Tab le 5)
18-Nov-2002 3.3Modifying SMT solution text (Figure 2, 4;Ta bl e 2 )
17-Sep-20033.4 Remove references to M68ZXXX (obsolete) parts (Figure 4; Ta b l e 2 ); 
update disclaimer
22-Feb-2005 4 Reformatted; IR reflow, SO package updates (Ta b l e 5 )
20-Jul-2010 5
Reformatted document; updated Features, Section 3: Maximum ratings, 
Ta b l e 1 1 , 12; added ECOPACK® text to Section 5; added Section 7: 
Environmental information; removed SOH28, SNAPHAT® housing and 
all references from datasheet.
26-Sep-2011 6
Devices are not recommended for new design (updated cover page, 
Ta b l e 1 2 ); updated footnote of Table 5: Absolute maximum ratings; 
updated Section 7: Environmental information; removed M48Z128V.

M48Z128, M48Z128Y

20/20 Doc ID 2426 Rev 6

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