REVISIONS LIR DESCRIPTION DATE (R-MO-DA) APPROVED A Add CAGE number 34335 as approved source for 01 device. Add CAGE number 66579, for devices 01 through 04. Add device 04, deleted footnote 4/ from t Lov condition block, added footnote [| 1989 AUG 23 MG. oye i 4/ to tenoz condition block! Removed test condition C. Made editorial change to margin test method B. Made editorial change to power dissipation. REV SHEET REV SHEET REV STATUS REV ALATA Ja A ALTAIA ALA TATA OF SHEETS SHEET 1213404 $596 1748 J of ofits | 123 fats Ti6 PMIC N/A PREPARED BY . Tie, DEFENSE ELECTRONICS SUPPLY CENTER CHECKED BY DAYTON, OHIO 45444 STANDARDIZED MILITARY MICROCIRCUITS, MEMORY, DIGITAL, CMOS, DRAWING 64 K x 8 UVEPROM, MONOLITHIC SILICON THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS | DRAWING APPROVAL JA SIZE CAGE CODE AND AGENCIES OF THE 13 JUNE 1988 A 67268 9622-87648 DEPARTMENT OF DEFENSE REVISION LEVEL AMSC N/A A SHEET 7 | best a 193 *# U.S. GOVERNMENT PRINTING OFFICE: 1987 748-129/60911 5962-E1413 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.1. SCOPE 1.1 Scope. This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices". 1.2 Part number. The complete part number shall be as shown in the following example: 5962-87648 01 bs X | | 1 1 | | | | | | | | Drawing number Device type Case outline Lead finish per (1.2.1) (1.2.2) MIL-M-38510 1.2.1 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 270512 64K x 8-bit UVEPROM 150 ns 02 270512 64K x 8-bit UVEPROM 200 ns 03 270512 64K x 8-bit UVEPROM 250 ns 04 270512 64K x 8-bit UVEPROM 120 ns 1.2.2 Case outlines. The case outlines shal] be as designated in appendix C of MIL-M-38510, and as follows: Outline letter Case outline x D-10 (28-lead, 1.490" x .610" x .232"), dual-in-line package 1/ Y C-12 (32-terminat, .560" x .458" x .120"), rectangular chip carrier package 1/ 1.3 Absolute maximum ratings. Storage temperature range- -----+-----+--+-- -65C to +150C Input voltages with respect to ground- - - - - - - - -0.6 V dc to +6.25 V dc Output voltages with respect to ground - - - - - - - ~-0.6 V dc to +6.25 V de Yoltage on pin AQ with respect to ground - - - - - - -0.6 V de to +13.5 V de Vpp supply voltage with respect to ground- - - - - - ~0.6 V de to +14.0 V de Power dissipation (Py) 2/ -------+-----+-- 350 mW Lead temperature (soll dering, 10 seconds) - - - - - - 300 C Thermal resistance, junction-to-case (@jc} - - - - - See MIL-M-38510, appendix C Junction temperature (Tj) - --+--------- +150 C 1.4 Recommended operating conditions. Case operating temperature range (Tc)- - - - - - - - -55C to +125C Supply voltage range (Voc) - - - - - -------- +4.5 V dc to 5.5 V dc I7_ Lid shall be transparent to permit ultraviolet light erasure. Z/ Must withstand the added Pp due to short-circuit test; e.g., Ios. STANDARDIZED SIZE MILITARY DRAWING A 5962-87648 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 A 9 DESC FORM 193A SE P 8 7 + U. S. GOVERNMENT PRINTING OFFICE: 1968549-9042. APPLICABLE DOCUMENTS 2.1 Government specification, standard,and bulletin. Unless otherwise specified, the following specification, standard, and bulletin of the Tssue listed in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein. SPECIFICATION MILITARY MIL-M-38510 - Microcircuits, General Specification for. STANDARD MILITARY MIL-STD-883 - Test Methods and Procedures for Microelectronics. BULLETIN MILITARY MIL-BUL-103 - List of Standardized Military Drawings (SMD's). (Copies of the specification, standard, and bulletin required by manufacturers in connection with specific acquisition functions should be obtained from the contracting activity or as directed by the contracting activity.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with 1.2.1 of MIL-STD-883, Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices" and as specified herein, 3.2 Design, construction, and physical dimensions, The design, construction, and physical dimensions shall be as specified in MIL-M-30510 and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.2.1 Unprogrammed or erased devices. The truth table for unprogrammed devices shall be as specified on figure 2. 3.2.2.2 Programmed devices. The requirement for supplying programmed devices are not part of this drawing. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. STANDARDIZED SIZE MILITARY DRAWING A 5962-87648 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 A 3 DESC FORM 193A SEP 87 # U. &. GOVERNMENT PRINTING OFFICE: 1988-549-9041 { { ! Device types 01-04 ! | I | | Case outlines | X Y ! \ I | 1 | Terminal number ! Terminal | Symbol ! T I ] | | 1 { Als | NC \ | 2 | Ayo l Ais | I 3 I AZ | Alp | | 4 | Ag | A; | l 5 | As I Ag | i 6 { Ag { As | | 7 | A3 | Ag | | 8 I Ad I A3 \ | 9 { AY | Ag | \ 10 | " | Ay { | 11 i 1/09 { + i { 12 | 1/04 | N | I 13 I 1/09 | 1/05 i | 14 | GND | 1/0, | | 15 \ 1/03 | 1/0 | | 16 1 1/04 | GND | | 47 | 1/05 | NC | {| 18 | 1/0 | 1/03 | i 19 { 1/07 { 1/04 | | 20 | CE | 1/05, | | 21 \ Aig | 1/06 | | 22 | OE/Vpp | 1/07 | | 23 | Ay { CE | \ 24 \ Ag | A I | 25 | Ag | OL Vpp | | 26 { Ay3 { NC | | 27 | Aga | Aji | | 28 I Voc | Ag | | 29 ee | Ag | i 30 | --- | Ai3 | | 31 \ ~-- | Aig | | 32 \ ser | Vec | \ | | | FIGURE 1. Terminal connections. STANDARDIZED SIZE MILITARY DRAWING A 5962-87648 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 A 4 DESC FORM 193A SEP 87 w U. S. GOVERNMENT PRINTING OFFICE: 1988-550-5474 l 1 ] I l | | Pins | TE | DE/Vpp 1 Ag 1 Vcc | Outputs | | Mode | | I | | | | | | | | | | T T T I T T | ! Read | VIL VIL ! x | Voc D out T T | T l T Output disable VIL Vin X Voc High Z | | | | Standby | Vin x x Vec High Z | T I 7 Program VIL Vpp X ! 6.0 V ! Din ! I Tr | | | Program verify ! Vib VoL X |! 6.0 | D out ! T T T T T I Program inhibit Vin Ypp | X 6.0 V High Z | e Ma fm Tie Tey | Identity IL IL H CC Identity | | I | | | code (s) | | | | | | | | Vy = 11.5 to 12.5 V. X can be either Vy, or Vy_ (don't care state). FIGURE 2. Truth table. STANDARDIZED ir 5962-87648 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 DESC FORM 193A SEP 87 U.S. GOVERNMENT PRINTING OFFICE: 1988550-547ADDRESSES OE/Vpp | OUTPUT CONTROL 4 OUTPUT BUFFERS ADDRESS > pecope BUFFERS x DECODE enoRY MEMO _ MATRIX CE POWER > DOWN > ag T/0,t/0, PROGRAMMING LOGIC FIGURE 3. Block diagram. STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 SIZE A 5962-87648 REVISION LEVEL SHEET 6 DESC FORM 193A SEP 87 w U.S. GOVERNMENT PRINTING OFFICE: 1988550-547A.C. - testing input, output waveform 2.4 2.0 ~*__ TEST _ 2.0 0.8 ~a POINTS ___ m 0.8 0.45 AC testing: Inputs are driven at 2.4 V for a Logic "1" and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a Logic "1" and 0.8 V for a logic O". A.C. waveforms IH IL ADDRESS ADDRESS VALID IH IL << << teLav E/Vpp IH t VoL OLQV EHQZ t <= AVQZ OH OUTPUT VALID OUTPUT OL. < NOTES: 1. tengz 1s specified from DE/Vpp or CE, whichever occurs first. 2. OE/Vpp may be delayed up to troy - toLoy after the falling edge of CE without impact on te gy. ma ota FIGURE 4. Switching waveform. STANDARDIZED SIZE MILITARY DRAWING A 5962-87648 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 A 7 DESC FORM 193A SEP 87 t U.S. GOVERNMENT PRINTING OFFICE: 1968550-547Electrical performance characteristics. I. TABLE w U. 8. GOVERNMENT PRINTING OFFICE: 1988549-904 re = =< << <x > > > > > > Le Lo = 5 5] = a = a 5 = oO pT LS SY EC Q x oa oS oS ~ uw eo N Ww So ~N N co wee [ev |r |e Slols sy | go | = s} jo 3 wo - + > + ~ + oS 4 ~ er eee fee oe a hE se SS Ee I CE Or @ = iS) ( _ = Oo o aw NN oO . as N a om a et . . . wo . wo x = i} o oO Ww oOo Nw a o t 1 ~ 1 w PE dE oun og - oO lead a - ol - - - - Lam _- - _ rm - > > = - -_ - tad - ld uo - - - ~ - ar =< = <= < <= << << < < < = < ft <x Poo wn < = o ~ a o ise) om ~ - ~ om a g ao a a a a e o a n * 25 ~ N N N rN N nN N Nn N nN nN x + ~~] La a o . * - a a - * os - _ wt - el _ 4 7 - ce re ww a a ee ee it ee i me i ee fe fe ee ee we ee pe ee ee a a ee ee es sa n ee eee" =~ ae) So wy Ho > > Ne oO Qo nm wv = . o wo =>W oO . oO @ u > s oO wo eo? CH) > in _ E " Wl a >? tw o _ om vin uw . = < = > N w= AN . w > s > _ _ u a Po ve wn > an " e+ CO fo} a _ N > o oc > a - < oO be covf < > o<6 > a < 3 e ve > a oS > > Ye oe oo of > > > o Nol > Ne > Qo O <= x= o moO oo ~m =a w o E - _ Oo oo soe > =zZom ozo vin w Ht os > > NO tm oO . on ff a oO as wets ot Ee ie U1 il won Hou tt = =z => vu " uo rie . w s o Oo Lid os maz = @w > wv wn > > oo (a) om om oO me WD Or | > > > > = fa are mm mr fe ee a fp a fe ae Pp ee EE a ~ ~ ~ ~ _ a] ~d ~ NI | ~ ~ a = 2 | wy Ln] s 3 a N on ~ eK a NWN : > oon] oO Oo oO oO a ~ =x xn} _ = n =~ = a 2 =) a oO oO oO _ mi | - oO oO =) ct | ost o _. : a _ on > > > > > > _ oO So 5 a Pod ee ep ye 2 zj/oO c a c m4 1 wo w = w % x wv o nD = a 5 x v wy rm Dn mn io] vo wo 2 me * 3 = D nD io) O os] Oa s rar) c to] ae: eo wo a Pe ce] i) + - om) + < o : : a w o cap cul - _ aa pa oO c his o fag wv Dn Se oun or - _ o 9 > i aad - wy -_ B n ; 3 Le 3 > > > o ei 6 we o <3} sat > > < . oO 3 olWM n x cs Sal sc = = = an 3 a S tf a os ve yn eo Or = = nm m o _ = a 4 s be o - = - 3 oe oa - & n oS oO Q ei pt o > >wo r-wWN =< awn Q O F i Ps 2 aS ! =) 2 - ao - ~ = 4 a= Bk ee] T= Pre p= pe r= 3 3 3 - 3 = as S Sk O se 30 Se BO a a a s a wo Qa FO ov Fe in ae aA a ante on v a wo o 3 a ~~ oe) <= < = c s = 3 c Ss w . a So Oo _ m _ m o o o OQ DESC FORM 193A SEP 87TABLE I. Electrical performance characteristics - Continued. address CE or DE/V whichever occurred first Pp | | ! l i ] Test | Symbo? | . Conditions | Group A | Device | Limits | Unit | |-55C < Tc < +125C Vss = 0 V;|subgroups} types | 1 | | i 4.BV < Voc < 5.5 | { | Min | Max | i 1 unless otherwise specified | | | | | 1 | | i | | 1 Address to output |tavay CE = OE/Vpp = Vy, 6/ 7/ 19, 10, 11101 { 1150 | ns delay ~ 7 T T T ] i | | 02 | {200 | | | i | 03 | 1250 | i | | | l T | | I | 04 { 1120 | ! I | | | I | CE to output delay |tELQV OE/Vpp = Vi_ 6/ 7/ IS, 10, 1110 | {150 | ns | | I 02 I {200 | i | | 7 | | ! | 03 | 1250 | i | | | I | 04 | {120 | | I I T ] T T DE to output delay |torev CE = Vy 6/ 7/ 19, 10, 11] 01 | 170 | ns ~ TOT TT | |! ! {02 | 175 | ! ! | 03 | 1100 | | | | | 04 [50 | | | | | T I DE high to output I te HQZ | CE = Vy 4/ 6/ 7/ | lo, 11] o1 | is0 =| ns float | 7~ 7 7 | I | | 02 | [55 | | | | | | | | 03 j60 | | | | | | | 04 145 | [ | Output hold from \tavgz ! CE = DE/Vpp = Vy_ 6/ 7/ | ns | 7 | | i | | I { | | l 9,10, 111 All | 0 | | | | I | i Connect all address inputs and UE to Vy and measure ILo with the output under test connected to . 2/ Test tor all input and control pins. 3/ May not be tested, but shall be guaranteed to the limits specified in table I. 4/ Tested initially and after any design changes that affect this parameter, and therefore shall] be guaranteed to the limits specified in table I. 5/ All pins not being tested shall be grounded. 5/ See figure 4, 7/ Equivalent ac test conditions (actual load conditions vary by tester): Output load = 1 TTL gate and C, = 100 pF. Input rise and fall times < 20 ns. Input pulse levels: 0.45 Vand 2.4 V. Timing measurement reference levels: Inputs = 0.8 V and 2.0 V Outputs = 0.8 VY and 2.0 V STANDARDIZED SIZE sose- ante MILITARY DRAWING A : 62-87648 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 A 9 DESC FORM 193A SEP 87 w U. S. GOVERNMENT PRINTING OFFICE: 1988549-9043.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IT. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-STD-883 (see 3.1 herein). The part shall be marked with the part number listed in 1.2 herein. In addition, the manufacturer's part number may also be marked as listed in MIL-~BUL-103 (see 6.6 herein). 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be Tisted as an approved source of supply in MIL-BUL-103 (see 6.6 herein). The certificate of compliance submitted to DESC-ECS prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-STD-883 (see 3.1 herein} and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-STD-883 (see 3.1 herein) shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DESC-ECS shall be required in accordance with MIL-STD-883 (see 3.1 herein). 3.9 Verification and review, DESC, DESC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing EPROMs. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.10.1 Erasure of EPROMS. When specified, devices shall be erased in accordance with the procedure and characteristics specified in 4.4 herein. 3.10.2 Programmability of EPROMs. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5 herein, 3.10.3 Verification of erasure and/or programmability of EPROMs. When specified devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper State. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection, Sampling and inspection procedures shall be in accordance with section 4 of MLM 3E5T0 to the extent specified in MIL-STD-883 {see 3.1 herein). 4.2 Screening. Screening shal} be in accordance with method 5004 of MIL-STD-883, and shall be conducted on aT devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D using the circuit submitted with the certificate of compliance (see 3.6 herein). (2) Ty = *125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. c. A data retention stress test shail be included as part of the screening procedure and shall consist of the following steps performed in the listed sequence. STANDARDIZED SIZE MILITARY DRAWING A 5962-87648 DEFENSE ELECTRONIGS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 A 1D DESC FORM 193A #U. 8. GOVERNMENT PRINTI : 549-1 SEP 87 ING OFFICE: 1B8549-804Margin test method A. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Program at 25C with a greater than 95 percent pattern (example, diagonal "1's") (see 3.10.2). Unbiased bake for 72 hours at 150C or 24 hours at 200C, Test at 25C (see 3.10.3), including a margin test at Vq = 5.8 V and loose timing (i.e. Tacc = 1 us). Erase (see 3.10.1). Program at 25C with a 50 percent pattern (example, checkerboard bar)(see 3.10.2). (Programmed with checkerboard at wafer sort). Burn-in (see 4.2a). Test at 25C and perform PDA calculations (see table II for required PDA tests to be done here and at step (3). Test at -55C (see 3.10.3). Test at +125C (see 3.10.3). Erase (see 3.10.1). Devices may be submitted for groups A, B, C, and D testing prior to erasure provided the devices have been 100 percent seal tested in accordance with method 5004 of MIL-STD-883. Verify erasure at 25C (see 3.5.3). Margin test method B. * Steps 1 through 3 may be performed at wafer level. (1*) Program greater than 95 percent of the bit locations, including the slowest programming cell (see 3.10.2). The remaining cells shall provide a worst case speed pattern. (2*) Bake, unbiased, for 72 hours at +140C. (3*) Perform a margin test using Vm = +5.8 V at +25C using loose timing (i.e., Tacc = 1 us). (4) Perform dynamic burn-in (see 4.2a). (5) Margin at Vy = +5.8 V at 25C, (6) Perform electrical tests (see 4.2). (7) Erase (see 3.10.1). Devices may be submitted for groups A, B, C, and D testing at this point. (8) Verify erasure (see 3.10.3). STANDARDIZED A MILITARY DRAWING 5962-87648 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 A il DESC FORM 193A SEP 87 + U. 8. GOVERNMENT PRINTING OFFICE: 1988549-904Margin test method C. I Wafer margin test method: {1) Program at 25C with a greater than 95 percent pattern. (example, all "O's"), (2) Measure Vcc maximum and store in die signature row. (3) Unbiased bake for 2 hours at 250C. (4) Test at 25C. Measure Veg maximum and compare to Vcc maximum stored in die. Any die with a delta greater than .66 V constitutes a failure and that die is removed from the lot. II Back end margin test method: (1) Program at 25C with a greater than 95 percent pattern. (example, al] "O's"), (see 3.10.2). (2) Test at 25C. (6.0 V < Veco maximum range < 8.0 ) Measure and record Vec maximum in signature row, (3) Unbiased bake for 32 hours at 200C. The storage time may be modified by using other temperatures in accordance with the Arrhenius relationship: | tr Te 72 Ap =e 1 Ap = acceleration factor (unitless quantity) = t,/t2. = temperature in Kelvin (i.e. C + 273 = Kk). 1 = time (hrs) at temperature T). to = time (hrs) at temperature Tp. . K = Boltzmanns constant = 8.62 x 10-5 eV/K using an apparent activation energy (Eq) of 0.6 V. the maximum storage temperature shal? not exceed 200 C for packaged devices or 300C for unassembled devices. ro. (4) Test at 25C (see step 4 above), (5) Erase (see 3.10.1). (6) Program at 25C with a 50 percent pattern (example checkerboard bar) (see 3.10.2). (7) Test at 25C (see 3.10.3). (8) Burn-in (see 4.2a). (9} Test at 25C (see 3.10.3). (10) Test at 125C (see 3.10.3). (11) Test at -55C (see 3.10.3). (12) Erase (see 3.10.1). Devices may be submitted for groups A, B, , and D testing at this point. (13) Verify erasure at 25C (see 3.10.3). STANDARDIZED SIZE / DRAWING A 5962-87648 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET BRAYTON, OHIO 45444 12 DESC FORM 193A SEP 87 42 U. 8. GOVERNMENT PRINTING OFFICE: 1968550-5474.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 Tncluding groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table 1, method 5005 of MIL-STD-883 shall be omitted. . Subgroup 4 (Cy and Coyy measurements) shall be measured for the initial . characterizatton and Mer any process or design changes which may affect capacitance. Sample size is fifteen devices with no failures, and all input and output terminals tested. d. All devices selected for testing shall have the EPROM programmed with a checkerboard pattern or equivalent. After completion of all testing, the devices shall be erased and verified (except devices submitted for Groups B, , and D testing). e, Subgroups 7 and 8 shall consist of verifying the EPROM pattern specified in 4,.3.1d. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition D using the circuit submitted with the certificate of compliance (see 3.6 herein). (2) Ty = +125C, minimum, (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. c. All devices selected for testing shall be programmed with a checkerboard pattern or equivalent. After completion of all testing those devices that were subjected to a nondestructive subgroup for testing shall be erased and verified. 4.4 Erasing procedure. The recommended erasure procedure for the device is exposure to shortwave ultraviolet Tight which has a wavelength of 2537 Angstroms (A). The in egrated dose (i.e. UV intensity x exposure time) for exposure should be a minimum of 15 Ws/cm. The erasure time with this dosage is approximately 25 minutes using an ultraviolet lamp with a 12000 uW/cm power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integpated dose the device can be exposed to without damage is 7258 Ws/cm (1 week at 12000 uW/cm). Exposure of EPROMs to high intensity UV light for long periods may cause permanent damage. 4.5 Programming procedures. The programming procedures shall be as specified by the device manufacturer. STANDARDIZED SIZE MILITARY DRAWING A 5962-87648 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 A 13 DESC FORM 193A SEP 87 # U. S. GOVERNMENT PRINTING OFFICE: 1988549-904TABLE II. Electrical test requirements. 1/ 2/ 3/ 4/ Groups C and D end-point electrical parameters (method 5005) 2,3,7,8 qT | Subgroups T | MIL-STD-883 test requirements | (per method | ! ! 5005, table I) y { T | Interim electrical parameters | --- \ | (method 5004) | { | i | | I | | Final electrical test parameters | 1*,2,3,7*,8,9, | | (method 5004) ! 10,11 ! T T T | Group A test requirements | 1,2,3,4***,7,8, | ! (method 5005) S/ | 9,10**,11** I i | | i | | | \ i i | { | | 1/ (*) indicates PDA applies to subgroups 1 and 7. 2/ (**) indicates that subgroups 10 and 11, if not tested, shall be guaranteed to the specified limits in table 1. (***) see 4.3.1c, 4/ Any subgroups at the same temperature may be combined when using a multifunction tester. 5/ Subgroups 7 and 8 shall consist of verifying the applicable data pattern, see 4.3.1le. 5, PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL -M-38510. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use when military specifications do not exist and qualified military devices that will perform the required function are not available for OEM application. When a military specification exists and the product covered by this drawing has been qualified for listing on QPL-38510, the device specified herein will be inactivated and will not be used for new design. The QPL-38510 product shall be the preferred item for all applications. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished in accordance with MIL-STD-481 using DD Form 1693, Engineering Change Proposal (Short Form). STANDARDIZED SIZE MILITARY DRAWING A 5962-87648 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DRTON, OHIO 45444 A 14 DESC FORM 193A : U. S. GOVERNMENT : SEP 8 7 e PRINTING OFFICE: 1988549-9046.4 Record of users. Military and industrial users shall inform Defense Electronics Supply Center when a system application requires configuration control and the applicable SMD. DESC will Maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DESC-ECS, telephone (513) 296-6022. 6.5 Comments. Comments on this drawing should be directed to DESC-ECS, Dayton, Ohio 45444, or telephone 513-296-5375. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-BUL-103. Addi tional sources will be adted to MIL-BUL-103 as they become available. The vendors listed in MIL-BUL-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DESC-ECS. The approved sources of supply listed below are for information purposes only and are current only to the date of the last action of this document. | T Vendor | Vendor | Replacement { | Military drawing | CAGE { similar part = Imilitary specification] ! part number | number | number 1/ | part number | { | | | | i T 1 | \ | 34335 |AM27C512-150/BXA | | [5962-8764801XX | 60991 | 270512-15MR/J | l | | 66579 {WS27C512L-15DMB | | | | 1FN41 |AT27C512R-15DM/883 | I | { | | | | 34335 |AM27C512-150/BUA | | |5962-8764801YX 1 60991 | 270512-15MR/K | | | 1 66579 |WS27C512L-15CMB | { | 1FN41 |AT27C512R-15LM/883 | i | { [ | |5962-8764802XX | 60991 | 27C512-20MR/J ( | | | 1FN41 |AT27C0512R-20DM/883 | | { | 34335 |AM27C512-200/BXA | | | | 66579 |WS27C512L-20DMB ssi | | | 01295 |SMJ27C512-20JM I l | | | I { 15962-8764802YX | 60991 | 27512-20MR/K t | | | 1FN41 [AT27C512R-20LM/883 | | I | 66579 {wS27C512L-20CMB- { | | 34335 |AM27C512-200/BUA | | { | | i 7 |5962-8764803XX | 60991 | 27C512-25MR/J | \ | | 1FN41 |AT27C512R-25DM/883 | | I | 34335 1AM27C512-250/BXA [| | i | 66579 |WS27C512L-250MB | | | | 01295 |SMJ27C512-25JM | | See footnote at end of table. STANDARDIZED MILITARY DRAWING 5962-87648 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 A 15 DESC FORM 193A SEP 87 # U. . GOVERNMENT PRINTING OFFICE: 1988550-547| T Yendor | Vendor T Replacement | | Military drawing | CAGE | similar part military specificationl l part number { number | number 1/ | part number | | l | ~ | I T | | | I | 5962-8764803YX | 60991 | 27C0512-25MR/K | | | | 1FN41 |AT27C512R-25LM/883| | | | 66579 |WS27C512L-25CMB | | | | 34335 |AM27C512-250/BUA | | 7 I J | I }5962-8764804XX | 66579 |WS27C512L-12DMB | | | | 1FN41 }AT27C512R-12DM/883}| | ! -| | | T |5962-8764804YX | 66579 |wS27C512L-12CMB | | ! ! 1FN41 | | | JAT27C512R-12LM/883 | / Caution. drawing. Vendor CAGE number 01295 1FN41 34335 60991 66579 Do not use this number for item acquisition. to this number may not satisfy the performance requirements of this Vendor name and address Texas Instruments P. 0. Box 6448 Midland, TX 79711 ATMEL Corporation 2095 Ringwood Avenue San Jose, CA 95131 Advanced Micro Devices 901 Thompson Place Sunnyvale, CA 94086 General Instruments Corporation Microelectronics Division 2355 W. Chandler Boulevard Chandler, AZ 85224 Waferscale Integration, Incorporated 47280 Kato Road Fremont, CA 94538 Items acquired Margin test method Cc STANDARDIZED ween BRAWING SIZE 5962-87648 REVISION LEVEL SHEET 16 Dest FORM 133A SEP 87 wr U.S. GOVERNMENT PRINTING OFFICE: 1988--550-547