82541PI(ER) & 82562GZ(GX) Design Checklist v1.1 Project Name Fab Revision Date Designer Intel Contact Reviewer SECTION General CHECK ITEMS REMARKS Have up-to-date product documentation and spec Documents are subject to frequent change updates Observe instructions for special pins needing pull- Do not connect pull-up or pull-down resistors to up or pull-down resistors any pins marked No Connect. 82562GZ(GX) Connect LCI signals to corresponding signals on LCI Device ICH device. Option Each of the four control pins TESTEN, ISOL_TCK, ISOL_TI, and ISOL_EXEC should be connected to a LAN disable circuit through 100 resistors. Verify LAN disable circuit. Contact Intel for latest LAN disable circuit recommendations. If the LOM disable function is not used, connect Ball A13 to ground through a 3.3 K resistor. Mode 0: see the related 82562ET(EM) and 82562GT(G) documentation. For Modes 1-4, see the related 82562GZ(GX) datasheet. Use a 93C46 EEPROM for non-alerting EEPROM for 82562GZ(GX) attaches to ICHx. applications or a 93C66 EEPROM for ASF 1.0. Add decoupling capacitor. EEPROMs should be Note: DO NOT use a Catalyst 93C46 Revision H. rated for at least 1 MHz. Connect Ball B14 RBIAS10 to ground through a 619 1% resistor. Recommended starting value. Measure PCB's output amplitude and adjust as required to meet IEEE specification. See the 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide for more information. Connect Ball B13 RBIAS100 to ground through a Recommended starting value. Measure PCB's output amplitude and adjust as required to meet 649 1% resistor. IEEE specification. See the 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide for more information. Page 1 DONE COMMENTS SECTION CHECK ITEMS REMARKS 82541PI(ER) Connect 32-bit PCI interface pins to Controller corresponding pins on system. Option Connect Ball A9 LAN_PWR_GOOD to RSM_RST# or other voltage supervisor circuit. For the 82541PI, connect ball A6 PME# to system for wake up signaling. Connect Ball J12 AUX_PWR signals correctly. Input should remain low until all power supplies are stable and for approximately 80ms. LAN_PWR_GOOD works like an auxiliary chip reset. It should be a clean, glitch-free signal. It is not intended for use as a LAN Disable. LAN_PWR_GOOD must be asserted during power down states to allow wakeup. Typical connection is PME# on ICHx. AUX_PWR is a logic input denoting that auxiliary power is connected to the device. AUX_PWR = 1 is a requirement for wakeup. Connect Ball B9 RST# to RST# on system. Bring out Ball B14's (IEEE_TEST+) and Ball D14's (IEEE_TEST-) traces as a differential pair and place a resistor pad between traces, but do not populate a resistor. This is to facilitate IEEE testing. Connect a 0.01 F capacitor between Ball C2 M66EN and ground. M66EN should have a pullup resistor somewhere in the system. Capacitor per spec for signal integrity. This signal may be grounded anywhere on the segment for any PCI device incapable of 66 MHz operation. Connect Ball G2 VIO to 5 V Standby or 3.3 V Standby to match PCI signaling voltage. Ball H4 and G4 are connected to PLL_1.2 V. Use a 100 K resistor as a current limiter and a 0.1 F bypass capacitor. Place appropriate stuffing options for each controller. For the 82541ER, if a LAN disable function is required, drive Ball P9 FLSH_SO /LAN_ DISABLE#. Use a Super I/O GP. For the 82541ER, use a 93C46 EEPROM. Note: For Microwire* EEPROMs, install a 100 pull-down resistor on Ball J4 EEMODE. Do not install a pullDO NOT use a Catalyst 93C46 Revision H. down resistor on the EEDO pin. For SPI EEPROMs, use a 3.3 K pull-up resistor on write protect (WP#) and a 3.3 K pull-up resistor on HOLD#. Microwire EEPROMs should be rated for at least 1 MHz and SPI EEPROMs should be rated for at least 2 MHz. Page 2 DONE COMMENTS SECTION CHECK ITEMS REMARKS For the 82541PI, use a 93C46 EEPROM for non- For Microwire* EEPROMs, install a 100 pull-down alerting applications, an AT25040 for ASF 1.0, or resistor on Ball J4 EEMODE. Do not install a pulldown resistor on the EEDO pin. an AT25080 for ASF 2.0. Note: DO NOT use a Catalyst 93C46 Revision H For SPI EEPROMs, install a 1K pull-up resistor on ball J4 EEMODE, use a 3.3 K pull-up resistor on write protect (WP#) and a 3.3 K pull-up resistor on HOLD#. Microwire EEPROMs should be rated for at least 1 MHz and SPI EEPROMs should be rated for at least 2 MHz. For the 82541PI, check reference schematic for connection of Software Defined Pins (SDPs). Intel driver software may expect to use SDPs for special functions. Connect Ball A13 TEST to ground, using a 1 K resistor for dual layout designs with 82562GZ(GX). For the 82541ER, connect Balls C9, A10, B10 to VCC. 1 K pull-up resistors are reasonable values. Provide a test point for IEEE PHY conformance testing. Depopulate the header for production. This equates to a header between Balls B14 and D14 (differential clock output). Clock Source Use 25 MHz 30 ppm accuracy @ 25 C clock source. Avoid components that introduce jitter. Connect two 22 pF load caps to crystal. EEPROM and Use decoupling capacitor. FLASH Memory EEPROM ORG ties to 3.3 V for x16 access. Consider whether to use FLASH memory. Parallel resonant crystals are preferred. Capacitance affects accuracy of the frequency. Must be matched to crystal specs, including estimated trace capacitance in calculation. Use low ESR caps. Applies to EEPROM or FLASH devices. For Microwire EEPROMs. Depends on EEPROM used. Most LOM systems with boot ROM place the image in the system FLASH. If FLASH memory is used, select the appropriate The 82541PI(ER) uses serial FLASH. device. Page 3 DONE COMMENTS SECTION SMBus (82541PI) CHECK ITEMS REMARKS If SMBus is not used, connect pull-up resistors to 4.7 K pull-ups are reasonable values. SMBCLK, SMBDATA, and SMB_ALERT#. If SMBus is used, system should have pull-up SMBus signals are open-drain. resistors. Connect Ball B10 SMB_ALERT# to the system Use 3.3 V, not 3.3 V AUX. Alternatively, ball B10 LAN_PWR_GOOD signal or to Vcc through a 3.3 can be configured as an SMB_ALERT# output. K W pull-up resistor. Transmit and 82562GZ(GX) PLC devices use pairs of 54.9 Receive termination resistors. Differential Pairs 82541(PI)ER controllers use pairs of 49.9 termination resistors with 0.1 F capacitors attached between center nodes and ground. Apply to both differential pairs. Magnetics Integrated magnetics modules/RJ-45 connectors are available to minimize space requirements. Module (10/100/1000 Base-T Applications) Qualify magnetics module carefully for Return Loss, Insertion Loss, Open Circuit Inductance, Common Mode Rejection, and Crosstalk Isolation Modules with pin compatibility from 10/100 to Gigabit are available, containing internal jumpers for the unused pairs. Multivendor pin compatibility is possible. Contact manufacturers. Apply to all four differential pairs. Magnetics module is critical to passing IEEE PHY conformance tests and EMI test. 82562GZ(GX) PLC devices use a 5-core model. The 82541(PI)ER controller uses a 12-core model. Autotransformer models (10/100) provide better cable termination. All Gigabit models contain autotransformers. For 82562GZ(GX) PLC devices that do not support MDI-X, use 0.1 F capacitor on receive center tap. Improves bit error rate. For 82562GZ(GX) PLC devices that support MDI- For severe EMI problems, a capacitor up to 22 X, do not use capacitor on receive center tap. pF can be used. Larger values will diminish signal strength and fail IEEE PHY conformance. 82562GZ(GX) PLC devices do not use capacitor on transmit center tap. For severe EMI problems, a capacitor up to 22 pF can be used. Larger values will diminish signal strength and fail IEEE PHY conformance. For 82541ER controller, supply 1.8 V to the transformer center taps and use 0.1 F bypass capacitors. These voltages bias the controller's output buffers. Magnetics with four center tap pins may have better characteristics than those with 1-2 center tap pins. Use capacitors with low Equivalent Series Resistance (ESR). Page 4 DONE COMMENTS SECTION Discrete Magnetics Module/RJ-45 Connector Option (10/100/1000 Base-T applications) CHECK ITEMS REMARKS Bob Smith termination: use 4 x 75 resistors for Terminates pair-to-pair common mode impedance of the CAT5 cable. cable-side center taps and unused pins. Bob Smith termination: use an EFT capacitor attached to the termination plane. Suggested values are 1500 pF/2KV or 1000 pF/3KV For the 82541(PI)ER controller, maintain greater than 25 mil spacing from capacitor to traces and components. For high-voltage isolation on 82562GZ(GX) designs, maintain greater than 70 mil spacing from capacitor to traces and components. Round all acute metal-fill angles to remove corners. Connect signal pairs correctly to RJ-45 connector. The differential pairs use pins 1-2 (Transmit in 10/100), 3-6 (Receive in 10/100), 4-5 (Gigabit only), and 7-8 (Gigabit only). Take care not to reverse the polarity. Power Supply For the 82541PI(ER) controller, connect external and Signal PNP transistors to the regulator control CTRL12 and CTRL18 outputs to supply 1.2 V and 1.8 V, Ground respectively. The connections and transistor parameters are critical. Alternatively, provide external regulators to generate these voltages. If the internal voltage regulator control circuit is not used, the CTRL pins may be left unconnected. For the 82541PI, consider using two 0.5 resistors in parallel to the emitter path of the 1.2 V power supply PNP transistor for regulator power dissipation. For 82541PI(ER) controllers and 82562GZ(GX) The 82562GZ(GX) is a single-voltage PLC PLC devices, provide a 3.3 V supply. device. Design with power supplies that start up properly. A good guideline is that all voltages should ramp to within their control bands in 20 ms. or less. It is desirable that voltages ramp in sequence and that the voltage rise be monotonic. For the 82541ER, ensure that there is adequate capacitance on the PNPs. Please check the reference schematic. Use auxiliary power supplies. Auxiliary power is necessary to support wake up from power down states. Page 5 DONE COMMENTS SECTION CHECK ITEMS Use decoupling and bulk capacitors generously. REMARKS Use approximately 12 bypass capacitors for the 82541ER controller. Add approximately 20-30 F of bulk capacitance per voltage rail, typically using 10 F capacitors. If power is distributed on traces, bulk capacitors should be used at both ends. If power is distributed on cards, bulk capacitors should be used at the connector. If possible, provide a separate chassis ground to This design improves EMI behavior. Chassis connect the shroud of the RJ-45 connector and to Ground (10/100/1000 terminate the line side of the magnetics module. Base-T applications) Place pads for approximately four "stitching" Typical values range from 0.1 F to 4.7 F. capacitors to bridge the gap from chassis ground Determine experimentally. to signal ground. Termination For designs with non-integrated magnetics modules, lay out Bob Smith termination plane. Plane Term plane floats over chassis ground. Splits in ground plane should be at least 50 mils to prevent arcing during hi-pot tests. LED Circuits Basic recommendation is a single green LED for Activity and a dual (bi-color) LED for Speed. Many other configurations are possible. A two-LED configuration is compatible with integrated magnetics modules. For the Link/Activity LED, connect the anode to the ACTIVITY#/ACTLED# pin (Ball C11) and the cathode to the LINK_LED/LINK_UP#/LILED# pin (Ball A12). For the bi-color speed LED pair, have the Link 100#/SPDLED# signal drive one end. The other end should be connected to 3.3 V for the 82562GZ(GX) PLC device or to LINK1000# for the 82541ER device (use 0 resistors for dual footprint designs.) Connect LEDs to 3.3 V as indicated in reference schematics. Use 3.3 V AUX for designs supporting wakeup. Consider adding 1-2 filtering capacitors per LED for extremely noisy situations. Suggested starting value 470 pF. Add current limiting resistors to LED paths. Typical current limiting resistors are 250 to 330 (300 to 330 for the 82541PI) when using a 3.3 V supply. Current limiting resistors are typically included with integrated magnetics modules. Page 6 DONE COMMENTS SECTION Mfg Test CHECK ITEMS REMARKS DONE COMMENTS 82541PI(ER) controller uses a JTAG Test Access Place 100 pull-down resistors on Ball L13 Port. JTAG_TRST# and Ball L14 JTAG_TCK. These connections hold the TAP controller in an inactive state. For 82562GZ(GX) PLC devices, depopulate the pull-down resistors. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. The 82541PI(ER) Gigabit Ethernet Controller and 82562GZ(G Fast Ethernet Controllers may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. *Other names and brands may be claimed as the property of others. Copyright (c) Intel Corporation 2005. Page 7