80960CF-33 - Intel - Datasheet.Live

80960CF-40, -33, -25

32-Bit High-Performance Superscalar

Embedded Microprocessor

Datasheet

Product Features

■Socket and Object Code Compatible with 80960CA

■Two Instructions/Clock Sustained Execution

■Four 71 Mbytes/s DMA Channels with Data Chaining

■Demultiplexed 32-Bit Burst Bu s with Pipelining

■32-Bit Parallel Archi tectu re

—Two Instructions/clock Execution

—Load/Store Architect ure

—Sixteen 32-Bit Global Registers

—Sixteen 32-Bit Local Registers

—Manipulates 64-Bit Bit Fields

—11 Addressing Modes

—Full Parallel Fault Model

—Supervisor Protection Model

■Fast Procedure Call/Return Model

—Full Procedure Call in 4 C lo c ks

■On-Chip Register Cache

—Caches Registers on Call/Ret

—Minimum of 6 Fram es Pr ovided

—Up to 15 Programmable Frames

■On-Chip Instruction C ache

—4 Kbyte Two-Way Set Associative

—128-Bit Path to Instruction Sequencer

—Cache-Lock Modes

—Cache-Off Mode

■High Bandwidth On-Chip Data RAM

—1 Kbyte On-Chip Data RAM

—Sust ain s 128 bits per Clock Acce ss

■Selectable Big or Little Endian Byte

Ordering

■Four On-Chip DMA Channels

—71 M bytes/ s Fly-b y Transfers

—40 Mbytes/s Two-Cycle Transfers

—Data Chaining

—Data Packing/Unpacking

—Programmable Prio rity Method

■32-Bit Demultiplexed Burs t Bus

—128-Bit Internal Data Paths to and from

Registers

—Burst Bus for DRAM Interfacing

—Address Pipelining Option

—Fully Programmable Wait States

—Supports 8-, 16- or 32-Bit Bus Widths

—Supports Unaligned Accesses

—Supervisor Protection Pin

■High-Speed Interrupt Controller

—Up to 248 External Interrupts

—32 Fully Progra mmable Priorities

—Multi-mode 8-Bit Interrupt Port

—Four Internal DMA Interrupts

—Separate, Non-maskable Interrupt Pin

—Context Switch in 625 ns Typical

■On-Chip Data Cache

—1 Kbyte Direct-Mapped, Write Through

—128 bits per Clock Access on Cache Hit

Order Number: 272886-002

September 2002

2 Datasheet

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Datasheet 3
Contents
Contents
0 Purpose ..........................................................................................................................................7
0 809 60CF Pro c ess or Over vie w ......................................................................................................7
1 The 80960C-Series Core......................................................................................................8
2 Pipelined, Burst Bus .............................................................................................................9
3 Instruction Set Summary ......................................................................................................9
4 Flexible DMA Controller........................................................................................................9
5 Priority Interrupt Controller....................................................................................................9
0 Package Information ...................................................................................................................10
1 Package Introduction..........................................................................................................10
2 Pin Descriptions..................................................................................................................11
3 80960CF Mechan ic al Data ................ ...... ............................................. .......................... ....16
3.1 80960CF PGA Pinou t ........... ...... ....... ...... ...... ....... ...... ...........................................16
3.2 80960CF PQFP Pinout (80960CF-33 and -25 Only).............................................20
4 Package Thermal Specifications ........................................................................................22
5 Stepping Register Information ............................................................................................24
6 Sources for Accessories.....................................................................................................25
0 Elect rica l Specifications .............................................................................................................26
1 Absolute Maximum Ratings................................................................................................26
2 Operating Conditions..........................................................................................................26
3 Recommended Connections ..............................................................................................27
4 D.C. Specificat ion s ............... ...... ....... ...... ....... ...... .......................... ....................................27
5 A.C. Specifications..............................................................................................................29
5.1 A.C. Test Conditions..............................................................................................35
5.2 A.C. Timing Waveforms.........................................................................................36
5.3 Derating Curves.....................................................................................................40
0 Reset, Backoff and Hold Acknowledge.....................................................................................41
0 Bus Waveforms ...........................................................................................................................43
Figures
80960CF Processor-Block Diagram.............................................................................................7
80960CF PGA Pinout—View from Top (Pins Facing Down)......................................................16
80960CF PGA Pinout—View from Bottom (Pins Facing Up) .....................................................17
80960CF PQFP Pinout—Top View (80960CF-33 and -25 Only) ...............................................22
Measuring 80960CF PGA and PQFP Case Temperature..........................................................23
Register g0 .................................................................................................................................25
A.C. Test Load................. .......................... ......................... .......................... ..............................35
Input and Output Clocks Waveform............................................................................................36
CLKIN Waveform........................................................................................................................36
Output Delay and Float Waveform .............................................................................................37
Input Setup and Hold Waveform.................................................................................................37
NMI, XINT7:0 Input Setup and Hold Waveform..........................................................................38
Hold Acknowledge Timings ........................................................................................................38

Contents
Datasheet
Bus Backoff (BOFF) Timings......................................................................................................39
Relative Timings Waveforms......................................................................................................39
Output Delay or Hold vs. Load Capacitance ..............................................................................40
Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC ................40
ICC vs. Frequency and Temperature—80960CF-33 and -25......................................................40
ICC vs. Frequency and Temperature—80960CF-40...................................................................41
Cold Reset Waveform ................................................................................................................43
Warm Reset Waveform ..............................................................................................................44
Entering the ONCE State ...........................................................................................................45
Clock Synchronization in the 2-x Clock Mode ............................................................................46
Clock Synchronization in the 1-x Clock Mode ............................................................................46
Non-Burst, Non-Pipelined Requests Without Wait States..........................................................47
Non-Burst, Non-Pipelined Read Request With Wait States .......................................................48
Non-Burst, Non-Pipelined Write Request With Wait States .......................................................49
Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus .......................................50
Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................51
Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus........................................52
Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus.............................................53
Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................54
Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ..............................................55
Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus .......................................56
Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................57
Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ...............................................58
Burst, Pipelined Read Request With Wait States, 32-Bit Bus ....................................................59
Burst, Pipelined Read Request With Wait States, 16-Bit Bus ....................................................60
Burst, Pipelined Read Request With Wait States, 8-Bit Bus......................................................61
Using External READY...............................................................................................................62
Terminating a Burst with BTERM ...............................................................................................63
BOFF Functional Timing.............................................................................................................64
HOLD Functional Timing ............................................................................................................65
DREQ and DACK Functional Timi ng..... ....... ...... ....... ......................... .......................... ..............66
EOP Functional Timing...............................................................................................................66
Terminal Count Functional Timing..............................................................................................67
FAIL Functional Timing...............................................................................................................67
A Summary of Aligned and Unaligned Transfers for Little Endian Regions ...............................68
A Summary of Aligned and Unaligned Transfers for Little Endian Regions ...............................69
Idle Bus Operation......................................................................................................................70
Tables
80960CF Instruct ion  Set........... ....... ...... ....... ...... .......................... .......................... ....................10
Symbol Legend................... ...... .......................... .......................... .......................... ....................11
80960CF Pi n Descr iption—External Bus  Signal s...... ...... ...... ....... ...... ....... ...... ....... ....................12
80960CF Pin Description—Processor Control Signals ..............................................................14
80960CF Pi n Descr iption—DMA and Interrupt Unit Control Signals..........................................15
80960CF PG A Pi nou t—In Si gna l Order ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ....................18
80960CF PG A Pi nou t—In Pi n Order............................... .......................... .......................... .......19
80960CF PQ FP Pinout—In Signal Order (80960CF-33 and -25 Only)......................................20
80960CF PQ FP Pinout—In Pin Order (80960CF-33 and -25 Only)...........................................21
Maximum TA at Various Airflows in oC (PGA Package Only).....................................................23
80960CF PGA Pac kage  Therma l Charac teri sti cs ........... ...... ....... ...... ....... .................................24

Datasheet 5
Contents
12 80960CF PQFP Package Thermal Characteristics....................................................................24
13 Die Stepping Cross Reference...................................................................................................25
14 Absolute Maximum Ratings........................................................................................................26
15 Operating Conditions..................................................................................................................26
16 D.C. Specifications .....................................................................................................................28
17 80960CF AC Characteristics (40 MHz) ......................................................................................29
18 80960CF AC Characteristics (33 MHz) ......................................................................................31
19 80960CF AC Characteristics (25 MHz) ......................................................................................33
20 Reset Conditions ........................................................................................................................42
21 Hold Acknowledge and Backoff Conditions................................................................................42
Revision History
Date Revision Description
September 2002 002 References to the -16 MHz product have been removed from the datasheet.
June 1996 001 Initial release of the datasheet.

Contents

6 Datasheet

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80960-40, -33, -25

Datasheet 7

1.0 Purpose

This document provides electrical characteristics of Intel’s i960® CF embedded microprocessor.

For functional d e scr iptions consult the i960® CA/CF Microprocessor User’s Manual (order

number 270710). To obtain data sheet updates and errata, visit the Intel World Wide Web site at

http://www.intel.com or contact your Intel field sales representative.

2.0 80960CF Processor Overview

Intel’s 80960CF is the second processor in the series of superscalar i960 microprocessors that also

includes t he 80960 CA and the 8096 0HA/ HD/HT. Upgrading fro m the 80960C A to the 8096 0CF is

straightforward because the two processors are socket- and object code-compatible.

As shown in Figure 1, the 80960CF’s instruction cache is 4 Kbytes; data cache is 1 Kbyte

(80960CA instruction cache is 1 Kbyte; it does not have a data cache.) This extra cache on the CF

adds a significant performance boost over the CA.

Figure 1. 80960CF Processor-Block Diagram

Execution

Unit

Programmable

Bus Controller

Bus Request

Queues

Six-Port

64-Bit

SRC1 Bus

64-Bit

SRC2 Bus

64-Bit

DST Bus

32-Bit

Base Bus

128-Bit

Load Bus

128-Bit

Store Bus

Instruction

Instruction Cache

(4 Kbyte, Two-Way

Set Associative)

128-BIT CACHE BUS

Prefetch Queue

Interrupt Controller

Control

Address

Data

Memory-side

Machine Bus

Machine Bu s

Parallel

Instruction

Scheduler

Memory Region

Configuration

Multiply/Divide

Unit

Four-Channel

DMA Controller

Interrupt

Port

1 Kbyte

5 to 15 Sets

Data RAM

Address

Gene ra tion Uni t

F_CF001A

DMA Port

1 Kbyte

Direct Mapped

Data Cache

80960-40, -33, -25

8 Datasheet

The 80960CF, object code compatible with the 32-bit 80960 core Architecture, employs Special

Function Reg ister extensions to control on-chip peripherals and instruction set extensi ons to shift

64-bit operands and configure on-chip hardware. Multiple 128-bit internal buses, on-chip

instruction caching and a sophisticated instruction scheduler allow the processor to sustain

execution of two instructions per clock with peak execution of three instructions per clock.

A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte/s bandwidth to a system’s

high-speed external memory subsystem. Also, the 80960CF’s on-chip caching of instructions,

procedure context and critical program data substantially decouples system performance from the

wait states associated with accesses to the system’s slo w er, cost sensitive, main memory

subsystem.

The 80960CF bus controller integrates full wait state and bus width control for highest system

performance with minimal system design comp lexity. Unaligned access and Big End ian byte order

support reduces the cost o f porti ng existing applications to the 80960CF.

The processor also integrates four complete data-chaining DMA channels and a high-speed

interrupt controller on-chip. DMA channels p er form single-cy cle or two - cycle transfers, data

packing and unpacking and data chaining. Block transfers — in addition to source o r destination

synchronized transfers — are supported.

The interrupt controller pr ovides full programmability of 248 interrup t so urces in to 32 priority

levels with a typical in ter rup t task switch (latency) time of 625 ns.

2.1 The 80960C-Series Core

The C-Series core is a very high perfo rmance microarchitectural imp lementation of the 8 0960 Core

Architecture. This core may sustain execution of two instructions per clock (80 MIPS at 40 MHz).

To achieve this level of performance, Intel has incorporated state-of-the-art silicon technology and

innovative microarchitectural constructs into the C-Series core implementation. Factors that

contribute to the core’s performance include:

•Parallel instruction decoding allows issuance of up to three instructions per clock.

•Single-clock execution of most instructions

•Parallel instruction decode allows sustained, simultaneous execution of two single-clock

instructions every clock cycle.

•Efficient instruction pipeline minimizes pipeline break losses.

•Register and resource scoreboarding allow simultaneous multi-clock instruction execution.

•Branch look-ahead and prediction allows many branches to execute with no pipeline break.

•Local Register Cache integrated on-chip caches Call/R etu rn context.

•Two-way set associative, 4 Kbyte integrated instruction cache

•1 Kbyte integrated Data RAM sustains a four-word (128-bit) access every clock cycle.

•Direct mapped, 1 Kbyte data cache, write through, write allocate

80960-40, -33, -25

Datasheet 9

2.2 Pipelined, Burst Bus

A 32-bit high performance bus controller interfaces the 80960CF to external memory and

peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at

40 MHz). Internally programmable wait states an d 16 separately conf ig urab le memo r y regi ons

allow the processor to interface with a variety of memory subsystems with a minimum of system

complexity and a maximum of performance. The Bus Control Unit’s main features include:

•Demultiplexed, burst bus to exploi t most efficient DRAM access modes

•Address pipelining to reduce memory cost while maintaining performance

•32-, 16- and 8-bit modes for I/O interfacing ease

•Full internal wait state generation to reduce system cost

•Little and Big Endian support to ease ap pli cation development

•Unaligned access support for code portability

•Three-deep request queue to decouple the bus from the core

2.3 Instruction Set Summary

Table 1 summarizes the 80960CF instruction set by logical groupings. For a complete description

of the instruction s et, s ee th e i960® CA/CF Micro pr ocessor User’s Manual (order num ber 270710 ).

2.4 Flexible DMA Controller

A four-channel DMA controller provides high speed DMA control for data transfers involving

peripherals and memory. The DMA provides advanced features such as data chaining, byte

assembly and di sassem bly and a high p erfo rmance fly-by mode capable of transfer speeds of u p to

71 Mbytes per second at 40 MHz. The DMA controller features a performance and flexibility

which is only possible by in tegratin g the DMA controller and the 80960CF core.

2.5 Priority Interr upt Contro ll er

A progr ammabl e-p riority interru pt co nt roll er manages u p to 24 8 external sources throu gh t he 8 -bit

external interrupt port. The Interrupt Unit also handles the four internal so urces from the DMA

controller and a single non-maskable interrupt input. The 8-bit interrupt port may also be

configured to provide individual inter r upt sources that are level or edge triggered.

80960CF interrupts are prioritized and signaled within 225 ns of the request. When the interrupt is

of higher priority than the pro cessor priority, the context switch to the interrupt routine typically

completes in another 400 ns. The interrupt unit provides the mechanis m for the lo w latency and

high throughput interrupt s ervice which is essential for embedded applications.

Table 1 presents the 80960CF Instr uction Set.

80960-40, -33, -25

10 Datasheet

3.0 Package Information

3.1 Package Introduction

This section desc ribes the pi ns , pinou ts and t her mal charact eris tics for the 80 960 CF in th e 168- pin

Ceramic Pin Grid Array (PGA) package; the 80960CF-33 and -25 devices are also available in the

196-pin Plastic Quad Flat Package (PQFP). For complete package specifications and information,

see the Intel Packaging Databook, available in individual chapters, at http://www.intel.com.

Table 1. 80960CF Instruction Set

Data Movement Arithmetic Logical Bit / Bit Field / Byte

Load

Store

Move

Load Address

Add

Subtract

Multiply

Divide

Remainder

Modulo

Shift

*Extended Shift

Extended Multiply

Extended Divide

Add with Carry

Subtract with Carry

Rotate

And

Not And

And Not

Exclusive Or

Not Or

Or Not

Nor

Exclusive Nor

Not

Nand

Set Bit

Clear Bit

Not Bit

Alter Bit

Scan For Bit

Span Over Bit

Extract

Modify

Scan Byte for Equal

Comparison Branch Call/Return Fault

Compare

Conditional Compare

Compare and Increment

Compare and Decrement

Test Condition Code

Check Bit

Unconditional Branch

Conditional Branch

Compare and Branch

Call

Call Extended

Call System

Return

Branch and Link

Conditional Fault

Synchronize Faults

Debug Processor Mgmt Atomic

Modify Trace Controls

Mark

Force Mark

Flush Local Registers

Modify Arithmetic

Controls

Modify Process Controls

*System Control

*DMA Control

Atomic Add

Atomic Modify

NOTE: Instructions marked by (*) are 80960Cx extensions to the 80960 instruction set.

80960-40, -33, -25

Datasheet 11

3.2 Pin Descriptions

This section defines the 80960CF pins. Table 2 presen ts the legend for interpreting the pin

descriptions in Tables 3 through 5. Table 3 presents the external bus signals. Table 4 presents

processor control signals. Table 5 presents the DMA and Interrupt Unit control signals.

Note: All pins float while the processor is in the ONCE mode.

Table 2. Symbol Legend

Symbol Description

IInput only pin

OOutput only pin

I/O Pin may be either an input or output

–Pins “must be” connected as described

S(...)

Synchronous. Inputs must meet setup and hold times relative to PCLK2:1 for proper operation.

Outputs are synchronous to PCLK2:1.

S(E) Edge sensitive input

S(L) Level sensitive input

A(...) Asynchronous. Inputs may be asynchronous to PCLK2:1.

A(E)Edge sensitive input

A(L)Level sensitive input

H(...)

While the bus is in the Hold Acknowledge or Bus Backoff state, the pin:

H(1) is driven to VCC

H(0)is driven to VSS

H(Z) floats

H(Q)continues to be a valid input

R(...)

While the processor ’s RESET pin is low, the pin:

R(1) is driven to VCC

R(0)is driven to VSS

R(Z) floats

R(Q)continues to be a valid output

80960-40, -33, -25

12 Datasheet

Table 3. 80960CF Pin Description—External Bus Signals (Sheet 1 of 2)

Name Type Description

A31:2

H(Z)

R(Z)

ADDRESS BUS carries the physical address’ upper 30 bit s . A31 is the most significant

bit; A2 is least significant. During a bus access, A31:2 identify all external addresses to

word (4-byte) boundaries. Byte enable signals indicate the selected byte in each word.

During burst accesses, A3:2 increment to indicate success ive data cycles.

D31:0

I/O

S(L)

H(Z)

R(Z)

DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width

configuration. The least significant bit is carried on D0 and the most significant on D31.

When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-

bit data bus widths, D15:0 are used. For 32-bit bus widths the full data bus is used.

BE3:0

H(Z)

R(1)

BYTE ENABLES select which of the four bytes addressed by A31:2 are active during

an access to a memory region configured for a 32-bit data-bus width. BE3 applies to

D31:24; BE2 applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0.

32-bit bus:

BE3 Byte Enable 3 enable D31:24

BE2 Byte Enable 2 enable D23:16

BE1 Byte Enable 1 enable D15:8

BE0 Byte Enable 0 enable D7:0

For accesses to a memory region configured for a 16-bit data-bus width, the processor

uses the BE3, BE1 and BE0 pins as BHE, A1 and BLE respectively.

16-bit bus:

BE3 Byte High Enable (BHE) enable D15:8

BE2 Not used (driven high or low)

BE1 Address Bit 1 (A1)

BE0 Byte Low Enable (BLE) enable D7:0

For accesses to a memory region configured for an 8-bit data-bus width, the processor

uses the BE1 and BE0 pins as A1 and A0 respectively.

8-bit bus:BE3 Not used (driven high or low)

BE2 Not used (driven high or low)

BE1 Address Bit 1 (A1)

BE0 Address Bit 0 (A0)

W/R

H(Z)

R(0)

WRITE/READ is asserted for read requests and deasserted for write requests.

The W/R signal changes in the same clock cycle as ADS. It remains valid for the entire

access in non-pipelined regions. In pipelined regions, W/R is not ensured to be valid in

the last cycle of a read access.

ADS

H(Z)

R(1)

ADDRESS STROBE indicates a valid address and the start of a new bus access. ADS

is asserted for the first clock of a bus access.

READY

S(L)

H(Z)

R(Z)

READY is an input which signals the termination of a data transfer. READY is used to

indicate that read data on the bus is valid or that a write-data transfer has completed.

The READY signal works in conjunction with the internally programmed wait-state

generator. When READY is enabled in a region, the pin is sampled after the

programmed number of wait-states has expired. When the READY pin is deasserted,

wait states continue to be inserted until READY becomes asser ted. This is true for the

NRAD, NRDD, NWAD and NWDD wait states. The NXDA wait st ates cannot be extended.

BTERM

S(L)

H(Z)

R(Z)

BURST TERMINATE is an input which breaks up a burst access and causes another

address cycle to occur. The BTERM signal works in conjunction with the internally

programmed wait-state generator. When READY and BTERM are enabled in a region,

the BTERM pin is sampled after the programmed number of wait states has expired.

When BTERM is asserted, a new ADS signal is generated and the access is completed.

The READY input is ignored when BTERM is asserted. BTERM must be externally

synchronized to satisfy BTERM setup and hold times.

WAIT

H(Z)

R(1)

WAIT indicates internal wait state generator status. WAIT is asserted when wait states

are being caused by the internal wait state generator and not by the READY or BTERM

inputs. WAIT may be used to derive a write-data strobe. WAIT may also be thought of

as a READY output that the processor provides when it is inserting wait states.

80960-40, -33, -25

Datasheet 13

BLAST

H(Z)

R(0)

BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the last

data transfer of burst and non-burst accesses after the wait state counter reaches zero.

BLAST remains asserted until the clock following the last cycle of the last data transfer

of a bus access. When the READY or BTERM input is used to extend wait states, the

BLAST signal remains asserted until READY or BTERM terminates the access.

DT/R

H(Z)

R(0)

DATA TRANSMIT/RECEIV E indicates direction for data transceivers. DT/R is used in

conjunction with DEN to provide control for data transceivers attached to the external

bus. When DT/R is asserted, the signal indicates that the processor receives data.

Conversely , when deasserted, the processor sends data. DT/R changes only while DEN

is high.

DEN

H(Z)

R(1)

DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of

the bus request first data cycle and is deasserted at the end of the last data cycle. DEN

is used in conjunction with DT/R to provide control for data transceivers attached to the

external bus. DEN remains asserted for sequential reads from pipelined memory

regions. DEN is deasserted when DT/R changes.

LOCK

H(Z)

R(1)

BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK

may be used to prevent external agents from accessing memory which is currently

involved in an atomic operation. LOCK is asserted in the first clock of an atomic

operation and deasserted in the clock cycle following the last bus access for the atomic

operation. To allow the most flexibility for memor y system enforcement of locked

accesses, the processor acknow ledges a bus hold request when LOCK is asserted.

The processor performs DMA transfers while LOCK is active.

HOLD

S(L)

H(Z)

R(Z)

HOLD REQUEST signals that an external agent requests access to the external bus.

The processor asserts HOLDA after completing the current bus request. HOLD, HOLDA

and BREQ are used together to arbitrate access to the processor’s external bus by

external bus agents.

BOFF

S(L)

H(Z)

R(Z)

BUS BACKOFF, when asserted, suspends the current access and causes the bus pins

to float. When BOFF is deasserted, the ADS signal is asserted on the next clock cycle

and the access is resumed.

HOLDA

H(1)

R(Q)

HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has

relinquished control of the external bus. When HOLDA is asserted, the external address

bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ are

used together to arbitrate access to the processor’s external bus by external bus

agents. Since the processor grants HOLD requests and enters the Hold Acknowledge

state even while RESE T is asserted, the state of the HOLDA pin is independent of the

RESET pin.

BREQ

H(Q)

R(0)

BUS REQUEST is asserted when the bus controller has a request pending. BREQ may

be used by external bus arbitration logic in conjunction with HOLD and HOLDA to

determine when to return mastership of the external bus to the processor.

D/C

H(Z)

R(Z)

DATA OR CODE is asserted for a data request and deasserted for instruction requests.

D/C has the same timing as W/R.

DMA

H(Z)

R(Z)

DMA ACCESS indicates whether the bus request was initiated by the DMA controller.

DMA is asserted for any DMA request. DMA is deasserted for all other requests.

SUP

H(Z)

R(Z)

SUPERVISOR ACCESS indicates whether the bus request is issued while in supervisor

mode. SUP is asserted when the request has supervisor privileges and is deasserted

otherwise. SUP may be used to isolate supervisor code and data structures from non-

supervisor requests.

Table 3. 80960CF Pin Description—External Bus Signals (Sheet 2 of 2)

Name Type Description

80960-40, -33, -25

14 Datasheet

Table 4. 80960CF Pin Description—Processor Control Signals (Sheet 1 of 2)

Name Type Description

RESET

A(L)

H(Z)

R(Z)

RESET causes the chip to reset. When RESET is asserted, all external signals return

to the reset state. When RESET is deasserted, initialization begins. When the 2-x

clock mode is selected, RESET must remain asserted for 32 CLKIN cycles before

being deasserted to ensure correct processor initialization. When the 1-x clock mode

is selected, RESET must remain asserted for 10,000 CLKIN cycles before being

deasserted to ensure correct processor initialization. The CLKMOD E pin selects 1-x

or 2-x input clock division of the CLKIN pin.

The Hold Acknowledge bus state functions while the chip is reset. When the bus is in

the Hold Acknowledge state when RESET is asserted, the processor internally

resets, but maintains the Hold Acknowledge state on external pins until the Hold

request is removed. When a Hold request is made while the processor is in the reset

state, the processor bus grants HOLDA and enters the Hold Acknowledge state.

FAIL

H(Q)

R(0)

FAIL indicates failure of the self-test performed at initialization. When RESET is

deasserted and initializat ion begins, the FAIL pin is asserted. An internal self-test is

performed as part of the initialization process. When this self-test passes, the FAIL

pin is deasserted; otherwise it remains asserted. The FAIL pin is reasserted while the

processor performs an external bus self-confidence test. When this self-test passes,

the processor deasserts the FAIL pin and branches to the user’s initializ ation routine;

otherwise the FAIL pin remains asserted. Internal self-test and the use of the FAI L pin

may be disabled with the STEST pin.

STEST

S(L)

H(Z)

R(Z)

SELF TEST enables or disables the internal self-test feature at initialization. STEST

is read on the rising edge of RESET. When asserted, internal self-test and external

bus confidence tests are performed during processor initialization. When deasserted,

only the bus confidence tests are performed during initialization.

ONCE

A(L)

H(Z)

R(Z)

ON CIRCUIT EMULATION, when asserted, causes all outputs t o be floated. ONCE is

continuously sampled while RESET is low and is latched on the rising edge of

RESET. To place the processor in the ONCE state:

(1) Assert RES ET and ONCE (order does not matter)

(2) Wait for at least 16 CLKIN periods in 2-x mode—or 10,000 CLKIN

periods in 1-x mode—after VCC and CLKIN are within operating

specifications

(3) Deassert RESET

(4) Wait at least 32 CLKIN periods

(The processor may now be latched in the ONCE state while RESET is high.)

To exit the ONCE state, bring VCC and CLKIN to operating conditions, then assert

RESET and bring ONCE high prior to deasserting R ESE T.

CLKIN must operate within the specified operating conditions until Step 4 completes.

CLKIN may then be changed to DC to achieve the lowest possible ONCE mode

leakage current.

ONCE may be used by emulator products or board testers to effectively make an

installed processor transparent in the board.

CLKIN

A(E)

H(Z)

R(Z)

CLOCK INPUT is an input for the external clock needed to run the processor. The

external clock is internally divided as prescribed by the CLKMODE pin to produce

PCLK2:1.

CLKMODE

A(L)

H(Z)

R(Z)

CLOCK MODE selects the division factor applied to the external clock input (CLKIN).

When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the

processor’s internal clock. When CLKMODE is low , CLKIN is divided by two to create

PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high or low in

a system as the clock mode is not latched by the processor. When left unconnected,

the processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode.

80960-40, -33, -25

Datasheet 15

PCLK2:1

H(Q)

R(Q)

PROCESSOR OUTPUT CLOCKS provide a timing reference for all inputs and

outputs. All input and output timings are specified in relation to PCLK2 and PCLK1.

PCLK2 and PCLK1 are identical signals. Two output pins are provided to allow

flexibility in the system’s allocation of capacitive loading on the clock. PCLK2:1 may

also be connected at the processor to form a single clock signal.

VSS –GROUND connections must be connected externally to a VSS board plane.

VCC –POWER connections must be connected externally to a VCC board plane.

VCCPLL –VCCPLL is a separate VCC supply pin for the phase lock loop used in 1-x clock mode.

Connecting a simple lowpass filter to VCCPLL may help reduce clock jitter (TCP) in

noisy environments. Otherwise, VCCPLL should be connected to VCC.

NC –NO CONNECT pins must not be connected in a system.

Table 5. 80960CF Pin Description—DMA and Interrupt Unit Control Signals

Name Type Description

DREQ3:0

A(L)

H(Z)

R(Z)

DMA REQUEST is used to request a DMA transfer. Each of the four signals

requests a transfer on a single channel. DREQ0 requests channel 0, DREQ1

requests channel 1, etc. When two or more channels are requested simultaneously,

the channel with the highest priority is serviced first. Channel priority mode is

programmable.

DACK3:0

H(1)

R(1)

DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of

the four signals acknowledges a transfer for a single channel. DACK0

acknowledges channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are

asserted when the requesting device of a DMA is accessed.

EOP/TC3:0

I/O

A(L)

H(Z/Q)

R(Z)

END OF PROCESS/TERMINAL COUNT may be programmed as either an input

(EOP3:0) or output (TC3:0), but not both. Each pin is individually programmable.

When programmed as an input, EOPx causes termination of a current DMA transfer

for the channel that corresponds to the EOPx pin. EOP0 corresponds to channel 0,

EOP1 corresponds to channel 1, etc. When a channel is configured for source and

destination chaining, the EOP pin for that channel causes termination of only the

current buffer transferred and causes the next buffer to be transferred. EOP3:0 are

asynchronous inputs.

When programmed as an output, the channel’s TCx pin indicates that the channel

byte count has reached 0 and a DMA has terminated. TCx is driven with the same

timing as DACKx during the last DMA transfer for a buffer. When the last bus

request is executed as multiple bus accesses, TCx stays asserted for the entire bus

request.

XINT7:0

A(E/L)

H(Z)

R(Z)

EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins may

be configured in three modes:

Dedicated Mode: Each pin is a dedicated external interrupt source. Dedicated

inputs may be individually programmed to be level (low) or edge (falling) activated.

Expanded Mode: The eight pins act together as an 8-bit vectored interrupt source.

The interrupt pins in this mode are level activated. Since the interrupt pins are active

low, the vector number requested is the 1’s complement of the positive logic value

place on the port. This eliminates glue logic to interface to combinational priority

encoders which output negative logic.

Mixed Mode: XINT7:5 are dedicated sources and XINT4:0 act as the five most

significant bits of an expanded mode vector. The least significant bits are set to 010

internally.

NMI

A(E)

H(Z)

R(Z)

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.

NMI is the highest priority interrupt recognized . NMI is an edge (falling) activated

source.

Table 4. 80960CF Pin Description—Processor Control Signals (Sheet 2 of 2)

Name Type Description

80960-40, -33, -25

16 Datasheet

3.3 80960CF Mechanical Data

3.3.1 80960CF PGA Pinout

Figure 2 shows the complete 80960CF PGA pinout as viewed from the top side of the component

(i.e., pins facing down). Figure 3 shows the complete 80960CF PGA pinout as viewed from the

pin-side of the package (i.e., pins facing up).

Table 6 presents the 80960CF pin names and packag e location in sign al order. Table 7 presents the

pin names and package location in pin order. See Section 4.0, “Electrical Specifications” on

page 26 for specifications and recommended connections.

Figure 2. 80960CF PGA Pinout—View from Top (Pins Facing Down)

D5D7D8D9D11D12D13D15D16D17D19D21D24D25

D2D4D6VCC

D10VCC

VCC

D14VCC

D18D20D23D27D29

NCD0VCC

VSS

VCC

D22D31READY D26

D28

BTERM

HOLDA

D30HOLDBE3

VCC

ADSBE2

VSS

VCC

BE1

VSS

VCC

BLAST

VSS

BE0DEN

VSS

VCC

W/R

VSS

VCC

DT/R

A29LOCK

SUPWAIT DMA

A28

A30BREQD/C

ONCE

VCC

VSS

CLKIN

CLKMODE

VSS

BOFF

STEST

DREQ0

DREQ2

VCC

DACK0

VCC

VCCPLL

VCC

PCLK2

PCLK1

VCC

FAIL

DREQ1

DREQ3

DACK1

DACK2

DACK3

EOP/TC0

EOP/TC2

EOP/TC3

EOP/TC1

VSS

VCC

A22A25

A20 VSS

A3A5

NMI

VCC

VSS

VSS VSS

A24A31 A26

A4VCC

A6A8A9A10A11A12A14A15A17A18

VCC

A13VCC

A16A19A21A23A27 A7 XINT6

XINT7

XINT4

XINT3

XINT5

XINT0

RESET

XINT2

XINT1

ABCDEFGHJKLMNPQRS

F_CA002A

ABCDEFGHJKLMNPQRS

80960-40, -33, -25

Datasheet 17

Figure 3. 80960CF PGA Pinout—View from Bottom (Pins Facing Up)

D5 D7 D8 D9 D11 D12 D13 D15 D16 D17 D19 D21 D24 D25

D2 D4 D6 VCC D10 VCC VCC D14 VCC D18 D20 D23 D27 D29

NC D0 VCC VSS VSS VSS VSS VSS VSS VCC D22 D31 READYD26

D28 BTERM HOLDA

D30 HOLD BE3

VCC ADS BE2

VSS VCC BE1

VSS VCC BLAST

VSS BE0 DEN

VSS VCC W/R

VSS VCC DT/R

A29 LOCK

SUP WAITDMA

A28

A30 BREQ D/C

ONCE

VCC

VSS

CLKIN

CLK MODE

VSS

BOFF

STEST

DREQ0

DREQ2

VCC

DACK0

VCC

VCCPLL

VCC

PCLK2

PCLK1

VCC

FAIL

DREQ1

DREQ3

DACK1

DACK2

DACK3

EOP/TC0

EOP/TC2

EOP/TC3

EOP/TC1

VSS

VCC

A22 A25

A20VSS

A3 A5

NMI VCC VSS VSS VSS VSS

VSS A24 A31A26

A4 VCC

A6 A8 A9 A10 A11 A12 A14 A15 A17 A18

VCC VCC VCC A13 VCC A16 A19 A21 A23 A27A7XINT6

XINT7

XINT4

XINT3

XINT5

XINT0

RESET

XINT2

XINT1

F_CA003A

ABCDEFGHJKLMNPQRS

Metal Lid

80960-40, -33, -25

18 Datasheet

Table 6. 80960CF PGA Pinout—In Signal Order

Address Bus Data Bus Bus Control Processor Control I/O

Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin

A31 S15 D31 R3 BE3 S5 RESET A16 DREQ3 A7

A30 Q13 D30 Q5 BE2 S6 DREQ2 B6

A29 R14 D29 S2 BE1 S7 FAIL A2 DREQ1 A6

A28 Q14 D28 Q4 BE0 R9 DREQ0 B5

A27 S16 D27 R2 STEST B2

A26 R15 D26 Q3 W/R S10 DACK3 A10

A25 S17 D25 S1 ONCE C3 DACK2 A9

A24 Q15 D24 R1 ADS R6 DACK1 A8

A23 R16 D23 Q2 CLKIN C13 DACK0 B8

A22 R17 D22 P3 READY S3 CLKMODE C14

A21 Q16 D21 Q1 BTERM R4 PLCK1 B14 EOP/TC3 A14

A20 P15 D20 P2 PLCK2 B13 EOP/TC2 A13

A19 P16 D19 P1 WAIT S12 EOP/TC1 A12

A18 Q17 D18 N2 BLAST S8 VSS EOP/TC0 A11

A17 P17 D17 N1 Location

A16 N16 D16 M1 DT/R S11 C7, C8, C9, C10, C11,

C12, F15, G3, G15,

H3, H15, J3, J15, K3,

K15, L3, L15, M3,

M15, Q7, Q8, Q9,

Q10, Q11

XINT7 C17

A15 N17 D15 L1 DEN S9 XINT6 C16

A14 M17 D14 L2 XINT5 B17

A13 L16 D13 K1 LOCK S14 XINT4 C15

A12 L17 D12 J1 XINT3 B16

A11 K17 D11 H1 VCC XINT2 A17

A10 J17 D10 H2 HOLD R5 Location XINT1 A15

A9 H17 D9 G1 HOLDA S4 B7, B9 , B11, B12, C6,

E15, F3, F16, G2,

H16, J2, J16, K2, K16,

M2, M 1 6, N3, N 1 5 ,

Q6, R7, R8, R10, R11

XINT0 B15

A8 G17 D8 F1 BREQ R13

A7 G16 D7 E1 NMI D15

A6 F17 D6 F2 D/C S13

A5 E17 D5 D1 DMA R12

A4 E16 D4 E2 SUP Q12 VCCPLL B10

A3 D17 D3 C1 No Connect

A2 D16 D2 D2 BOFF B1 Location

D1 C2 A1, A3, A4, A5, B3,

B4, C4, C5, D3

D0 E3

80960-40, -33, -25

Datasheet 19

Table 7. 80960CF PGA Pinout—In Pin Order

Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal

A1 NC C1 D3 F17 A6 M15 VSS R3 D31

A2 FAIL C2 D1 G1 D9 M16 VCC R4 BTERM

A3 NC C3 ONCE G2 VCC M17 A14 R5 HOLD

A4 NC C4 NC G3 VSS N1 D17 R6 ADS

A5 NC C5 NC G15 VSS N2 D18 R7 VCC

A6 DREQ1 C6 VCC G16 A7 N3 VCC R8 VCC

A7 DREQ3 C7 VSS G17 A8 N15 VCC R9 BE0

A8 DACK1 C8 VSS H1 D11 N16 A16 R10 VCC

A9 DACK2 C9 VSS H2 D10 N17 A15 R11 VCC

A10 DACK3 C10 VSS H3 VSS P1 D19 R12 DMA

A11 EOP/TC0 C11 VSS H15 VSS P2 D20 R13 BREQ

A12 EOP/TC1 C12 VSS H16 VCC P3 D22 R14 A29

A13 EOP/TC2 C13 CLKIN H17 A9 P15 A20 R15 A26

A14 EOP/TC3 C14 CLKMODE J1 D12 P16 A19 R16 A23

A15 XINT1 C15 XINT4 J2 VCC P17 A17 R17 A22

A16 RESET C16 XINT6 J3 VSS Q1 D21 S1 D25

A17 XINT2 C17 XINT7 J15 VSS Q2 D23 S2 D29

B1 BOFF D1 D5 J16 VCC Q3 D26 S3 READY

B2 STEST D2 D2 J17 A10 Q4 D28 S4 HOLDA

B3 NC D3 NC K1 D13 Q5 D30 S5 BE3

B4 NC D15 NMI K2 VCC Q6 VCC S6 BE2

B5 DREQ0 D16 A2 K3 VSS Q7 VSS S7 BE1

B6 DREQ2 D17 A3 K15 VSS Q8 VSS S8 BLAST

B7 VCC E1 D7 K16 VCC Q9 VSS S9 DEN

B8 DACK0 E2 D4 K17 A11 Q10 VSS S10 W/R

B9 VCC E3 D0 L1 D15 Q11 VSS S11 DT/R

B10 VCCPLL E15 VCC L2 D14 Q12 SUP S12 WAIT

B11 VCC E16 A4 L3 VSS Q13 A30 S13 D/C

B12 VCC E17 A5 L15 VSS Q14 A28 S14 LOCK

B13 PCLK2 F1 D8 L16 A13 Q15 A24 S15 A31

B14 PCLK1 F2 D6 L17 A12 Q16 A21 S16 A27

B15 XINT0 F3 VCC M1 D16 Q17 A18 S17 A25

B16 XINT3 F15 VSS M2 VCC R1 D24

B17 XINT5 F16 VCC M3 VSS R2 D27

80960-40, -33, -25

20 Datasheet

3.3.2 80960CF PQFP Pinout (80960CF-33 and -25 Only)

Table 8 and Table 9 present the 80960CF pin names with package location. Figure 4 shows the

80960CF P Q FP pinout as viewed from the top side. See Section 4.0 , “Electrical Specifications” on

page 26 for specifications and recommended connections.

Table 8. 80960CF PQFP Pinout—In Signal Order (80960CF-33 and -25 Only)

Address Bus Data Bus Bus Control Processor Control I/O

Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin

A31 153 D31 186 BE3 176 RESET 91 DREQ3 60

A30 152 D30 187 BE2 175 FAIL 45 DREQ2 59

A29 151 D29 188 BE1 172 STEST 46 DREQ1 58

A28 145 D28 189 BE0 170 ONCE 43 DREQ0 57

A27 144 D27 191 CLKIN 87

A26 143 D26 192 W/R 164 CLKMOD

E85 DACK3 65

A25 142 D25 194 PCLK2 74 DACK2 64

A24 141 D24 195 ADS 178 PCLK1 78 DACK1 63

A23 139 D23 3VSS DACK0 62

A22 138 D22 4READY 182 Location

A21 137 D21 5BTERM 184 2, 7, 16, 24, 30, 38,

39, 49, 56, 70, 75,

77, 81, 83, 88, 89,

92, 98, 105, 109,

110, 121, 125, 131,

135, 147, 150, 161,

165, 173, 174, 185,

196

EOP/TC3 69

A20 136 D20 6EOP/TC2 68

A19 134 D19 8WAIT 162 EOP/TC1 67

A18 133 D18 9BLAST 169 EOP/TC0 66

A17 132 D17 10

A16 130 D16 11 DT/R 163 XINT7 107

A15 129 D15 13 DEN 167 VCC XINT6 106

A14 128 D14 14 Location XINT5 102

A13 124 D13 15 LOCK 156 1, 12, 20, 28, 32, 37,

44, 50, 61, 71, 79,

82, 96, 99, 103, 115,

127, 140, 148, 154,

168, 171, 180, 190

XINT4 101

A12 123 D12 17 XINT3 100

A11 122 D11 18 HOLD 181 XINT2 95

A10 120 D10 19 HOLDA 179 XINT1 94

A9 119 D9 21 BREQ 155 XINT0 93

A8 118 D8 22 VCCPLL 72

A7 117 D7 23 D/C 159 No Connect NMI 108

A6 116 D6 25 DMA 160 Location

A5 114 D5 26 SUP 158 29, 31, 41, 42, 47,

48, 51, 52, 53, 54,

55, 73, 76, 80, 84,

86, 90, 97, 104, 126,

146, 149, 157, 166,

177, 183, 193

A4 113 D4 27

A3 112 D3 33 BOFF 40

A2 111 D2 34

D1 35

D0 36

80960-40, -33, -25

Datasheet 21

Table 9. 80960CF PQFP Pinout—In Pin Order (80960CF-33 and -25 Only)

Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal

1VCC 34 D2 67 EOP/TC1 100 XINT3 133 A18 166 NC

2VSS 35 D1 68 EOP/TC2 101 XINT4 134 A19 167 DEN

3D23 36 D0 69 EOP/TC3 102 XINT5 135 VSS 168 VCC

4D22 37 VCC 70 VSS 103 VCC 136 A20 169 BLAST

5D21 38 VSS 71 VCC 104 NC 137 A21 170 BE0

6D20 39 VSS 72 VCCPLL 105 VSS 138 A22 171 VCC

7VSS 40 BOFF 73 NC 106 XINT6 139 A23 172 BE1

8D19 41 NC 74 PCLK2 107 XINT7 140 VCC 173 VSS

9D18 42 NC 75 VSS 108 NMI 141 A24 174 VSS

10 D17 43 ONCE 76 NC 109 VSS 142 A25 175 BE2

11 D16 44 VCC 77 VSS 110 VSS 143 A26 176 BE3

12 VCC 45 FAIL 78 PCLK1 111 A2 144 A27 177 NC

13 D15 46 STEST 79 VCC 112 A3 145 A28 178 ADS

14 D14 47 NC 80 NC 113 A4 146 NC 179 HOLDA

15 D13 48 NC 81 VSS 114 A5 147 VSS 180 VCC

16 VSS 49 VSS 82 VCC 115 VCC 148 VCC 181 HOLD

17 D12 50 VCC 83 VSS 116 A6 149 NC 182 READY

18 D11 51 NC 84 NC 117 A7 150 VSS 183 NC

19 D10 52 NC 85 CLKMODE 118 A8 151 A29 184 BTERM

20 VCC 53 NC 86 NC 119 A9 152 A30 185 VSS

21 D9 54 NC 87 CLKIN 120 A10 153 A31 186 D31

22 D8 55 NC 88 VSS 121 VSS 154 VCC 187 D30

23 D7 56 VSS 89 VSS 122 A11 155 BREQ 188 D29

24 VSS 57 DREQ0 90 NC 123 A12 156 LOCK 189 D28

25 D6 58 DREQ1 91 RESET 124 A13 157 NC 190 VCC

26 D5 59 DREQ2 92 VSS 125 VSS 158 SUP 191 D27

27 D4 60 DREQ3 93 XINT0 126 NC 159 D/C192 D26

28 VCC 61 VCC 94 XINT1 127 VCC 160 DMA 193 NC

29 NC 62 DACK0 95 XINT2 128 A14 161 VSS 194 D25

30 VSS 63 DACK1 96 VCC 129 A15 162 WAIT 195 D24

31 NC 64 DACK2 97 NC 130 A16 163 DT/R196 VSS

32 VCC 65 DACK3 98 VSS 131 VSS 164 W/R

33 D3 66 EOP/TC0 99 VCC 132 A17 165 VSS

80960-40, -33, -25

22 Datasheet

3.4 Package Thermal Specifications

The 80960CF is specified for operation when case temperature (TC) is within the range of

0 °C–100 °C for 33 and 25 MHz, and 0 °C–85 °C for 40 MHz. TC may be measured in any

environment to determine whether the 80960CF is within specified operating range. Case

temperature should be measured at the center of the top surface, opposite the pins.

Refer to Figure 5 for more information.

Ambient temperature (TA) is calculated from thermal resistance from case to ambient (θCA) using

Equation 1:

Equation 1. Calculation of Ambient Temperature (TA)

Table 10 shows the maximum TA allowable (without exceeding TC) at various airflows and

operating frequencies (fPCLK).

Note that TA is greatly improved by attaching fins or a heatsink to the package. Maximum power

consumption (P) is calculated by using the typical ICC as tabulated in Section 4.4, “D.C.

Specifications” on page 27 and VCC of 5 V.

Figure 4. 80960CF PQFP Pinout—Top View (80960CF-33 and -25 Only)

5098

147

148 196

Pin 1

F_CA004A

TATCPθCA

⋅()–=

80960-40, -33, -25

Datasheet 23

Figure 5. Measuring 80960CF PGA and PQFP Case Temperature

Table 10. Maximum TA at Various Airflows in oC (PGA Package Only)

Airflow-ft/min (m/sec)

fPCLK

(MHz) 0

(0) 200

(1.01) 400

(2.03) 600

(3.04) 800

(4.06) 1000

(5.07)

TA with Heat sink (†)

TA without Heatsink (†)

†0.285” high unidirectional heat sink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).

Measure PQFP case temperature

at center of top surfac e.

Measure PGA temperature at

center of top surface

168 - Pin PGA Pin 196 Pin 1

center of top surface

80960-40, -33, -25

24 Datasheet

3.5 Stepping Register Information

Upon reset, register g0 contains die stepping information (see Figure 6). The most significant byte

contains ASCII 0; the upper middle byte contains an ASCII C; the lower middle byte contains an

ASCII F. The least significant byte contains the stepping number in ASCII, and g0 retains this

information until it is overwritten by the user program. Table 13 contains a cross reference of the

number in the least significant byte of register g0 to the die stepping number.

Table 11. 80960CF PGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

Parameter

Airflow — ft./min (m/sec)

(0) 200

(1.01) 400

(2.03) 600

(3.07) 800

(4.06) 1000

(5.07)

θ Junction-to-Case

(Case measured as

shown in Figure 5.) 1.5 1.5 1.5 1.5 1.5 1.5

θ Case-to-Ambient

(No Heatsink) 17 14 11 9 7.1 6.6

θ Case-to-Ambient

(With Heatsink)

(See Note 3.) 13 9 5.5 5 3.9 3.4

NOTES:

1. This table applies to 80960CF PGA plugged into socket or soldered directly to board.

2. θJA = θJC + θCA

3. 0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).

Table 12. 80960CF PQFP Package Thermal Characteristics

Thermal Resistance — °C/Watt

Parameter

Airflow — ft./min (m/sec)

(0) 50

(0.25) 100

(0.50) 200

(1.01) 400

(2.03) 600

(3.04) 800

(4.06)

θ Junction-to-Case (Case Measured

as shown in Figure 5.) 5555555

θ Case-to-Ambient (No Heatsink) 19 18 17 15 12 10 9

NOTES:

1. This table applies to 80960CF PQFP soldered directly to board.

2. θJA = θJC + θCA

θJC

θJA

80960-40, -33, -25

Datasheet 25

3.6 Sources for Accessories

The following is a list of suggested sources for 80960CF accessories. This is neither an

endorsement nor a warranty of the performance of any of the listed products and/or companies.

Sockets

1. 3M Textool Test and Interconnection Products

6801 River Place Blvd. Mail Stop 130-3N-29

Austin, TX 78726-9000

(800) 328-04 11

2. Augat, Inc. Int erco nnection Product s Grou p

452 John Dietsch Blvd.

Attleboro Falls, MA 02763

(508) 699-76 46

3. Concept Mfg., Inc. (Decoupling Sockets)

400 Walnut St. Suite 609

Redwood City, CA 94063

(415) 365-1162 FAX: (415)265-1164

Heatsinks/Fins

1. Thermalloy, Inc.

2021 West Valley View Lane

Dallas, TX 75234

(214) 243-43 21

FAX: (214) 241-4656

2. Wakefield Engineer ing

60 Audubon Road

Wakefield, MA 01880

(617) 245-59 00

Figure 6. Register g0

Table 13. Die Stepping Cross Reference

g0 Least Significant Byte Di e Stepping

01 A

02 B

03 C

04 D

05 E

ASCII 00 43 46 Stepping Number

DECIMAL 0 C FStepping Number

MSB LSB

80960-40, -33, -25

26 Datasheet

4.0 Electrical Specifications

4.1 Absolute Maximum Ratings

Table 14 presents the absolute maximum ratings for the 80960CF.

Note: The specifications are subject to chan ge without notice. Verify with yo ur local Intel sales of fice that

you have the late st data sheet befor e finalizing a design.

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended

and extended exposure beyond the “Operating Conditions” may affect device reliability.

4.2 Oper ating Cond itions

Table 15 presents the operating conditions for the 80960CF.

Table 14. Absolute Maximum Ratings

Pa rameter Max imu m Rati ng

Storage Temperature –65 °C to +150 °C

Case Temperature Under Bias –65 °C to +110 °C

Supply Voltage wrt. VSS –0.5 V to + 6.5 V

Voltage on Other Pins wrt. VSS –0.5 V to VCC + 0.5 V

Table 15. Operating Conditions

Symbol Parameter Min Max Units Notes

VCC

Supply Voltage

80960CF-40

80960CF-33

80960CF-25

4.75

4.50

5.25

5.50

fCLK2x

Input Clock Frequency (2-x Mode)

80960CF-40

80960CF-33

80960CF-25

MHz

fCLK1x

Input Clock Frequency (1-x Mode)

80960CF-40

80960CF-33

80960CF-25

MHz (†)

Case Temp Under Bias

PGA Pkg. (80960CF-40)

PGA Pkg. (80960CF-33, -25 Only)

196-Pin PQFP (80960CF-33, -25 Only)

100

†When in the 1-x input clock mode, CLKIN is an input t o an internal phase-locked loop and must maintain a

minimum frequency of 8 M Hz for proper processor operation. However, in the 1-x mode, CLKIN may still

be stopped when the processor is in a reset condition. When CLKIN is stopped, the specified RESET low

time must be provided once CLKIN restarts and has stabilized.

80960-40, -33, -25

Datasheet 27

4.3 Recommended Connections

Power and ground connections must be made to multiple VCC and VSS (GND) pins. Every

80960CF-based circuit board should include power (VCC) and ground (VSS) planes for power

distribution. Every VCC pin must be connected to the power plane, and every VSS pin must be

connected to the ground plane. Pins identified as ‘NC’ must not be connected in the system.

Liberal decoupling capacitance should be placed near the 80960CF. The processor may cause

transient power su rges whe n its numerous o utput buf fers transition, p articularly when conn ected to

large capacitive loads.

Low inductance capacitors and interconnects are recommended for best high frequency electrical

performance. Ind uctance may be reduced by shortening the board traces between the processor and

decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages

may offer the lowest possible inductance.

For reliable operation, always connect unused inputs to an appropriate signal level. In particular,

any unused interrupt (XINT, NMI), DMA (DREQ), or BTERM input should be connected to VCC

through a pu ll-up r esistor. Pull-up resistors should be in the in the ra nge of 20 KW fo r each pin tied

high. Wh en READY or HOLD ar e not used, the unused inpu t should be conn ected to gro und. N.C.

pins must always remain unconnected. For additional information refer to the i960® CA/CF

Microprocessor User’s Manual (order number 270710).

4.4 D.C. Specifications

Table 16 presents the D.C. specifications of the 80960CF.

80960-40, -33, -25 
28  Datasheet
Table 16.  D.C. Specifications
Symbol Parameter (1) Min Max Units Notes
VIL Input Low Voltage for all pins except RESET – 0.3 +0.8 V
VIH Input High Voltage for all pins except RESET 2.0 VCC + 0.3 V
VOL Output Low V oltage 0.45 V IOL = 5 mA
VOH Output High V oltage IOH = –1 mA
IOH = – 200 µA2.4
VCC – 0.5 V
V
VILR Input Low Voltage for RESET – 0.3 1.5 V
VIHR Input High Voltage for RESET 3.5 VCC + 0.3 V
ILI1
Input Leakage Current for each pin except:
BTERM, ONCE, DREQ3:0, STES T,
EOP3:0/TC3:0, NMI, XINT7:0, BOFF, READY,
HOLD, CLKMODE ±15 µA 0 ≤ VIN ≤ VCC (2)
ILI2 Input Leakage Current for:
BTERM, ONCE, DREQ3:0, STES T,
EOP3:0/TC3:0, NMI, XINT7:0, BOFF 0– 300 µ A VIN = 0.45 V (3)
ILI3 Input Leakage Current for:
READY, HOLD, CLKMODE 0 500 µA VIN = 2.4 V (4, 8)
ILO Output Leakage Current ±15 µA 0. 45 ≤ VOUT ≤ 
VCC
ICC Supply Current (80960CF-40, 33):
ICC Max
ICCTyp 1150
1000 mA
mA (5)
(6)
ICC Supply Current (80960CF-25):
ICC Max
ICCTyp 950
775 mA
mA (5)
(6)
ICC Supply Current (80960CF-16):
ICC Max
ICCTyp 750
575 mA (5)
(6)
IONCE
ONCE-mode Supply Curren t
80960CF-40
80960CF-33, -25, -16 225
150 mA
CIN Input Capacitance for: CLKIN, RESET, ONCE, 
READY, HOL D , D R EQ3:0 , BOFF, XINT7:0 , 
NMI, BTE R M, CLKMODE 012pFF
C = 1 MHz 
COUT Output Capacitance of each output pin 12 pF FC = 1 MHz (7)
CI/O I/O Pin Capacitance 12 pF FC = 1 MHz 
NOTES:
1. 80960CF-33 and -25 under the conditions described in Section 4.2, “Operating Conditions” on page 26.
2. No pullup or pulldown.
3. These pins have internal pullup resistors.
4. These pins have internal pulldown resistors.
5. Measured at worst case frequency, VCC and temperature, with device operating and output s loaded to the 
test conditions described in Section 4.5.1, “A.C. Test Conditions” on page 35.
6. ICC Typical is not tested.
7. Output Capacitance is the capacit ive load of a floating output.
8. CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted.

 80960-40, -33, -25
 Datasheet 29
4.5 A.C. Specifications
Table 17. 80960CF AC Characteristics (40 MHz)  (Sheet 1 of 2)
Symbol Parameter (1) Min Max Units Notes
Input Clock (2, 10)
TFCLKIN Frequency 0 80  MHz
TCCLKIN Period In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)25
12.5 125
∞ns
ns (12)
TCS CLKIN Period Stability In 1-x Mode (fCLK1x) ±0.1% ∆(13)
TCH CLKIN High Time In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)5
562.5
∞ns
ns (12)
TCL CLKIN Low Time In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)5
562.5
∞ns
ns (12)
TCR CLKIN Rise Time 0 6 ns
TCF CLKIN Fall Time 0 6 ns
Output Clocks (2, 9)
TCP CLKIN to PCLK2:1 Delay In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)– 2
22
25 ns
ns (4, 13)
(4)
TPCLK2:1 Period In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)TC
2TCns
ns (13)
(4)
TPH PCLK2:1 High Time (T/2) – 2 T/2 ns (13)
TPL PCLK2:1 Low Time (T/2) – 2 T/2 ns (13)
TPR PCLK2:1 Rise Time 1 4 ns (4)
TPF PCLK2:1 Fall Time 1 4 ns (4)
Synchronous Outputs (9)
TOH
TOV
Output Valid Delay, Output Hold
TOH1, TOV1 A31:2
TOH2, TOV2 BE3:0
TOH3, TOV3 ADS
TOH4, TOV4 W/R
TOH5, TOV5 D/C, SUP, DMA
TOH6, TOV6 BLAST, WAIT
TOH7, TOV7 DEN
TOH8, TOV8 HOLDA, BREQ
TOH9, TOV9 LOCK
TOH10, TOV10 DACK3:0
TOH11, TOV11 D31:0
TOH12, TOV12 DT/R
TOH13, TOV13 FAIL
TOH14, TOV14 EOP3:0/TC3:0
3
3
6
3
4
5
3
4
4
4
3
T/2 + 3
2
3
14
16
16
16
16
16
16
16
16
16
16
T/2 + 14
14
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(7, 11)
(7, 11)
TOF Output Float for all outputs 3 22 ns (7)
Synchr onous Inputs (2, 10, 11)
TIS
Input Setup
TIS1 D31:0
TIS2 BOFF
TIS3 BTERM/READY
TIS4 HOLD
3
15
7
5
ns
ns
ns
ns

80960-40, -33, -25 
30  Datasheet
TIH
Input Hold
TIH1 D31:0
TIH2 BOFF
TIH3 BTERM/READY
TIH4 HOLD
5
5
2
3
ns
ns
ns
ns
Relative Output Timings (2, 3, 4, 9)
TAVSH1 A31:2 Valid to ADS Rising T – 4T + 4ns
TAVSH2 BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS 
Rising T – 6T + 6ns
TAVEL1 A31:2 Valid to DEN Falling T – 4T + 4ns
TAVEL2 BE3:0, W/R, SUP, INST,DMA, DACK3:0 Valid to DEN 
Falling T – 6T + 6ns
TNLQV WAIT Falling to Output Data Valid ± 6 ns
TDVNH Output Data Valid to WA IT Rising N*T – 6N*T + 6ns (5)
TNLNH WAIT Falling to WAIT Rising N*T ± 4 ns (5)
TNHQX Output Data Hold after WAIT Rising (N+1)*T–8 (N+1)*T+6 ns (6)
TEHTV DT/R Hold after DEN High T/2 – 7ns(7)
TTVEL DT/R Vali d  to  DE N Falling T/2 – 4ns
Relative Input Timings (2, 3, 4)
TIS5 RESET Input Setup (2-x Clock Mode) 6 ns (14)
TIH5 RESET Input Hold (2-x Clock Mode) 5 ns (14)
TIS6 DREQ3:0 Input Setup 12 ns (8)
TIH6 DREQ3:0 Input Hold 7 ns (8)
TIS7 XINT7:0, NMI Input Setup 7 ns (16)
TIH7 XINT7:0, NMI Input Hold 3 ns (16)
TIS8 RESET Input Setup (1-x Clock Mode) 3 ns (15)
TIH8 RESET Input Hold (1-x Clock Mode) T/4 + 1 ns (15)
NOTES:
1. 80960CF-40 only, per the conditions in Section 4.2, Operating Conditions and Section 4.5.1, A.C. Test 
Conditions.
2. See Table 19 for all notes related to AC specifications.
Table 17.  80960CF AC Characteristics (40 MHz)  (Sheet 2 of 2)
Symbol Parameter (1) Min Max Unit s Notes

 80960-40, -33, -25
 Datasheet 31
Table 18. 80960CF AC Characteristics (33 MHz)  (Sheet 1 of 2)
Symbol Parameter (1) Min Max Units Notes
Input Clock (2, 10)
TFCLKIN Frequency 0 66.66 MHz
TCCLKIN Period In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)30
15 125
∞ns
ns (12)
TCS CLKIN Period Stability In 1-x Mode (fCLK1x)±0.1% ∆(13)
TCH CLKIN High Time In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)5
562.5
∞ns
ns (12)
TCL CLKIN Low Time In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)5
562.5
∞ns
ns (12)
TCR CLKIN Rise Time 0 6ns
TCF CLKIN Fall Time 0 6ns
Output Clocks (2, 9)
TCP CLKIN to PCLK2:1 Delay In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)– 2
22
25 ns
ns (4,13)
(4)
TPCLK2:1 Period In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)TC
2TC ns
ns (13)
(4)
TPH PCLK2:1 High Time (T/2) – 2T/2ns(13)
TPL PCLK2:1 Low Time (T/2) – 2T/2ns(13)
TPR PCLK2:1 Rise Time 1 4 ns (4)
TPF PCLK2:1 Fall Time 14ns(4)
Synchronous Outputs (9)
TOH
TOV
Output Valid Delay, Output Hold
TOH1, TOV1 A31:2
TOH2, TOV2 BE3:0
TOH3, TOV3 ADS
TOH4, TOV4 W/R
TOH5, TOV5 D/C, SUP, DMA
TOH6, TOV6 BLAST, WAIT
TOH7, TOV7 DEN
TOH8, TOV8 HOLDA, BREQ
TOH9, TOV9 LOCK
TOH10, TOV10 DACK3:0
TOH11, TOV11 D31:0
TOH12, TOV12 DT/R
TOH13, TOV13 FAIL
TOH14, TOV14 EOP3:0/TC3:0
3
3
6
3
4
5
3
4
4
4
3
T/2 + 3
2
3
14
16
18
18
16
16
16
16
16
18
16
T/ 2 + 14
14
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(7, 11)
(7, 11)
TOF Output Float for all outputs 3 22 ns (7)
Synchronous Inputs (2, 10 , 11)
TIS
Input Setup
TIS1 D31:0
TIS2 BOFF
TIS3 BTERM/READY
TIS4 HOLD
3
17
7
7
ns
ns
ns
ns
TIH
Input Hold
TIH1 D31:0
TIH2 BOFF
TIH3 BTERM/READY
TIH4 HOLD
5
5
2
3
ns
ns
ns
ns

80960-40, -33, -25 
32  Datasheet
Relative Output T imings (2, 3, 4, 9)
TAVSH1 A31:2 Valid to ADS Rising T – 4T + 4ns
TAVSH2 BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS 
Rising T – 6T + 6ns
TAVEL1 A31:2 Valid to DEN Falling T – 4T + 4ns
TAVEL2 BE3:0, W/R, SUP, INST,DMA, DACK3:0 V alid to DEN 
Falling T – 6T + 6ns
TNLQV WAIT Falling to Output Data Valid ± 6 ns
TDVNH Output Data Valid to WAIT Rising N*T – 6N*T + 6ns (5)
TNLNH WAIT Fallin g  to  WAIT Rising N*T ± 4 ns (5)
TNHQX Output Data Hold after WAIT Rising (N+1)*T–8 (N+1)*T+6 ns (6)
TEHTV DT/R Hold  a fte r  D E N High T/2 – 7 ∞ns (7)
TTVEL DT/R Valid to DEN Falling T/2 – 4ns
Relati ve  Input Timings (2, 3, 4)
TIS5 RESET Input Setup (2-x Clock Mode) 6 ns (14)
TIH5 RESET Input Hold (2-x Clock Mode) 5 ns (14)
TIS6 DREQ3:0 Input  Setup 12 ns (8)
TIH6 DREQ3:0 Input Hold 7 ns (8)
TIS7 XINT7:0, NMI Input Setup 7 ns (16)
TIH7 XINT7:0, NMI Input Hold 3 ns (16)
TIS8 RESET Input Setup (1-x Clock Mode) 3 ns (15)
TIH8 RESET Input Hold (1-x Clock Mode) T/4 + 1 ns (15)
NOTES:
1. 80960CF-33 only, per the conditions in Section 4.2, Operating Conditions and Section 4.5.1, A.C. Test 
Conditions.
2. See Table 19 for all notes related to AC specifications.
Table 18.  80960CF AC Characteristics (33 MHz)  (Sheet 2 of 2)
Symbol Parameter (1) Min Max Units Notes

 80960-40, -33, -25
 Datasheet 33
Table 19. 80960CF AC Characteristics (25 MHz)  (Sheet 1 of 3)
Symbol Parameter (1) Min Max Unit Notes
Input Clock  (2, 10 )
TFCLKIN Frequency 0 50 MHz
TCCLKIN Period In 1-x Mode (f CLK1x)
In 2-x Mode (f CLK2x)40
20 125
∞ns
ns (12)
TCS CLKIN Period Stability In 1-x Mode (f CLK1x) ±0.1% ∆(13)
TCH CLKIN High Time In 1-x Mode (f CLK1x)
In 2-x Mode (f CLK2x)8
862.5
∞ns
ns (12)
TCL CLKIN Low Time In 1-x Mode (f CLK1x)
In 2-x Mode (f CLK2x)8
862.5
∞ns
ns (12)
TCR CLKIN Rise Time 0 6 ns
TCF CLKIN Fall Time 0 6 ns
Output Clocks (2, 9)
TCP CLKIN to PCLK2:1 Delay In 1-x Mode (f CLK1x)
In 2-x Mode (f CLK2x)– 2
22
25 ns
ns (4, 13)
(4)
TPCLK2:1 Period In 1-x Mode (f CLK1x)
In 2-x Mode (f CLK2x)TC
2TCns
ns (13)
(4)
TPH PCLK2:1 High Time (T/2) – 3T/2 ns(13)
TPL PCLK2:1 Low Time (T/2) – 3T/2 ns(13)
TPR PCLK2:1 Rise Time 1 4 ns (4)
TPF PCLK2:1 Fall Time 1 4 ns (4)
Synchronous Outputs (9)
TOH
TOV
Output Valid Delay, Output Hold
TOH1, TOV1 A31:2
TOH2, TOV2 BE3:0
TOH3, TOV3 ADS
TOH4, TOV4 W/R
TOH5, TOV5 D/C, SUP, DMA
TOH6, TOV6 BLAST, WAIT
TOH7, TOV7 DEN
TOH8, TOV8 HOLDA, BREQ
TOH9, TOV9 LOCK
TOH10, TOV10 DACK3:0
TOH11, TOV11 D31:0
TOH12, TOV12 DT/R
TOH13, TOV13 FAIL
TOH14, TOV14 EOP3:0/TC3:0
3
3
6
3
4
5
3
4
4
4
3
T/2 + 3
2
3
16
18
20
20
18
18
18
18
18
20
18
T/2 + 16
16
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(7, 11)
(7, 11)
TOF Output Float for all outputs 3 22 ns (7)
Synchr onous Inputs (2, 10, 11)
TIS Input Setup
TIS1 D31:0
TIS2 BOFF
TIS3 BTERM/READY
TIS4 HOLD
5
19
9
9
ns
ns
ns
ns
TIH Input Hold
TIH1 D31:0
TIH2 BOFF
TIH3 BTERM/READY
TIH4 HOLD
5
19
9
9
ns
ns
ns
ns

80960-40, -33, -25 
34  Datasheet
Relative Output Timings (2, 3, 4, 9)
TAVSH1 A31:2 Valid to ADS Rising T – 4T + 4ns
TAVSH2 BE3:0, W/R, SUP, D/C, 
DMA, DACK3:0 Valid to ADS Rising T – 6T + 6ns
TAVEL1 A31: 2 Valid to DEN Falling T – 4T + 4ns
TAVEL2 BE3:0, W/R, SUP, INST,
DMA, DACK3:0 Valid to DEN Falling T – 6T + 6ns
TNLQV WAIT Falling to Output Data Valid ± 6 ns
TDVNH Output Data Valid to WAIT Rising N*T – FN*T + 6ns (5)
TNLNH WAIT Falling to WAIT Rising N*T ±  4 ns (5)
TNHQX Output Data Hold after W AIT Rising (N+1)*T–
8(N+1)*T+6 ns (6)
TEHTV DT/R Ho ld after DEN High T/2 – 7 ∞ns (7)
TTVEL DT/R Valid to DEN Falling T/2 – 4ns
Relative Input Timings (2, 3, 4)
TIS5 RESET Input Setup (2-x Clock Mode) 8 ns (14)
TIH5 RESET Input Hold (2-x Clock Mode) 7 ns (14)
TIS6 DREQ3:0 Input Setup 14 ns (8)
TIH6 DREQ3:0 Input Hold 9 ns (8)
TIS7 XINT7:0, NMI Input Setup 9 ns (16)
TIH7 XINT7:0, NM I Input Hold 5 ns (16)
TIS8 RESET Input Setup (1-x Clock Mode) 3 ns (15)
TIH8 RESET Input Hold (1-x Clock Mode) T/4 + 1 ns (15)
Table 19.  80960CF AC Characteristics (25 MHz)  (Sheet 2 of 3)
Symbol Parameter (1) Min Max Unit Notes

 80960-40, -33, -25
 Datasheet 35
4.5.1 A.C. Test Conditions
The AC Specifications in Section 4.5,  “A.C. Specifications” on pa ge 29 are tested with the 50 pF 
load shown in  Figure 7. Figure 16 shows how timin gs vary wit h load  capacitance.
Specifications are measured at the 1.5 V crossing point, unless otherwise indicated. Input 
waveforms are assumed to have a rise and fall time of < 2 ns from 0.8 V to 2.0 V. See Section 4.5.2, 
“A.C. Timing Waveforms” on page 36 for AC specification definitions, test points and 
illustrations.
NOTES:
1. 80960CF-25 only, per the conditions in Section 4.2, Operating Conditions and Sec tion 4.5.1, A.C. Test 
Conditions.
2. See Section 4.5.2, A.C. Timing Waveforms for waveforms and definitions.
3. See Figure 16 for capacitive derating information for output delays and hold times.
4. See Figure 17 for capacitive derating information for rise and fall times.
5. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus 
Controller Region Table. WAIT never goes active when there are no wait states in an access.
6. N = Number of wait states inserted with READY.
7. Output Data and/or DT/R may be driven indefinitely following a cycle when there is no subsequent bus 
activity.
8. Since asynchronous inputs are synchronized internally by the 80960CF, they have no required setup or 
hold times to be recognized and for proper operation. However, to ensure recognition of the input at a 
particular edge of PCLK2:1, the setup times shown must be met. Asynchronous inputs must be active for 
at least two consecutive PCLK2:1 rising edges to be seen by the processor.
9. These specifications are ensured by the processor.
10.Thes e specifications must  be met by the system for proper operation of the processor.
11.This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating 
Curves to adjust the timing for PCLK2:1 loading.
12.In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is 
operating. When the processor is in reset, the input clock may stop even in 1-x mode.
13.When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation 
of less than ± 0.1% between adjacent cycles.
14.In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper 
operation. However, to ensure the device exits reset synchronized to a particular clock edge, the RESET 
pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 23.)
15.In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper 
operation. However, to ensure the device exits reset synchronized to a particular clock edge, the RESET 
pin must meet setup and hold times to the rising edge of the CLKIN. (See Figure 24.)
16.The interrupt pins are synchronized internally by the 80960CF. They have no required setup or hold times 
for proper operation. These pins are sampled by the interrupt controller every other clock and must be 
active for at least three consecutive PCLK2:1 rising edges when asserting them asynchronously. To ensure 
recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive 
PCLK2:1 rising edges.
Table 19. 80960CF AC Characteristics (25 MHz)  (Sheet 3 of 3)
Symbol Parameter (1) Min Max Unit Notes
Figure 7.  A.C. Test Load
Output Pin
CL = 50 pF for all signals
CL
F_CX008A

80960-40, -33, -25

36 Datasheet

4.5.2 A.C. Timing Waveforms

Figure 8. Input and Output Clocks Waveform

Figure 9. CLKIN Waveform

PCLK2:1 2.4 V

1.5 V

1.5 V 1.5 V

0.45 V

F_CX009A

CLKIN

2.0 V

1.5 V

0.8 V

TCF

TCH TCL

TCR

F_CX010A

80960-40, -33, -25

Datasheet 37

Figure 10. Output Delay and Float Waveform

NOTES:

1. TOV TOH - OUTPUT DELAY - Maximum output delay is referred to as Output Valid Delay (TOV); minimum

output delay is referred to as Output Hold (TOH).

2. TOF - OUTPUT FLOAT DELAY - Output float condition occurs when the maximum output current becomes

less that ILO in magnitude.

Figure 11. Input Setup and Hold Waveform

NOTE: TIS TIH - INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling

window during which synchronous inputs must be stable for correct processor operation.

PCLK2:1

Outputs

1.5 V

TOV

Min Max

TOH

Min Max

TOF

1.5 V 1. 5 V

1.5 V

Outputs

F_CX011A

PCLK2:1

Inputs:

1.5 V1.5 V1.5 V

Valid

TIS TIH

(READY, HOLD, BTERM,

BOFF, DREQ3:0,

D31:0 on reads)

F_CX012A

Min Max

80960-40, -33, -25

38 Datasheet

Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform

Figure 13. Hold Acknowledge Timings

NOTES:

1. TOV TOH - OUTPUT DELAY - Maxim um outpu t delay is referred to as Output Valid Delay (TOV); min imum

output delay is referred to as Output Hold (TOH).

2. TOF - OUTPUT FLOAT DEL AY - Output float condition occurs when the maximum output current becomes

less that ILO in magnitude.

3. TIS TIH - INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window

during which synchronous inputs must be stable for correct proces sor operation.

PCLK2:1 1.5 V1.5 V1.5 V

Valid

TIS TIH

NMI, XINT7:0

Min Min

F_CX013A

1.5 V

PCLK2:1 1.5 V

1.5 V 1.5 V

Outputs:

A31:2, D31:0, BE3:0,

ADS, BLAST, WAIT, W/R,

DT/R, DEN, LOCK,

D/C, SUP, DMA

Min Max Min Max

Valid 1.5 V Valid

TOF TOV

HOLD

TIS

TIH

1.5 V 1.5 V

TIH TIS

HOLDA

TOV

Min

Min Min

Min

MaxMin MaxMin

F_CX014A

1.5 V 1.5 V 1.5 V

1.5 V

TOV

80960-40, -33, -25

Datasheet 39

Figure 14. Bus Backoff (BOFF) Timings

Figure 15. Relative Timings Waveforms

PCLK2:1 1.5 V

1.5 V 1.5 V

Outputs:

A31:2, D31:0, BE3:0,

ADS, BLAST, WAIT, W/R,

DT/R, DEN, LOCK,

D/C, SUP, DMA

Min

Max

Min

Max

Valid 1.5 V Valid

TOF TOV

BOFF

TIS

TIH

1.5 V 1.5 V 1.5 V

TIH

TIS

F_CX015A

1.5 V

PCLK2:1 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V

TAVSH

TDVNH TNHQX

TNLNH

TAVEL

TVEL

TEHTV

TNLQV

ADS

A31:2, BE3:0,

W/R, LOCK,

SUP, D/C, DMA

D31:0

WAIT

DT/R

DEN

D31:0 F_CX016A

1.5 V

In VIH

VIL

Out

80960-40, -33, -25

40 Datasheet

4.5.3 Derating Curves

Figure 16. Output Delay or Hold vs. Load Capacitance

Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC

Figure 18. ICC vs. Frequency and Temperature—80960CF-33 and -25

50 100 150

CL (pF)

nom + 10

nom + 5

nom

All outputs except: LOCK,

EOP3:0/TC3:0, FAIL

F_CX017A

DMA, SUP, BREQ, DACK3:0,

Note: PCLK Load = 50pF

Output Valid Delays (ns) @ 1.5 V

LOCK, DMA, SUP, BREQ,

DACK3:0, EOP3:0/TC3:0, FAIL

50 100 150

Time (ns)

(pF)

50 100 150

Time (ns)

(pF)

a) All outputs except: LOCK, DMA, SUP, HOLDA, BREQ

DACK3:0, E O P 3 : 0/

TC3:0

, FAIL b) LOCK, DMA, SUP, HOLDA, BREQ, DACK3 :0 ,

EOP3:0/TC3:0, F AIL

0.8 V to 2.0 V

F_CX019A

900

0033

TC = 100° C

TC = 0° C

fPCLK (MHz)

(mA)

ICC - ICC under test conditions F_CX020A

80960-40, -33, -25

Datasheet 41

5.0 Reset, Back off and Hold Acknowledge

Table 20 lists th e condition of each processor output pin while RESET is asserted (low). Table 21

lists the condition of each process or o utput pin while HOLDA is asserted (high).

In Table 21, with regard to bus output pin s tate only, the Hold Acknowledge state takes precedence

over the reset state. Although asserting the RESET pin internally resets the processor, the

processor’s bus output pins do not enter the reset state when Hold Acknowledge has been granted

to a previous HOLD request (HOLDA is active). Furthermore, the processor grants new HOLD

requests and enters the Hold Acknowledge state even while in reset.

For example, when HOLD is asserted while HOLDA is inactive and the processor is in the reset

state, the processor’s bus pins enter the Hold Acknowledge state and HOLDA is granted. The

processor is not able to perform memory accesses until the HOLD request is removed, even when

the RESET pin is brought high. This operation is provided to simplify boot-up synchronization

among multiple processors sharing the same bus.

Figure 19. ICC vs. Frequency and Temperature—80960CF-40

1100

0040

fPCLK (MHz)

(mA)

ICC - ICC under test conditions

F_CX020A

TC = 10 00°

TC = 85° C

80960-40, -33, -25

42 Datasheet

Table 20. Reset Conditions

Pins St ate During Reset (HOLDA inactive)

A31:2 Floating

D31:0 Floating

BE3:0 Driven high (Inactive)

W/R Driven low (Read)

ADS Driven high (Inactive)

WAIT Driven high (Inactive)

BLAST Driven low (Active)

DT/R Driven low (Receive)

DEN Driven high (Inactive)

LOCK Driven high (Inactive)

BREQ Driven low (Inactive)

D/C Floating

DMA Floating

SUP Floating

FAIL Driven low (Active)

DACK3:0 Driven high (Inactive)

EOP3:0/TC3:0 Floating (Set to input mode)

Table 21. Hold Acknowledge and Backoff Conditions

Pins State During HOLDA

A31:2 Floating

D31:0 Floating

BE3:0 Floating

W/R Floating

ADS Floating

WAIT Floating

BLAST Floating

DT/R Floating

DEN Floating

LOCK Floating

BREQ Drive n (High or low)

D/CFloating

DMA Floating

SUP Floating

FAIL Driven high (Inactive)

DACK3:0 Driven high (Inactive)

EOP3:0/TC3:0 Driven (When output)

80960-40, -33, -25

Datasheet 43

6.0 Bus Waveforms

Figure 20. Cold Reset Waveform

CLKIN

PCLK2:1

ADS,

W/R, DT/R,

INST, SUP,

D31:0,

STEST

RESET

- ONCE

BLAST

LOCK, WAIT,

DEN, DACK3:0

BREQ, FAIL

DMA, A31:2,

D/C, BE3:0

EOP/TC3:0

∼

∼∼

∼

∼∼

∼

∼∼

∼

Invalid

Valid

∼

∼∼

∼

CLKIN and V

Stable to RESET high,

32 CLKIN Periods in 2x Mode,

periods in 1x Mode.

∼

Inputs

Tdelay

1 PCLK

Tsetup

1PCLK Thold

1 PCLK

∼

∼∼

∼

∼∼

∼

minimum

10,000 CLKIN

F_CX021A

∼

RESET high to First Bus

activity, approximately

32 PCLK periods.

and CLKIN Stable

to Outputs Valid, maximum

32 CLKIN Periods.

80960-40, -33, -25

44 Datasheet

Figure 21. Warm Reset Waveform

Tdelay

1PCLK

∼

∼∼

∼

∼∼

∼

Maximum

RESET

Low to

RESET

State

4 PCLK Perio ds

1 PCLK

∼

∼∼

∼

∼∼

∼

F_CX022A

PCLK2:1

ADS,

W/R, DT/R,

SUP,

D31:0,

STEST

RESET

BLAST

LOCK, WAIT,

DEN, DACK3:0

BREQ, F AIL

DMA, A31:2,

D/C, BE3:0

EOP/TC3:0

Valid

∼

∼∼

∼

Thold

Tsetup

1 PC LK

RESET

High to First Bus Activity,

Approximately 32 PCLK Periods

Minimum

RESET

Low Time

16 PCLK Periods

∼

80960-40, -33, -25

Datasheet 45

Figure 22. Entering the ONCE State

CLKIN

PCLK2:1

ADS, BE3 :0, A31:2 ,

RESET

ONCE

∼

∼∼

∼

and CLKIN Stable

to Outputs Valid, maximum

32 CLKIN Periods.

∼

CLKIN and V

Stable and RESET low and ONCE low to

RESET high, minimum 32 CLKIN Periods in 2x Mode,

10,000 CLKIN Periods in 1x Mode.

∼

D31:0, LOCK, WAIT,

BLAST,W/R, D/C, DEN,

DT/R, HOLD, HOLDA,

DMA, EOP

3:0

/TC3:0,

STEST, XINT7:0, NMI,

DACK3:0, DREQ3:0

READY, BTERM

BLAST, FAIL, SUP,BREQ,

∼

∼∼

∼

∼∼

∼

Maximum 32 CLKIN Periods

Required after ONCE Mode entered

∼

∼∼

∼

F_CX023A

∼

CLKIN may not float. It must be

driven high or low or continue to run

80960-40, -33, -25

46 Datasheet

Figure 23. Clock Synchronization in the 2-x Clock Mode

Figure 24. Clock Synchronization in the 1-x Clock Mode

CLKIN

RESET

PCLK2:1

(Case 1)

PCLK2:1

(Case 2)

1.5 V

TIH TIS

1.5 V

1.5 V1.5 V

1.5 V 1.5 V

TCP

Max

Min TCP

Max

Min TCP

SYNC

Note: Case 1 and Case 2 show two possible polarities of PCLK2:1

Min

1.5 V

F_CX024A

Max

CLKIN 1.5 V1.5 V

RESET

TIH TIS

1.5 V

2x CLK

Note: In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2xCLK. 2xCLK is an internal signal

generated by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising

edge of CLKIN. The RESET pin is sampled when PCLK is high. F_CX025A

80960-40, -33, -25

Datasheet 47

Figure 25. Non-Burst, Non-Pipelined Requests Without Wait States

ADS

A31:4, SUP

DMA, D/C,

BE3:0, LOCK

BLAST

DEN

A3:2

WAIT

D31:0

PCLK

ADADAD

Valid Valid Valid

Valid Valid

reserved

Byte

Order Bus

Width N

WDD

WAD

XDA

RDD

RAD

Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

xx 0

00000 X

xx 0

00000 OFF

0Disabled

0..0 Disabled

Valid

F_CX026A

Out

Function

Bit

Value

80960-40, -33, -25

48 Datasheet

Figure 26. Non-Burst, Non-Pipelined Read Request With Wait States

ADS

A31:2, BE3:0

DMA, D/C,

SUP, LOCK

W/R

BLAST

DT/R

DEN

WAIT

D31:0

PCLK

A3 21D1

reserved

Byte

Order Bus

Width N

WDD

WAD

XDA

RDD

RAD

Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

xx X

xxxxx X

xx 3

00011 OFF

0Disabled

0..0 Disabled

Function

Bit

Value

Valid

F_CX027A

80960-40, -33, -25

Datasheet 49

Figure 27. Non-Burst, Non-Pipelined Write Request With Wait States

ADS

A31:2,

W/R

BLAST

DT/R

DEN

SUP, DMA,

WAIT

D31:0

PCLK

A3 21 D1

reserved

Byte

Order Bus

Width N

WDD

WAD

XDA

RDD

RAD

Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

xx X

xx 3

00011 X

xx X

xxxxxx OFF

0Disabled

0..0 Disabled

Out

Function

Bit

Value

Valid

D/C, LOCK

F_CX028A

BE3:0

80960-40, -33, -25

50 Datasheet

Figure 28. Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus

In0

ADS

A31:4, SUP,

DMA, D/C ,

BE3:0, LOCK

BLAST

DEN

A3:2

WAIT

D31:0

PCLK

ADDDDA

reserved

Byte

Order Bus

Width N

WDD

WAD

XDA

RDD

RAD

Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

32-Bit

10 X

xx X

xxxxx 0

00 0

00000 OFF

0Enabled

0..0 Disabled

F_CX029A

Function

Bit

Value

In3In2In1

Valid

00 01 10 11

80960-40, -33, -25

Datasheet 51

Figure 29. Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus

ADS

A31:4, SU P,

DMA, D/C,

BE3:0, LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

reserved

Byte

Order Bus

Width N

WDD

WAD

XDA

RDD

RAD

Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

32-bit

10 X

xx X

xxxxx 1

01 2

00010 OFF

0Enabled

0..0 Disabled

A21 D 1D1 D1D1 A

In1 In2 In3

In0

Valid

00 1101 10

Function

Bit

Value

F_CX030A

80960-40, -33, -25

52 Datasheet

Figure 30. Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

32-bit

10 0

00 0

00000 X

xx X

xxxxx OFF

0Enabled

0..0 Disabled

ADS

A31:4, SUP,

DMA, D/C,

BE3:0, LOC K

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

ADDDDA

Function

Bit

Value

00 01 10 11

Out0

Valid

Out3Out2Out1

F_CX031A

80960-40, -33, -25

Datasheet 53

Figure 31. Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

BE3:0, LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

32-bit

10 1

01 2

00010 X

xx X

xxxxx OFF

0Enabled

0..0 Disabled

A21 D 1D 1 D1D 1 A

Out0

Valid

00 1101 10

Function

Bit

Value

Out1 Out2 Out3

F_CX032A

80960-40, -33, -25

54 Datasheet

Figure 32. Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus

ADS

SUP, DMA,

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

16-bit

01 X

xx X

xxxxx 1

01 2

00010 OFF

0Enabled

0..0 Disabled

A21 D 1D 1 D1D1 A

Function

Bit

Value

Valid

A3:2 = 00 or 10 A3:2 = 01 or 11

D15:0

A1=0 D15:0

A1=1 D15:0

A1=0 D15:0

A1=1

D/C, LOCK,

A31:4, BE3/BHE,

BE1/A1

BE0/BLE

F_CX033A

80960-40, -33, -25

Datasheet 55

Figure 33. Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus

ADS

SUP, DMA,

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

8-bit

00 X

xx X

xxxxx 1

01 2

00010 OFF

0Enabled

0..0 Disabled

A21 D 1D 1 D1D1 A

Function

Bit

Value

Valid

A3:2 = 00, 01, 10 or 11

D7:0

Byte 0 D7:0

Byte 1 D7:0

Byte 2 D7:0

Byte 3

D/C, LOCK,

A31:4

BE1/A1, A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 =11

BE0/A0

F_CX034A

80960-40, -33, -25

56 Datasheet

Figure 34. Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus

Non-pipelined request concludes

pipelined read s begin. Pipelined reads conclude,

non-pipelined requests begin.

ADS

A31: 4, SU P,

DMA, D/C,

LOCK

BLAST

WAIT

D31:0

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

xx X

xxxxx X

xx 0

00000 ON

1Disabled

0..0 X

Function

Bit

Value

DIN

D’IN

D’’ IN

D’’’ IN

D’’’’

AA’

DA’’

D’A’’’

D’’ A’’’’

D’’’ D’’’’

Valid Valid Valid Valid Valid Invalid

Invalid

DT/R

DEN

A3:2

BE3:0 Valid Valid Valid Valid Valid Invalid

W/R

F_CX035A

80960-40, -33, -25

Datasheet 57

Figure 35. Non-Burst, Pipelined Read Request With Wait St ates, 32-Bit Bus

Non-pipelined request concludes

pipelined reads begin. Pipelined reads conclude,

non-pipelined requests begin.

ADS

A31:4, SUP,

DMA, D/C,

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

BE3:0

A1 A’

D1D’

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-109-8 210

xx X

xxxxx X

xx 1

00001 ON

1Disabled

0..0 X

D’

Invalid

Valid Valid Invalid

LOCK Valid Valid Invalid

Function

Bit

Value

F_CX036A

80960-40, -33, -25

58 Datasheet

Figure 36. Burst, Pipelined Read Request Wi thout Wait States, 32-Bit Bus

Pipelined reads

conclude, non-pipelined

requests begin

ADS

A31:4, SUP,

DMA, D/C,

BE3:0, LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

Non-pipelined request

concludes, pipelined

reads begin

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

32-bit

10 X

xx X

xxxxx 0

00 0

00000 ON

1Enabled

0..0 Disabled

ADDDA’D’D’

Valid Valid

In-

ValidValid01 10 1100

DIN

Valid

Function

Bit

Value

In-

Valid

In-

Valid

F_CX037A

80960-40, -33, -25

Datasheet 59

Figure 37. Burst, Pipelined Read Request With Wait States, 32-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

BE3:0, LOCK

W/R

A3:2

D31:0

WAIT

BLAST

DT/R

DEN

PCLK

reserved

Byte

Order Bus

Width N

WDD

WAD

XDA

RDD

RAD

Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-109-8 210

32-bit

10 X

xx X

xxxxx 1

01 2

00010 ON

1Enabled

0..0 Disabled

Function

Bit

Value

DIN

D’

A21 D 1D 1 D1A’21

Valid

DD’

Valid In-

valid

In-

valid

00 01 10 11 Valid In-

valid

Non-pipelined request concludes,

pipelined reads begin. Pipelined reads conc lud e,

non-pipelined requests begin.

F_CX038A

80960-40, -33, -25

60 Datasheet

Figure 38. Burst, Pipelined Read Request With Wait States, 16-Bit Bus

ADS

A31:4, S UP,

DMA, D/C,

BE0/BLE,

W/R

A3:2

BE1/A1

WAIT

BLAST

DT/R

DEN

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

16-bit

01 X

xx X

xxxxx 1

01 2

00010 ON

1Enabled

0..0 Disabled

Function

Bit

Value

D15:0

A1=0 D15:0

A1=1 D15:0

A1=0 D15:0

A1=1 D15:0

D’

A21 D 1D1 D1A’21

DD’

In-

valid

Non-pipelined request conclu des,

pipelined reads begin. Pipelined reads conclude,

non-pi peli n ed req ues ts begi n .

A3:2 = 00 or 10 A 3 :2 = 01 or 11 Valid In-

valid

Valid In-

valid

BE3/BHE,

D31:0

F_CX040A

LOCK

Valid Valid In-

valid

80960-40, -33, -25

Datasheet 61

Figure 39. Burst, Pipelined Read Request With Wait States, 8-Bit Bus

ADS

A31:4, S UP,

DMA, D/C,

LOCK

W/R

A3:2

BE1/A1,

WAIT

BLAST

DT/R

DEN

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-109-8 210

8-bit

00 X

xx X

xxxxx 1

01 2

00010 ON

1Enabled

0..0 Disabled

Function

Bit

Value

D7:0

Byte 0 D7:0

Byte 1 D7:0

Byte 2 D7:0

Byte 3 D7:0

D’

A21 D 1D1 D1A’21

DD’

In-

valid

Non-pipelined request concludes,

pipelined reads begin. Pipelin ed rea ds c onclu de ,

non-pipeline d requests begin.

Valid In-

valid

BE0/A0

D31:0

A3:2 = 00, 01, 10, or 11 Valid In-

valid

A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 = 11

Valid Valid In-

valid

F_CX039A

80960-40, -33, -25

62 Datasheet

Figure 40. Using External READY

PCLK

ADS

A31:4, S UP,

DT/R

DEN

READY

W/R

DMA, INST,

BLAST

BTERM

A3:2

WAIT

D31:0

D/C, BE3:0,

LOCK

D0 D1 D2 D3 D0 D1 D2 D3

00 01 10 11 00 01 10 11

ValidValid

Quad-Word Read Request

NRAD = 0, NRDD = 0, NXDA = 0

Ready Enabled

Quad-Word Write Requ est

NWAD = 1, NWDD = 0, NWDA = 0

Ready Enabled

F_CX041A

80960-40, -33, -25

Datasheet 63

Figure 41. Terminating a Burst with BTERM

PCLK

ADS

A31:4, SUP,

DT/R

DEN

READY

W/R

DMA, INST,

BLAST

BTERM

A3:2

WAIT

D31:0

D/C, BE3:0,

LOCK

D0 D1 D2 D3

Valid

Quad-Word Write Request

NWAD = 0, NWDD = 0, NWDA = 0

Ready Enabled

00 01 10 11

Note: READY adds memory access time to data transfers, whether or not the

bus access is a burst access. BTERM interrupts a bus access, whether or not

the bus access has more data transfers pending. Either the READY signal or

the BTERM signal may terminate a bus access when the signal is asserted during

the last (or only) data transfer of the bus access.

See Note

F_CX042A

80960-40, -33, -25

64 Datasheet

Figure 42. BOFF Functional Timing

ADS

BLAST

READY

BOFF

A31:2, SUP,

D31:0,

BOFF may not

be asserted

BOFF may not

be asserted

BOFF may be asserted to suspend request

Begin Request End Request

SUSPEND REQUEST

NON-BURST

Regenerate ADS

DMA, D/C,

BE3:0, W AIT,

DEN, DT/R

(WRITES)

BURST

RESUME REQUEST

BURST

∼

Note: READY/BTERM must be enabled; NRAD, NRDD, NWAD, NWDD= 0

∼

F_CX043A

MAY CHANGE

∼

80960-40, -33, -25

Datasheet 65

Figure 43. HOLD Functional Timing

Word Read Request

NRAD=1, NXDA=1

Word Read

Request

NRAD=0,

NXDA=0

Hold State Hold State

PCLK2:1

ADS

A31:2, SU P,

DMA, D/C,

BE3:0, W AIT,

DEN, DT/R

BLAST

HOLD

HOLDA

ValidValid

F_CX044A

80960-40, -33, -25

66 Datasheet

Figure 44. DREQ and DACK Functional Timing

Figure 45. EOP Functional Timing

PCLK2:1

ADS

! (BLAST

& READY

DACKx

(All Modes)

DREQx

(Case 1)

DREQx

(Case 2)

Note:

F_CX018A

& !WAIT)

∼

System

Clock

Start DMA

Bus Request

End DMA

Bus Request

DMA

Acknowledge

DMA

Request

tIS6 tIH6

(see Note )

1. Case 1: DREQ must deassert before DACK deasserts. This applies to all Fly-By modes: source synchronized

packing modes and destination synchronized unpacking modes.

2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high.

This applies to all other DMA transfers.

3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus

accesses (defined by ADS and BLAST).

∼

high to prevent next bus cycle

PCLK2:1

EOP

F_CX045A

∼

Note: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge

held for a minimum of 2 clock cycles then deasserted within 15 clock cycles.

triggered. EOP must be

15 CLKs Max

2 CLKs Min

80960-40, -33, -25

Datasheet 67

Figure 46. Terminal Count Functional Timing

Figure 47. FAIL Functio nal Timing

Note: Terminal Count becomes active during the last bus request of a buffer transfer. When the

last LOAD/STORE bus request is executed as multiple bus accesses, the TC may be active

for the entire bus request. Refer to the i960® Cx Microprocessor User’s Manual for

further information.

PCLK2:1

DREQ

ADS

DACK

F_CX046A

RESET

FAIL

~65,000 Cycles 5 Cycles 102 Cycles

(Bus Test)

Pass

(Internal Self-Test)

Pass

∼

Fail Fail

F_CX047A

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68 Datasheet

Figure 48. A Summary of Aligned and Unaligned Transfers for Little Endian Regions

04 812162024

0123456

One Doub le-Wo rd

Short-Word

Load/Store

Word

Load/Store

Double-Word

Load/Store

Byte, Byte Requests

Short Request (Aligned)

Short Requ est (A ligned)

Byte, Byte Requests

Word Request (Aligned)

Byte, Short, Byte, Requests

Short, Short Requests

Byte, Short, Byte Requests

Byte Offset

Word Offset

F_CX048A

One Doub le-Wo rd Burst (A li gne d)

Byte, Short, Word, Byte Requests

Short, Word, Short Requests

Byte, Word, Short, Byte Requests

Word, Word Requests

Request (Aligned)

80960-40, -33, -25

Datasheet 69

Figure 49. A Summary of Aligned and Unaligned Transfers for Little Endian Regions

04 812162024

0123456

Triple-Word

Load/Store

Quad-Word

Load/Store

Word, Word,

Word Requests

Requests

Double-

Word, Word, Word,

Word Requests

Byte Offset

Word Offset

One Three-Word

Request (Aligned)

Byte , Sh o r t, Word,

Word, Byte Requests

Short Requests

Short, Word, Word,

Byte, Word, Word,

Short, Byte Requests

Word, Word,

Word Requests

One Four-Word

Request (Aligned)

Byte, Short, Word, Word,

Word, Byte Reques ts

Short, Word, Word, Word,

Short Reque sts

Byte, W ord, Word, Word,

Short, Byte Requests

F_CX049A

Requests

Word,

Word

Word,

80960-40, -33, -25

70 Datasheet

Figure 50. Idle Bus Operation

PCLK

ADS

A31:4, S UP,

DMA, INST,

D/C, BE3:0

LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

READY,

BTERM

Write Request

NWAD=2, NXDA = 0

Ready Disabled

Idle Bus

(not in Hold Acknowledge state) Read Request

NWAD=2, NXDA = 0

Ready Disabled

Out

Valid

Valid Valid

F_CX050A