MC10H131P - ON Semiconductor

 Semiconductor Components Industries, LLC, 2002

May, 2002 – Rev. 2 1Publication Order Number:

AND8066/D

Interfacing with ECLinPS

Prepared by: Paul Shockman

ON Semiconductor Logic Applications Engineering

STANDARD ECL INTERFACE: DIFFERENTIAL

DRIVER AND RECEIVER

A typical Emitter Coupled Logic (ECL) circuit interface

may b e d efined as a differential d river d evice s ending a p aired

set of commentary signals – True and Invert – over a pair of

standard, controlled impedance lines to an ECL differential

receiver device. A typical ECL output line driver consists of

a b ipolar t ransistor in a n E mitter F ollower c onfiguration with

the collector at V CC power supply r ail a nd t he e mitter pinned

out. A standard, typical differential ECL receiver consists of

a p air o f b ipolar t ransistors i n a d if ferential c onfiguration w ith

the True and Invert signals providing base drives to the two

base i nputs. P roper d ifferential l evels a re s pecified a s V pp and

VIHCMR. When an input is interconnected as a differential

signal, t he D C S ingle E nded p arameters o f V IL and VIH do not

apply. Terminations are r equired t o p reserve optimum signal

integrity, as shown in Figure 1. The standard, controlled

impedance lines a ssume a s uf ficient return c urrent c apability.

VEE

VCC

VEE

VTT

VCC

Figure 1. Standard Differential ECL Interconnect

True

Invert

SINGLE–ENDED INTERFACE

Signals may be imported as full differential lines or as a

Single–Ended (SE) line interconnection. The SE

interconnection may be seen as a special variation of the

typical differential interface using only one driver source

trace line. This single trace line drives a (Base) input pin of

the receiver, as shown in Figure 2. Although a receiver may

present only a single, dedicate SE input pin instead of a

differential i nput p air o f p ins, s uch a receiver still w ould h ave

a differential structure with the unavailable input controlled

by internal circuitry.

VEE

VCC

VEE

Figure 2. Standard Single–Ended ECL Interconnect

True

VTT

VCC

Single–ended receiver input levels are specified in data

sheets DC CHARACTERISTICS block as VIH and VIL

Parameters. Each temperature has a minimum and

maximum limit pair to VIH and VIL parameters, thus

defining the Single–Ended input swing, Vpp(SE). The

Vpp(SE) ranges from 595 mV to 890 mV, depending on the

temperature and family. The Vpp(SE) limits constitute the

receiver device’s input single–ended sensitivity.

Both output lines of the typical differential output may

drive t wo independent s ingle–ended receivers s eparately ( see

Figure 3).

VEE

VCC

VEE

Figure 3. Differential Driver with Independent

Standard Single–Ended Receivers

True

VTT

VCC

Invert

VEE

VCC

VTT

APPLICATION NOTE

http://onsemi.com

AND8066/D

http://onsemi.com

VBB Reference

For a standard differential receiver with two input pins –

D and D – only one of two inputs is suitably selected to

receive the signal while the non–driven input must be biased

to a (DC) reference voltage, VBB (see Figure 4).

VEE

VCC

VEE

Figure 4. Standard SE Receivers with VBB

True

VBB

VCC

VTT

The VBB value is designed to be maintained midway

(50%) between the HIGH and LOW levels of the received

signal, that is, the crosspoint voltage of a differential signal

pair, to preserve the duty cycle and signal integrity (see

Figure 5).

VBB or Crosspoint

Figure 5. VBB Crosspoint Voltage

True

Invert

LOW

HIGH

If VBB shifts, due to drift or noise, above the input signal

50% crosspoint, the device output signal will shift the duty

cycle away from a pure 50% point to a decreased, narrowing

pulse width (see Figure 6).

Figure 6.

VBB

Input

HIGH

LOW

Output Shift Narrower

If VBB shifts below the input signal 50% crosspoint, the

device output signal will shift the duty cycle away from a

pure 50% point to an increased, widening pulse width (see

Figure 7).

Figure 7.

VBB

Input

HIGH

LOW

Output Shift Wider

Obviously, any error voltage present on the VBB reference

level injects jitter directly into the signal.

VBB: Voltage Reference Sources

A V BB r eference v oltage o utput s ource p in m ay b e a vailable

on the receiver device. When present, VBB is an internally

generated voltage supply and available only to that device’s

inputs. C urrent d emand o n t he V BB p in s hould b e l imited t o 0 .5

mA. Bypass (0.01 F) V BB to t he quietest p lane, usually V CC,

since n oise o n V BB w ill i nject j itter a nd c orrupt d uty c ycle. T he

VBB voltage is derived from referencing the VCC supply and

will track changes in V CC 100% or 1:1. If VCC shifts 1 mV,

then V BB also changes 1 mV. Changes in VEE also affect the

VBB voltage a nd w ill t rack a t t he r ate o f 0 t o 2 0%, t ypically 5 %.

If VEE shifts 100 mV, t hen V BB follows w ith a 0 m V to 2 0 mV

shift of the same polarity, typically 5 mV.

A VBB reference voltage may be generated off–device and

supplied to the input pins. Ripple content must be kept as low

as possible on VCC since it transfers to the signal as jitter and

phase error. A VBB voltage reference level may be supplied

from a VBB generator, as shown in Figure 8. Any of the “16”

type buffers are recommended to produce a high current gain

VBB buffer. For example, the E416, EL16, LVEL16, EP16,

LVEP16, EL17, LVEL17, etc. type devices have a VBB pin

available. A 1 K resistor may be needed the feedback path

to stabilize higher gain buffers.

Figure 8. VBB Voltage Reference Generator

VBB(out)

VTT

VCC or VTT

VBB

0.01 F

1 K

AND8066/D

http://onsemi.com

Depending on system requirements, VBB may be

generated by a dedicated supply, a “16” type buffer, or by

using a bypassed resistor voltage divider.

Dedicated Single–Ended Input Structure

A device may have a dedicated single–ended input, having

only o ne of the internal d ifferential base inputs pinned o ut of the

package, available to be driven by a signal. Internal circuitry

connects a VBB voltage reference to the other internal,

non–driven input base node of the differential buffer gate, as

shown in Figure 2. This internal, fixed reference voltage, VBB,

is maintained at the midpoint between VIL and VIH for

dedicated s ingle–ended inputs. The internal VBB is derived from

referencing the VCC supply and tracks changes 1:1 in this

supply. Noise and drift in VCC will inject jitter and phase noise

directly into the signal.

DIFFERENTIAL INTERFACE

A standard differential interconnect driver signal will be

received as signal swing. Historically, standard ECL driver

signal swing may range from 750 mV to 1040 mV depending

on the family, although 800 mV is typical. Newer devices may

offer RSECL (Reduced Swing ECL) or Variable Output Swing

(NBSG16VS). R eceiver sensitivity is specified by d ata sheets as

the input swing voltage peak–to–peak (Vpp). Proper output

operation i s displayed as the typical amplitude through the entire

range of input swing, from minimum to maximum as shown in

Figure 9: Vpp – Input Swing Voltage Peak–to–Peak. Input

swings greater than specification limit maximum may cause

degraded frequency performance and increased tpd input. Input

swings less than specification minimum will cause diminished

output a mplitude due to t he device voltage gain and low enough

input amplitude will result in a loss of output signal. All

waveforms are measured with single ended probes with

reference t o ground (not a s a differential probe value). O peration

in the small signal level range less than Vpp minimum display

a c haracteristic gain and may obviously b e operated as a limited

linear amplifier this input swing range.

Figure 9. Vpp – Input Swing Voltage Peak–to–Peak

Input Vpp Output Vpp

Max

Min Typ

Noise c ommon t o b oth d ifferential l ines a nd w ithin the i nput

operating range will be rejected and ignored by the receiver.

The transfer threshold p oint is d etermined b y the c rosspoint o f

the differential signal. A v oltage shift in input operating range

of the transfer point has no voltage or timing effect on the

signal, t herefore, p reserving integrity. A r eceiver’s t olerance of

common mode interference is illustrated in Figure 10.

Figure 10. Differential Input High Noise Immunity

t1t2t1t2

Input Output

VIHCMR

Each input signal to a differential pair receiver will display a

Vin HIGH voltage (VIH) level and a Vin LOW voltage VIL.

Proper operation is achieved when the Vin HIGH voltage (VIH)

level falls within spec limits, VIHCMR (Voltage Input High

Common Mode Range) minimum to maximum as represented

in Figure 11.

Figure 11. VIH Common Mode Range, VIHCMR

VIN(pp

)

t1t2t3t4

VIH(max)

VIH(min)

VIHCMR

Input

t1t2t3t4

VOUT(pp)

Output

Considerations for Single–Ended and Differential

Interconnects

Several advantages and disadvantages are listed below.

Single–Ended (SE) Interconnects

Advantages may include:

•Decreased board real estate routing.

•Reduced system power demand.

Disadvantages may include:

•Higher jitter, phase error, and duty cycle skew.

•High noise sensitivity.

•Critically narrow interface windows.

•Poor receiver sensitivity.

•Higher EMI emission.

Differential Interconnects

Advantages may include:

•High common mode noise rejection (low noise

sensitivity).

AND8066/D

http://onsemi.com

•Wide signal interface windows.

•High receiver sensitivity.

•Low EMI emission.

Disadvantages may include:

•Increased board routing real estate.

•Increased system power demand.

ECL 10 and 100 Performance Standards

There currently exist two basic legacy standards for high

performance ECL logic devices.

10 Series (compatible with 10H)

100 Series (compatible with 100K)

Both standards display similar highly compatible output

amplitude swings of about 800 mVpp over a wide range of

operating conditions and loads. This is due to drivers

enjoying a remaining internal output impedance ranging

from 6 t o 8  in both HIGH and LOW level state levels (see

Figure 12).

Figure 12. Outputs vs. Load Drive Characteristics

25 

to –2.0 V

–2.0

–5

–10

–15

–0.75–1.0–1.25

–20

–25

–30

–35

–40 –1.75 –0.5 –0.25

OUTPUT VOLTAGE (V)

OUTPUT CURRENT (mA)

SLOPE = 6  – 8 

VOH

–1.5

VOL

TA = 25°C

50 

to –2.0 V

150 

to –2.0 V

100 

to –2.0 V

For loads of 35 ohms or less, outputs may need to be

“ganged” (wire “ANDed”), or specialized 25– driver

circuits deployed. These specialized drivers ensure reduced

power dissipation and improve long term reliability. Both

standards display similar rise/fall times, propagation delays,

and toggle frequencies.

Differential Interface Between 10 and 100

Standards

When interfacing differentially, the two basic standards

are completely, directly compatible over all operational

conditions. This results from receivers of both standards

exhibiting wide VIH Common Mode Range and fine

minimum input sensitivity, Vpp. Output temperature

variations associated with 10 Series devices are well within

these receiver input characteristic limitations.

Single–Ended (SE) Interface Between 10 and 100

Standards

Single–Ended (SE) line signal interconnects require

analysis of both the driver output levels, VOH and VOL,

across temperature and the receiver input voltage level

limits, VIH and VIL, to determine complete interface

compatibility. Although 100 Series standard devices

incorporate a temperature compensation network in the

output driver, some variation may still be observed.

Variation of the driver output levels, VOH and VOL, across

temperature is typically present in 10 Series devices.

Device series voltage transfer curves characterize the

input and output behavior function across temperature. This

is shown in Figures 13 through 16 for 10E, 100E, 10K, and

10KH Series. Changes in technology refinements to the 10K

Series led to the 10KH Series with better performance in VIH

and VOL as Vin approached VCC. the 10E Series is similar

to the 10KH Series. Temperature compensation allowed the

development of the 100 Series.

–2.0

–1.2

–1.4

–1.8

–1.6–1.8

Vout, RELATIVE TO VCC

Vin, (RELATIVE TO VCC)

Vout, RELATIVE TO VCC

–0.8

25°C

Vin, (RELATIVE TO VCC)

–1.6

–1.4

–1.0

–1.2 –0.8

–1.0 –2.0

–1.2

–1.4

–1.8

–1.6–1.8

–0.8

–1.6

–1.4

–1.0

–1.2 –0.8–1.0

25°C

25°C0°C

85°C

Figure 13. 10E Series Vin vs. Vout Transfer Curves Figure 14. 100E Series Vin vs. Vout Transfer Curves

AND8066/D

http://onsemi.com

Vin, (RELATIVE TO VCC)V

in, (RELATIVE TO VCC)

Vout, RELATIVE TO VCC

–1.2

–1.8

–0.8

–1.6

–1.4

–1.0

–1.2

–1.8

–0.8

–1.6

–1.4

–1.0

–2.0 –1.4–1.6–1.8 –1.2 –0.8–1.0–2.0 –1.4–1.6–1.8 –1.2 –0.8–1.0

85°C 25°C –30°

C70°C 25°C 0°C

Figure 15. 10K Series Vin vs. Vout Transfer Curves Figure 16. 10KH Series Vin vs. Vout Transfer Curves

The difference in the DC b ehavior of the i nputs and outputs

of the two different standards necessitates caution when

mixing the two technologies in single–ended designs. Output

levels b ecome c ritical to t he r eceiver w hen t he VOH m inimum,

VOHA, drives i nto t he r eceiver a s the VIH m inimum. Levels a re

also c ritical when t he d river V OL maximum, V OLA, drives i nto

the receiver as the VIL maximum.

Figure 17. Single–Ended Noise Margin

VOH(max)

VOH(min)

VOHA

VIH(max)

VIH(min)

VOL(max)

VOLA

VOL(min)

VIL(max)

VIH(min)

Noise margin quantifies the susceptibility of a driver and

receiver interface to any non–signal voltage levels and

therefore risking false switching. Two measurements –

NOISE MARGIN HIGH and NOISE MARGIN LOW –

describe the false switching risk across temperature as

follows:

NOISE MARGIN(HIGH) = VOH(min) – VIH(min)

NOISE MARGIN(LOW) = VOL(max) – VIL(max)

An MC10EP16DT, operating in LVPECL mode w ith 3.3 V

on VCC and 0.0 V on VEE, interfaced to an MC10EP16DT

receiver, single–ended, has a noise margin at the specification

ambient temperature shown in Table 1. Notice the safety

margin levels are positive for NOISE MARGIN HIGH

indicating the driver exceeds the receiver’s requirement for a

minimum and the delta is positive. For a NOISE MARGIN

LOW, the driver must be below the receiver’s maximum and

the delta is negative.

Table 1. Noise Margins: MC10EP16DT Interfaced to

an MC10EP16DT Receiver

10 to 10 Noise

Margin HIGH Temp. VOH(min) –

VIH(min)

Delta

(mV)

–40°C2165 – 2090 75

25°C2230 – 2155 75

85°C2290 – 2215 75

10 to 10 Noise

Margin LOW Temp. VOL(max) –

VIL(max)

Delta

(mV)

–40 °C1615 – 1690 –40

25°C1680 – 1755 –75

85°C1740 – 1810 –70

When a 10 Series device drives a 100 Series device

single–ended, the noise margins become a risk factor requiring

careful evaluation as indicated in Table 2.

Table 2. Noise Margins: MC10EP16DT Interfaced to

an MC100EP16DT Receiver

10 to 100 Noise

Margin HIGH Temp. VOH(min) – VIH(min)

Delta

(mV)

–40°C2165 – 2075 90

25°C2230 – 2075 155

85°C2290 – 2075 215

10 to 100 Noise

Margin LOW Temp. VOL(max) – VIL(max)

Delta

(mV)

–40 °C1615 – 1675 –60

25°C1680 – 1675 5

85°C1740 – 1675 65

AND8066/D

http://onsemi.com

When a 100 Series device drives a 10 Series device,

single–ended, the noise margins are very robust and immunity

is optimized (See Table 3).

Table 3. Noise Margins: MC100EP16DT Interfaced to

an MC10EP16DT Receiver

100 to 10 Noise

Margin HIGH Temp. VOH(min) – VIH(min)

Delta

(mV)

–40°C2405 – 2090 315

25°C2405 – 2155 250

85°C2405 – 2215 190

100 to 10 Noise

Margin LOW Temp. VOL(max) – VIL(max)

Delta

(mV)

–40 °C1605 – 1690 –85

25°C1605 – 1755 –150

85°C1605 – 1810 –205

Edge Rates (dV/dT)

As a driver rising edge approaches the transfer voltage

point of t he r eceiver i nput, t he r eceiver d iminishes in v oltage

according to the small signal gain of the device. When the

input voltage l evel p asses t hrough t he t ransfer crosspoint, t he

output will “switch” states in an analog or operational

amplifier mode. Non–signal voltage fluctuations and noise

will be amplified. These phenomena will determine the

suitable edge rate limitation. As the edge becomes slower,

ambient n oise p resent o n t he i nput p in w ill t ypically c onstrain

practical usability. Typically, this may be from 5 ns to 35 ns

and further precaution, such as shielding, will extend the

operating edge times.

For s ignal e dges s lower t han 2 0 n s, a S chmitt t rigger c ircuit

may be considered to reliably sharpen the edge rates. In

theory, ECL logic may operate from sub–hertz (< 1.0 Hz)

frequencies, b ut r eal c ircuit c onditions w ill c onstrain p ractical

limits.

Figure 18. Schmitt Trigger with 228 mV Hysteresis

Qout

VTT

VCC or VTT

VBB

0.01 F

400 

1 k

DIN Qout

Schmitt conditioning may be determined by the resistor

values. An R1 resistor of 1 k provides inverted output

feedback resistor (Rfb) from Qout to the threshold voltage

point, D. A 400  bias resistor, R2, to VBB sets the voltage

offset as a fraction of the output voltage from VBB. With an

800 mV Vout swing, VBB will be the midpoint between VOH

and VOL, or 400 mV from a state level. The two resistors

form a voltage divider from either state level to VBB.About

28% of the LOW or HIGH state level is developed at the

voltage divider node and ported to D. This will be the offset

a signal must exceed to force the buffer to switch states.

For trVoffset R2

R1 R2 (V

OL VBB )

400

1400 400

114mV

For tfVoffset R2

R1 R2 (V

OH VBB )

400

1400 400

114mV

This creates a total of 228 mV of hysteresis conditioning.

The effect of the hysteresis delay in a signal must be

considered in the timing analysis.

AND8066/D

http://onsemi.com

Notes

AND8066/D

http://onsemi.com

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make

changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all

liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC

and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: 81–3–5740–2700

Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local

Sales Representative.

AND8066/D

Literature Fulfillment:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

N. American Technical Support: 800–282–9855 Toll Free USA/Canada