S3C2450/16/51 400/533MHz 32-BIT CMOS MICROCONTROLLER Application Note - Power Design Guide Revision 0.3 i Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. 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Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BVQ1 Certificate No. 9330). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(031)-209-5621 FAX: (82) (331) 209-0837 Home-Page URL: Http://www.samsungsemi.com/ Printed in the Republic of Korea ii Revision History Revision No Description of Change Refer to Author(s) Date 0.00 - Initial Release for review - K.Y.SHIM June 30, 2008 0.30 - Revised Power on/off sequence - K.Y.SHIM March 23, 2009 S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL 1. POWER DESIGN GUIDE OVERVIEW This document describes S3C2450/16/51 power design guide for circuit designer. It shows as follows, - recommend DC operating conditions - recommend system power design - power on/off sequence - PLL design guide - power consumption data It will help you design your system properly. 1 S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL RECOMMENDED OPERATING CONDITIONS Table 1-1. Recommended Operating Conditions (400MHz) Parameter Symbol DC Supply Voltage for Alive Block VDDalive DC Supply Voltage for Core Block ARMCLK / HCLK 400/133 MHz VDDiarm VDDi VDDA_MPLL VDDA_EPLL Min Typ Max 1.15 1.2 1.25 1.25 1.3 1.35 DC Supply Voltage for I/O Block1 VDD_OP1** 1.7 1.8 / 2.5 /3.3 3.6 DC Supply Voltage for I/O Block2 VDD_OP2 1.7 1.8 / 2.5 / 3.3 3.6 DC Supply Voltage for I/O Block3 VDD_OP3 1.7 1.8 / 2.5 / 3.3 3.6 DC Supply Voltage for USBOSC PAD VDD_USBOSC 1.7 1.8 / 2.5 / 3.3 3.6 DC Supply Voltage for SRAM I/F VDD_SRAM 1.7 1.8 / 2.5 /3.3 3.6 DC Supply Voltage for SDRAM I/F VDD_SDRAM 1.7 1.8 / 2.5 2.7 DC Supply Voltage for RTC VDD_RTC 1.7 1.8 / 2.5 / 3.0 3.3 DC Supply Voltage for CAM/SD/LCD VDD_CAM 1.7 1.8 / 2.5 / 3.3 3.6 VDD_SD 1.7 1.8 / 2.5 / 3.3 3.6 VDD_LCD 1.7 1.8 / 2.5 / 3.3 3.6 DC Supply Voltage for USB PHY 3.3V VDDA33x 3.3-5% 3.3 3.3+5% DC Supply Voltage for USB PHY 1.2V VDDI_UDEV 1.2-5% 1.2 1.2+5% DC Supply Voltage for ADC VDDA_ADC 3.0 3.3 3.6 DC Input Voltage VIN 3.0 3.3 3.6 2.3 2.5 2.7 1.7 1.8 1.95 3.0 3.3 3.6 2.3 2.5 2.7 1.7 1.8 1.95 DC Output Voltage Operating Temperature VOUT TA Industrial -40 to 85 Extended -20 to 70 Unit V o C NOTE 1: **If not use USB function, VDD_OP1 have a range from 2.3V to 3.6V. NOTE 2: S3C2416X does not support VDD_CAM conditions. 2 S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL Table 1-2. Recommended Operating Conditions (533MHz) Parameter Symbol Min Typ Max 1.15 1.2 1.25 VDDiarm 1.275 1.325 1.375 VDDi VDDA_MPLL VDDA_EPLL 1.15 1.2 1.25 DC Supply Voltage for Alive Block VDDalive DC Supply Voltage for Core Block ARMCLK / HCLK 533/133 MHz DC Supply Voltage for I/O Block1 VDD_OP1** 1.7 1.8 / 2.5 /3.3 3.6 DC Supply Voltage for I/O Block2 VDD_OP2 1.7 1.8 / 2.5 / 3.3 3.6 DC Supply Voltage for I/O Block3 VDD_OP3 1.7 1.8 / 2.5 / 3.3 3.6 DC Supply Voltage for USB OSC PAD VDD_USBOSC 1.7 1.8 / 2.5 / 3.3 3.6 DC Supply Voltage for SRAM I/F VDD_SRAM 1.7 1.8 / 2.5 /3.3 3.6 DC Supply Voltage for SDRAM I/F VDD_SDRAM 1.7 1.8 / 2.5 2.7 DC Supply Voltage for RTC VDD_RTC 1.7 1.8 / 2.5 / 3.0 3.3 DC Supply Voltage for CAM/SD/LCD VDD_CAM 1.7 1.8 / 2.5 / 3.3 3.6 VDD_SD 1.7 1.8 / 2.5 / 3.3 3.6 VDD_LCD 1.7 1.8 / 2.5 / 3.3 3.6 DC Supply Voltage for USB PHY 3.3V VDDA33x 3.3-5% 3.3 3.3+5% DC Supply Voltage for USB PHY 1.2V VDDI_UDEV 1.2-5% 1.2 1.2+5% DC Supply Voltage for ADC VDDA_ADC 3.0 3.3 3.6 DC Input Voltage VIN 3.0 3.3 3.6 2.3 2.5 2.7 1.7 1.8 1.95 3.0 3.3 3.6 2.3 2.5 2.7 1.7 1.8 1.95 DC Output Voltage Operating Temperature VOUT TA Industrial -40 to 85 Extended -20 to 70 NOTE 3: **If not use USB function, VDD_OP1 have a range from 2.3V to 3.6V. NOTE 4: S3C2416X does not support 533MHz conditions. 3 Unit V C S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL RECOMMEND SYSTEM POWER DESIGN (1) Power generation using controllable PMIC Recommended Power on sequence: Alive -> Core -> I/O with Memory -> nRESET When All of Power source must be controlled by PMIC, PWREN is no meaningful when power on/off reset. In order to enter/exit the SLEEP mode, PWREN signal is used for controlling on/off core power. System designer has to make this manner. (2) Power generation using Discrete Buck & LDO Regulator Recommended Power on sequence: I/O with Memory -> Alive -> Core(controlled by PWREN) -> nRESET PWREN signal is invoked when I/O power is on & waked up from SLEEP mode. So it is easy to make this PWREN signal to use core power enable signal as these two cases. In this case, we recommend this power on sequence. System designer easily makes its system as this manner. Note) Alive part I/O signal has unknown state which is described in the Figure 1-3. Power on sequence. At this time, Some I/O signal may occur glitch, but has no problem to enter the normal operation mode. For example, when using this I/O as LED on/off control signal, it causes unwanted flickering. To protect this glitch, System designer can use external AND gate device with nRESET signal. VDD_IO Camera Flash LCD Back light Vibrator Audio Pop-up LED GPxx nRESET Table 1-3. 400MHz operating voltage Power Pins Voltage spec. Normal operating voltage VDDiarm VDDi/VDDmpll/VDDepll 1.25V ~ 1.35V 1.3V Table 1-4. 533MHz operating voltage Power Pins Voltage spec. Normal operating voltage VDDarm 1.275V ~ 1.375V 1.325V VDDi/VDDmpll/VDDepll 1.15V ~ 1.25V 1.2V 4 S3C2450/16/51 POWER DESIGN GUIDE Figure 1-1. Power Scheme Diagram: (400MHz) Figure 1-2. Power Scheme Diagram : (533MHz) 5 SAMSUNG CONFIDENTIAL S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL POWER ON and OFF SEQUENCE Figure 1-3. Power on sequence Table 1.5 Power on Reset Timing Specifications Symbol Description Min tOA VDDpadIO to VDDalive 0 tAI VDDalive to VDDarm/i/xpll tAE VDDalive to PWREN tOSC VDDarm/i/xpll to Oscillator stabilization tOR Oscillator stabilization to nRESET & nTRST high Typical Max ms It depends on Regulator. 0 10 500 10 Units us ns us cycle 6 S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL VDDA33x VDDi_UDEV tIP tPI Symbol Description Min Typical Max Units tIP VDDi_UDEV to VDDA33x 0 ms tPI VDDA33x to VDDi_UDEV 0 ms Figure 1-4. USB power on/off sequence VDD_Opx VDD_CAM VDD_LCD VDD_SD VDD_SDRAM VDD_SRAM VDDalive VDDlogic /VDDarm /VDDpll tIOC Symbol Description Min tIOC VDDpadIO to VDDcore(VDDalive/VDDiarm/VDDi/VDDpll) 0 Figure 1-5. Power off sequence 7 Typical Max Units ms S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL Figure 1-6. Sleep mode & wakeup sequence 8 S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL PLL DESIGN GUIDE Inside of a Chip Inside of a Chip ExtCLK External OSC ExtCLK Inside of a Chip CEXT X-tal EPLLCAP 1Mohm CEXT XTOPLL A) X-TAL Oscillation (OM[0]=0) XTOPLL B) External CLK SRC (OM[0]=1) * S3C2450X only has NC pin for compatibility with S3C2443X Figure 1-7. Main Oscillator circuit examples Figure 1-8. USB Oscillator circuit examples Figure 1-9. RTC Oscillator circuit examples 9 NC(MPLLCAP) XTIPLL XTIPLL 1.8nF 5% S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL (1) MPLL Specification The output frequencies of MPLL can be calculated using the following equations: FOUT = (m x FIN) / (p x 2S) (should be 40~1600MHz) Fvco = (m x FIN) / p (should be 800~1600MHz) where, m = MDIV, p = PDIV, s = SDIV, Fin = 10~30Mhz Don't set the value PDIV[5:0] or MDIV[9:0] to all zeros. (6'b00 0000 / 10'b00 0000 0000) NOTE: Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL value recommendation table. If you have to use other values, please contact us. FIN Target FOUT MDIV PDIV SDIV (MHz) (MHz) (decimal) (decimal) (decimal) 12 240 320 4 2 40~60% 12 400 400 3 2 40~60% 12 450 225 3 1 40~60% 12 500 250 3 1 40~60% 12 533 267 3 1 40~60% 12 600 300 3 1 40~60% 12 800 400 3 1 40~60% Duty (2) EPLL Specification The output frequencies of EPLL can be calculated using the following equations: s FOUT = ((m+k/216 )x FIN) / (p x 2 ) (should be 20~100MHz) Fvco = (m x FIN) / p where, m = MDIV, p = PDIV, s =SDIV, k = KDIV Fin = 10~40MHz Don't set the value PDIV[5:0] or MDIV[7:0] to all zeros. (6'b00 0000 / 8'b0000 0000) NOTE: Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL value recommendation table. If you have to use other values, please contact us. FIN (MHz) FOUT (MHz) MDIV (decimal) PDIV (decimal) SDIV (decimal) KDIV (decimal) Error [%] 12 36 48 1 4 0 0 12 48 32 1 3 0 0 12 60 40 1 3 0 0 12 72 48 1 3 0 0 12 84 28 1 2 0 0 12 96 32 1 2 0 0 10 S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL (3) Usual Conditions for MPLL/EPLL & Clock Generator PLL & Clock Generator generally use the following conditions. Table 1.6 MPLL/EPLL & Clock Generator condition MPLLCAP : N/A CLF Loop filter capacitance EPLLCAP :Typical 1.8nF 5% - Fin MPLL: 10 - 30 MHz EPLL: 10 - 40 MHz - Fout MPLL: 40 - 1600 MHz EPLL: 20 - 100 MHz External capacitance used for X-tal CEXT 15 pF Feedback Resistor used for X-tal RF 1M (4) USB2.0 PLL Specification PLL & Clock Generator generally uses the following conditions. Table 1.7 USBPLL & Clock Generator condition REXT R 44.2 1% VDDA33V V 3.3V ( 5%) VDDI_UDEV V 1.2V ( 5%) External X-tal frequency - 12M/24M/48 MHzI Recommend a quartz crystal External capacitance used for X-tal CEXT NOTE: For usb2.0 device, user should obey a layout rule of PCB. 11 12M/24MHz - 20 pF 48MHz - 16 pF