Product Folder Sample & Buy Support & Community Tools & Software Technical Documents bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 bq24266 3-A, 30-V Standalone Single-Input, Single-Cell Switchmode Li-Ion Battery Charger 1 Features 3 Description * The bq24266 is highly integrated single cell Li-Ion battery charger and system power path management devices that supports operation from either a USB port or wall adapter supply. The power path feature allows the bq24266 to power the system from a high efficiency DC to DC converter while simultaneously and independently charging the battery. The power path also permits the battery to supplement the system current requirements when the adapter cannot. To support USB OTG applications, the bq24266 is configurable to boost the battery voltage to 5V and supply up to 1A at the input. The battery is charged with three phases: precharge, constant current and constant voltage. Thermal regulation prevents the die temperature from exceeding 125C. Additionally, a JEITA compatible battery pack thermistor monitoring input (TS) is included to prevent the battery from charging outside of its safe temperature range. 1 * * * * * * Charge Time Optimizer (Enhanced CC/CV Transition) for Faster Charging Integrated FETs for Up to 3A Charge Rate at 5% Accuracy and 93% Peak Efficiency Boost Capability to Supply 5V at 1A at IN for USB OTG Supply Integrated Power Path MOSFET and optional BGATE control to Maximize Battery Life and Instantly Startup From a Deeply Discharged Battery or No Battery 30V Input Rating with Over-Voltage Protection Supports 5V USB2.0/3.0 and 12V USB Power Delivery Small Solution Size In a 4mm x 4mm QFN-24 Package Safe and Accurate Battery Management Functions Programmed Using IUSB and /CE - Input Current Limit and VIN_DPM Threshold - Thermal Regulation Protection for Input Current Control - Thermal Shutdown and Protection Device Information(1) PART NUMBER Handheld Scanner and Point of Sale Terminals Handheld Products Power Banks and External Battery Packs Small Power Tools Portable Media Players and Gaming BODY SIZE (NOM) VQFN (24) 4.00mm x 4.00mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 2 Applications * * * * * PACKAGE bq24266 Application Schematic IN VBUS D+ 1.5H DGND SW 4.7F >10F 0.033F PGND 10F System Load BOOT PMID SYS 1F 26.7kY BGATE VDPM BAT 10kY VDRV 1F HOST 5.62kY PACK+ TEMP DRV TS 2.2F bq24266 12.4kY ISET PACK- 400Y 1.5kY PG GPIO CHG 1.5kY CE GPIO IUSB1 GPIO IUSB2 GPIO IUSB3 GPIO 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 1 1 1 2 4 6 Absolute Maximum Ratings ..................................... 6 ESD Ratings ............................................................ 6 Recommended Operating Conditions....................... 6 Thermal Information ................................................. 7 Electrical Characteristics........................................... 7 Switching Characteristics ........................................ 11 Typical Characteristics ............................................ 12 Detailed Description ............................................ 13 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 13 14 16 16 8 Applications and Implementation ...................... 26 8.1 Application Information............................................ 26 8.2 Typical Applications ................................................ 26 9 Power Supply Recommendations...................... 31 9.1 Requirements for SYS Output ................................ 31 9.2 Requirements for Charging ..................................... 31 10 Layout................................................................... 32 10.1 Layout Guidelines ................................................. 32 10.2 Layout Example .................................................... 32 11 Device and Documentation Support ................. 33 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ....................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 33 33 33 33 33 33 12 Mechanical, Packaging, and Orderable Information ........................................................... 33 4 Revision History Changes from Revision F (August 2015) to Revision G Page * Changed absolute maximum value for SYS, TS and I/O pins from 5.0 V to 5.5 V. .............................................................. 6 * Added VIN > VUVLO test condition for VBATUVLO. ..................................................................................................................... 10 * Changed image object for Figure 26 ................................................................................................................................... 28 Changes from Revision E (December 2014) to Revision F Page * Deleted devices bq24265 and bq24267 ................................................................................................................................ 1 * Changed bq2426x To: bq24266 throughout the datasheet ................................................................................................... 1 * Deleted Features: Host-controlled JEITA Compatible NTC Monitoring Input (bq24265)....................................................... 1 * Deleted Features: Voltage-based, JEITA Compatible NTC Monitoring Input (bq24266)....................................................... 1 * Changed text in the Description From: "The bq24265, bq24266, and bq24267 are.." To: "The bq24266 is.."...................... 1 * Changed 1F to 2.2F on the DRV pin of the Application Schematic ................................................................................... 1 * Deleted the Device Comparison Table................................................................................................................................... 4 * Deleted the bq24265 pinout image......................................................................................................................................... 4 * Changed the DRV pin description From: "1F of ceramic capacitance" To: "a 2.2uF, 10V, X5R or better capacitor" in the Pin Functions table ....................................................................................................................................................... 5 * Changed absolute maximum value for DRV pin from 5.0 V to 5.5 V. ................................................................................... 6 * Moved the Stroage temperature to Absolute Maximum Ratings (1) ....................................................................................... 6 * Changed the Handling Ratings table To: ESD Ratings table................................................................................................. 6 * Deleted references to BQ24265 and BQ24266 in VBATREG of the Electrical Characteristics ................................................. 8 * Deleted references to BQ24265 and BQ24266 in KISET of the Electrical Characteristics ..................................................... 8 * Deleted text from the Overview section: "The bq24265 allows a host to monitor a NTC thermistor and adjust the charge current and voltage using the CE1 and CE2 pins." and "The bq24267 features a TS input with HOT/COLD support only." ........................................................................................................................................................................ 13 * Deleted text from the Charge Profile section: "using CE1 and CE2 (bq24265) or CE (bq24266/7)." ................................. 17 * Deleted text from the Safety Timer in Charge Mode section: " (bq24266/7) and when CE1 and CE2 (bq24265) are configured according to Table 2. .......................................................................................................................................... 21 2 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 * Changed the External NTC Monitoring (CE1, CE2, and TS) section To: External NTC Monitoring (TS) ........................... 21 * Deleted Table "CE1, CE2 Configurations" ........................................................................................................................... 21 * Deleted text from the Application Information section: "but can be used to evaluate the bq24265 or bq24267 as well. To configure the board to use the bq24265, the /CE1 and /CE2 pins are used to comply with JEITA per Table 2. .......... 26 * Deleted the bq24265 Typical Application No External Discharge FET image .................................................................... 26 Changes from Revision D (October 2014) to Revision E * Page Changed "Select 100k for the bottom resistor" to "Select 10k for the bottom resistor" in the Input Voltage Based Dynamic Power Management (VIN-DPM) section................................................................................................................. 16 Changes from Revision C (October 2014) to Revision D Page * Deleted text "TS faults are reported by the I2C interface"; bq24266/7 TS pin description. ................................................... 5 * Deleted text "or 2A (depending on the I2C setting)" from PWM Controller in Boost Mode description. .............................. 24 Changes from Revision B (September 2014) to Revision C Page * Changed the Test Conditions of VSYSREG(LO) From: VBAT < VMINSYS To: * Deleted list item 3: CE pin = high from Battery Discharge FET (BGATE) .......................................................................... 20 BAT < VMINSYS, battery attached ................................ 7 Changes from Revision A (August 2014) to Revision B Page * Changed the text in the Boost Mode Operation section....................................................................................................... 24 * Added a NOTE to the Application and Implementation section .......................................................................................... 26 Changes from Original (June 2014) to Revision A * Page Removed the Product Preview banner. ................................................................................................................................. 1 Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 3 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com 5 Pin Configuration and Functions 4 SW SW PGND PGND AGND IN RGE Package 24-Pin VQFN Top View 24 23 22 21 20 19 17 IUSB1 DRV 3 16 IUSB2 CE 4 15 VDPM TS 5 14 IUSB3 SYS 6 13 CHG Submit Documentation Feedback 7 8 9 10 11 12 ISET 2 BGATE BOOT PG IN BAT 18 BAT 1 SYS PMID Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 Pin Functions PIN NAME PIN NUMBER I/O 20 - 8, 9 I/O Battery Connection. Connect to the positive pin of the battery. Bypass BAT to GND with at least 1F of ceramic capacitance. See Application section for additional details. 11 O External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET to provide a very low resistance discharge path. Connect BGATE to the gate of the external MOSFET. BGATE is low during high impedance mode or when no input is connected. If no external FET is required, leave BGATE disconnected. Do not connect BGATE to GND. 2 I High Side MOSFET Gate Driver Supply. Connect 0.033F of ceramic capacitance (voltage rating > 10V) from BOOT to SW to supply the gate drive for the high side MOSFET. 4 I IC Charge Enable Input. Drive CE high to place the part to disable charge. Drive CE low for normal operation. CE is pulled low internally with 100k. 13 O Charge Status Open Drain Output. CHG is pulled low when a charge cycle starts and remains low while charging. CHG is high impedance when the charging terminates and when when no supply exists. 3 O Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV to PGND with at least a 2.2F, 10V, X5R or better capacitor. DRV may be used to drive external loads up to 10mA. DRV is active whenever the input is connected and VIN > VUVLO and VIN > (VBAT + VSLP). 18, 19 I DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port). Bypass IN to PGND with at least a 4.7F of ceramic capacitance. 12 I Charge Current Programming Input. Connect a resistor from ISET to GND to program the fast charge current. The charge current is programmable from 500mA to 3A. IUSB1 17 I IUSB2 16 I IUSB3 14 I 10 O Power Good Open Drain output. PG is pulled low wehn a valid supply is connected. A valud supply is between VBAT+VSLP and VOVP. The output is high impedance if the supply is not in this range. 21,22 - Ground pin. Connect to the thermal pad (for QFN only) and the ground plane of the circuit. 1 I High Side Bypass Connection. Connect at least 1F of ceramic capacitance from PMID to PGND as close to the PMID and PGND pins as possible. 23, 24 O Inductor Connection. Connect to the switched side of the external inductor. The inductance must be between 1.5H and 2.2H. 6, 7 I System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the output bulk capacitors. Bypass SYS locally with at least 10F of ceramic capacitance. The SYS rail must have at least 20F of total capacitance for stable operation. See Application section for additional details. 5 I Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA compatibility. Pull TS high to VDRV to disable the TS function if unused. See the NTC Monitor section for more details on operation and selecting the resistor values. 15 I Input DPM Programming Input. Connect a resistor divider from IN to GND with VDPM connected to the center tap to program the Input Voltage based Dynamic Power Management (VIN_DPM) threshold. The input current is reduced to maintain the supply voltage at VIN_DPM. See the Input Voltage based Dynamid Power Management section for a detailed explanation. - - There is an internal electrical connection between the exposed thermal pad and the PGND pin of the device. The thermal pad must be connected to the same potential as the PGND pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. PGND pin must be connected to ground at all times. AGND BAT BGATE BOOT CE CHG DRV IN ISET PG PGND PMID SW SYS TS VDPM Thermal PAD DESCRIPTION Analog Ground. Connect to the thermal pad (for QFN only) and the ground plane of the circuit. USB Input Current Limit Programming Inputs. IUSB1, IUSB2 and IUSB3 program the input current limit for the USB input. USB2.0 and USB3.0 current limits are available for easy implementation of these standards. Table 1 shows the settings for these inputs. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 5 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VALUE Pin Voltage (with respect to PGND) MIN MAX IN -1.3 30 BOOT, PMID -0.3 30 SW -0.7 20 BAT -0.3 5 DRV, BGATE, CE, ISET, IUSB1, IUSB2, IUSB3, PG, CHG, SYS, TS -0.3 5.5 -0.3 0.3 AGND BOOT to SW Output Current (Continuous) -0.3 V 5 SW 4.5 SYS, BAT (charging/ discharging) 3.5 Input Current (Continuous) Output Sink Current CHG, PG V A 2.75 A 10 mA Operating free-air temperature -40 85 Junction temperature, TJ -40 125 Storage temperature, Tstg (1) UNIT C 300 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground pin unless otherwise noted. 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIN NOM MAX IN voltage range 4.2 13.5 (1) IN operating voltage range 4.2 14 UNIT V IIN Input current, IN input 2.5 A ISW Output Current from SW, DC 3 A IBAT, ISYS Charging 3 Discharging, using internal battery FET 3 TJ (1) 6 Operating junction temperature range 0 125 A C The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight layout minimizes switching noise. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 6.4 Thermal Information bq24266 THERMAL METRIC (1) RGE (24 PINS) UNIT RJA Junction-to-ambient thermal resistance 32.6 C/W RJC(top) Junction-to-case (top) thermal resistance 30.5 C/W RJB Junction-to-board thermal resistance 3.3 C/W JT Junction-to-top characterization parameter 0.4 C/W JB Junction-to-board characterization parameter 9.3 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 2.6 C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics Circuit of , VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = -40C to 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENTS VUVLO < VIN < VOVP and VIN>VBAT+VSLP PWM switching IIN IBAT_HIZ Supply current for control Battery discharge current in High Impedance mode, (BAT, SW, SYS) 15 mA VUVLO < VIN < VOVP and VIN>VBAT+VSLP PWM NOT switching 6.65 0C< TJ < 85C, VIN = 5V, High-Z Mode 250 0C< TJ < 85C, VBAT = 4.2 V, VIN = 5V, SCL, SDA = 0V or 1.8V, High-Z Mode 15 0C< TJ < 85C, VBAT = 4.2 V, VIN = 0V, SCL, SDA = 0V or 1.8V 80 A A POWER-PATH MANAGEMENT VSYSREG(LO) System Regulation Voltage VBAT < VMINSYS, battery attached VMINSYS + 80mV VMINSYS + 100mV VMINSYS + 120mV V VSYSREG(HI) System Regulation Voltage Battery FET turned off, no charging, VBAT > 3.5V VBATREG +2.2% VBATREG +2.5% VBATREG +2.77% V VMINSYS Minimum System Voltage Regulation Threshold VBAT + VDO(SYS_BAT) < 3.5V 3.44 3.5 3.55 V tDGL(MINSYS_CMP) Deglitch time, VMINSYS comparator rising VBSUP1 Enter supplement mode threshold VBSUP2 8 ms VBAT > VBUVLO VBAT - 20mV V Exit supplement mode threshold VBAT > VBUVLO VBAT - 5mV V ILIM(DISCH) Current Limit, Discharge or Supplement Mode VLIM(BGATE) = VBAT - VSYS 6 A tDGL(SC1) Deglitch Time, OUT Short Circuit during Discharge or Supplement Mode Measured from IBAT = 7A to FET off 250 s tREC(SC1) Recovery time, OUT Short Circuit during Discharge or Supplement Mode 2 s Battery Range for BGATE Operation Copyright (c) 2014-2015, Texas Instruments Incorporated 4 2.5 4.5 Submit Documentation Feedback V 7 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com Electrical Characteristics (continued) Circuit of , VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = -40C to 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 32 47 m BATTERY CHARGER RON(BAT-SYS) VBATREG ICHARGE Internal battery charger MOSFET on-resistance Measured from BAT to SYS, VBAT = 4.2V, High-Z mode Charge Voltage TJ = 25C 4.18 4.2 4.22 V Charge Voltage TJ = 0C to 85C 4.17 4.2 4.23 V Charge Voltage TJ = 0C to 85C, TS WARM 4.03 4.06 4.09 V Voltage Regulation Accuracy TJ = 0C to 125C Fast Charge Current Range VBATSHRT VBAT < VBAT(REG) Fast Charge Current Accuracy 500 mA ICHARGE 1A Programmable Fast Charge Current Factor KISET mA 1200 1260 A CE1=X, CE2=0, 500 mA ICHARGE 1A 1080 1200 1320 A TS COOL, ICHARGE > 1000 mA 570 600 630 A TS COOL, 500 mA ICHARGE 1A 540 600 660 A 2.9 3 3.1 Battery voltage falling Deglitch time for battery short to fastcharge transition VBAT rising or falling Battery short circuit charge current VBAT < VBATSHRT Termination charge current 50mA ITERM 300 mA ITERM 50 mA 50 mA < ITERM < 200 mA ITERM 200 mA tDGL(TERM) Deglitch time for charge termination Both rising and falling, 2-mV over-drive, tRISE, tFALL=100ns VRCH Recharge threshold voltage Below VBATREG tDGL(RCH) Deglitch time VBAT falling below VRCH, tFALL=100ns VDET(SRC1) Battery detection voltage threshold (TE = 1) VDET(SNK) 10% -5% Hysteresis for VBATSHRT VDET(SRC2) 3000 1140 VBATSHRT_HYS Termination charge current accuracy 500 -10% CE1=X, CE2=0, ICHARGE > 1000 mA Battery short circuit threshold ITERM 1.0% ICHARGE > 1000 mA VBATSHRT IBATSHRT -1.0% 33.5 5% mV 1 ms .50 66.5 -30% 30% -15% 15% -15% 10% 32 120 mA % of ICHARGE 10 100 V 100 ms 150 mV 32 ms During current source (Turn IBATSHRT off) VRCH V During current source (Turn IBATSHRT on) VRCH - 200mV V During current sink VBATSHRT V IDETECT Battery detection current before charge done (sink current) Termination enabled (TE = 1) 7 mA tDETECT(SRC) Battery detection time (sourcing current) Termination enabled (TE = 1) 2 s tDETECT(SNK) Battery detection time (sinking Termination enabled (TE = 1) current) 250 ms 8 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 Electrical Characteristics (continued) Circuit of , VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = -40C to 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENT LIMITING IINLIM Input current limiting threshold VIN_DPM Input based DPM threshold range VVDPM Feedback threshold USB charge mode, VIN = 5V, Current pulled from SW Charge mode, programmable via VDPM IINLIM=USB100 90 95 100 IINLIM=USB500 450 475 500 IINLIM=USB150 125 140 150 IINLIM=USB900 800 850 900 IINLIM=1.5A 1425 1500 1575 IINLIM=2.5A 2225 2500 2825 4.2 mA 11.6 V V 1.15 1.2 1.25 4.3 4.8 5.3 V 10 mA IIN = 1A, VIN = 4.2V, IDRV = 10mA 450 mV 0.4 V 1 A 0.4 V VDRV BIAS REGULATOR VDRV Internal bias regulator voltage IDRV DRV Output Current VDO_DRV DRV Dropout Voltage (VIN - VDRV) VIN>5V 0 STATUS OUTPUT (PG, CHG) VOL Low-level output saturation voltage IO = 10 mA, sink current IIH High-level leakage current V PG = V CHG = 5V INPUT PINS (CE1, CE2, IUSB1, IUSB2, IUSB3) VIL Input low threshold VIH Input high threshold RPULLDOWN Copyright (c) 2014-2015, Texas Instruments Incorporated 1.4 V 100 Submit Documentation Feedback k 9 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com Electrical Characteristics (continued) Circuit of , VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = -40C to 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 3.3 3.4 UNIT PROTECTION VUVLO IC active threshold voltage VIN rising VUVLO_HYS IC active hysteresis VIN falling from above VUVLO 3.2 300 VBATUVLO Battery Undervoltage Lockout threshold VBAT falling, VIN>VUVLO 2.4 2.6 V VSLP Sleep-mode entry threshold, VIN-VBAT 2.0 V < VBAT < VBATREG, VIN falling 40 120 mV tDGL(BAT) Deglitch time, BAT above VBATUVLO before SYS starts to rise VSLP_HYS Sleep-mode exit hysteresis VIN rising above VSLP tDGL(VSLP) Deglitch time for supply rising above VSLP+VSLP_HYS Rising voltage, 2-mV over drive, tRISE=100ns VOVP Input supply OVP threshold voltage IN rising, 100mV hysteresis tDGL(BUCK_OVP) Deglitch time, VIN OVP in Buck Mode IN falling below VOVP VBOVP Battery OVP threshold voltage VBAT threshold over VOREG to turn off charger during charge VBOVP_HYS VBOVP hysteresis Lower limit for VBAT falling from above VBOVP tDGL(BOVP) BOVP Deglitch Battery entering/exiting BOVP ICbCLIMIT Cycle-by-cycle current limit VSYS shorted TSHTDWN Thermal trip 0 1.2 40 Thermal regulation threshold 13.6 190 14 1.03 x VBATREG 1.05 x VBATREG 14.4 1.07 x VBATREG ms 4.9 A 150 C 10 C 125 29160 V % of VBATREG 8 4.5 V ms 1 4.1 mV ms 30 Input current begins to cut off Safety Timer Time ms 30 Thermal hysteresis TREG 100 V mV C 32400 35640 s PWM RDSON_Q1 Internal top MOSFET onresistance Measured from IN to SW 80 135 m RDSON_Q2 Internal bottom N-channel MOSFET on-resistance Measured from SW to PGND 80 135 m fOSC Oscillator frequency 1.5 1.65 MHz DMAX Maximum duty cycle DMIN Minimum duty cycle 1.35 95% 0% BATTERY-PACK NTC MONITOR VHOT High temperature threshold VTS falling, 2% VDRV Hysteresis 27.3 30 32.6 %VDRV VWARM Warm temperature threshold VTS falling, 2% VDRV Hysteresis 36.0 38.3 41.2 %VDRV VCOOL Cool temperature threshold VTS rising, 2% VDRV Hysteresis 54.7 56.4 58.1 %VDRV VCOLD Low temperature threshold VTS rising, 2% VDRV Hysteresis 58.2 60 61.8 %VDRV TSOFF TS Disable threshold VTS rising, 4% VDRV Hysteresis 80 85 %VDRV tDGL(TS) Deglitch time on TS change Applies to VHOT, VWARM, VCOOL and VCOLD 10 Submit Documentation Feedback 50 ms Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 Electrical Characteristics (continued) Circuit of , VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = -40C to 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 100 A 4.5 V 5.2 V OTG BOOST SUPPLY Quiescent current during boost mode (BAT pin) 3.3V<VBAT<4.5V, no switching Battery voltage range for specified boost operation VBAT falling 3.3 VIN_BOOST Boost output voltage (to pin VBUS) 3.3V<VBAT<4.5V over line and load 4.95 IBO Maximum output current for boost 3.3V<VBAT<4.5V IBLIMIT Cycle by cycle current limit for boost (measured at low-side FET) 3.3V<VBAT<4.5V VBOOSTOVP Over voltage protection threshold for boost (IN pin) Signals fault and exits boost mode tDGL(BOOST_OVP) Deglitch Time, VIN OVP in Boost Mode VBURST(ENT) Upper VIN voltage threshold to enter burst mode (stop switching) 5.1 5.2 5.3 V VBURST(EXIT) Lower VBUS voltage threshold to exit burst mode (start switching) 4.9 5 5.1 V IQBAT_ BOOST BOOST_ILIM = 1 1000 BOOST_ILIM = 0 500 5.05 mA BOOST_ILIM = 1 4 BOOST_ILIM = 0 2 5.8 6 A 6.2 V 170 s 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER fOSC Oscillator frequency DMAX Maximum duty cycle DMIN Minimum duty cycle Copyright (c) 2014-2015, Texas Instruments Incorporated TEST CONDITIONS MIN TYP MAX UNIT 1.35 1.5 1.65 Mhz 95% 0% Submit Documentation Feedback 11 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com 6.7 Typical Characteristics 10 95 6 90 4 2 Efficiency (%) Charge Current Accuracy (%) 8 0 -2 TA=25C -4 85 80 TA=0C VIN=5V -6 TA=85C -8 TA=60C -10 2.9 3.1 3.3 3.5 3.7 3.9 VBAT (V) 4.1 75 4.3 70 4.5 0 Figure 1. Charge Current vs Battery Voltage 1 1.5 2 Load Current (A) 2.5 3 Figure 2. Efficiency vs Output Current 0.0 90 -0.5 VBAT Accuracy (%) 100 80 Efficiency (%) 0.5 70 60 -1.0 -1.5 -2.0 TA=25C 50 TA=60C TA=0C -2.5 40 2 2.5 3 3.5 4 -3.0 4.5 0 VBAT (V) 16 700 14 600 12 500 Input Current (A) Input Current - mA Figure 3. Efficiency vs Battery Voltage 10 8 6 4 1 1.5 IBAT (A) Figure 4. VBAT Accuracy vs IBAT - 4.2 VBAT 2 400 300 200 Input Current (A) 100 2 0 0 -100 -2 0 2 4 6 8 10 Input Voltage - V 12 14 Figure 5. Input IQ - No Battery, No System 12 0.5 Submit Documentation Feedback 16 3 5 7 9 11 13 15 Input Voltage (V) Figure 6. Input IQ with Hi-Z Enabled Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 7 Detailed Description 7.1 Overview The bq24266 is a highly integrated single cell Li-Ion battery charger and system power path management devices targeted for space-limited, portable applications with high capacity batteries. The single cell charger has a single input that supports operation from either a USB port or wall adapter supply for a versatile solution. The power path management feature allows the bq24266 to power the system from a high efficiency DC to DC converter while simultaneously and independently charging the battery. The charger monitors the battery current at all times and reduces the charge current when the system load requires current above the input current limit or the adapter cannot support the required load, causing the adapter voltage to fall (VIN_DPM). This allows for proper charge termination and timer operation. The system voltage is regulated to the battery voltage but will not drop below 3.5V (VMINSYS). This minimum system voltage support enables the system to run with a defective or absent battery pack and enables instant system turn-on even with a totally discharged battery or no battery. The powerpath management architecture also permits the battery to supplement the system current requirements when the adapter cannot deliver the peak system currents. The power-path feature coupled with VIN-DPM, enables the use of many adapters with no hardware change. The charge parameters are programmable using the ISET pin. To support USB OTG applications, the bq24266 is configurable to boost the battery voltage to 5V at the input. In this mode, the bq24266 supplies up to 1A and operates with battery voltages down to 3.3V. The battery is charged using a standard Li-Ion charge profile with three phases: precharge, constant current and constant voltage. In all charge phases, an internal control loop monitors the IC junction temperature and reduces the input current to prevent the junction temperature from rising above 125C. With the bq24266 a voltagebased, JEITA compatible battery pack thermistor monitoring input (TS) is included that monitors battery temperature and automatically changes charge parameters to prevent the battery from charging outside of its safe temperature range. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 13 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com 7.2 Functional Block Diagram PMID 4.8-V Reference DRV IN 5A + BOOT CbC Current Limit IINLIM Q1 DC-DC CONVERTER PWM LOGIC, COMPENSATION AND BATTERY FET CONTROL VINDPM VDPM VSYS(REG) IBAT(REG) VBAT(REG) SW Q2 DIE Temp Regulation PGND OVP Comparator VIN + VINOVP Termination Reference Sleep Comparator + VIN SYS VSUPPLY References + Q3 IBAT Termination Comparator VBAT+VSLP BAT Recharge Comparator Start Recharge Cycle IUSB1 IUSB2 + VBATREG 0.12V VBAT Hi-Impedance Mode VSYSREG Comparator Input ILIM Control Enable Linear Charge IUSB3 + BGATE VSYS VMINSYS VBATSC Comparator Enable IBATSHRT + VBAT VBATSHRT ISET Supplement Comparator VSYS + VBAT VBSUP CE Charge Enable VDRV VBOVP Comparator + VBAT VBATOVP TSOFF Disable TS Junction + + DISABLE TS COLD bq24266 Only PG + 1C/0.5C TS COOL + VBATREG 0.14V TS WARM CHG DISABLE CHARGE CONTROLLER w/ Timer + bq24266 TS HOT TS Figure 7. Block Diagram in Charging Mode 14 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 Functional Block Diagram (continued) PMID 4.8-V Reference DRV IN Not used in Boost Mode VDPM BOOT VBOOST Amp + Q1 VIN_BOOST VBURST_ENT Burst Mode Enter Comparator DC-DC Low Side Current CONVERTER Limit Comparator PWM LOGIC AND COMPENSATION IBLIMIT + VBURST_EXT SW + + VDRV Q2 Burst Mode Exit Comparator PGND Boost Short Circuit Comparator VBOOSTSHRT + VBOOSTOVP + VBOOST OVP Comparator VBAT SYS VBIAS Battery Short Circuit Battery SC Comparator + ILIM(SUPP) IUSB3 IUSB2 BAT Mode Decode IUSB1 CHG BGATE Digital Control PG TS Figure 8. Block Diagram in Boost Mode Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 15 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com 7.3 Feature Description The bq24266 is a highly integrated single cell Li-Ion battery charger and system power path management devices that supports operation from either a USB port or wall adapter supply. The power path feature allows the bq24266 to power the system from a high efficiency DC to DC converter while simultaneously and independently charging the battery. The power path also permits the battery to supplement the system current requirements when the adapter cannot. Many features are programmable using dedicated pins. To support USB OTG applications, the bq24266 is configurable to boost the battery voltage to 5V and supply up to 1A at the input. The battery is charged with three phases: precharge, constant current and constant voltage. Thermal regulation prevents the die temperature from exceeding 125C. With the bq24266, a JEITA compatible battery pack thermistor monitoring input (TS) is included to prevent the battery from charging outside of its safe temperature range. 7.4 Device Functional Modes 7.4.1 High Impedance Mode High Impedance mode (Hi-Z mode) is the low quiescent current state for the bq24266. During Hi-Z mode, the buck converter is off, and the battery FET and BGATE are on. SYS is powered by BAT. The bq24266 is in Hi-Z mode when VIN < VUVLO or the IUSB1, IUSB2, and IUSB3 pins are all driven high. Hi-Z mode resets the safety timer. When exiting Hi-Z mode, charging resumes in approximately 110ms. 7.4.2 Battery Only Connected When the battery is connected with no input source, the battery FET turns on, connecting BAT and SYS, after the battery voltage rises above VBATUVLO and the deglitch time, tDGL(BAT). In this mode, the current is not regulated; however, there is a short circuit current limit. If the short circuit limit (ILIM(DISCHG)) is reached for the deglitch time (tDGL(SC)), the battery FET is turned off for the recovery time (tREC(SC)). After the recovery time, the battery FET is turned on to test and see if the short has been removed. If it has not, the FET turns off and the process repeats until the short is removed. This process protects the internal FET from over current. If an external FET is used for discharge, the body diode prevents the load on SYS from being disconnected from the battery and tDGL(BAT) is not applicable. 7.4.3 Input Connected 7.4.3.1 Input Voltage Protection in Charge Mode 7.4.3.1.1 Sleep Mode The bq24266 enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entry threshold, VBAT+VSLP, and VIN is higher than the undervoltage lockout threshold, VUVLO. In sleep mode, the input is isolated from the battery. This feature prevents draining the battery during the absence of VIN. When VIN < VBAT+ VSLP, the bq24266 turns off the PWM converter and turns the battery FET and BGATE on. Once VIN > VBAT+ VSLP, the device initiates a new charge cycle. 7.4.3.1.2 Input Voltage Based Dynamic Power Management (VIN-DPM) During normal charging process, if the input power source is not able to support the programmed or default charging current, the supply voltage deceases. Also, at higher currents, large input line impedances may cause the voltage at the device to droop. Once the supply drops to VIN_DPM (default 4.2V), the charge current limit is reduced to prevent the further drop of the supply. When the IC enters this mode, the charge current is lower than the set value. This feature ensures IC compatibility with adapters with different current capabilities without a hardware change. Figure 9 shows the VIN-DPM behavior to a current limited source. In this figure the input source has a 2A current limit and the device is charging at 1A. A 2.5A load transient then occurs on VSYS causing the adapter to hit its current limit and collapse, while VSYS goes from VSYSREG(LO) to VMINSYS. The safety timer is extended while VIN-DPM is active. Additionally, termination is disabled. The VINDPM threshold for the adapter modes (1.5A and 2.5A) is set using a resistor divider with VDPM connected to the center tap. Select 10k for the bottom resistor. The top resistor is selected using equation Equation 1. Where VIN_DPM is the desired VIN_DPM threshold and VDPM is the regulation threshold at the pin specified in the Electrical Characteristics table. 16 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 Device Functional Modes (continued) RTOP = 10kW VIN_DPM-VDPM VDPM (1) . VIN 1V/div Input voltage regulated to VIN_DPM (5V Offset) Input current limit reduced to avoid crashing adapter 2A/div IIN 500mV/div VSYS (3.6V Offset) IBAT Normal Charging (1A) SYS enters supplement mode to ensure SYS load is supported SYS load removed, normal charging resumes 2A/div 2A/div ISYS 800us/div Figure 9. bq24266 VIN-DPM 7.4.3.1.3 Input Overvoltage Protection The built-in input overvoltage protection protects the bq24266 and downstream components connected to SYS and/or BAT against damage from overvoltage on the input supply (Voltage from VIN to PGND). When VIN > VOVP, the bq24266 turns off the PWM converter immediately. After the deglitch time tDGL(BUCK_OVP), an OVP fault is determined to exist. During the OVP fault the bq24266 turns the battery FET and BGATE on. Once the OVP fault is removed, the device returns to normal operation. The OVP threshold is 14V for operation from standard adapters and from 12V sources. 7.4.3.2 Charge Profile When a valid input source is connected (VIN>VUVLO and VBAT+VSLP<VIN<VOVP), charging is enabled. The charge current, ICHARGE, is set using the ISET pin by connecting a resistor form ISET to GND. The current is programmable from 500mA to 3A using Equation 2, where ICHARGE is in Amperes, and KISET is the value specified in the Electrical Characteristics table. K RCHARGE = ISET RISET (2) The bq24266 supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. Charging is done through the internal battery MOSFET. There are 6 loops that influence the charge current; constant current loop (CC), constant voltage loop (CV), thermal regulation loop, minimum system voltage loop (MINSYS), input current limit and VIN-DPM. During the charging process, all six loops are enabled and the one that is dominant takes control. The minimum system output feature regulates the system voltage to VSYSREG(LO), so that startup is enabled even for a missing or deeply discharged battery. Figure 10 shows a typical charge profile including the minimum system output voltage feature. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 17 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com Device Functional Modes (continued) Precharge Phase Current Regulation Phase Voltage Regulation Phase Regulation Voltage Regulation Current System Voltage VSYS (3.6V) VBATSHORT (3 V) Battery Voltage Charge Current Termination IBATSHORT 50mA Linear Charge to Close Pack Protector Linear Charge to Maintain Minimum System Voltage Battery FET (Q3) is ON Battery FET is OFF Figure 10. Typical Charging Profile of bq24266 7.4.4 Battery Charging Process When the battery is deeply discharged or shorted, the bq24266 applies a IBATSHRT current to close the battery protector switch and bring the battery voltage up to acceptable charging levels. During this time, the battery FET is off and the system output is regulated to VSYSREG(LO). Once the battery rises above VBATSHRT, the charge current is regulated to the value set by ISET. The battery FET is linearly regulated to maintain the system voltage at VSYSREG(LO). Under normal conditions, the time spent in this region is a very short percentage of the total charging time, so the linear regulation of the charge current does not affect the overall charging efficiency for very long. If the die temperature does heat up, the thermal regulation loop reduces the input current to maintain a die temperature at 125C. If the current limit for the SYS output is reached (limited by the input current limit, VINDPM, or 100% duty cycle), the SYS output drops to the VMINSYS output voltage. When this happens, the charge current is reduced to ensure the system is supplied with all the current that is needed while maintaining the minimum system voltage. If the charge current is reduced to 0mA, pulling further current from SYS causes the output to fall to the battery voltage and enter supplement mode (see the "Dynamic Power Path Management" section for more details). 18 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 Device Functional Modes (continued) Once the battery is charged enough that the system voltage rises above VSYSREG(LO) (approximately 3.5V), the battery FET is turned on fully and the battery is charged with the full programmed charge current set by ISET. The charge current is regulated to ICHARGE until the voltage between BAT and PGND reaches the regulation voltage. The voltage between BAT and PGND is regulated to VBATREG (CV mode) while the charge current naturally tapers down as shown in Figure 10. During CV mode, the SYS output remains connected to the battery. The impedance of the battery FET is increased to 4x of the fully on value when IBAT falls below ~350mA to provide increased accuracy during termination. This will show a small rise in the SYS voltage when the RDS(ON) increases below ~350mA. Once the charge current tapers down to the termination threshold, ITERM, and the battery voltage is above the recharge threshold, the bq24266 terminates charge, turns off the battery charging FET and enters battery detection (see Battery Detection section for more details). The system output is regulated to the VSYSREG(HI) and supports the full current available from the input. The battery supplement mode is available to supply any SYS load that cannot be supported by the input source (see the Dynamic Power Path Management section for more details). The termination current level is set to 10% of the charge current. Termination is disabled when any loop is active other than CC or CV. This includes VINDPM, input current limit, or thermal regulation. Termination is also disabled during TS warm/cool conditions. A charge cycle is initiated when one of the following conditions is detected: 1. The battery voltage falls below the VBATREG-VRCH threshold. 2. IN Power-on reset (POR) 3. Charge disabled then enabled using CE 4. IUSB toggeld from high impedance to any charge state 7.4.5 Charge Time Optimizer The CC to CV transition is enhanced in the bq24266 architecture. The "knee" between CC and CV is very sharp. This enables the charger to remain in CC mode as long as possible before beginning to taper the charge current (CV mode). This provides a decrease in charge time as compared to older topologies. 7.4.6 Battery Detection When termination conditions are met, a battery detection cycle is started. During battery detection, IDETECT is pulled from VBAT for tDETECT(SNK) to verify there is a battery. If the battery voltage remains above VDETECT for the full duration of tDETECT(SNK), a battery is determined to present and the IC enters "Charge Done". If VBAT falls below VDETECT, battery detection continues. The next cycle of battery detection, the bq24266 turns on IBATSHRT for tDETECT(SRC). If VBAT rises to VDET(SRC1), the current source is turned off. In order to keep VBAT high enough to close the battery protector, the current source turns on if VBAT falls to VDET(SRC2). The source cycle continues for tDETECT(SRC). After tDETECT(SRC), the battery detection continues through another current sink cycle. Battery detection continues until charge is disabled, the bq24266 enters high-z mode or a battery is detected. Once a battery is detected, a new charge cycle begins. With no battery connected, the BAT output will transition from VRCH to PGND with a high period of tDETECT(SRC) and a low period of tDETECT(SNK). See Figure 16 in the Application Curves section. 7.4.7 Battery Overvoltage Protection (BOVP) If the battery is ever above the battery OVP threshold (VBOVP), the battery OVP circuit shuts the PWM converter off and the battery FET is turned on to discharge the battery to safe operating levels. In this condition, the VBATREG is reset and may be below the battery voltage. This state can be entered when TS WARM conditions decrease the VBATREG to less than the battery voltage. The battery OVP condition is cleared when the battery voltage falls below the hysteresis of VBOVP by the battery discharging. When a battery OVP event exists for tDGL(BOVP), the bq24266 turns the battery FET and BGATE on. 7.4.8 Dynamic Power Path Management The bq24266 features a SYS output that powers the external system load connected to the battery. This output is active whenever a valid source is connected to IN or BAT. When VSYS > VSYSREG(LO), the SYS output is connected to VBAT. If the battery voltage falls to VMINSYS, VSYS is regulated to the VSYSREG(LO) threshold to maintain the system output even with a deeply discharged or absent battery. In this mode, the SYS output voltage is regulated by the buck converter and the battery FET is linearly regulated to regulate the charge current Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 19 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com Device Functional Modes (continued) into the battery. The current from the supply is shared between charging the battery and powering the system load at SYS. The dynamic power path management (DPPM) circuitry of the bq24266 monitors the current limits continuously and if the SYS voltage falls to the VMINSYS threshold, it adjusts charge current to maintain the minimum system voltage and supply the load on SYS. If the charge current is reduced to zero and the load increases further, the bq24266 enters battery supplement mode. During supplement mode, the battery FET is turned on and VBAT = VSYS while the battery supplements the system load. 2000mA 1800mA ISYS 800mA 0mA 1500mA IIN ~850mA 0mA 1A IBAT 0mA -200mA 3.6V 3.5V DPPM loop active VSYS ~3.1V Supplement Mode Figure 11. Example DPPM Response (VSupply = 5V, VBAT = 3.1V, 1.5A Input Current Limit) 7.4.9 Battery Discharge FET (BGATE) The bq24266 contains a MOSFET driver to drive an external discharge FET between the battery and the system output. This external FET provides a low impedance path for supplying the system from the battery. Connect BGATE to the gate of the external discharge P-channel MOSFET. BGATE is on (low) under the following conditions: 1. No input supply connected. 2. IUSB1, IUSB2, IUSB3 pins = high 7.4.10 IUSB1, IUSB2, and IUSB3 Input The bq24266 has three inputs that configure the input current limit and VINDPM thresholds. These input are also used to enable the USB OTG Boost function. The bq24266 incorporates all of the necessary input current limits to support USB2.0 and USB3.0 standards, as well as 1.5A to support wall adapters. Driving IUSB1, IUSB2, and IUSB3 all high places the bq24266 in Hi-Z mode where the buck converter is shutdown regardless if an input is connected to IN. Table 1 shows the configuration for IUSB1, IUSB2, and IUSB3. 20 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 Device Functional Modes (continued) Table 1. IUSB1, IUSB2, and IUSB3 Configurations IUSB3 IUSB2 IUSB1 MODE INPUT CURRENT LIMIT VINDPM THRESHOLD 0 0 0 Charger 100mA 4.28V 0 0 1 Charger 500mA 4.44V 0 1 0 Charger 1.5A External 0 1 1 Boost --- --- 1 0 0 Charger 150mA 4.28V 1 0 1 Charger 900mA 4.44V 1 1 0 Charger 2500mA External 1 1 1 High Impedance --- --- 7.4.11 Safety Timer in Charge Mode At the beginning of the charging process, the bq24266 starts the safety timer. This timer is active during the entire charging process. If charging has not terminated before the safety timer expires, the IC enters suspend mode where charging is disabled. CE, or power must be toggled in order to clear the safety timer fault. The bq24266 also contains a 2X_TIMER that doubles the safety timer to prevent premature safety timer expiration when the charge current is reduced by a load on SYS or a NTC condition. When 2X_TIMER is active, the timer runs at half speed when any loop is active other than CC or CV. This includes VINDPM, input current limit, or thermal regulation. The timer also runs at half speed during TS warm/cool conditions. 7.4.12 LDO Output (DRV) The bq24266 contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other circuitry. Additionally, DRV supplies up to 10mA external loads to power the PG or CHG LED or the USB transceiver circuitry. The maximum value of the DRV output is 5.3V so it ideal to protect voltage sensitive USB circuits. The LDO is on whenever a supply is connected to the input of the bq24266. The DRV is disabled under the following conditions: 1. VSUPPLY < UVLO 2. VSUPPLY < VBAT + VSLP 3. Thermal Shutdown 7.4.13 External NTC Monitoring (TS) The bq24266 provides a flexible, voltage based TS input for monitoring the battery pack NTC thermistor. The bq24266 implements the full JEITA standard. The voltage at TS is monitored to determine that the battery is at a safe temperature during charging. The JEITA specification is shown in Figure 12. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 21 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com 1.0 C Charging Current 0.5 C Portion of spec not covered by TS Implementation on bq2426x 4.25 V VBAT 4.15 V 4.1 V T1 (0C) T2 (10C) T3 T4 (45C) (50C) Cold Cool Warm T5 (60C) Hot Figure 12. Charge Current During TS Conditions To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold (TNTC < 0C), the cool battery threshold (0C < TNTC < 10C), the warm battery threshold (45C < TNTC < 60C) and the hot battery threshold (TNTC > 60C). These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT thresholds in the EC table. Charging is suspended and timers are suspended when VTS < VHOT or VTS > VCOLD. When VCOOL < VTS < VCOLD, the charging current is reduced to half of the programmed charge current. When VHOT < VTS < VWARM, the battery regulation voltage is reduced to 4.06V from the 4.2V regulation threshold. The TS function is disabled by connecting TS directly to DRV (VTS > VTSOFF). The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS connected to the center tap to set the threshold. The connections are shown in Figure 13. The resistor values are calculated using the following equations: e 1 1 u VDRV RCOLD RHOT e u VCOLD VHOT u e RLO = eV u e V u RHOT e DRV - 1u - RCOLD e DRV - 1u e VHOT u e VCOLD u (3) VDRV -1 VCOLD RHI = 1 1 + RLO RCOLD (4) Where: VCOLD = 0.60 x VDRV VHOT = 0.30 x VDRV RLO RHI 0.564 RCOOL = RLO - RLO 0.564 - RHI 0.564 22 Submit Documentation Feedback (5) Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 RWARM = RLO RHI 0.383 RLO - RLO 0.383 - RHI 0.383 (6) Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold temperature. The WARM and COOL thresholds are not independently programmable. The COOL and WARM NTC resistances for a selected resistor divider are calculated using Equation 5 and Equation 6. DISABLE VBATREG - 140 mV 1 x Charge/ 0.5 x Charge VDRV TS COLD TS COOL + + TS WARM + VDRV TS HOT RHI + TS TEMP PACK+ bq24266 RLO PACK- Figure 13. TS Circuit 7.4.14 Thermal Regulation and Protection During the charging process, to prevent overheating in the chip, bq24266 monitors the junction temperature, TJ, of the die and reduces the input current once TJ reaches the thermal regulation threshold, TREG. The input current is reduced to zero when the junction temperature increases about 10C above TREG. Once the input current is reduced to 0, the system current is reduced while the battery supplements the load to supply the system. When the input current is completely reduced to 0 and TJ>125C, this is may cause a thermal shutdown of the bq24266 if the die temperature rises too high. At any state, if TJ exceeds TSHTDWN, bq24266 stops charging and disables the buck converter. During thermal shutdown mode, PWM is turned off and all timers are suspended. The charge cycle resumes when TJ falls below TSHTDWN by approximately 10C. 7.4.15 Status Outputs (CHG, PG) The CHG and PG outputs are used to indicate operating conditions for the bq24266. The PG output indicates that a valid input source is connected to VIN. PG is low when (VBAT + VSLP) < VIN < VOVP. When there is no supply connected to the input within this range, PG is high impedance. Table 2 illustates the PG behavior under different conditions. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 23 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com Table 2. PG Behavior CHARGE STATE PG BEHAVIOR VSUPPLY < VUVLO High Impedance VSUPPLY < (VBAT + VSLP) High Impedance (VBAT + VSLP) < VIN < VOVP Low VSUPPLY > VOVP High Impedance The CHG output indicates new charge cycles. When a new charge cycle is initiated by CE or toggling the input power, CHG goes low and remains low until termination. After termination, CHG remains high impedance until a new charge cycle is initiated or the battery is removed/re-inserted. CHG does not go low during recharge cycles. Table 3 illustrates the CHG behavior under different conditions. Connect PG and CHG to the DRV output through an LED for visual indication, or connect through a 100k pullup to the required logic rail for host indication. Table 3. CHG Behavior CHARGE STATE CHG BEHAVIOR Charge in Progress Charge suspended by /CE or TS function Low (first charge cycle) High-Impedance (recharge cycles) Charging Suspended by Thermal Loop Charging Done Recharge Cycle after Termination Timer Fault High-Impedance No Valid Supply VIN > VOVP or VIN < (VBAT + VSLP) No Battery Present 7.4.16 Boost Mode Operation When the IUSB inputs are configured in Boost Mode (IUSB3 = 0, IUSB2 = IUSB1 = 1), the device operates in boost mode and delivers 5V to IN to supply USB OTG devices connected to the USB connector. 7.4.16.1 PWM Controller in Boost Mode Similar to charge mode operation, in boost mode the IC switches at 1.5MHz to regulate the voltage at IN to 5V. The voltage control loop is internally compensated to provide enough phase margin for stable operation with the the battery from 3.3V to 4.2V up to 1A. In boost mode, the cycle-by-cycle current limit is set to 4A to provide protection against short circuit conditions. If the cycle-by-cycle current limit is active for 8ms, an overload condition is detected and the device exits boost mode, and signals an over-current fault. Additionally, discharge current limit (ILIM(DISCHG)) is active to protect the battery from overload. Synchronous operation and burst mode are used to maximize efficiency over the full load range. The bq24266 will not enter boost mode unless the IN voltage is less than the UVLO. When the boost function is enabled, the bq24266 enters a linear mode to bring IN up to the battery voltage. Once VIN > (VBAT - 1V), the bq24266 begins switching and regulates IN up to 5V. If VIN does not rise to within 1V of VBAT within 8ms, an over-current event is detected and boost mode is exited. 7.4.16.2 Burst Mode during Light Load In boost mode, the IC operates using burst mode to improve light load efficiency and reduce power loss. During boost mode, the PWM converter is turned off when the device reaches minimum duty cycle and the output voltage rises to VBURST(ENT) threshold. This corresponds to approximately a 75mA inductor current. The converter then restarts when VIN falls to VBURST(EXT). See Figure 22 in the Typical Operating Characteristics for an example waveform. 24 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com 7.4.16.3 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 CHG and PG During Boost Mode During boost mode, the CHG and PG outputs are high impedance. 7.4.16.4 Protection in Boost Mode 7.4.16.4.1 Output Over-Voltage Protection The bq24266 contains integrated over-voltage protection on the IN pin. During boost mode, if an over-voltage condition is detected (VIN > VBOOSTOVP), after deglitch tDGL(BOOST_OVP), the IC turns off the PWM converter unitl the IUSB pins are toggled. The converter does not restart when VIN drops to the normal level until the IUSB pins are toggled. 7.4.16.4.2 Output Over-Current Protection The bq24266 contains over current protection to prevent the device and battery damage when IN is overloaded. When an over-current condition occurs, the cycle-by-cycle current limit limits the current from the battery to the load. If the overload condition lasts for 8ms, the overload fault is detected. When an overload condition is detected, the bq24266 turns off the PWM converter. The boost operation starts only after the fault is cleared and the IUSB pins are toggled. 7.4.16.4.3 Battery Voltage Protection During boost mode, when the battery voltage is below the minimum battery voltage threshold, VBATUVLO, the IC turns off the PWM converter. Once the battery voltage returns to the acceptable level, the boost starts only after the IUSB pins are toggled. Proper operation below 3.3V down to the VBATUVLOis not specified. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 25 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com 8 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The bq24266EVM-609 evaluation module (EVM) is a complete charger module for evaluating the bq24266. The application curves were taken using the bq24266EVM-609 (SLUUB40). See Related Documentation . The bq24266EVM is shipped with the bq24266 populated, For the bq24266, the TS input is available and the resistors are chosen using Equation 3 and Equation 4. 8.2 Typical Applications 8.2.1 Typical Application, External Discharge FET IN VBUS D+ 1.5H DGND SW 4.7F >10F 0.033F PGND 10F System Load BOOT PMID SYS 1F 26.7kY BGATE VDPM BAT 10kY VDRV 1F HOST 5.62kY PACK+ TEMP DRV TS 2.2F bq24266 12.4kY ISET PACK- 400Y PG 1.5kY GPIO CHG 1.5kY CE GPIO IUSB1 GPIO IUSB2 GPIO IUSB3 GPIO Figure 14. bq24266 Typical Application Circuit 26 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 Typical Applications (continued) 8.2.1.1 Design Requirements Table 4. Design Requirements DESIGN PARAMATER EXAMPLE VALUE Input Voltage Range 4.75 V to 5.25 V nominal, withstand 28 V Input Current Limit 2500 mA Input DPM Threshold 4.2 V (Externally Set) Fast Charge Current 3000 mA Battery Charge Voltage 4.2 V Termination Current 300 mA 8.2.1.2 Detailed Design Procedure The parameters are configurable using the EVM jumper options as described in the Users Manual. The typical application for the bq24266EVM is shown in Figure 14. The default IUSB settings are for 2.5A input current limit and external VINDPM threshold, which is IUSB3 = 1, IUSB = 2 = 1, IUSB1 = 0. The VDPM resistors were selected using Equation 1. The charge current, ICHARGE, was set to be 3A using Equation 2. The typical application circuit shows the minimum capacitance requirements for each pin. Options for sizing the inductor outside the 1.5 H recommended value and additional SYS pin capacitance are explained in the next section. The resistors on PG and CHG are sized per each LED's current requirements. The TS resistor divider for configuring the TS function to work with the battery's specific thermistor can be computed from Equation 3 and Equation 4. The external battery FET is optional. 8.2.1.2.1 Output Inductor and Capacitor Selection Guidelines When selecting an inductor, several attributes must be examined to find the right part for the application. First, the inductance value should be selected. The bq24266 is designed to work with 1.5H to 2.2H inductors. The chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some efficiency gain is reached using the 2.2H inductor, however, due to the physical size of the inductor, this may not be a viable option. The 1.5H inductor provides a good tradeoff between size and efficiency. Once the inductance has been selected, the peak current must be calculated in order to choose the current rating of the inductor. Use Equation 7 to calculate the peak current. ae % o IPEAK = ILOAD(MAX) c 1 + RIPPPLE / 2 e o (7) The inductor selected must have a saturation current rating greater than or equal to the calculated IPEAK. Due to the high currents possible with the bq24266, a thermal analysis must also be done for the inductor. Many inductors have 40C temperature rise rating. This is the DC current that will cause a 40C temperature rise above the ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted for the duty cycle of the load transients. For example, if the application requires a 1.5A DC load with peaks at 2.5A 20% of the time, a 40C temperature rise current must be greater than 1.7A: ITEMPRISE = ILOAD + D x (IPEAK - ILOAD) = 1.5 A + 0.2 x (2.5 A - 1.5 A) = 1.7 A (8) The internal loop compensation of the bq24266 is designed to be stable with 10F to 150F of local capacitance but requires at least 20F total capacitance on the SYS rail (10F local + 10F distributed). The capacitance on the SYS rail can be higher than 150F if distributed amongst the rail. To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 10F and 47F is recommended for local bypass to SYS. If greater than 100F effective capacitance is on the SYS rail, place at least 10F bypass on the BAT pin. Pay special attention to the DC bias characteristics of ceramic capacitors. For small case sizes, the capacitance can be derated as high as 70% at workable voltages. All capacitances specified in this datasheet are effective capacitance, not capacitor value. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 27 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com 8.2.2 Application Curves 28 Figure 15. Startup With No Battery Figure 16. Battery Detection Figure 17. Battery Removal Figure 18. VSYS Transient Without Supplement Mode Figure 19. VSYS Transient With Supplement Mode Figure 20. VSYS Transient With Supplement Mode Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 Figure 21. Boost Startup No Load Figure 23. Boost Startup 1A Load Figure 22. Boost Burst Mode During Light Load Figure 24. Boost Transient Response VBAT = 3.6 V VBATREG = 4.2 V ICHG = 2 A ILIM = 0.5 A ISYS = 0A VDPM = 4.36 V Figure 25. Input OVP Event with CHG Copyright (c) 2014-2015, Texas Instruments Incorporated Figure 26. Startup, 4.2V Submit Documentation Feedback 29 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com VIN = 5 V VIN = 5 V Figure 27. USB Inrush Current, IUSB3 = 0, IUSB2 = 0, IUSB1 = 1 Figure 28. Default Startup, IUSB3 = 0, IUSB2 = 0, IUSB1 = 1 VIN = 12 V Figure 29. Default Startup, IUSB3 = 1, IUSB2 = 1, IUSB1 = 0 30 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 9 Power Supply Recommendations 9.1 Requirements for SYS Output In order to provide an output voltage on SYS, the bq24266 requires either a power supply between 4.2 and 14 V with at least 100 mA current rating connected to IN; or, a single-cell Li-Ion battery with voltage > VBATUVLO connected to BAT. The source current rating needs to be at least 2.5 A in order for the buck converter of the charger to provide maximum output power to SYS. 9.2 Requirements for Charging In order for charging to occur the source voltage measured at the IN pins of the IC, factoring in cable/trace losses from the source, must be greater than the VINDPM threshold, but less than the maximum values shown above. The current rating of the source must be higher than the buck converter needs to provide the load on SYS. For charging at a desired charge current of ICHRG, VIN x IIN x > VSYS x (ISYS+ ICHRG) where is the efficiency estimate from Figure 2 or Figure 3 and VSYS = VBAT when VBAT charges above VMINSYS. The charger limits IIN to the current limit setting of that input. With ISYS = 0 A, the charger consumes maximum power at the end of CC mode, when the voltage at the BAT pin is near VBATREG but ICHRG has not started to taper off toward ITERM. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 31 bq24266 SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 www.ti.com 10 Layout 10.1 Layout Guidelines The following provides some guidelines: * Place 1F input capacitor as close to PMID pin and PGND pin as possible to make high frequency current loop area as small as possible. * Connect the GND of the PMID and IN caps as close as possible. * Place 4.7F input capacitor as close to IN pin and PGND pin as possible to make high frequency current loop area as small as possible. * The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the PGND pin. * Place all decoupling capacitors close to their respective IC pin and as close as to PGND as possible. Do not place components such that routing interrupts power stage currents. All small control signals should be routed away from the high current paths. * The PCB should have a ground plane (return) connected directly to the return of all components through vias. Two vias per capacitor for power-stage capacitors and one via per capacitor for small-signal components. It is also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noisecoupling and ground-bounce issues. A single ground plane for this design gives good results. * The high-current charge paths into IN, BAT, SYS and from the SW pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the ground plane to return current through the internal low-side FET. * For high-current applications, the balls for the power paths should be connected to as much copper in the board as possible. This allows better thermal performance as the board pulls heat away from the IC. 10.2 Layout Example It is important to pay special attention to the PCB layout. Figure 30 provides a sample layout for the high current paths of the bq24266RGE. PGND SW PMID PMID and IN Cap Gnds BOOT Close together SYS Cap Close to SYS Pins IN Cap Close to IN Pin BAT Cap Thermal Close to Vias connect BAT Pins To GND Figure 30. Recommended bq24266 PCB Layout for QFN Package spacer 32 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated bq24266 www.ti.com SLUSBY5G - JUNE 2014 - REVISED DECEMBER 2015 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation User's Guide for QFN Packaged bq24265, bq24266, and bq24267 3-A Battery Charger Evaluation Module, SLUUB40 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback 33 PACKAGE OPTION ADDENDUM www.ti.com 2-Nov-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) BQ24266RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ 24266 BQ24266RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ 24266 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 2-Nov-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Nov-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ24266RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24266RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Nov-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24266RGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ24266RGET VQFN RGE 24 250 210.0 185.0 35.0 Pack Materials-Page 2 GENERIC PACKAGE VIEW RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204104/H PACKAGE OUTLINE VQFN - 1 mm max height RGE0024H PLASTIC QUAD FLATPACK- NO LEAD A 4.1 3.9 B 4.1 3.9 PIN 1 INDEX AREA 1 MAX C SEATING PLANE 0.05 0.00 0.08 C (0.2) TYP 2X 2.5 12 7 20X 0.5 6 13 25 2X 2.5 SYMM 1 PIN 1 ID (OPTIONAL) 18 24X 0.30 0.18 24 19 SYMM 24X 0.48 0.28 0.1 0.05 C A B C 4219016 / A 08/2017 NOTES: 1. 2. 3. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. This drawing is subject to change without notice. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT VQFN - 1 mm max height RGE0024H PLASTIC QUAD FLATPACK- NO LEAD (3.825) ( 2.7) 19 24 24X (0.58) 24X (0.24) 1 18 20X (0.5) 25 SYMM (3.825) 2X (1.1) TYP 6 13 (R0.05) 12 7 2X(1.1) SYMM LAND PATTERN EXAMPLE SCALE: 20X 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND METAL SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 4219016 / A 08/2017 NOTES: (continued) 4. 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN VQFN - 1 mm max height RGE0024H PLASTIC QUAD FLATPACK- NO LEAD (3.825) 4X ( 1.188) 19 24 24X (0.58) 24X (0.24) 1 18 20X (0.5) SYMM (3.825) (0.694) TYP 6 13 (R0.05) TYP METAL TYP 25 7 SYMM 12 (0.694) TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 78% PRINTED COVERAGE BY AREA SCALE: 20X 4219016 / A 08/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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