© 2006 Microchip Technology Inc. Preliminary DS41302A
PIC12F609/HV609
PIC12F615/HV615
Data Sheet
8-Pin Flash-Based, 8-Bit
CMOS Microcontrollers
*8-bit, 8-pin D evic es Prot ect ed by Mic rochip’s Low Pin C ount Pat ent: U .S. Patent N o. 5, 847,450. Addit ional U.S. and
f oreign patent s and applic ations m ay be is sued or pending.
DS41302A-page ii Preliminary © 2006 Microchip Technology Inc.
Information contained in this publication regarding device
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The Microchip name and logo, the Microchip logo, Accuron,
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© 2006, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrit y of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violat ion of the Digital Millennium Copyright Act. If suc h ac t s
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Microchip received ISO/TS-16949:2002 certification for its worldwide
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microperipherals, nonvolatile memory and analog products. In addition,
Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc. Preliminary DS41302A-page 1
PIC12F609/615/12HV609/615
High-Performance RISC CPU:
Only 35 instructions to learn:
- All single-cycle instructions except branches
Operati ng spe ed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
Interrupt capability
8-level deep hardware stack
Direct, Indirect and Relative Addressing modes
Special Microcontroller Features:
Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency: 4 MHz or
8 MHz
Power-Saving Sleep mode
Volta ge rang e:
- PIC12F609/615: 2.0V to 5.5V
- PIC12HV609/615: 2.0V to user defined
maximum (see note)
Industri al and Extended Temperature range
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Brown-out Reset (BOR)
Watchdog Timer (WDT) with independent
oscilla tor for reliable operation
Multiplexed Master Clear with pull-up/input pin
Programmable code protection
High Endurance Flash:
- 100,000 write Flash endurance
- Flash retenti on: > 40 years
Low-Power Features:
Standby Cu rre nt:
- 50 nA @ 2.0V, typical
Operati ng Curren t:
-11μA @ 32 kHz, 2.0V, typical
-260μA @ 4 MHz, 2.0V, typical
Watchdog Timer Current:
-1μA @ 2.0V, typical
Note: Voltage across the shunt regulator should
not exceed 5V.
Peripheral Feat ures:
Shunt Voltage Regulator (PIC12HV609/615 only):
- 5 volt regulation
- 4 mA to 50 mA shunt range
5 I/O pins and 1 input only
High current source/sink for direct LED drive
- Interrupt-on-pin change or pins
- Individually programmable weak pull-ups
Analog Comparator module with:
- One analog comparator
- Programmable on-chip voltage reference
(CVREF) module (% of VDD)
- Comparator inputs and output externally
accessible
- Built-In Hysteresis (software selectable)
Timer0: 8-bit timer/counter with 8-bit
progra mmab le pres caler
Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Timer1 Gate (count enable)
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator if INTOSC mode
selected
- Option to use system clock as Timer1
In-Circuit Serial ProgrammingTM (ICSPTM) via two
pins
PIC12F615/HV615 ONLY:
Enhanced Capture, Compare, PWM module:
- 16-bit Capture, max. resolut ion 12.5 ns
- Compare, max. resolution 200 ns
- 10-bit PWM with 1 or 2 output channels, 1
output channel programmable “dead time”,
max. frequency 20 kHz, auto-shutdown
A/D Converter:
- 10-bit resolution and 4 channels, samples
internal voltage references
Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers
PIC12F609/615/12HV609/615
DS41302A-page 2 Preliminary © 2006 Microchip Technology Inc.
8-Pin Diagram, PIC12F609/HV609 (PDIP, SOI C, TSSOP, DFN)
TABLE 1: PIC12F609/HV609 PIN SUMMARY (PDIP, SOIC, TSSOP, DFN)
Device Program Memory Data Memory I/O 10-bit A/D
(ch) Comparators Timers
8/16-bit Voltage Range
Flash
(words) SRAM (bytes)
PIC12F609 1024 64 5 0 1 1/1 2.0V-5.5V
PIC12HV609 1024 64 5 0 1 1/1 2.0V-user defined
PIC12F615 1024 64 5 4 1 2/1 2.0V-5.5V
PIC12HV615 1024 64 5 4 1 2/1 2.0V-user defined
I/O Pin Comparators Timer Interrupts Pull-ups Basic
GP0 7CIN+ IOC YICSPDAT
GP1 6 CIN0- IOC Y ICSPCLK
GP2 5COUT T0CKI INT/IOC Y
GP3(1) 4— IOC Y(2) MCLR/VPP
GP4 3CIN1- T1G IOC YOSC2/CLKOUT
GP5 2 T1CKI IOC Y OSC1/CLKIN
1 VDD
8 ——— VSS
Note 1: Input only.
2: Only when pin is configured for external MCLR.
1
2
3
45
6
7
8
PIC12F609/
HV609
VSS
GP0/CIN+/ICSPDAT
GP1/CIN0-/ICSPCLK
GP2/T0CKI/INT/COUT
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/CIN1-/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
© 2006 Microchip Technology Inc. Preliminary DS41302A-page 3
PIC12F609/615/12HV609/615
8-Pin Diagram, PIC12F615/HV615 (PDIP, SOIC, TSSOP, DFN)
TABLE 2: PIC12F615/HV615 PIN SUMMARY (PDIP, SOIC, TSSOP, DFN)
I/O Pin Analog Comparators Timer CCP Interrupts Pull-ups Basic
GP0 7AN0 CIN+ P1B IOC YICSPDAT
GP1 6 AN1 CIN0- IOC Y ICSPCLK/VREF
GP2 5AN2 COUT T0CKI CCP1/P1A INT/IOC Y
GP3(1) 4— T1G*— IOCY
(2) MCLR/VPP
GP4 3AN3 CIN1- T1G P1B* IOC YOSC2/CLKOUT
GP5 2 T1CKI P1A* IOC Y OSC1/CLKIN
1 VDD
—8 VSS
* Alternate pin function.
Note 1: Input only.
2: Only when pin is configured for external MCLR.
1
2
3
45
6
7
8
PIC12F615/
HV615
VSS
GP0/AN0/CIN+/P1B/ICSPDAT
GP1/AN1/CIN0-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
VDD
GP5/T1CKI/P1A*/OSC1/CLKIN
GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT
GP3/T1G*/MCLR/VPP
* Alternate pin function.
PIC12F609/615/12HV609/615
DS41302A-page 4 Preliminary © 2006 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory O rganization................................................................................................................................................................... 9
3.0 Oscillator Module........................................................................................................................................................................ 25
4.0 I/O Ports ........... ...... ....... ...... .................................. ...... ...... ...... ....... ...... ...... ....... ......................................................................... 31
5.0 Timer0 Module ........................................................................................................................................................................... 41
6.0 Timer1 Module with Gate Control............................................................................................................................................... 45
7.0 Timer2 Module (PIC12F615/HV 615 only) .................................................................................................................................. 51
8.0 Comparator Module................... .... ....... .... .. .... .... ....... .... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......................................................... 53
9.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/HV615 only)......... ......... .. .... .... .. ......... .... .. .... ....... .... ........................... 65
10.0 Enhanc ed Capture/Com pare/PW M (With Auto-Shutdown and Dead Band) Module (PIC12F615/HV615 only)........................ 75
11.0 Specia l Features of the CPU......... ....... ...... ...... ....................... ....... ....................... ...... ...... ......................................................... 93
12.0 Voltage Regulator................ .. .. .. .. .. ....... .. .. .. .. .. .. .. ..... .... .. .. .. .. .. .. ..... .. .... .. .. .. .. .. ..... .. .... .. .. .. ........................................................... 111
13.0 Instruction Set Summary.......................................................................................................................................................... 113
14.0 Development Support............................................................................................................................................................... 123
15.0 Electrical Specifications............................................................................................................................................................ 127
16.0 DC and AC Characteristics Graphs and Tables...................... ......... .... .. .... ......... .... .. .... .... ......... .... .. ........................................ 149
17.0 Packagin g In fo r mation............. ...... ....... ....................... ...... ...... ........................ ...... ...... ............................................................. 151
Appendix A: Data Sheet Revision History................................. .... .... ......... .... .... .... ......... .... .. .... ......................................................... 157
Appendix B: Migrating from other PIC® Devices.................... .... .... ......... ...... .... .... ......... .... .... .... ....................................................... 157
Index .................................................................................................................................................................................................. 159
The Micro chip Web Site........ ...... ...... ...... ....... ...... ...... ....... ...... ...... ....................... ....... ...... ................................................................. 163
Customer Change Notification Service ........................................... ............... .... ............... ...... ........................................................... 163
Customer Support....................... ...... ...... ........... ...... ............. ...... .... ............. ...... ............. ................................................................... 163
Reader Response.............................................................................................................................................................................. 164
Product Identification System............................................................................................................................................................. 165
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© 2006 Microchip Technology Inc. Preliminary DS41302A-page 5
PIC12F609/615/12HV609/615
1.0 DEVICE OVERVIEW
The PIC12F609/615/12HV609/615 devices are covered
by this data sheet. They are available in 8-pin PDIP,
SOIC, TSSOP and DFN packages.
Block Diagrams and pinout descriptions of the devices
are as follows:
PIC12F609/HV609 (Figure 1-1, Table 1-1)
PIC12F615/HV615 (Figure 1-2, Table 1-2)
FIGURE 1-1: PIC12F609/HV609 BLOCK DIAGRAM
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
GPIO
8
8
8
3
8-Level Stack 64 Bytes
1K X 14
(13-Bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VSS
Brown-out
Reset
Timer0 Timer1
GP0
GP1
GP2
GP3
GP4
GP5
Analog Comparator
T0CKI
INT
T1CKI
Configuration
Internal
Oscillator
and Reference
T1G VDD
Block
CIN+
CIN0-
CIN1-
COUT
Comparator Voltage Reference
Absolute Voltage Reference
Shunt Regulator
(PIC12HV609 only)
PIC12F609/615/12HV609/615
DS41302A-page 6 Preliminary © 2006 Microchip Technology Inc.
FIGURE 1-2: PIC12F615/HV615 BLOCK DIAGRAM
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
GPIO
8
8
8
3
8-Level Stack 64 Bytes
1K X 14
(13-Bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VSS
Brown-out
Reset
Timer0 Timer1
GP0
GP1
GP2
GP3
GP4
GP5
Analog Comparator
T0CKI
INT
T1CKI
Configuration
Internal
Oscillator
VREF
and Reference
T1G VDD
Timer2
Block Shunt Regulator
(PIC12HV615 only)
Analog-To-Digital Converter
AN0
AN1
AN2
AN3
CIN+
CIN0-
CIN1-
COUT
ECCP
CCP1/P1A
P1B
P1A*
P1B*
Comparator Voltage Reference
Absolute Voltage Reference
* Altern ate pin func ti on.
T1G*
© 2006 Microchip Technology Inc. Preliminary DS41302A-page 7
PIC12F609/615/12HV609/615
TABLE 1-1: PIC12F609/HV609 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
GP0/CIN+/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change
CIN+ AN Comparator non-inverting input
ICSPDAT S T CMOS Serial Programm ing Data I/O
GP1/CIN0-/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change
CIN0- AN Comparator inverting input
ICSPCLK ST Serial Programm ing Clock
GP2/T0CKI/INT/COUT GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-on-change
T0CKI ST Timer0 clock input
INT S T External Interrupt
COUT CMOS Comparator output
GP3/MCLR/VPP GP3 TTL General purpose input with interrupt-on-change
MCLR ST Master Clear w/internal pull-up
VPP HV Programming voltage
GP4/CIN1-/T1G/OSC2/
CLKOUT GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change
CIN1- AN Comparator inverting input
T1G ST Timer1 gate (count enable)
OSC2 XTAL Crystal/Resonator
CLKOUT CMOS FOSC/4 output
GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and int errupt -on-c hange
T1CKI ST Timer1 clock input
OSC1 XTAL Crystal/Resonator
CLKIN ST External clock input/RC oscillator connection
VDD VDD Power Positive supply
VSS VSS Power Ground reference
Legend: AN = Analog input or output CMOS= CMOS com patible input or output HV = H igh Voltage
ST = Schmitt Trigger input with CMOS levels T T L = TTL compatible input XTAL = C rystal
PIC12F609/615/12HV609/615
DS41302A-page 8 Preliminary © 2006 Microchip Technology Inc.
TABLE 1-2: PIC12F615/HV615 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
GP0/AN0/CIN+/P1B/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
AN0 AN A/D Channel 0 input
CIN+ AN Comparator non-inverting input
P1B CMOS PWM output
ICSPDAT S T CMOS Serial Programm ing Data I/O
GP1/AN1/CIN0-/VREF/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
AN1 AN A/D Channel 1 input
CIN0- AN Comparator inverting input
VREF AN External Voltage Reference for A/D
ICSPCLK ST Serial Programm ing Clock
GP2/AN2/T0CKI/INT/COUT/CCP1/
P1A GP2 S T CMO S G eneral purpose I/O with prog. pull-up and interrupt-on-
change
AN2 AN A/D Channel 2 input
T0CKI ST Timer0 clock input
INT S T External Interrupt
COUT CMOS Comparator output
CCP1 ST CMOS Capture input/Compare input/PWM output
P1A CMOS PWM output
GP3/T1G*/MCLR/VPP GP3 TTL General purpose input with interrupt-on-change
T1G* ST Timer1 gate (count enable), alternate pin
MCLR ST Master Clear w/internal pull-up
VPP HV Programming voltage
GP4/AN3/CIN1-/T1G/P1B*/OSC2/
CLKOUT GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
AN3 AN A/D Channel 3 input
CIN1- AN Comparator inverting input
T1G ST Timer1 gate (count enable)
P1B* CMOS PWM output, alternate pin
OSC2 XTAL Crystal/Resonator
CLKOUT CMOS FOSC/4 output
GP5/T1CKI/P1A*/OS C 1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
T1CKI ST Timer1 clock input
P1A* CMOS PWM output, alternate pin
OSC1 XTAL Crystal/Resonator
CLKIN ST External clock input/RC oscillator connection
VDD VDD Power Positive supply
VSS VSS Power Ground reference
* Alternate pin function.
Legend: A N = Analog input or output CMOS=CMOS compatible input or output HV = High Voltage
ST = Schmitt Trigger input with CMOS levels TTL =TTL compatible input XTAL= Crystal
© 2006 Microchip Technology Inc. Preliminary DS41302A-page 9
PIC12F609/615/12HV609/615
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC12F609/615/12HV609/615 has a 13-bit pro-
gram counter capable of addressing an 8K x 14 pro-
gram memory space. Only the first 1K x 14 (0000h-
03FFh) for the PIC12F609/615/12HV609/615 is physi-
cally implemented. Accessing a location above these
boundaries will cause a wraparound within the first 1K
x 14 sp ac e. The Rese t vec tor is at 0000 h and the int er-
rupt vector is at 0004h (see Figure 2-1).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F609/615/12HV609/615
2.2 Data Memory Organiza tion
The data memo ry (see Figure 2-2) is partitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. Register locations F0h-FFh in Bank 1 point
to addresses 70h-7Fh in Bank 0. All other RAM is
unimplemented and returns ‘0when read. The RP0 bit
of the STATUS register is the bank select bit.
RP0
0Bank 0 is selected
1Bank 1 is selected
2.2. 1 GENERAL PURPO SE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC12F609/615/12HV609/615. Each register is
accessed, either directly or indirectly, through the File
Select Register (FSR) (see Section 2.4 “Indirect
Addressing, INDF and FSR Registers”).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
PC<12:0>
13
0000h
0004h
0005h
03FFh
0400h
1FFFh
Stack Level 1
Stack Level 8
Reset V ector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Wraps to 0000h-07FFh
Note: The IRP and RP1 bits of the STATUS
register are reserved and should always be
maint ained as 0’s.
PIC12F609/615/12HV609/615
DS41302A-page 10 Preliminary © 2006 Microchip Technology Inc.
FIGURE 2-2: DATA MEMORY MAP OF
THE PIC12F60 9/HV 609 FIGURE 2-3: DATA MEMORY MAP OF
THE PIC12F61 5/HV 615
Indirect Addr.(1)
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L
TMR1H
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
7Fh
Bank 0
Unimplemented data memory l ocations, read as ‘0’.
Note 1: Not a physical register.
General
Purpose
Registers
64 Bytes
File
Address File
Address
WPU
IOC
Indirect Addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
FFh
Bank 1
ANSEL
Accesses 70h-7Fh F0h
VRCON
CMCON0
OSCTUNE
40h
3Fh
CMCON1
EFh
T1CON
Indirect Addr.(1)
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
7Fh
Bank 0
Unimplemented data memory l ocations, read as ‘0’.
Note 1: Not a physical register.
General
Purpose
Registers
64 Bytes
File
Address File
Address
WPU
IOC
Indirect Addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
FFh
Bank 1
ADRESH
ADCON0
ADRESL
ANSEL
Accesses 70h-7Fh F0h
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
PWM1CON
ECCPAS
VRCON
CMCON0
OSCTUNE
PR2
40h
3Fh
CMCON1
EFh
APFCON
© 2006 Microchip Technology Inc. Preliminary DS41302A-page 11
PIC12F609/615/12HV609/615
TABLE 2-1: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Value on
POR, BOR Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 100
01h TMR0 Timer0 Module ’s Regi ster xxxx xxxx 41, 100
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 100
03h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 15, 100
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 100
05h GPIO GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 31, 100
06h Unimplemented
07h Unimplemented
08h Unimplemented
09h Unimplemented
0Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 100
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 17, 100
0Ch PIR1 —CMIF—TMR1IF---- 0--0 19, 100
0Dh Unimplemented
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 100
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 100
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 49, 100
11h Unimplemented
12h Unimplemented
13h Unimplemented
14h Unimplemented
15h Unimplemented
16h Unimplemented
17h Unimplemented
18h Unimplemented
19h VRCON CMVREN VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 62, 101
1Ah CMCON0 CMON COUT CMOE CMPOL —CMR—CMCH0000 -0-0 58, 101
1Bh
1Ch CMCON1 T1ACS CMHYS T1GSS CMSYNC ---0 0-10 59, 101
1Dh Unimplemented
1Eh Unimplemented
1Fh Unimplemented
Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
PIC12F609/615/12HV609/615
DS41302A-page 12 Preliminary © 2006 Microchip Technology Inc.
TABLE 2-2: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 101
01h TMR0 Timer0 Module ’s Regi ster xxxx xxxx 41, 101
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 101
03h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 15, 101
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 101
05h GPIO GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 31, 101
06h Unimplemented
07h Unimplemented
08h Unimplemented
09h Unimplemented
0Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 101
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 17, 101
0Ch PIR1 ADIF CCP1IF —CMIF TMR2IF TMR1IF -00- 0-00 19, 101
0Dh Unimplemented
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 101
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 101
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 49, 101
11h TMR2 Timer2 Module Reg ister 0000 0000 51, 101
12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52, 101
13h CCPR1L Capture/Compare/PWM Register 1 Low Byte XXXX XXXX 76, 101
14h CCPR1H Capture/Compare/PWM Register 1 High Byte XXXX XXXX 76, 101
15h CCP1CON P1M DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 75, 101
16h PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 91, 101
17h ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 88, 101
18h Unimplemented
19h VRCON CMVREN VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 62, 101
1Ah CMCON0 CMON COUT CMOE CMPOL —CMR—CMCH0000 -0-0 58, 101
1Bh
1Ch CMCON1 T1ACS CMHYS T1GSS CMSYNC ---0 0-10 59, 101
1Dh Unimplemented
1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 71, 101
1Fh ADCON0 ADFM VCFG CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 70, 101
Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
© 2006 Microchip Technology Inc. Preliminary DS41302A-page 13
PIC12F609/615/12HV609/615
TABLE 2-3: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 101
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 16, 101
82h PCL Pro gr am Coun ter’s (PC) Least Significa nt Byt e 0000 0000 22, 101
83h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 15, 101
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 101
85h TRISIO TRISIO5 TRISIO4 TRISIO3(4) TRISIO2 TRISIO1 TRISIO0 --11 1111 31, 101
86h Unimplemented
87h Unimplemented
88h Unimplemented
89h Unimplemented
8Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 101
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF(3) 0000 0000 17, 101
8Ch PIE1 —CMIE—TMR1IE---- 0--0 18, 101
8Dh Unimplemented
8Eh PCON —PORBOR ---- --qq 20, 101
8Fh Unimplemented
90h OSCTUNE TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 29, 101
91h Unimplemented
92h Unimplemented
93h Unimplemented
94h Unimplemented
95h WPU(2) —WPU5WPU4 WPU2 WPU1 WPU0 --11 -111 34, 101
96h IOC IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 34, 101
97h Unimplemented
98h Unimplemented
99h Unimplemented
9Ah Unimplemented
9Bh Unimplemented
9Ch Unimplemented
9Dh Unimplemented
9Eh Unimplemented
9Fh ANSEL —ANS3 ANS1 ANS0 ---- 1-11 33, 101
Legend: – = Unimplemented locations read as0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: GP3 pull-up is enabled when MCLRE is1’ in the Configuration Word register.
3: MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
4: TRISIO3 always reads as ‘1’ since it is an input only pin.
PIC12F609/615/12HV609/615
DS41302A-page 14 Preliminary © 2006 Microchip Technology Inc.
TABLE 2-4: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 101
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 16, 101
82h PCL Pro gr am Coun ter’s (PC) Least Significa nt Byt e 0000 0000 22, 101
83h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 15, 101
84h FSR Indirect Data Memory Ad dress Pointer xxxx xxxx 22, 101
85h TRISIO TRISIO5 TRISIO4 TRISIO3(4) TRISIO2 TRISIO1 TRISIO0 --11 1111 31, 101
86h Unimplemented
87h Unimplemented
88h Unimplemented
89h Unimplemented
8Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 101
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF(3) 0000 0000 17, 101
8Ch PIE1 ADIE CCP1IE —CMIE TMR2IE TMR1IE -00- 0-00 18, 101
8Dh Unimplemented
8Eh PCON —PORBOR ---- --qq 20, 101
8Fh Unimplemented
90h OSCTUNE TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 29, 101
91h Unimplemented
92h PR2 Timer2 Module Period Register 1111 1111 51, 101
93h APFCON T1GSEL P1BSEL P1ASEL ---0 --00 18, 101
94h Unimplemented
95h WPU(2) —WPU5WPU4 WPU2 WPU1 WPU0 --11 -111 34, 101
96h IOC IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 34, 101
97h Unimplemented
98h Unimplemented
99h Unimplemented
9Ah Unimplemented
9Bh Unimplemented
9Ch Unimplemented
9Dh Unimplemented
9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 71, 101
9Fh ANSEL ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 33, 101
Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: GP3 pull-up is enabled when MCLRE is1’ in the Configuration Word register.
3: MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
4: TRISIO3 always reads as ‘1’ since it is an input only pin.