High Voltage, Latch-up Proof,
4-Channel Multiplexer
ADG5404
Rev. A
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FEATURES
Latch-up proof
8 kV HBM ESD rating
Low on resistance (<10 Ω)
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VSS to VDD analog signal range
APPLICATIONS
Relay replacement
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
FUNCTIONAL BLOCK DIAGRAM
S
1
1 OF 4
DECODER
ADG5404
S
2
D
S
3
S
4
A0 A1 EN
09203-001
Figure 1.
GENERAL DESCRIPTION
The ADG5404 is a complementary metal-oxide semiconductor
(CMOS) analog multiplexer, comprising four single channels.
The on-resistance profile is very flat over the full analog input
range, ensuring excellent linearity and low distortion when
switching audio signals.
The ADG5404 is designed on a trench process, which guards
against latch-up. A dielectric trench separates the P and N
channel transistors, thereby preventing latch-up even under
severe overvoltage conditions.
The ADG5404 switches one of four inputs to a common output,
D, as determined by the 3-bit binary address lines, A0, A1, and
EN. Logic 0 on the EN pin disables the device. Each switch
conducts equally well in both directions when on and has an
input signal range that extends to the supplies. In the off condi-
tion, signal levels up to the supplies are blocked. All switches
exhibit break-before-make switching action.
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up. A dielectric
trench separates the P and N channel transistors, thereby
preventing latch-up even under severe overvoltage
conditions.
2. Low RON.
3. Dual-Supply Operation. For applications where the analog
signal is bipolar, the ADG5404 can be operated from dual
supplies of up to ±22 V.
4. Single-Supply Operation. For applications where the
analog signal is unipolar, the ADG5404 can be operated
from a single-rail power supply of up to 40 V.
5. 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
6. No VL logic power supply required.
ADG5404
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
±20 V Dual Supply ....................................................................... 4
+12 V Single Supply ..................................................................... 5
+36 V Single Supply ..................................................................... 6
Continuous Current per Channel, S or D ................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions............................9
Truth Table .....................................................................................9
Typical Performance Characteristics ........................................... 10
Test Circuits..................................................................................... 14
Terminology .................................................................................... 17
Trench Isolation .............................................................................. 18
Applications Information.............................................................. 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
7/11—Rev. 0 to Rev. A
Changes to Product Highlights....................................................... 1
Change to ISS Parameter, Table 2..................................................... 4
Updated Outline Dimensions....................................................... 20
7/10—Revision 0: Initial Version
ADG5404
Rev. A | Page 3 of 20
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 9.8 Ω typ VS = ±10 V, IS = −10 mA; see Figure 23
11 14 16 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match
Between Channels, ∆RON
0.35 Ω typ VS = ±10 V, IS = −10 mA
0.7 0.9 1.1 Ω max
On-Resistance Flatness, RFLAT(ON) 1.2 Ω typ VS = ±10 V, IS = −10 mA
1.6 2 2.2 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off) ±0.05 nA typ VS = VS = ±10 V, VD = ∓10 V; see Figure 24
±0.25 ±0.75 ±3.5 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = VS = ±10 V, VD = ∓10 V; see Figure 24
±0.4 ±2 ±12 nA max
Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = ±10 V; see Figure 25
±0.4 ±2 ±12 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 187 ns typ RL = 300 Ω, CL = 35 pF
242 285 330 ns max VS = 10 V; see Figure 30
tON (EN) 160 ns typ RL = 300 Ω, CL = 35 pF
204 247 278 ns max VS = 10 V; see Figure 32
tOFF (EN) 125 ns typ RL = 300 Ω, CL = 35 pF
145 168 183 ns max VS = 10 V; see Figure 32
Break-Before-Make Time Delay, tD 45 ns typ RL = 300 Ω, CL = 35 pF
12 ns min VS1 = VS2 = 10 V; see Figure 31
Charge Injection, QINJ 220 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation −78 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see
Figure 26
Channel-to-Channel Crosstalk −58 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion + Noise 0.009 % typ RL = 1k Ω, 15 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
−3 dB Bandwidth 53 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 27
Insertion Loss −0.7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
CS (Off) 19 pF typ VS = 0 V, f = 1 MHz
CD (Off) 92 pF typ VS = 0 V, f = 1 MHz
CD, CS (On) 132 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 45 μA typ Digital inputs = 0 V or VDD
55 70 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/max GND = 0 V
1 Guaranteed by design; not subject to production test.
ADG5404
Rev. A | Page 4 of 20
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 9 Ω typ VS = ±15 V, IS = −10 mA; see Figure 23
10 13 15 Ω max VDD = +18 V, VSS = −18 V
On-Resistance Match
Between Channels, ∆RON
0.35 Ω typ VS = ±15 V, IS = −10 mA
0.7 0.9 1.1 Ω max
On-Resistance Flatness, RFLAT(ON) 1.5 Ω typ VS = ±15 V, IS = −10 mA
1.8 2.2 2.5 Ω max
LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V
Source Off Leakage, IS (Off) ±0.05 nA typ VS = ±15 V, VD = ∓15 V; see Figure 24
±0.25 ±0.75 ±3.5 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = ±15 V, VD = ∓15 V; see Figure 24
±0.4 ±2 ±12 nA max
Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = ±15 V; see Figure 25
±0.4 ±2 ±12 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 175 ns typ RL = 300 Ω, CL = 35 pF
224 262 301 ns max VS = +10 V; see Figure 30
tON (EN) 148 ns typ RL = 300 Ω, CL = 35 pF
185 222 250 ns max VS = 10 V; see Figure 32
tOFF (EN) 120 ns typ RL = 300 Ω, CL = 35 pF
142 159 173 ns max VS = 10 V; see Figure 32
Break-Before-Make Time Delay, tD 40 ns typ RL = 300 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 10 V; see Figure 31
Charge Injection, QINJ 290 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation −78 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 26
Channel-to-Channel Crosstalk −58 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion +
Noise
0.008 % typ RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
−3 dB Bandwidth 54 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 27
Insertion Loss −0.6 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
CS (Off) 18 pF typ VS = 0 V, f = 1 MHz
CD (Off) 88 pF typ VS = 0 V, f = 1 MHz
CD, CS (On) 129 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +22 V, VSS = −22 V
IDD 50 μA typ Digital inputs = 0 V or VDD
70 110 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/max GND = 0 V
1 Guaranteed by design; not subject to production test.
ADG5404
Rev. A | Page 5 of 20
+12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance, RON 19 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 23
22 27 31 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match
Between Channels, ∆RON
0.4 Ω typ VS = 0 V to 10 V, IS = −10 mA
0.8 1 1.2 Ω max
On-Resistance Flatness, RFLAT(ON) 4.4 Ω typ VS = 0 V to 10 V, IS = −10 mA
5.5 6.5 7.5 Ω max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
±0.25 ±0.75 ±3.5 nA max
Drain Off Leakage, ID (Off) ±0.05 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
±0.4 ±2 ±12 nA max
Channel On Leakage, ID, IS (On) ±0.05 nA typ VS = VD = 1 V/10 V; see Figure 25
±0.4 ±2 ±12 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 266 ns typ RL = 300 Ω, CL = 35 pF
358 446 515 ns max VS = +8 V; see Figure 30
tON (EN) 260 ns typ RL = 300 Ω, CL = 35 pF
339 423 485 ns max VS = 8 V; see Figure 32
tOFF (EN) 135 ns typ RL = 300 Ω, CL = 35 pF
162 189 210 ns max VS = 8 V; see Figure 32
Break-Before-Make Time Delay, tD 125 ns typ RL = 300 Ω, CL = 35 pF
45 ns min VS1 = VS2 = 8 V; see Figure 31
Charge Injection, QINJ 92 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation −78 dB typ RL = 50 Ω, CL = 5 pF, f = 1MHz; see Figure 26
Channel-to-Channel Crosstalk −58 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion + Noise 0.075 % typ RL = 1k Ω, 6 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
−3 dB Bandwidth 43 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 27
Insertion Loss −1.36 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
CS (Off) 22 pF typ VS = 6 V, f = 1 MHz
CD (Off) 105 pF typ VS = 6 V, f = 1 MHz
CD, CS (On) 140 pF typ VS = 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 13.2 V
IDD 40 μA typ Digital inputs = 0 V or VDD
50 65 μA max
VDD 9/40 V min/max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
ADG5404
Rev. A | Page 6 of 20
+36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance, RON 10.6 Ω typ VS = 0 V to 30 V, IS = −10 mA; see Figure 23
12 15 17 Ω max VDD = 32.4 V, VSS = 0 V
On-Resistance Match
Between Channels, ∆RON
0.35 Ω typ VS = 0 V to 30 V, IS = −10 mA
0.7 0.9 1.1 Ω max
On-Resistance Flatness, RFLAT(ON) 2.7 Ω typ VS = 0 V to 30 V, IS = −10 mA
3.2 3.8 4.5 Ω max
LEAKAGE CURRENTS VDD =39.6 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.05 nA typ VS = 1 V/30 V, VD = 30 V/1 V; see Figure 24
±0.25 ±0.75 ±3.5 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = 1 V/30 V, VD = 30 V/1 V; see Figure 24
±0.4 ±2 ±12 nA max
Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = 1 V/30 V; see Figure 25
±0.4 ±2 ±12 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 196 ns typ RL = 300 Ω, CL = 35 pF
256 276 314 ns max VS = 18 V; see Figure 30
tON (EN) 170 ns typ RL = 300 Ω, CL = 35 pF
214 247 273 ns max VS = 18 V; see Figure 32
tOFF (EN) 130 ns typ RL = 300 Ω, CL = 35 pF
172 167 176 ns max VS = 18 V; see Figure 32
Break-Before-Make Time Delay, tD 52 ns typ RL = 300 Ω, CL = 35 pF
13 ns min VS1 = VS2 = 18 V; see Figure 31
Charge Injection, QINJ 280 pC typ VS = 18 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation −78 dB typ RL = 50 Ω, CL = 5 pF, f = 1MHz; see Figure 26
Channel-to-Channel Crosstalk −58 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion +
Noise
0.03 % typ RL = 1k Ω, 18 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
−3 dB Bandwidth 47 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 27
Insertion Loss −0.85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
CS (Off) 18 pF typ VS = 18 V, f = 1 MHz
CD (Off) 89 pF typ VS = 18 V, f = 1 MHz
CD, CS (On) 128 pF typ VS = 18 V, f = 1 MHz
POWER REQUIREMENTS VDD = 39.6 V
IDD 80 μA typ Digital inputs = 0 V or VDD
100 130 μA max
VDD 9/40 V min/max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
ADG5404
Rev. A | Page 7 of 20
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 5.
Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, S OR D
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W) 165 96 49 mA max
LFCSP (θJA = 30.4°C/W) 290 141 57 mA max
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W) 176 101 51 mA max
LFCSP (θJA = 30.4°C/W) 282 146 58 mA max
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W) 114 72 42 mA max
LFCSP (θJA = 30.4°C/W) 203 112 53 mA max
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W) 149 89 48 mA max
LFCSP (θJA = 30.4°C/W) 263 133 56 mA max
ADG5404
Rev. A | Page 8 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter Rating
VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, Sx or D Pins 515 mA (pulsed at 1 ms,
10% duty cycle maximum)
Continuous Current, S or D2 Data + 15%
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Thermal Impedance, θJA
16-Lead TSSOP, θJA Thermal
Impedance (4-Layer Board)
112.6°C/W
16-Lead LFCSP, θJA Thermal
Impedance (4-Layer Board)
30.4°C/W
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
1 Overvoltages at the Sx and D pins are clamped by internal diodes. Limit
current to the maximum ratings given.
2 See . Table 5
ADG5404
Rev. A | Page 9 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG5404
NC = NO CONNECT
1
2
3
4
5
6
7
EN
V
SS
S1
NC
D
S2
A0
14
13
12
11
10
9
8
GND
V
DD
S3
NC
NC
S4
A1
TOP VIEW
(Not to Scale)
09203-002
Figure 2. TSSOP Pin Configuration
PIN 1
INDICATOR
NOTES
1. NC = NO CONNECT.
2
. EXPOSED PAD TIED TO SUBSTRATE, V
SS
.
1V
SS
2NC
3S1
4S2
11 V
DD
12 GND
10 S3
9S4
5
NC
6
D
7
NC
8
NC
15 A0
16 EN
14 A1
13 NC
TOP VIEW
(Not to Scale)
ADG5404
09203-003
Figure 3. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 15 A0 Logic Control Input.
2 16 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are off.
When this pin is high, the Ax logic inputs determine the on switches.
3 1 VSS Most Negative Power Supply Potential.
4 3 S1 Source Terminal. Can be an input or an output.
5 4 S2 Source Terminal. Can be an input or an output.
6 6 D Drain Terminal. Can be an input or an output.
7 to 9 2, 5, 7, 8, 13 NC No Connection.
10 9 S4 Source Terminal. Can be an input or an output.
11 10 S3 Source Terminal. Can be an input or an output.
12 11 VDD Most Positive Power Supply Potential.
13 12 GND Ground (0 V) Reference.
14 14 A1 Logic Control Input.
EP Exposed Pad
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
TRUTH TABLE
Table 8.
EN A1 A0 S1 S2 S3 S4
0 X1 X1 Off Off Off Off
1 0 0 On Off Off Off
1 0 1 Off On Off Off
1 1 0 Off Off On Off
1 1 1 Off Off Off On
1 X = don’t care.
ADG5404
Rev. A | Page 10 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0
2
4
6
8
10
12
14
16
–20 –15 –10
10
–5 0 5 10 15 20
ON RESISTANCE ()
V
S
, V
D
(V)
T
A
= 25°C V
DD
= +9V
V
SS
= –9V
V
DD
= +10V
V
SS
= –10V
V
DD
= +13.5V
V
SS
= –13.5V V
DD
= +15V
V
SS
= –15V
V
DD
= +16.5V
V
SS
= –16.5V
V
DD
= +11V
V
SS
= –11V
09203-029
Figure 4. RON as a Function of VD (VS), Dual Supply
0
2
4
6
8
10
12
–25 –20 –15 –10 –5 0 5 10 15 20 25
ON RESISTANCE ()
V
S
, V
D
(V)
T
A
= 25°C
V
DD
= +18V
V
SS
= –18V
V
DD
= +20V
V
SS
= –20V
V
DD
= +22V
V
SS
= –22V
09203-030
Figure 5. RON as a Function of VD (VS), Dual Supply
0
5
10
15
20
25
02468101214
ON RESISTANCE ()
V
S
, V
D
(V)
T
A
= 25°C
V
DD
= +9V
V
SS
= 0V
V
DD
= +10V
V
SS
= 0V V
DD
= 10.8V
V
SS
= 0V
V
DD
= 11V
V
SS
= 0V
V
DD
= 13.2V
V
SS
= 0V
V
DD
= 12V
V
SS
= 0V
09203-027
Figure 6. RON as a Function of VD (VS), Single Supply
0
2
4
6
8
10
12
0 5 10 15 20 25 30 35 40 45
ON RESISTANCE ()
T
A
= 25°C
V
DD
= 32.4V
V
SS
= 0V
V
DD
= 36V
V
SS
= 0V
V
DD
= 39.6V
V
SS
= 0V
V
S
, V
D
(V)
09203-028
Figure 7. RON as a Function of VD (VS), Single Supply
09203-023
0
2
4
6
8
10
12
14
18
16
–15 –10 –5 0 5 10 15
ON RESISTANCE ()
V
S
, V
D
(V)
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
V
DD
= +15V
V
SS
= –15V
Figure 8. RON as a Function of VD (VS) for Different Temperatures,
±15 V Dual Supply
0
2
4
6
8
10
12
14
16
–20 –15 –10 –5 0 5 10 15 20
ON RESISTANCE ()
V
S
, V
D
(V)
V
DD
= +20V
V
SS
= –20V
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
09203-024
Figure 9. RON as a Function of VD (VS) for Different Temperatures,
±20 V Dual Supply
ADG5404
Rev. A | Page 11 of 20
0
5
10
15
20
25
30
024681012
ON RESISTANCE ()
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
V
DD
= 12V
V
SS
= 0V
VS, VD (V)
09203-025
Figure 10. RON as a Function of VD (VS) for Different Temperatures,
12 V Single Supply
0
2
4
6
8
10
12
14
16
0 5 10 15 20 25 30 35 40
ON RESISTANCE ()
V
S
, V
D
(V)
V
DD
= 36V
V
SS
= 0V
09203-026
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
Figure 11. RON as a Function of VD (VS) for Different Temperatures,
36 V Single Supply
0 25 50 75 100 125
LEAKAGE CURRENT (nA)
1.0
–1.0
0.5
–0.5
–1.5
0
I
D
, I
S
(ON) – –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
, I
S
(ON) + +
I
S
(OFF) + –
I
D
(OFF) – +
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V/–10V
TEMPERATURE (°C)
09203-032
Figure 12. Leakage Currents vs. Temperature, ±15 V Dual Supply
0 255075100125
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
1.0
–1.0
0.5
–2.0
–0.5
–1.5
0
V
DD
= +20V
V
SS
= –20V
V
BIAS
= +15V/–15V
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
S
(OFF) + –
09203-033
Figure 13. Leakage Currents vs. Temperature, ±20 V Dual Supply
0 255075100125
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
0.6
–0.2
0.4
–0.6
0
–0.4
0.2
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1V/10V
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
I
D
(OFF) + –
I
S
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
09203-031
Figure 14. Leakage Currents vs. Temperature, 12 V Single Supply
1.0
–1.0
0.5
–2.0
–0.5
–1.5
0
0 25 50 75 100 125
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
V
DD
= 36V
V
SS
= 0V
V
BIAS
= 1V/30V
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
I
D
(OFF) + –
I
S
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
09203-034
Figure 15. Leakage Currents vs. Temperature, 36 V Single Supply
ADG5404
Rev. A | Page 12 of 20
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
OFF ISOLATION (dB)
FREQUENCY (Hz)
1k 10k 100k 1M 10M 100M 1G
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
09203-019
Figure 16. Off Isolation vs. Frequency, ±15 V Dual Supply
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
CROSSTALK (dB)
FREQUENCY (Hz)
100k 1M 10M 100M 1G10k
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
09203-016
Figure 17. Crosstalk vs. Frequency, ±15 V Dual Supply
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
INSERTION LOSS (dB)
FREQUENCY (Hz)
10k 100k 1M 10M1k 100M
TA = 25°C
VDD = +15V
VSS = –15V
09203-020
Figure 18. On Response vs. Frequency, ±15 V Dual Supply
50
100
150
200
250
300
350
400
450
–20–100 10203040
CHARGE INJECTION (pC)
V
S
(V)
T
A
= 25°C
V
DD
= +20V
V
SS
= –20V
V
DD
= +15V
V
SS
= –15V
V
DD
= 36V
V
SS
= 0V
V
DD
= 12V
V
SS
= 0V
09203-021
Figure 19. Charge Injection vs. Source Voltage
0
50
100
150
200
250
300
350
–40 –20 0 20 40 60 80 100 120
TIME (ns)
TEMPERATURE (°C)
V
DD
= +12V, V
SS
= 0V
V
DD
= +15V, V
SS
= –15V
V
DD
= +36V, V
SS
= 0V
V
DD
= +20V, V
SS
= –20V
09203-022
Figure 20. Transition Time vs. Temperature
ACPSRR (dB)
FREQUENCY (Hz)
1k 1M 10M10k 100k
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
DECOUPLING
CAPACITORS
NO DECOUPLING
CAPACITORS
09203-017
Figure 21. ACPSRR vs. Frequency, ±15 V Dual Supply
ADG5404
Rev. A | Page 13 of 20
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0 5 10 15 20
THD + N (%)
FREQUENCY (MHz)
LOAD = 1k
T
A
= 25°C
V
DD
= 12V, V
SS
= 0V, V
S
= 6V p-p
V
DD
= 36V, V
SS
= 0V, V
S
= 18V p-p
V
DD
= 15V, V
SS
= 15V, V
S
= 15V p-p
V
DD
= 20V, V
SS
= 20V, V
S
= 20V p-p
09203-018
Figure 22. THD + N vs. Frequency, ±15 V Dual Supply
ADG5404
Rev. A | Page 14 of 20
TEST CIRCUITS
I
DS
Sx D
V
S
V
09203-005
Figure 23. On Resistance
V
S
V
D
Sx D
A A
I
S
(OFF) I
D
(OFF)
09203-006
Figure 24. Off Leakage
Sx D A
VD
ID(ON)
NC
NC = NO CONNECT
09203-007
Figure 25. On Leakage
V
OUT
50
NETWORK
ANALYZER
R
L
50
Sx
D
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
50
OFF ISOLATION = 20 log V
OUT
V
S
09203-008
Figure 26. Off Isolation
V
OUT
50
NETWORK
ANALYZER
RL
50
Sx
D
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
INSERTION LOSS = 20 log
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
09203-009
Figure 27. Bandwidth
CHANNEL-TO-CHANNEL CROSSTALK = 20 log V
OUT
GND
S1
D
S2
V
OUT
NETWORK
ANALYZER
R
L
50
R
L
50
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
09203-010
Figure 28. Channel-to-Channel Crosstalk
ADG5404
Rev. A | Page 15 of 20
V
OUT
R
S
AUDIO PRECISION
R
L
1k
IN
V
IN
Sx
D
V
S
V p-p
0.1µF
V
DD
0.1µF
V
SS
V
DD
V
SS
GND
09203-011
Figure 29. THD + Noise
V
DD
V
SS
V
DD
V
SS
V
IN
S1
D
GND C
L
35pF
R
L
300
V
OUT
V
OUT
50% 50%
90%
90%
ADDRESS
DRIVE (V
IN
)
)
A0
A1
S4
S3
S2
V
S1
V
S4
EN
2.4V
0V
3V
t
TRANSITION
t
TRANSITION
0.1µF 0.1µF
09203-012
Figure 30. Address to Output Switching Times
V
DD
V
SS
V
DD
V
SS
C
L
35pF
R
L
300
ADDRESS
DRIVE (V
IN
)
V
OUT
V
OUT
V
IN
S1
D
GND
300A0
A1
S4
S3
S2
V
S1
EN
2.4V
0.1µF 0.1µF
t
BBM
80% 80%
0V
3V
09203-013
Figure 31. Break-Before-Make Time Delay
ADG5404
Rev. A | Page 16 of 20
ENABLE
DRIVE (V
IN
)
S1
D
GND C
L
35pF
R
L
300
A0
A1
S4
S3
S2
EN
0.1µF 0.1µF
V
IN
300
t
OFF
(EN)
t
ON (EN)
50% 50%
0.9V
OUT
0.9V
OUT
OUTPUT
0V
3V
V
OUT
0V
V
DD
V
SS
V
DD
V
SS
V
S
V
OUT
09203-014
Figure 32. Enable-to-Output Switching Delay
Sx D
V
S
GND
R
S
SW OFF SW OFF
SW ON
SW OFF SW OFF
A2A1
EN
V
DD
V
SS
V
DD
DECODER
V
SS
V
OUT
V
OUT
V
IN
V
IN
V
OUT
C
L
1nF
Q
INJ
= C
L
× V
OUT
09203-015
Figure 33. Charge Injection
ADG5404
Rev. A | Page 17 of 20
TERMINOLOGY
IDD
The positive supply current.
ISS
The negative supply current.
VD (VS)
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between Terminal D and Terminal S.
RFLAT(ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the
specified analog signal range.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
ID, IS (On)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.
IINL (IINH)
The input current of the digital input.
CS (Off)
The off switch source capacitance, which is measured with
reference to ground.
CD (Off)
The off switch drain capacitance, which is measured with
reference to ground.
CD, CS (On)
The on switch capacitance, which is measured with reference to
ground.
CIN
The digital input capacitance.
tTRANSITION
The delay time between the 50% and 90% points of the digital
input and switch-on condition when switching from one
address state to another.
tON (EN)
The delay between applying the digital control input and the
output switching on. See Figure 32.
tOFF (EN)
The delay between applying the digital control input and the
output switching off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
ACPSRR (AC Power Supply Rejection Ratio)
The ratio of the amplitude of signal on the output to the
amplitude of the modulation. This is a measure of the part’s
ability to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.
ADG5404
Rev. A | Page 18 of 20
TRENCH ISOLATION
In the ADG5404, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction-isolated switches, are eliminated, and the result is a
completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
NMOS PMOS
P-WELL N-WELL
BURIED OXIDE LAYER
HANDLE WAFER
TRENCH
09203-004
Figure 34. Trench Isolation
ADG5404
Rev. A | Page 19 of 20
APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persists until the power supply is
turned off. The ADG5404 high voltage multiplexer allows
single-supply operation from 9 V to 40 V and dual-supply
operation from ±9 V to ±22 V. The ADG5404, as well as three
other ADG54xx family members, ADG5412/ADG5413 and
ADG5436, achieve an 8 kV human body model ESD rating that
provides a robust solution and eliminates the need for separate
protection circuitry designs in some applications.
ADG5404
Rev. A | Page 20 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 35. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
2.70
2.60 SQ
2.50
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC.
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN1
INDICATOR
4.10
4.00 SQ
3.90
0.45
0.40
0.35
S
EATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.35
0.30
0.25
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-16-2010-C
Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG5404BRUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADG5404BRUZ-REEL7 −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADG5404BCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17
1 Z = RoHS Compliant Part.
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09203-0-7/11(A)
