PIC16C554T-04I/SO301 - Microchip Technology

 2002 Microchip Technology Inc. Preliminary DS40143D

PIC16C55X

Data Sheet

EPROM-Based 8-Bit CMOS

Microcontrollers

DS40143D - page ii Preliminary  2002 Microchip Technology Inc.

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Trademarks

The Microchip name and logo, the Microchip logo, KEELOQ,

MPLAB, PIC, PICmicro, PICSTART and PRO MATE are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense,

FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,

ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,

MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select

Mode and Total Endurance are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and Mountain View, California in March 2002.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of development

systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro® MCUs.

• The PICmicro family meets the specifications contained in the Microchip Data Sheet.

• Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.

The person doing so may be engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.

• Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 1

PIC16C55X

Devices Included in this Data Sheet:

Referred to collectively as PIC16C55X.

• PIC16C554

• PIC16C557

• PIC16C558

High Performance RISC CPU:

• Only 35 instructions to learn

• All single-cycle instructions (200 ns), except for

program branches which are two-cycle

• Operating speed:

- DC - 20 MHz clock input

- DC - 20 ns instruction cycle

• Interrupt capability

• 16-18 special function hardware registers

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Peripheral Features:

• 13-22 I/O pins with individual direction control

- Pull-up resistors on PORTB

• High current sink/source for direct LED drive

• Timer0: 8-bit timer/counter with 8-bit programma-

ble prescaler

Pin Diagram

Device Program

Memory Data Memory

PIC16C554 512 80

PIC16C557 2 K 128

PIC16C558 2 K 128

RA1

RA0

OSC2/CLKOUT

VDD

RB7

RB6

RB5

RB4

OSC1/CLKIN

RA2

RA3

MCLR/Vpp

VSS

RB0/INT

RB1

RB2

RB3

RA4/T0CKI

PIC16C554/558

PDIP, SOIC, Windowed CERDIP

SSOP

•1 18

RA1

RA0

OSC2/CLKOUT

VDD

RB7

RB6

RB5

OSC1/CLKIN

RA2

RA3

MCLR/VPP

VSS

RB1

RB2

RA4/T0CKI

PIC16C557

RB4

RB3

•1

N/C

RA5

RB0/INT

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

PDIP, SOIC, Windowed CERDIP

RA1

RA0

OSC2/CLKOUT

VDD

RB7

RB6

RB5

OSC1/CLKIN

RA2

RA3

MCLR/VPP

VSS

RB1

RB2

RA4/T0CKI

PIC16C557

RB4

RB3

•1

RA5

RB0/INT

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

SSOP

VSS

RA1

RA0

OSC2/CLKOUT

VDD

RB7

RB6

RB5

RB4

OSC1/CLKIN

RA2

RA3

MCLR/Vpp

VSS

RB0/INT

RB1

RB2

RB3

RA4/T0CKI

PIC16C554/558

•1 20

VSS

VDD

EPROM-Based 8-Bit CMOS Microcontrollers

PIC16C55X

DS40143D-page 2 Preliminary  2002 Microchip Technology Inc.

Special Microcontroller Features:

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options

• Serial in-circuit programming (via two pins)

• Four user programmable ID locations

CMOS Technology:

• Low power, high speed CMOS EPROM technol-

ogy

• Fully static design

• Wide operating voltage range

- 2.5V to 5.5V

• Commercial, Industrial and Extended temperature

range

• Low power consumption

- < 2.0 mA @ 5.0V, 4.0 MHz

-15 µA typical 3.0V, 32 kHz

-< 1.0 µA typical standby current @ 3.0V

Device Differences

Note: For additional information on enhance-

ments, see Appendix A

Device Voltage Range Oscillator

PIC16C554 2.5 - 5.5 (Note 1)

PIC16C557 2.5 - 5.5 (Note 1)

PIC16C558 2.5 - 5.5 (Note 1)

Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 3

PIC16C55X

Table of Contents

1.0 General Description...................................................................................................................................................................... 5

2.0 PIC16C55X Device Varieties ....................................................................................................................................................... 7

3.0 Architectural Overview ................................................................................................................................................................. 9

4.0 Memory Organization ................................................................................................................................................................. 13

5.0 I/O Ports ..................................................................................................................................................................................... 23

6.0 Special Features of the CPU...................................................................................................................................................... 31

7.0 Timer0 Module ........................................................................................................................................................................... 47

8.0 Instruction Set Summary ............................................................................................................................................................ 53

9.0 Development Support................................................................................................................................................................. 67

10.0 Electrical Specifications.............................................................................................................................................................. 73

11.0 Packaging Information................................................................................................................................................................ 87

Appendix A: Enhancements............................................................................................................................................................. 97

Appendix B: Compatibility ............................................................................................................................................................... 97

Index .................................................................................................................................................................................................... 99

On-Line Support................................................................................................................................................................................. 101

Systems Information and Upgrade Hot Line ...................................................................................................................................... 101

Reader Response .............................................................................................................................................................................. 102

Product Identification System ............................................................................................................................................................ 103

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PIC16C55X

DS40143D-page 4 Preliminary  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. Preliminary DS40143D-page 5

PIC16C55X

1.0 GENERAL DESCRIPTION

The PIC16C55X are 18, 20 and 28-Pin EPROM-based

members of the versatile PIC16CXX family of low cost,

high performance, CMOS, fully-static, 8-bit

microcontrollers.

All PICmicro® microcontrollers employ an advanced

RISC architecture. The PIC16C55X have enhanced

core features, eight-level deep stack, and multiple

internal and external interrupt sources. The separate

instruction and data buses of the Harvard architecture

allow a 14-bit wide instruction word with the separate 8-

bit wide data. The two-stage instruction pipeline allows

all instructions to execute in a single-cycle, except for

program branches (which require two cycles). A total of

35 instructions (reduced instruction set) are available.

Additionally, a large register set gives some of the

architectural innovations used to achieve a very high

performance.

PIC16C55X microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in their class.

The PIC16C554 has 80 bytes of RAM. The PIC16C557

and PIC16C558 have 128 bytes of RAM. The

PIC16C554 and PIC16C558 have 13 I/O pins and an 8-

bit timer/counter with an 8-bit programmable prescaler.

The PIC16C557 has 22 I/O pins and an 8-bit timer/

counter with an 8-bit programmable prescaler.

PIC16C55X devices have special features to reduce

external components, thus reducing cost, enhancing

system reliability and reducing power consumption.

There are four oscillator options, of which the single pin

RC oscillator provides a low cost solution, the LP

oscillator minimizes power consumption, XT is a

standard crystal, and the HS is for high speed crystals.

The SLEEP (power-down) mode offers power saving.

The user can wake-up the chip from SLEEP through

several external and internal interrupts and RESET.

A highly reliable Watchdog Timer, with its own on-chip

RC oscillator, provides protection against software

lock-up.

A UV-erasable CERDIP packaged version is ideal for

code development while the cost effective One-Time

Programmable (OTP) version is suitable for production

in any volume.

Table 1-1 shows the features of the PIC16C55X mid-

range microcontroller families.

A simplified block diagram of the PIC16C55X is shown

in Figure 3-1.

The PIC16C55X series fit perfectly in applications

ranging from motor control to low power remote sen-

sors. The EPROM technology makes customization of

application programs (detection levels, pulse genera-

tion, timers, etc.) extremely fast and convenient. The

small footprint packages make this microcontroller

series perfect for all applications with space limitations.

Low cost, low power, high performance, ease of use

and I/O flexibility make the PIC16C55X very versatile.

1.1 Family and Upward Compatibility

Users familiar with the PIC16C5X family of microcon-

trollers will realize that this is an enhanced version of

the PIC16C5X architecture. Please refer to Appendix A

for a detailed list of enhancements. Code written for

PIC16C5X can be easily ported to PIC16C55X family

of devices (Appendix B).

The PIC16C55X family fills the niche for users wanting

to migrate up from the PIC16C5X family and not need-

ing various peripheral features of other members of the

PIC16XX mid-range microcontroller family.

1.2 Development Support

The PIC16C55X family is supported by a full-featured

macro assembler, a software simulator, an in-circuit

emulator, a low cost development programmer and a

full-featured programmer.

PIC16C55X

DS40143D-page 6 Preliminary  2002 Microchip Technology Inc.

TABLE 1-1: PIC16C55X FAMILY OF DEVICES

PIC16C554 PIC16C557 PIC16C558

Clock Maximum Frequency of Operation

(MHz)

20 20 20

Memory

EPROM Program Memory

(x14 words)

512 2K 2K

Data Memory (bytes) 80 128 128

Peripherals Timer Module(s) TMR0 TMR0 TMR0

Features

Interrupt Sources 3 3 3

I/O Pins 13 22 13

Voltage Range (Volts) 2.5-5.5 2.5-5.5 2.5-5.5

Brown-out Reset — — —

Packages 18-pin DIP, SOIC;

20-pin SSOP

28-pin DIP, SOIC;

28-pin SSOP

18-pin DIP, SOIC,

SSOP

All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high

I/O current capability. All PIC16C55X Family devices use serial programming with clock pin RB6 and data pin RB7.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 7

PIC16C55X

2.0 PIC16C55X DEVICE VARIETIES

A variety of frequency ranges and packaging options

are available. Depending on application and production

requirements, the proper device option can be selected

using the information in the PIC16C55X Product

Identification System section at the end of this data

sheet. When placing orders, please use this page of

the data sheet to specify the correct part number.

2.1 UV Erasable Devices

The UV erasable version, offered in CERDIP package,

is optimal for prototype development and pilot

programs. This version can be erased and

reprogrammed to any of the oscillator modes.

Microchip's PICSTART and PROMATE

programmers both support programming of the

PIC16C55X.

2.2 One-Time Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need the flexibility for frequent code

updates and small volume applications. In addition to

the program memory, the configuration bits must also

be programmed.

2.3 Quick-Turnaround Production

(QTP) Devices

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium-to-high quantity of units and whose code pat-

terns have stabilized. The devices are identical to the

OTP devices, but with all EPROM locations and config-

uration options already programmed by the factory.

Certain code and prototype verification procedures

apply before production shipments are available.

Please contact your Microchip Technology sales office

for more details.

2.4 Serialized Quick-Turnaround

Production (SQTPSM) Devices

Microchip offers a unique programming service where

a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number which can serve as an entry code,

password or ID number.

PIC16C55X

DS40143D-page 8 Preliminary  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. Preliminary DS40143D-page 9

PIC16C55X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16C55X family can be

attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC16C55X uses a Harvard architecture in

which program and data are accessed from separate

memories using separate busses. This improves

bandwidth over traditional von Neumann architecture

where program and data are fetched from the same

memory. Separating program and data memory further

allows instructions to be sized differently from 8-bit

wide data words. Instruction opcodes are 14-bit wide

making it possible to have all single word instructions.

A 14-bit wide program memory access bus fetches a

14-bit instruction in a single cycle. A two-stage pipeline

overlaps fetch and execution of instructions.

Consequently, all instructions (35) execute in a single-

cycle (200 ns @ 20 MHz) except for program branches.

The table below lists the memory (EPROM and RAM).

The PIC16C554 addresses 512 x 14 on-chip program

memory. The PIC16C557 and PIC16C558 addresses

2 K x 14 program memory. All program memory is inter-

nal.

The PIC16C55X can directly or indirectly address its

registers, including the program counter, are mapped

into the data memory. The PIC16C55X has an orthog-

onal (symmetrical) instruction set that makes it possible

to carry out any operation on any register using any

Addressing mode. This symmetrical nature and lack of

‘special optimal situations’ make programming with the

PIC16C55X simple yet efficient. In addition, the

learning curve is reduced significantly.

The PIC16C55X devices contain an 8-bit ALU and

working register. The ALU is a general purpose

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the working register

(W register). The other operand is a file register or an

immediate constant. In single operand instructions, the

operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a Borrow and Digit Borrow out bit,

respectively, in subtraction. See the SUBLW and SUBWF

instructions for examples.

A simplified block diagram is shown in Figure 3-1, with

a description of the device pins in Table 3-1.

Device

Program

Memory

(EPROM)

Data

Memor

(RAM)

PIC16C554 512 80

PIC16C557 2 K 128

PIC16C558 2 K 128

PIC16C55X

DS40143D-page 10 Preliminary  2002 Microchip Technology Inc.

FIGURE 3-1: BLOCK DIAGRAM

EPROM

Program

Memory

2K x 14

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8-Level Stack

(13-bit)

RAM

File

Registers

128 x 8

Direct Addr 7

Addr MUX

Indirect

Addr

FSR

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

VPP VDD, VSS

Timer0

PORTA

PORTB

RA1

RA4/T0CKI

RB0/INT

RB7:RB1

RAM Addr(1)

RA0

RA2

RA3

512 x 14

80 x 8 to

Device Program

Memory

Data

Memory

PIC16C554 512 x 14 80 x 8

PIC16C557 2 K x 14 128 x 8

PIC16C558 2 K x 14 128 x 8

PORTC(2)

RC7:RC0

Note 1: Higher order bits are from STATUS Register.

2: PIC16C557 only.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 11

PIC16C55X

TABLE 3-1: PIC16C55X PINOUT DESCRIPTION

Name

Pin Number Pin

Type

Buffer

Type

PDIP SOIC SSOP Description

OSC1/CLKIN 16 16 18 I ST/CMOS Oscillator crystal input/external clock source output.

OSC2/CLKOUT 15 15 17 O — Oscillator crystal output. Connects to crystal or resonator

in Crystal Oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT which has 1/4 the frequency of OSC1, and

denotes the instruction cycle rate.

MCLR/VPP 4 4 4 I/P ST Master clear (Reset) input/programming voltage input.

This pin is an active low RESET to the device.

RA0 17 17 19 I/O ST Bi-directional I/O port

RA1 18 18 20 I/O ST Bi-directional I/O port

RA2 1 1 1 I/O ST Bi-directional I/O port

RA3 2 2 2 I/O ST Bi-directional I/O port

RA4/T0CKI 3 3 3 I/O ST Bi-directional I/O port or external clock input for TMR0.

Output is open drain type.

RB0/INT 6 6 7 I/O TTL/ST(1) Bi-directional I/O port can be software programmed for

internal weak pull-up. RB0/INT can also be selected as an

external interrupt pin.

RB1 7 7 8 I/O TTL Bi-directional I/O port can be software programmed for

internal weak pull-up.

RB2 8 8 9 I/O TTL Bi-directional I/O port can be software programmed for

internal weak pull-up.

RB3 9 9 10 I/O TTL Bi-directional I/O port can be software programmed for

internal weak pull-up.

RB4 10 10 11 I/O TTL Bi-directional I/O port can be software programmed for

internal weak pull-up. Interrupt-on-change pin.

RB5 11 11 12 I/O TTL Bi-directional I/O port can be software programmed for

internal weak pull-up. Interrupt-on-change pin.

RB6 12 12 13 I/O TTL/ST(2) Bi-directional I/O port can be software programmed for

internal weak pull-up. Interrupt-on-change pin. Serial pro-

gramming clock.

RB7 13 13 14 I/O TTL/ST(2) Bi-directional I/O port can be software programmed for

internal weak pull-up. Interrupt-on-change pin. Serial pro-

gramming data.

RC0(3) 18 18 18 I/O TTL Bi-directional I/O port input buffer.

RC1(3) 19 19 19 I/O TTL Bi-directional I/O port input buffer.

RC2(3) 20 20 20 I/O TTL Bi-directional I/O port input buffer.

RC3(3) 21 21 21 I/O TTL Bi-directional I/O port input buffer.

RC4(3) 22 22 22 I/O TTL Bi-directional I/O port input buffer.

RC5(3) 23 23 23 I/O TTL Bi-directional I/O port input buffer.

RC6(3) 24 24 24 I/O TTL Bi-directional I/O port input buffer.

RC7(3) 25 25 25 I/O TTL Bi-directional I/O port input buffer.

VSS 5 5 5,6 P — Ground reference for logic and I/O pins.

VDD 14 14 15,16 P — Positive supply for logic and I/O pins.

Legend: O = Output I/O = Input/output P = Power

— = Not used I = Input ST = Schmitt Trigger input

TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: PIC16C557 only.

PIC16C55X

DS40143D-page 12 Preliminary  2002 Microchip Technology Inc.

3.1 Clocking Scheme/Instruction

Cycle

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the

program counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The

instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution flow are shown in Figure 3-2.

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register (IR)” in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clocks

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

 2002 Microchip Technology Inc. Preliminary DS40143D-page 13

PIC16C55X

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16C55X has a 13-bit program counter capable

of addressing an 8 K x 14 program memory space.

Only the first 512 x 14 (0000h - 01FFh) for the

PIC16C554 and 2K x 14 (0000h - 07FFh) for the

PIC16C557 and PIC16C558 are physically imple-

mented. Accessing a location above these boundaries

will cause a wrap-around within the first 512 x 14

spaces in the PIC16C554, or 2K x 14 space of the

PIC16C558 and PIC16C557. The RESET vector is at

0000h and the interrupt vector is at 0004h (Figure 4-1,

Figure 4-2).

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16C554

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16C557 AND

PIC16C558

4.2 Data Memory Organization

The data memory (Figure 4-3 through Figure 4-5) is

partitioned into two banks which contain the General

Purpose Registers (GPR) and the Special Function

Registers (SFR). Bank 0 is selected when the RP0 bit

(STATUS <5>) is cleared. Bank 1 is selected when the

RP0 bit is set. The Special Function Registers are

located in the first 32 locations of each Bank. Register

locations 20-6Fh (Bank 0) on the PIC16C554 and 20-

7Fh (Bank 0) and A0-BFh (Bank 1) on the PIC16C558

and PIC16C557 are General Purpose Registers imple-

mented as static RAM. Some special purpose registers

are mapped in Bank 1.

4.2.1 GENERAL PURPOSE REGISTER

FILE

The register file is organized as 80 x 8 in the

PIC16C554 and 128 x 8 in the PIC16C557 and

PIC16C558. Each can be accessed either directly or

indirectly through the File Select Register, FSR

(Section 4.4).

PC<12:0>

000h

0004

0005

01FFh

0200h

1FFFh

Stack Level 1

Stack Level 8

RESET Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

PC<12:0>

000h

0004

0005

07FFh

0800h

1FFFh

Stack Level 1

Stack Level 8

RESET Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

PIC16C55X

DS40143D-page 14 Preliminary  2002 Microchip Technology Inc.

FIGURE 4-3: DATA MEMORY MAP FOR

THE PIC16C554

FIGURE 4-4: DATA MEMORY MAP FOR

THE PIC16C557

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

INDF(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PCON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

General

Purpose

7Fh FFh

Bank 0 Bank 1

File

Address

6Fh

70h

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

File

Address

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

INDF(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PCON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

General

Purpose

7Fh FFh

Bank 0 Bank 1

File

Address

BFh

C0h

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

File

Address

General

Purpose

INDF(1)

PORTC TRISC

 2002 Microchip Technology Inc. Preliminary DS40143D-page 15

PIC16C55X

FIGURE 4-5: DATA MEMORY MAP FOR

THE PIC16C558

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (Table 4-1). These

registers are static RAM.

The Special Function Registers can be classified into

two sets (core and peripheral). The special function

registers associated with the “core” functions are

described in this section. Those related to the operation

of the peripheral features are described in the section

of that peripheral feature.

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

INDF(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PCON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

General

Purpose

7Fh FFh

Bank 0 Bank 1

File

Address

BFh

C0h

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

File

Address

General

Purpose

PIC16C55X

DS40143D-page 16 Preliminary  2002 Microchip Technology Inc.

TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16C55X

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Reset

Detail on

Page:

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a

physical register)

xxxx xxxx 21

01h TMR0 Timer0 Module’s Register xxxx xxxx 47

02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 21

03h STATUS IRP(2) RP1(2) RP0 TO PD ZDCC0001 1xxx 17

04h FSR Indirect data memory address pointer xxxx xxxx 21

05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x xxxx 23

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 25

07h PORTC(4) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 27

08h —Unimplemented — —

09h —Unimplemented — —

0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 21

0Bh INTCON GIE (3) T0IE INTE RBIE T0IF INTF RBIF 0000 000x 19

0Ch —Unimplemented — —

0Dh-1Eh — Unimplemented — —

1Fh —Unimplemented — —

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a

physical register)

xxxx xxxx 21

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 18

82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 21

83h STATUS ——RP0TOPD ZDCC0001 1xxx 17

84h FSR Indirect data memory address pointer xxxx xxxx 21

85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 23

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 25

87h TRISC(4) TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 27

88h —Unimplemented — —

89h —Unimplemented — —

8Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 21

8Bh INTCON GIE (3) T0IE INTE RBIE T0IF INTF RBIF 0000 000x 19

8Ch —Unimplemented — —

8Dh —Unimplemented — —

8Eh PCON — — — — — —POR—---- --0- 20

8Fh-9Eh —Unimplemented — —

9Fh —Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: IRP & RP1 bits are reserved, always maintain these bits clear.

3: Bit 6 of INTCON register is reserved for future use. Always maintain this bit as clear.

4: PIC16C557 only.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 17

PIC16C55X

4.2.2.1 STATUS Register

The STATUS register, shown in Figure 4-2, contains

the arithmetic status of the ALU, the RESET status and

the bank select bits for data memory.

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as the destination may be different

than intended.

For example, CLRF STATUS will clear the upper-three

bits and set the Z bit. This leaves the STATUS register

as 000uu1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions be used to alter the

STATUS register because these instructions do not

affect any status bits. For other instructions, not affect-

ing any status bits, see the “Instruction Set Summary”.

Note 1: The IRP and RP1 bits (STATUS<7:6>)

are not used by the PIC16C55X and

should be programmed as ’0'. Use of

these bits as general purpose R/W bits is

NOT recommended, since this may affect

upward compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit7 bit0

bit 7 IRP: Register Bank Select bit (used for Indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

The IRP bit is reserved on the PIC16C55X, always maintain this bit clear

bit 6-5 RP1:RP0: Register Bank Select bits (used for Direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C55X, always maintain this bit clear.

bit 4 TO: Timeout bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT timeout occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity is

reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the

source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16C55X

DS40143D-page 18 Preliminary  2002 Microchip Technology Inc.

4.2.2.2 OPTION Register

The OPTION register is a readable and writable

the TMR0/WDT prescaler, the external RB0/INT

interrupt, TMR0 and the weak pull-ups on PORTB.

Note 1: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT

(PSA = 1).

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit7 bit0

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

 2002 Microchip Technology Inc. Preliminary DS40143D-page 19

PIC16C55X

4.2.2.3 INTCON Register

The INTCON register is a readable and writable

for all interrupt sources.

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

R/W-0 Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE — T0IE INTE RBIE T0IF INTF RBIF

bit7 bit0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6 Reserved: For future use. Always maintain this bit clear.

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16C55X

DS40143D-page 20 Preliminary  2002 Microchip Technology Inc.

4.2.2.4 PCON Register

The PCON register contains a flag bit to differentiate

between a Power-on Reset, an external MCLR Reset

or WDT Reset. See Section 6.3 and Section 6.4 for

detailed RESET operation.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — —POR—

bit7 bit0

bit 7-2 Unimplemented: Read as '0'

bit 1 POR: Power-on Reset status bit

1 = No Power-on Reset occurred

0 = Power-on Reset occurred

bit 0 Unimplemented: Read as '0'

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. Preliminary DS40143D-page 21

PIC16C55X

4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high bits (PC<12:8>) are not

directly readable or writable and come from PCLATH.

On any RESET, the PC is cleared. Figure 4-6 shows

the two situations for the loading of the PC. The upper

example in the figure shows how the PC is loaded on a

write to PCL (PCLATH<4:0> → PCH). The lower exam-

ple in Figure 4-6 shows how the PC is loaded during a

CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-6: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256 byte block). Refer to the

application note “Implementing a Table Read" (AN556).

4.3.2 STACK

The PIC16C55X family has an 8-level deep x 13-bit

wide hardware stack (Figure 4-1 and Figure 4-2). The

stack space is not part of either program or data space

and the stack pointer is not readable or writable. The

PC is PUSHed onto the stack when a CALL instruction

is executed or an interrupt causes a branch. The stack

is POPed in the event of a RETURN, RETLW or a RET-

FIE instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

4.4 Indirect Addressing, INDF and

FSR Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF reg-

ister. Any instruction using the INDF register actually

accesses data pointed to by the file select register

(FSR). Reading INDF itself indirectly will produce 00h.

Writing to the INDF register indirectly results in a no-

operation (although status bits may be affected). An

effective 9-bit address is obtained by concatenating the

8-bit FSR register and the IRP bit (STATUS<7>), as

shown in Figure 4-7. However, IRP is not used in the

PIC16C55X.

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: INDIRECT ADDRESSING

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions, or vectoring to an interrupt

address.

movlw 0x20 ;initialize pointer

movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF registe

incf FSR ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;no clear next

;yes continue

CONTINUE:

PIC16C55X

DS40143D-page 22 Preliminary  2002 Microchip Technology Inc.

FIGURE 4-7: DIRECT/INDIRECT ADDRESSING PIC16C55X

For memory map detail see Figure 4-3 and Figure 4-5.

Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.

Data

Memory

Indirect AddressingDirect Addressing

bank select location select

(1)RP1 RP0 6 0

from opcode IRP(1) FSR register

bank select location select

00 01 10 11

00h

7Fh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

not used

 2002 Microchip Technology Inc. Preliminary DS40143D-page 23

PIC16C55X

5.0 I/O PORTS

The PIC16C554 and PIC16C558 have two ports,

PORTA and PORTB. The PIC16C557 has three ports,

PORTA, PORTB and PORTC.

5.1 PORTA and TRISA Registers

PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger

input and an open-drain output. Port RA4 is multiplexed

with the T0CKI clock input. All other RA port pins have

Schmitt Trigger input levels and full CMOS output driv-

ers. All pins have data direction bits (TRIS registers)

which can configure these pins as input or output.

A '1' in the TRISA register puts the corresponding out-

put driver in a Hi-impedance mode. A '0' in the TRISA

selected pin(s).

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch. All

write operations are read-modify-write operations. So a

write to a port implies that the port pins are first read,

then this value is modified and written to the port data

latch.

FIGURE 5-1: BLOCK DIAGRAM OF

PORT PINS RA<3:0>

FIGURE 5-2: BLOCK DIAGRAM OF RA4

Note 1: On RESET, the TRISA register is set to all

inputs.

Data

Bus

PORTA

TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

Schmitt

input

buffer

VSS

VDD

I/O pin

Trigger

VSS

VDD

Data

bus

PORTA

TRISA

RD PORTA

Data Latch

TRISA Latch

RD TRISA

Schmitt

Trigger

input

buffer

VSS

I/O pin(1)

TMR0 clock input

VSS

PIC16C55X

DS40143D-page 24 Preliminary  2002 Microchip Technology Inc.

TABLE 5-1: PORTA FUNCTIONS

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit # Buffer

Type Function

RA0 Bit 0 ST Bi-directional I/O port.

RA1 Bit 1 ST Bi-directional I/O port.

RA2 Bit 2 ST Bi-directional I/O port.

RA3 Bit 3 ST Bi-directional I/O port.

RA4/T0CKI Bit 4 ST Bi-directional I/O port or external clock input for TMR0. Output is open

drain type.

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

All Other

RESETS

05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu

85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

Legend: — = Unimplemented locations, read as ‘0’, x = unknown, u = unchanged

Note 1: Shaded bits are not used by PORTA.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 25

PIC16C55X

5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The

corresponding data direction register is TRISB. A '1' in

the TRISB register puts the corresponding output driver

in a Hi-impedance mode. A '0' in the TRISB register

puts the contents of the output latch on the selected

pin(s).

Reading PORTB register reads the status of the pins

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. So a write

to a port implies that the port pins are first read, then

this value is modified and written to the port data latch.

Each of the PORTB pins has a weak internal pull-up

(≈200 µA typical). A single control bit can turn on all the

pull-ups. This is done by clearing the RBPU

(OPTION<7>) bit. The weak pull-up is automatically

turned off when the port pin is configured as an output.

The pull-ups are disabled on Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt-on-

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RBIF interrupt (flag

latched in INTCON<0>). This interrupt can wake the

device from SLEEP. The user, in the interrupt service

routine, can clear the interrupt in the following manner:

• Any read or write of PORTB (this will end the mis-

match condition)

• Clear flag bit RBIF

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow flag bit RBIF to be cleared.

The interrupt on mismatch feature, together with

software configurable pull-ups on these four pins,

allows easy interface to a key pad and make it possible

for wake-up on key-depression. (See AN552 in the

Microchip Embedded Control Handbook.)

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

FIGURE 5-3: BLOCK DIAGRAM OF RB7:RB4 PINS

Note 1: If a change on the I/O pin should occur

when the read operation is being exe-

cuted (start of the Q2 cycle), then the

RBIF interrupt flag may not get set.

VSS

VDD

Data Latch

From other

RBPU(1)

VDD

I/O

Data Bus

WR PORTB

WR TRISB

Set RBIF

TRIS Latch

RD TRISB

RD PORTB

RB7:RB4 pins

weak

pull-up

RD PORTB

Latch

TTL

Input

Buffer

RB7:RB6 in Serial Programming mode

VDD

VSS

Note 1: TRISB = 1 enables weak pull-up if RBPU = ‘0’ (OPTION<7>).

PIC16C55X

DS40143D-page 26 Preliminary  2002 Microchip Technology Inc.

FIGURE 5-4: BLOCK DIAGRAM OF RB3:RB0 PINS

TABLE 5-3: PORTB FUNCTIONS

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB AND TRISB

Name Bit # Buffer Type Function

RB0/INT Bit 0 TTL/ST(1) Bi-directional I/O port. Internal software programmable weak pull-up.

RB1 Bit 1 TTL Bi-directional I/O port. Internal software programmable weak pull-up.

RB2 Bit 2 TTL Bi-directional I/O port. Internal software programmable weak pull-up.

RB3 Bit 3 TTL Bi-directional I/O port. Internal software programmable weak pull-up.

RB4 Bit 4 TTL Bi-directional I/O port (with interrupt-on-change). Internal software programmable

weak pull-up.

RB5 Bit 5 TTL Bi-directional I/O port (with interrupt-on-change). Internal software programmable

weak pull-up.

RB6 Bit 6 TTL/ST(2) Bi-directional I/O port (with interrupt-on-change). Internal software programmable

weak pull-up. Serial programming clock pin.

RB7 Bit 7 TTL/ST(2) Bi-directional I/O port (with interrupt-on-change). Internal software programmable

weak pull-up. Serial programming data pin.

Legend: ST = Schmitt Trigger, TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

All Other

RESETS

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

0BH, 8BH INTCON GIE Reserved T0IE INTE BRIE T0IF INTF RBIF 0000 000x 0000 000x

Legend: x = unknown, u = unchanged

Note 1: Shaded bits are not used by PORTB.

VSS

VDD

RBPU(1)

VDD

I/O

Data Bus

WR PORTB

WR TRISB

RD TRISB

RD PORTB

weak

pull-up

RD PORTB

Latch

TTL

Input

Buffer

RB0/INT

VDD

VSS

Buffer

Data Latch

TRIS Latch

Note 1: TRISB = 1 enables weak pull-up if RBPU = ‘0’ (OPTION<7>).

 2002 Microchip Technology Inc. Preliminary DS40143D-page 27

PIC16C55X

5.3 PORTC and TRISC Registers(1)

PORTC is a 8-bit wide latch. All pins have data direc-

tion bits (TRIS registers) which can configure these

pins as input or output.

A '1' in the TRISC register puts the corresponding out-

put driver in a Hi-impedance mode. A '0' in the TRISC

selected pin(s).

Reading the PORTC register reads the status of the

pins, whereas writing to it will write to the port latch. All

write operations are read-modify-write operations. So a

write to a port implies that the port pins are first read,

then this value is modified and written to the port data

latch

FIGURE 5-5: BLOCK DIAGRAM OF

PORT PINS RC<7:0>

TABLE 5-5: PORTC FUNCTIONS

TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC AND TRISC

Data

Bus

PORTC

Data Latch

TRIS Latch

RD TRISC

RD PORTC

VSS

VDD

I/O pin

VSS

VDD

TRISC

TTL

Input

Buffer

Name Bit # Buffer Type Function

RC0 Bit 0 TTL Bi-directional I/O port.

RC1 Bit 1 TTL Bi-directional I/O port.

RC2 Bit 2 TTL Bi-directional I/O port.

RC3 Bit 3 TTL Bi-directional I/O port.

RC4 Bit 4 TTL Bi-directional I/O port.

RC5 Bit 5 TTL Bi-directional I/O port.

RC6 Bit 6 TTL Bi-directional I/O port.

RC7 Bit 7 TTL Bi-directional I/O port.

Legend: ST = Schmitt Trigger, TTL = TTL input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

All Other

RESETS

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged

Note 1: PIC16C557 ONLY.

PIC16C55X

DS40143D-page 28 Preliminary  2002 Microchip Technology Inc.

5.4 I/O Programming Considerations

5.4.1 BI-DIRECTIONAL I/O PORTS

Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF

instructions, for example, read the register into the

CPU, execute the bit operation and write the result

back to the register. Caution must be used when these

instructions are applied to a port with both inputs and

outputs defined. For example, a BSF operation on bit5

of PORTB will cause all eight bits of PORTB to be read

into the CPU. Then the BSF operation takes place on

bit5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bi-directional I/O pin

(e.g., bit 0) and it is defined as an input at this time, the

input signal present on the pin itself would be read into

the CPU and re-written to the data latch of this

particular pin, overwriting the previous content. As long

as the pin stays in the Input mode, no problem occurs.

However, if bit 0 is switched into Output mode later on,

the content of the data latch may now be unknown.

Reading the port register, reads the values of the port

pins. Writing to the port register writes the value to the

port latch. When using read-modify-write instructions

(ex. BCF, BSF, etc.) on a port, the value of the port pins

is read, the desired operation is done to this value, and

this value is then written to the port latch.

Example 5-1 shows the effect of two sequential read-

modify-write instructions (ex., BCF,BSF, etc.) on an

I/O port.

A pin actively outputting a low or high should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-and”).

The resulting high output currents may damage

the chip.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 29

PIC16C55X

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT

5.4.2 SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle, as shown

in Figure 5-6. Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should be

such to allow the pin voltage to stabilize (load

dependent) before the next instruction which causes

that file to be read into the CPU is executed. Otherwise,

the previous state of that pin may be read into the CPU

rather than the new state. When in doubt, it is better to

separate these instructions with an NOP or another

instruction not accessing this I/O port.

FIGURE 5-6: SUCCESSIVE I/O OPERATION

; Initial PORT settings: PORTB<7:4> Inputs

;

; PORTB<3:0> Outputs

; PORTB<7:6> have external pull-up and are

; not connected to other circuitry

;

; PORT latch PORT pins

; ---------- ---------

;

BCF PORTB, 7 ; 01pp pppp 11pp pppp

BCF PORTB, 6 ; 10pp pppp 11pp pppp

BSF STATUS, RP0 ;

BCF TRISB, 7 ; 10pp pppp 11pp pppp

BCF TRISB, 6 ; 10pp pppp 10pp pppp

Note 1: This example shows write to PORTB followed by a read from PORTB.

2: Data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to

output valid. Therefore, at higher clock frequencies, a write followed by a read may be problematic.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RB <7:0>

Port pin

sampled here

PC PC + 1 PC + 2 PC + 3

NOPNOPMOVF PORTB, W

Read PORTB

MOVWF PORTB

Write to

PORTB

Instruction

fetched

Execute

MOVWF

PORTB

Execute

MOVF

PORTB, W

Execute

NOP

PIC16C55X

DS40143D-page 30 Preliminary  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. Preliminary DS40143D-page 31

PIC16C55X

6.0 SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other

processors are special circuits to deal with the needs of

real-time applications. The PIC16C55X family has a

host of such features intended to maximize system

reliability, minimize cost through elimination of external

components, provide power saving operating modes

and offer code protection.

These are:

1. OSC selection

2. RESET

3. Power-on Reset (POR)

4. Power-up Timer (PWRT)

5. Oscillator Start-Up Timer (OST)

6. Interrupts

7. Watchdog Timer (WDT)

8. SLEEP

9. Code protection

10. ID Locations

11. In-circuit serial programming™

The PIC16C55X has a Watchdog Timer which is

controlled by configuration bits. It runs off its own RC

oscillator for added reliability. There are two timers that

offer necessary delays on power-up. One is the

Oscillator Start-up Timer (OST), which is intended to

keep the chip in RESET until the crystal oscillator is sta-

ble. The other is the Power-up Timer (PWRT), which

provides a fixed delay of 72 ms (nominal) on power-up

only, designed to keep the part in RESET while the

power supply stabilizes. With these two functions on-

chip, most applications need no external RESET cir-

cuitry.

The SLEEP mode is designed to offer a very low

current Power-down mode. The user can wake-up from

SLEEP through external RESET, Watchdog Timer

wake-up or through an interrupt. Several oscillator

options are also made available to allow the part to fit

the application. The RC oscillator option saves system

cost while the LP crystal option saves power. A set of

configuration bits are used to select various options.

6.1 Configuration Bits

The configuration bits can be programmed (read as '0')

or left unprogrammed (read as '1') to select various

device configurations. These bits are mapped in

program memory location 2007h.

The user will note that address 2007h is beyond

the user program memory space. In fact, it belongs

to the special test/configuration memory space

(2000h – 3FFFh), which can be accessed only during

programming.

PIC16C55X

DS40143D-page 32 Preliminary  2002 Microchip Technology Inc.

CP1 CP0 CP1 CP0 CP1 CP0 —Reserved CP1 CP0 PWRTE WDTE F0SC1 F0SC0

bit 13 bit 0

bit 13-8

bit 5-4

CP<1:0>: Code protection bits(1)

11 = Program Memory code protection off

10 = 0400h - 07FFh code protected

01 = 0200h - 07FFh code protected

11 = 0000h - 07FFh code protected

bit 7 Unimplemented: Read as '1'

bit 6 Reserved: Do not use

bit 3 PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

bit 2 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0 FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. Preliminary DS40143D-page 33

PIC16C55X

6.2 Oscillator Configurations

6.2.1 OSCILLATOR TYPES

The PIC16C55X can be operated in four different

oscillator options. The user can program two

configuration bits (FOSC1 and FOSC0) to select one of

these four modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

6.2.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1 and OSC2 pins to establish

oscillation (Figure 6-1). The PIC16C55X oscillator

design requires the use of a parallel cut crystal. Use of

a series cut crystal may give a frequency out of the

crystal manufacturers specifications. When in XT, LP or

HS modes, the device can have an external clock

source to drive the OSC1 pin (Figure 6-2).

FIGURE 6-1: CRYSTAL OPERATION

(OR CERAMIC

RESONATOR) (HS, XT OR

LP OSC

CONFIGURATION)

FIGURE 6-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR

LP OSC

CONFIGURATION)

TABLE 6-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

(PRELIMINARY)

TABLE 6-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

(PRELIMINARY)

Note 1: A series resistor may be required for AT strip cut

crystals.

2: See Table 6-1 and Table 6-2 for recommended val-

ues of C1 and C2.

XTAL

OSC2

OSC1

RF SLEEP

To internal logic

PIC16C55X

Note 1

Clock from

ext. system

PIC16C55X

OSC1

OSC2

Open

Ranges Characterized:

Mode Freq OSC1(C1) OSC2(C2)

XT 455 kHz

2.0 MHz

4.0 MHz

22 - 100 pF

15 - 68 pF

22 - 100 pF

15 - 68 pF

HS 8.0 MHz

16.0 MHz

10 - 68 pF

10 - 22 pF

10 - 68 pF

10 - 22 pF

Note 1: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time. These values are for design

guidance only. Since each resonator has

its own characteristics, the user should

consult with the resonator manufacturer for

appropriate values of external compo-

nents.

Mode Freq OSC1(C1) OSC2(C2)

LP 32 kHz

200 kHz

68 - 100 pF

15 - 30 pF

68 - 100 pF

15 - 30 pF

XT 100 kHz

2 MHz

4 MHz

68 - 150 pF

15 - 30 pF

150 - 200 pF

15 - 30 pF

HS 8 MHz

10 MHz

20 MHz

15 - 30 pF

Note 1: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time. These values are for design

guidance only. Rs may be required in HS

mode as well as XT mode to avoid over-

driving crystals with low-drive level specifi-

cation. Since each crystal has its own

characteristics, the user should consult

with the crystal manufacturer for appropri-

ate values of external components.

PIC16C55X

DS40143D-page 34 Preliminary  2002 Microchip Technology Inc.

6.2.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Either a pre-packaged oscillator can be used or a sim-

ple oscillator circuit with TTL gates can be built.

Prepackaged oscillators provide a wide operating

range and better stability. A well-designed crystal

oscillator will provide good performance with TTL

gates. Two types of crystal oscillator circuits can be

used: one with series resonance, or one with parallel

resonance.

Figure 6-3 shows implementation of a parallel resonant

oscillator circuit. The circuit is designed to use the

fundamental frequency of the crystal. The 74AS04

inverter performs the 180° phase shift that a parallel

oscillator requires. The 4.7 kΩ resistor provides the

negative feedback for stability. The 10 kΩ

potentiometers bias the 74AS04 in the linear region.

This could be used for external oscillator designs.

FIGURE 6-3: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Figure 6-4 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a 180°

phase shift in a series resonant oscillator circuit. The

330Ω resistors provide the negative feedback to bias

the inverters in their linear region.

FIGURE 6-4: EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

6.2.4 RC OSCILLATOR

For timing insensitive applications the “RC” device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the

resistor (REXT) and capacitor (CEXT) values, and the

operating temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal

process parameter variation. Furthermore, the

difference in lead frame capacitance between package

types will also affect the oscillation frequency,

especially for low CEXT values. The user also needs to

take into account variation due to tolerance of external

R and C components used. Figure 6-5 shows how the

R/C combination is connected to the PIC16C55X. For

REXT values below 2.2 kΩ, the oscillator operation may

become unstable, or stop completely. For very high

REXT values (e.g., 1 MΩ), the oscillator becomes

sensitive to noise, humidity and leakage. Thus, we

recommend to keep REXT between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external

capacitor (CEXT = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin, and can be used for test

purposes or to synchronize other logic (Figure 3-2 for

waveform).

FIGURE 6-5: RC OSCILLATOR MODE

20 pF

+5V

20 pF

10k

4.7k

10k

74AS04

XTAL

10k

74AS04

PIC16C55X

CLKIN

To other

Devices

330Ω

74AS04 74AS04

PIC16C55X

CLKIN

To other

Devices

XTAL

330Ω

74AS04

0.1 µF

OSC2/CLKOUT

CEXT

REXT

VSS

PIC16C55X

OSC1

Fosc/4

Internal Clock

VDD

 2002 Microchip Technology Inc. Preliminary DS40143D-page 35

PIC16C55X

6.3 RESET

The PIC16C55X differentiates between various kinds

of RESET:

• Power-on Reset (POR)

•MCLR

Reset during normal operation

•MCLR

Reset during SLEEP

• WDT Reset (normal operation)

• WDT wake-up (SLEEP)

Some registers are not affected in any RESET condi-

tion; their status is unknown on POR and unchanged in

any other RESET. Most other registers are reset to a

“RESET state” on Power-on Reset, on MCLR or WDT

Reset and on MCLR Reset during SLEEP. They are not

affected by a WDT wake-up, since this is viewed as the

resumption of normal operation. TO and PD bits are set

or cleared differently in different RESET situations as

indicated in Table 6-4. These bits are used in software

to determine the nature of the RESET. See Table 6-6

for a full description of RESET states of all registers.

A simplified block diagram of the on-chip RESET circuit

is shown in Figure 6-6.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Table 10-3 for pulse width

specification.

FIGURE 6-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

VDD

OSC1/

WDT

Module

VDD rise

detect

OST/PWRT

On-chip(1)

RC OSC

WDT

Timeout

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Reset

Enable OST

Enable PWRT

SLEEP

See Table 6-3 for timeout situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

CLKIN

VPP Pin

10-bit Ripple-counter

PIC16C55X

DS40143D-page 36 Preliminary  2002 Microchip Technology Inc.

6.4 Power-on Reset (POR), Power-up

Timer (PWRT), Oscillator Start-up

Timer (OST)

6.4.1 POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.6V – 1.8V). To

take advantage of the POR, just tie the MCLR pin

through a resistor to VDD. This will eliminate external

RC components usually needed to create Power-on

Reset. A maximum rise time for VDD is required. See

Electrical Specifications for details.

The POR circuit does not produce internal RESET

when VDD declines.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in RESET until the operating con-

ditions are met.

For additional information, refer to Application Note

AN607 “Power-up Trouble Shooting”.

6.4.2 POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 72 ms (nominal)

timeout on power-up only, from POR. The Power-up

Timer operates on an internal RC oscillator. The chip is

kept in RESET as long as PWRT is active. The PWRT

delay allows the VDD to rise to an acceptable level. A

configuration bit, PWRTE can disable (if set) or enable

(if cleared or programmed) the Power-up Timer. The

Power-Up Time delay will vary from chip to chip and

due to VDD, temperature and process variation. See

DC parameters for details.

6.4.3 OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-Up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized.

The OST timeout is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

6.4.4 TIMEOUT SEQUENCE

On power-up, the timeout sequence is as follows: First

PWRT timeout is invoked after POR has expired, then

OST is activated. The total timeout will vary based on

oscillator configuration and PWRTE bit status. For

example, in RC mode with PWRTE bit erased (PWRT

disabled), there will be no timeout at all. Figure 6-7,

Figure 6-8 and Figure 6-9 depict timeout sequences.

Since the timeouts occur from the POR pulse, if MCLR

is kept low long enough, the timeouts will expire. Then

bringing MCLR high will begin execution immediately

(see Figure 6-8). This is useful for testing purposes or

to synchronize more than one PIC16C55X device oper-

ating in parallel.

Table 6-5 shows the RESET conditions for some spe-

cial registers, while Table 6-6 shows the RESET condi-

tions for all the registers.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 37

PIC16C55X

6.4.5 POWER CONTROL/STATUS

Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a subse-

quent RESET if POR is ‘0’, it will indicate that a Power-

on Reset must have occurred (VDD may have gone too

low).

TABLE 6-3: TIMEOUT IN VARIOUS SITUATIONS

TABLE 6-4: STATUS BITS AND THEIR SIGNIFICANCE

Oscillator

Configuration

Power-up Wake-up from

SLEEP

PWRTE = 0 PWRTE = 1

XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 1024 TOSC

RC 72 ms — —

POR TO PD

011Power-on Reset

00XIllegal, TO is set on POR

0X0Illegal, PD is set on POR

10uWDT Reset

100WDT Wake-up

1uuMCLR Reset during normal operation

110MCLR Reset during SLEEP

PIC16C55X

DS40143D-page 38 Preliminary  2002 Microchip Technology Inc.

TABLE 6-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

TABLE 6-6: INITIALIZATION CONDITION FOR REGISTERS

Condition Program

Counter

STATUS

PCON

Power-on Reset 000h 0001 1xxx ---- --0-

MCLR Reset during normal operation 000h 000u uuuu ---- --u-

MCLR Reset during SLEEP 000h 0001 0uuu ---- --u-

WDT Reset 000h 0000 uuuu ---- --u-

WDT Wake-up PC + 1 uuu0 0uuu ---- --u-

Interrupt Wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --u-

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the inter-

rupt vector (0004h) after execution of PC+1.

MCLR Reset during normal

operation

MCLR Reset during SLEEP

WDT Reset

Wake-up from SLEEP

through interrupt

Wake-up from SLEEP

through WDT timeout

W—xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h — — —

TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h 0000 0000 0000 0000 PC + 1(2)

STATUS 03h 0001 1xxx 000q quuu(3) uuuq quuu(3)

FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu

PORTA 05h ---x xxxx ---u uuuu ---u uuuu

PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu

PORTC(4) 06h xxxx xxxx uuuu uuuu uuuu uuuu

PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu

INTCON 0Bh 0000 000x 0000 000u uuuu uuuu(1)

OPTION 81h 1111 1111 1111 1111 uuuu uuuu

TRISA 85h ---1 1111 ---1 1111 ---u uuuu

TRISB 86h 1111 1111 1111 1111 uuuu uuuu

TRISC(4) 86h 1111 1111 1111 1111 uuuu uuuu

PCON 8Eh ---- --0- ---- --u- ---- --u-

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: One or more bits in INTCON will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

3: See Table 6-5 for RESET value for specific condition.

4: PIC16C557 only.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 39

PIC16C55X

FIGURE 6-7: TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 6-8: TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIMEOUT

OST TIMEOUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIMEOUT

OST TIMEOUT

INTERNAL RESET

TPWRT

TOST

PIC16C55X

DS40143D-page 40 Preliminary  2002 Microchip Technology Inc.

FIGURE 6-9: TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): CASE 3

FIGURE 6-10: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIMEOUT

OST TIMEOUT

INTERNAL RESET

Note 1: External Power-on Reset circuit is required only if

VDD power-up slope is too slow. The diode D helps

discharge the capacitor quickly when VDD powers

down.

2: < 40 kΩ is recommended to make sure that voltage

drop across R does not violate the device’s electrical

specification.

3: R1 = 100Ω to 1 kΩ will limit any current flowing into

MCLR from external capacitor C in the event of

MCLR/VPP pin breakdown due to Electrostatic Dis-

charge (ESD) or Electrical Overstress (EOS).

VDD

MCLR

PIC16C55X

VDD

 2002 Microchip Technology Inc. Preliminary DS40143D-page 41

PIC16C55X

6.5 Interrupts

The PIC16C55X has 3 sources of interrupt:

• External interrupt RB0/INT

• TMR0 overflow interrupt

• PORTB change interrupts (pins RB7:RB4)

The interrupt control register (INTCON) records

individual interrupt requests in flag bits. It also has

individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. GIE is cleared on RESET.

The “Return from Interrupt” instruction, RETFIE, exits

the interrupt routine as well as sets the GIE bit, which

re-enables RB0/INT interrupts.

The INT pin interrupt, the RB port change interrupt and

the TMR0 overflow interrupt flags are contained in the

INTCON register.

When an interrupt is responded to, the GIE is cleared

to disable any further interrupt, the return address is

pushed into the stack and the PC is loaded with 0004h.

Once in the interrupt service routine the source(s) of

the interrupt can be determined by polling the interrupt

flag bits. The interrupt flag bit(s) must be cleared in soft-

ware before re-enabling interrupts to avoid RB0/INT

recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs (Figure 6-12).

The latency is the same for one or two cycle

instructions. Once in the interrupt service routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid multiple interrupt requests. Individual interrupt

flag bits are set regardless of the status of their

corresponding mask bit or the GIE bit.

FIGURE 6-11: INTERRUPT LOGIC

Note 1: Individual interrupt flag bits are set

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The CPU will execute a NOP

in the cycle immediately following the

instruction which clears the GIE bit. The

interrupts which were ignored are still

pending to be serviced when the GIE bit

is set again.

RBIF

RBIE

T0IF

T0IE

INTF

INTE

GIE

Wake-up

(If in SLEEP mode)

Interrupt

to CPU

PIC16C55X

DS40143D-page 42 Preliminary  2002 Microchip Technology Inc.

6.5.1 RB0/INT INTERRUPT

An external interrupt on RB0/INT pin is edge triggered:

either rising if INTEDG bit (OPTION<6>) is set, or fall-

ing if INTEDG bit is clear. When a valid edge appears

on the RB0/INT pin, the INTF bit (INTCON<1>) is set.

This interrupt can be disabled by clearing the INTE

control bit (INTCON<4>). The INTF bit must be cleared

in software in the interrupt service routine before re-

enabling this interrupt. The RB0/INT interrupt can

wake-up the processor from SLEEP, if the INTE bit was

set prior to going into SLEEP. The status of the GIE bit

decides whether or not the processor branches to the

interrupt vector following wake-up. See Section 6.8 for

details on SLEEP and Figure 6-14 for timing of wake-

up from SLEEP through RB0/INT interrupt.

6.5.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

be enabled/disabled by setting/clearing T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 7.0.

6.5.3 PORTB INTERRUPT

An input change on PORTB <7:4> sets the RBIF

(INTCON<0>) bit. The interrupt can be enabled/dis-

abled by setting/clearing the RBIE (INTCON<4>) bit.

For operation of PORTB (Section 5.2).

FIGURE 6-12: INT PIN INTERRUPT TIMING

Note: If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF inter-

rupt flag may get set.

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

Interrupt Latency

PC PC+1 PC+1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycle

Inst (PC) Inst (PC+1)

Inst (PC-1) Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single

cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC Oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 43

PIC16C55X

6.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key reg-

isters during an interrupt (e.g., W register and STATUS

Example 6-1 stores and restores the STATUS and W

registers. The user register, W_TEMP, must be defined

in both banks and must be defined at the same offset

from the bank base address (i.e., W_TEMP is defined at

0x20 in Bank 0 and it must also be defined at 0xA0 in

Bank 1). The user register, STATUS_TEMP, must be

defined in Bank 0. The Example 6-1:

• Stores the W register

• Stores the STATUS register in Bank 0

• Executes the ISR code

• Restores the STATUS (and bank select bit

• Restores the W register

EXAMPLE 6-1: SAVING THE STATUS

AND W REGISTERS IN

RAM

6.7 Watchdog Timer (WDT)

The Watchdog Timer is a free running on-chip RC oscil-

lator which does not require any external components.

This RC oscillator is separate from the RC oscillator of

the CLKIN pin. That means that the WDT will run, even

if the clock on the OSC1 and OSC2 pins of the device

has been stopped, for example, by execution of a

SLEEP instruction. During normal operation, a WDT

timeout generates a device RESET. If the device is in

SLEEP mode, a WDT timeout causes the device to

wake-up and continue with normal operation. The WDT

can be permanently disabled by programming the con-

figuration bit WDTE as clear (Section 6.1).

6.7.1 WDT PERIOD

The WDT has a nominal timeout period of 18 ms, (with

no prescaler). The timeout periods vary with tempera-

ture, VDD and process variations from part-to-part (see

DC specs). If longer timeout periods are desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT under software control by writing

to the OPTION register. Thus, timeout periods up to 2.3

seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the postscaler, if assigned to the WDT, and prevent

it from timing out and generating a device RESET.

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer timeout.

6.7.2 WDT PROGRAMMING

CONSIDERATIONS

It should also be taken in account that under worst case

conditions (VDD = Min., Temperature = Max., max.

WDT prescaler) it may take several seconds before a

WDT timeout occurs.

MOVWF W_TEMP ;copy W to TEMP

;register, could be in

;either bank

SWAPF STATUS,W ;swap STATUS to be

;saved into W

BCF STATUS,RP0 ;change to bank0

;regardless of

;current bank

MOVWF STATUS_TEMP ;save STATUS to bank0

;register

SWAPF STATUS_TEMP,W;swap STATUS_TEMP

;register into W, sets

;bank to original state

MOVWF STATUS ;move W into STATUS

;register

SWAPF W_TEMP,F ;swap W_TEMP

SWAPF W_TEMP,W ;swap W_TEMP into W

PIC16C55X

DS40143D-page 44 Preliminary  2002 Microchip Technology Inc.

FIGURE 6-13: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 6-7: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all

other RESETS

2007h Config. bits —Reserved CP1 CP0 PWRTE WDTE FOSC1 FOSC0

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’.

Shaded cells are not used by the Watchdog Timer.

Postscaler

Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.

From TMR0 Clock Source

(Figure 7-6)

Watchdog

Timer

WDT

Enable Bit

PSA

8 - to - 1 MUX

PS<2:0>

To TMR0

(Figure 7-6)

PSA

WDT

Timeout

MUX

 2002 Microchip Technology Inc. Preliminary DS40143D-page 45

PIC16C55X

6.8 Power-Down Mode (SLEEP)

The Power-down mode is entered by executing a

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit in the STATUS register is

cleared, the TO bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before SLEEP was executed (driving high, low, or hi-

impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD, or VSS, with no external

circuitry drawing current from the I/O pin. I/O pins that

are hi-impedance inputs should be pulled high or low

externally to avoid switching currents caused by float-

ing inputs. The T0CKI input should also be at VDD or

VSS for lowest current consumption. The contribution

from on-chip pull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level (VIHMC).

6.8.1 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1. External RESET input on MCLR pin

2. Watchdog Timer Wake-up (if WDT was enabled)

3. Interrupt from RB0/INT pin or RB Port change

The first event will cause a device RESET. The two lat-

ter events are considered a continuation of program

execution. The TO and PD bits in the STATUS register

can be used to determine the cause of device RESET.

PD bit, which is set on power-up is cleared when

SLEEP is invoked. TO bit is cleared if WDT Wake-up

occurred.

When the SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake-up through an interrupt event, the correspond-

ing interrupt enable bit must be set (enabled). Wake-up

is regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have an NOP after the SLEEP instruction.

The WDT is cleared when the device wakes-up from

SLEEP, regardless of the source of wake-up.

FIGURE 6-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Note: It should be noted that a RESET generated

by a WDT timeout does not drive MCLR

pin low.

Note: If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the correspond-

ing interrupt flag bits set, the device will

immediately wake-up from SLEEP. The

SLEEP instruction is completely executed.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency(2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC+2

Note 1: XT, HS or LP Oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

PIC16C55X

DS40143D-page 46 Preliminary  2002 Microchip Technology Inc.

6.9 Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out for verification purposes.

6.10 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code-identification numbers. These locations are

not accessible during normal execution but are

readable and writable during program/verify.

6.11 In-Circuit Serial Programming™

The PIC16C55X microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground, and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

The device is placed into a Program/Verify mode by

holding the RB6 and RB7 pins low while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

specification). RB6 becomes the programming clock

and RB7 becomes the programming data. Both RB6

and RB7 are Schmitt Trigger inputs in this mode.

After RESET, to place the device into Programming/

Verify mode, the program counter (PC) is at location

00h. A 6-bit command is then supplied to the device.

Depending on the command, 14 bits of program data

are then supplied to or from the device, depending if

the command was a load or a read. For complete

details of serial programming, please refer to the

PIC16C6X/7X Programming Specifications (Literature

#DS30228).

A typical in-circuit serial programming connection is

shown in Figure 6-15.

FIGURE 6-15: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

Note: Microchip does not recommend code

protecting windowed devices. External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC16C55X

VDD

VSS

MCLR/VPP

RB6

RB7

+5V

VPP

CLK

Data I/O

VDD

 2002 Microchip Technology Inc. Preliminary DS40143D-page 47

PIC16C55X

7.0 TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 7-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the TMR0 will increment

every instruction cycle (without prescaler). If Timer0 is

written, the increment is inhibited for the following two

cycles (Figure 7-2 and Figure 7-3). The user can work

around this by writing an adjusted value to TMR0.

Counter mode is selected by setting the T0CS bit. In

this mode Timer0 will increment either on every rising

or falling edge of pin RA4/T0CKI. The incrementing

edge is determined by the source edge (T0SE) control

bit (OPTION<4>). Clearing the T0SE bit selects the

rising edge. Restrictions on the external clock input are

discussed in detail in Section 7.2.

The prescaler is shared between the Timer0 module

and the Watchdog Timer. The prescaler assignment is

controlled in software by the control bit PSA

(OPTION<3>). Clearing the PSA bit will assign the

prescaler to Timer0. The prescaler is not readable or

writable. When the prescaler is assigned to the Timer0

module, prescale value of 1:2, 1:4, ..., 1:256 are

selectable. Section 7.3 details the operation of the

prescaler.

7.1 TIMER0 Interrupt

Timer0 interrupt is generated when the TMR0 register

timer/counter overflows from FFh to 00h. This overflow

sets the T0IF bit. The interrupt can be masked by

clearing the T0IE bit (INTCON<5>). The T0IF bit

(INTCON<2>) must be cleared in software by the

Timer0 module interrupt service routine before re-

enabling this interrupt. The Timer0 interrupt cannot

wake the processor from SLEEP since the timer is shut

off during SLEEP. See Figure 7-4 for Timer0 interrupt

timing.

FIGURE 7-1: TIMER0 BLOCK DIAGRAM

FIGURE 7-2: TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER

Note 1: Bits, T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.

2: The prescaler is shared with Watchdog Timer (Figure 7-6)

RA4/T0CKI

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks

TMR0

PSout

(2 Tcy delay)

PSout

Data bus

Set Flag bit T0IF

on Overflow

PSA

PS2:PS0

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

PIC16C55X

DS40143D-page 48 Preliminary  2002 Microchip Technology Inc.

FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

FIGURE 7-4: TIMER0 INTERRUPT TIMING

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 Read TMR0

reads NT0 + 1

T0+1 NT0

Instruction

Execute

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

TMR0 timer

T0IF bit

(INTCON<2>)

FEh

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

PC PC +1 PC +1 0004h 0005h

Instruction

executed

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

FFh 00h 01h 02h

Interrupt Latency Time

Note 1: T0IF interrupt flag is sampled here (every Q1).

2: Interrupt latency = 4 TCY, where TCY = instruction cycle time.

3: CLKOUT is available only in RC Oscillator mode.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 49

PIC16C55X

7.2 Using Timer0 with External Clock

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

7.2.1 EXTERNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 7-5). Therefore, it is necessary for T0CKI to be

high for at least 2TOSC (and a small RC delay of 20 ns)

and low for at least 2TOSC (and a small RC delay of

20 ns). Refer to the electrical specification of the

desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type

prescaler so that the prescaler output is symmetrical.

For the external clock to meet the sampling

requirement, the ripple-counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4TOSC (and a small RC delay of 40 ns)

divided by the prescaler value. The only requirement

on T0CKI high and low time is that they do not violate

the minimum pulse width requirement of 10 ns. Refer to

parameters 40, 41 and 42 in the electrical specification

of the desired device.

7.2.2 TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the TMR0 is

actually incremented. Figure 7-5 shows the delay from

the external clock edge to the timer incrementing.

FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK

7.3 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer, respectively (Figure 7-6). For simplicity, this

counter is being referred to as “prescaler” throughout

this data sheet.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine

the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1,

MOVWF 1, BSF 1,x....etc.) will clear the prescaler.

When assigned to WDT, a CLRWDT instruction will clear

the prescaler along with the Watchdog Timer. The

prescaler is not readable or writable.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or

Prescaler output (2)

External Clock/Prescaler

Output after sampling

Increment Timer0 (Q4)

Timer0 T0 T0 + 1 T0 + 2

Small pulse

misses sampling

(3)

(1)

Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4 T

OSC max.

2: External clock if no prescaler selected, prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

Note: There is only one prescaler available

which is mutually exclusive between the

Timer0 module and the Watchdog Timer.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the Watchdog Timer, and

vice-versa.

PIC16C55X

DS40143D-page 50 Preliminary  2002 Microchip Technology Inc.

FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

T0CKI

T0SE

CLKOUT (=Fosc/4)

SYNC

Tcy

TMR0 reg

8-bit Prescaler

8-to-1MUX

M U X

Watchdog

Timer

PSA

WDT

Timeout

PS0 - PS2

PSA

WDT Enable bit

Data Bus

Set flag bit T0IF

on Overflow

PSA

T0CS

Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 51

PIC16C55X

7.3.1 SWITCHING PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

control (i.e., it can be changed “on the fly” during

program execution). To avoid an unintended device

RESET, the following instruction sequence

(Example 7-1) must be executed when changing the

prescaler assignment from Timer0 to WDT. Lines 5-7

are required only if the desired postscaler rate is 1:1

(PS<2:0> = 000) or 1:2 (PS<2:0> = 001).

EXAMPLE 7-1: CHANGING PRESCALER

(TIMER0→WDT)

To change prescaler from the WDT to the TMR0

module use the sequence shown in Example 7-2. This

precaution must be taken even if the WDT is disabled.

EXAMPLE 7-2: CHANGING PRESCALER

(WDT→TIMER0)

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0

BCF STATUS, RP0 ;Skip if already in

;Bank 0 CLRWDT Clear WDT

CLRF TMR0 ;Clear TMR0 & Prescaler

BSF STATUS, RP0 ;Bank 1

MOVLW '00101111’b ;These 3 lines (5, 6, 7)

MOVWF OPTION ;Are required only if

;Desired PS<2:0> are

;CLRWDT 000 or 001

MOVLW '00101xxx’b ;Set Postscaler to

MOVWF OPTION ;Desired WDT rate

BCF STATUS, RP0 ;Return to Bank 0

CLRWDT ;Clear WDT and

;prescaler

BSF STATUS, RP0

MOVLW b'xxxx0xxx' ;Select TMR0, new

;prescale value and

;clock source

MOVWF OPTION

BCF STATUS, RP0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

All Other

RESETS

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

0Bh/8Bh INTCON GIE Reserved T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

Legend: — = Unimplemented locations, read as ‘0’,

Note 1: Shaded bits are not used by TMR0 module.

PIC16C55X

DS40143D-page 52 Preliminary  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. Preliminary DS40143D-page 53

PIC16C55X

8.0 INSTRUCTION SET SUMMARY

Each PIC16C55X instruction is a 14-bit word divided

into an OPCODE which specifies the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC16C55X instruc-

tion set summary in Table 8-2 lists byte-oriented, bit-

oriented, and literal and control operations. Table 8-

1 shows the opcode field descriptions.

For byte-oriented instructions, 'f' represents a file

designator. The file register designator specifies which

file register is to be used by the instruction.

The destination designator specifies where the result of

the operation is to be placed. If 'd' is zero, the result is

placed in the W register. If 'd' is one, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, 'b' represents a bit field

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

file in which the bit is located.

For literal and control operations, 'k' represents an

eight or eleven bit constant or literal value.

TABLE 8-1: OPCODE FIELD

DESCRIPTIONS

The instruction set is highly orthogonal and is grouped

into three basic categories:

•Byte-oriented operations

•Bit-oriented operations

•Literal and control operations

All instructions are executed within one single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of an

instruction. In this case, the execution takes two

instruction cycles with the second cycle executed as a

NOP. One instruction cycle consists of four oscillator

periods. Thus, for an oscillator frequency of 4 MHz, the

normal instruction execution time is 1 µs. If a

conditional test is true or the program counter is

changed as a result of an instruction, the instruction

execution time is 2 µs.

Table 8-1 lists the instructions recognized by the

MPASM™ assembler.

Figure 8-1 shows the three general formats that the

instructions can have.

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signifies a hexadecimal digit.

FIGURE 8-1: GENERAL FORMAT FOR

INSTRUCTIONS

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral field, constant data or label

xDon't care location (= 0 or 1)

The assembler will generate code with x = 0. It

is the recommended form of use for compatibil-

ity with all Microchip software tools.

dDestination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1

label Label name

TOS Top of Stack

PC Program Counter

PCLATH Program Counter High Latch

GIE Global Interrupt Enable bit

WDT Watchdog Timer/Counter

TO Timeout bit

PD Power-down bit

dest Destination either the W register or the specified

[ ] Options

( ) Contents

→Assigned to

< > Register bit field

∈In the set of

italics User defined term (font is courier)

Note: To maintain upward compatibility with

future PICmicro® products, do not use the

OPTION and TRIS instructions.

Byte-oriented file register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

PIC16C55X

DS40143D-page 54 Preliminary  2002 Microchip Technology Inc.

TABLE 8-2: PIC16C55X INSTRUCTION SET

Mnemonic,

Operands Description Cycles

14-Bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0000

dfff

lfff

0xx0

dfff

ffff

0011

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1(2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external

device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 Module.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 55

PIC16C55X

8.1 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [ label ] ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → (W)

Status Affected: C, DC, Z

Encoding: 11 111x kkkk kkkk

Description: The contents of the W register are

added to the eight bit literal 'k' and the

result is placed in the W register.

Words: 1

Cycles: 1

Example ADDLW 0x15

Before Instruction

W = 0x10

After Instruction

W = 0x25

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) + (f) → (dest)

Status Affected: C, DC, Z

Encoding: 00 0111 dfff ffff

Description: Add the contents of the W register

with register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

Words: 1

Cycles: 1

Example ADDWF FSR, 0

Before Instruction

W = 0x17

FSR = 0xC2

After Instruction

W=0xD9

FSR = 0xC2

ANDLW AND Literal with W

Syntax: [ label ] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. (k) → (W)

Status Affected: Z

Encoding: 11 1001 kkkk kkkk

Description: The contents of W register are

AND’ed with the eight bit literal 'k'. The

result is placed in the W register.

Words: 1

Cycles: 1

Example ANDLW 0x5F

Before Instruction

W=0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .AND. (f) → (dest)

Status Affected: Z

Encoding: 00 0101 dfff ffff

Description: AND the W register with register 'f'. If

'd' is 0 the result is stored in the W

back in register 'f'.

Words: 1

Cycles: 1

Example ANDWF FSR, 1

Before Instruction

W= 0x17

FSR = 0xC2

After Instruction

W=0x17

FSR = 0x02

PIC16C55X

DS40143D-page 56 Preliminary  2002 Microchip Technology Inc.

BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

Status Affected: None

Encoding: 01 00bb bfff ffff

Description: Bit 'b' in register 'f' is cleared.

Words: 1

Cycles: 1

Example BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

Status Affected: None

Encoding: 01 01bb bfff ffff

Description: Bit 'b' in register 'f' is set.

Words: 1

Cycles: 1

Example BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Status Affected: None

Encoding: 01 10bb bfff ffff

Description: If bit 'b' in register 'f' is '0' then the next

instruction is skipped. If bit 'b' is '0' then

the next instruction fetched during the

current instruction execution is dis-

carded, and a NOP is executed instead,

making this a two-cycle instruction.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSC

GOTO

•

FLAG,1

PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0,

PC = address TRUE

if FLAG<1> = 1,

PC = address FALSE

 2002 Microchip Technology Inc. Preliminary DS40143D-page 57

PIC16C55X

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Encoding: 01 11bb bfff ffff

Description: If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and a NOP is

executed instead, making this a two-

cycle instruction.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSS

GOTO

•

FLAG,1

PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0,

PC = address FALSE

if FLAG<1> = 1,

PC = address TRUE

CALL Call Subroutine

Syntax: [ label ] CALL k

Operands: 0 ≤ k ≤ 2047

Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected: None

Encoding: 10 0kkk kkkk kkkk

Description: Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is

loaded into PC bits <10:0>. The upper

bits of the PC are loaded from

PCLATH. CALL is a two-cycle instruc-

tion.

Words: 1

Cycles: 2

Example HERE CALL THERE

Before Instruction

PC = Address HERE

After Instruction

PC = Address THERE

TOS = Address HERE+1

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0 ≤ f ≤ 127

Operation: 00h → (f)

1 → Z

Status Affected: Z

Encoding: 00 0001 1fff ffff

Description: The contents of register 'f' are cleared

and the Z bit is set.

Words: 1

Cycles: 1

Example CLRF FLAG_REG

Before Instruction

FLAG_REG=0x5A

After Instruction

FLAG_REG=0x00

Z=1

PIC16C55X

DS40143D-page 58 Preliminary  2002 Microchip Technology Inc.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h → (W)

1 → Z

Status Affected: Z

Encoding: 00 0001 0000 0011

Description: W register is cleared. Zero bit (Z) is

set.

Words: 1

Cycles: 1

Example CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00

Z=1

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0100

Description: CLRWDT instruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT. Status bits TO

and PD are set.

Words: 1

Cycles: 1

Example CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00

WDT prescaler = 0

TO =1

PD =1

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 00 1001 dfff ffff

Description: The contents of register 'f' are

complemented. If 'd' is 0 the result is

stored in W. If 'd' is 1 the result is

stored back in register 'f'.

Words: 1

Cycles: 1

Example COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13

W = 0xEC

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (dest)

Status Affected: Z

Encoding: 00 0011 dfff ffff

Description: Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Words: 1

Cycles: 1

Example DECF CNT, 1

Before Instruction

CNT = 0x01

Z=0

After Instruction

CNT = 0x00

Z=1

 2002 Microchip Technology Inc. Preliminary DS40143D-page 59

PIC16C55X

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (dest); skip if result = 0

Status Affected: None

Encoding: 00 1011 dfff ffff

Description: The contents of register 'f' are

decremented. If 'd' is 0 the result is

placed in the W register. If 'd' is 1 the

result is placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded.

A NOP is executed instead making it a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Example HERE DECFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT - 1

if CNT = 0,

PC = address CONTINUE

if CNT ≠0,

PC = address HERE+1

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 2047

Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Status Affected: None

Encoding: 10 1kkk kkkk kkkk

Description: GOTO is an unconditional branch. The

eleven bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTO is a two-cycle instruction.

Words: 1

Cycles: 2

Example GOTO THERE

After Instruction

PC = Address THERE

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest)

Status Affected: Z

Encoding: 00 1010 dfff ffff

Description: The contents of register 'f' are

incremented. If 'd' is 0 the result is

placed in the W register. If 'd' is 1 the

result is placed back in register 'f'.

Words: 1

Cycles: 1

Example INCF CNT, 1

Before Instruction

CNT = 0xFF

Z=0

After Instruction

CNT = 0x00

Z=1

PIC16C55X

DS40143D-page 60 Preliminary  2002 Microchip Technology Inc.

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest), skip if result = 0

Status Affected: None

Encoding: 00 1111 dfff ffff

Description: The contents of register 'f' are

incremented. If 'd' is 0 the result is

placed in the W register. If 'd' is 1 the

result is placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded.

A NOP is executed instead making it a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Example HERE INCFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT + 1

if CNT = 0,

PC = address CONTINUE

if CNT ≠0,

PC = address HERE +1

IORLW Inclusive OR Literal with W

Syntax: [ label ] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → (W)

Status Affected: Z

Encoding: 11 1000 kkkk kkkk

Description: The contents of the W register is

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Words: 1

Cycles: 1

Example IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W=0xBF

Z=1

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .OR. (f) → (dest)

Status Affected: Z

Encoding: 00 0100 dfff ffff

Description: Inclusive OR the W register with

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1

Cycles: 1

Example IORWF RESULT, 0

Before Instruction

RESULT = 0x13

W = 0x91

After Instruction

RESULT = 0x13

W = 0x93

Z=1

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Encoding: 11 00xx kkkk kkkk

Description: The eight bit literal 'k' is loaded into W

as 0’s.

Words: 1

Cycles: 1

Example MOVLW 0x5A

After Instruction

W=0x5A

 2002 Microchip Technology Inc. Preliminary DS40143D-page 61

PIC16C55X

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 00 1000 dfff ffff

Description: The contents of register f is

moved to a destination dependant

upon the status of d. If d = 0, des-

tination is W register. If d = 1, the

destination is file register f itself. d

= 1 is useful to test a file register

since status flag Z is affected.

Words: 1

Cycles: 1

Example MOVF FSR, 0

After Instruction

W = value in FSR register

Z= 1

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0 ≤ f ≤ 127

Operation: (W) → (f)

Status Affected: None

Encoding: 00 0000 1fff ffff

Description: Move data from W register to register

'f'.

Words: 1

Cycles: 1

Example MOVWF OPTION

Before Instruction

OPTION = 0xFF

W = 0x4F

After Instruction

OPTION = 0x4F

W = 0x4F

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation

Status Affected: None

Encoding: 00 0000 0xx0 0000

Description: No operation.

Words: 1

Cycles: 1

Example NOP

OPTION Load Option Register

Syntax: [ label ] OPTION

Operands: None

Operation: (W) → OPTION

Status Affected: None

Encoding: 00 0000 0110 0010

Description: The contents of the W register are

loaded in the OPTION register. This

instruction is supported for code

compatibility with PIC16C5X products.

Since OPTION is a readable/writable

address it.

Words: 1

Cycles: 1

Example

To maintain upward compatibility

with future PICmicro™ products, do

not use this instruction.

PIC16C55X

DS40143D-page 62 Preliminary  2002 Microchip Technology Inc.

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE

Operands: None

Operation: TOS → PC,

1 → GIE

Status Affected: None

Encoding: 00 0000 0000 1001

Description: Return from Interrupt. Stack is POPed

and Top of Stack (TOS) is loaded in

the PC. Interrupts are enabled by

setting Global Interrupt Enable bit,

GIE (INTCON<7>). This is a two-cycle

instruction.

Words: 1

Cycles: 2

Example RETFIE

After Interrupt

PC = TOS

GIE = 1

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Encoding: 11 01xx kkkk kkkk

Description: The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two-cycle

instruction.

Words: 1

Cycles: 2

Example

TABLE

CALL TABLE;W contains table

;offset value

•;W now has table

value

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS → PC

Status Affected: None

Encoding: 00 0000 0000 1000

Description: Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a two-cycle instruction.

Words: 1

Cycles: 2

Example RETURN

After Interrupt

PC = TOS

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 00 1101 dfff ffff

Description: The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

stored back in register 'f'.

Words: 1

Cycles: 1

Example RLF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W= 1100 1100

C=1

 2002 Microchip Technology Inc. Preliminary DS40143D-page 63

PIC16C55X

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 00 1100 dfff ffff

Description: The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1

Cycles: 1

Example RRF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W= 0111 0011

C=0

SLEEP

Syntax: [ label

]

SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT prescaler,

1 → TO,

0 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0011

Description: The power-down status bit, PD is

cleared. Timeout status bit, TO is

set. Watchdog Timer and its

prescaler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

See Section 6.8 for more details.

Words: 1

Cycles: 1

Example: SLEEP

SUBLW Subtract W from Literal

Syntax: [ label ]SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k - (W) → (W)

Status

Affected:

C, DC, Z

Encoding: 11 110x kkkk kkkk

Description: The W register is subtracted (2’s com-

plement method) from the eight bit literal

'k'. The result is placed in the W register.

Words: 1

Cycles: 1

Example 1: SUBLW 0x02

Before Instruction

W=1

C=?

After Instruction

W=1

C = 1; result is positive

Example 2: Before Instruction

W=2

C=?

After Instruction

W=0

C = 1; result is zero

Example 3: Before Instruction

W=3

C=?

After Instruction

W=0xFF

C = 0; result is nega-

tive

PIC16C55X

DS40143D-page 64 Preliminary  2002 Microchip Technology Inc.

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - (W) → (dest)

Status

Affected:

C, DC, Z

Encoding: 00 0010 dfff ffff

Description: Subtract (2’s complement method)

W register from register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is 1

the result is stored back in register 'f'.

Words: 1

Cycles: 1

Example 1: SUBWF REG1,1

Before Instruction

REG1 = 3

W=2

C=?

After Instruction

REG1 = 1

W=2

C = 1; result is positive

Example 2: Before Instruction

REG1 = 2

W=2

C=?

After Instruction

REG1 = 0

W=2

C = 1; result is zero

Example 3: Before Instruction

REG1 = 1

W=2

C=?

After Instruction

REG1 = 0xFF

W=2

C = 0; result is negative

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>)

Status Affected: None

Encoding: 00 1110 dfff ffff

Description: The upper and lower nibbles of

the result is placed in W register. If 'd'

is 1 the result is placed in register 'f'.

Words: 1

Cycles: 1

Example SWAPF REG, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5

W = 0x5A

TRIS Load TRIS Register

Syntax: [ label ] TRIS f

Operands: 5 ≤ f ≤ 7

Operation: (W) → TRIS register f;

Status Affected: None

Encoding: 00 0000 0110 0fff

Description: The instruction is supported for code

compatibility with the PIC16C5X

products. Since TRIS registers are

readable and writable, the user can

directly address them.

Words: 1

Cycles: 1

Example

To maintain upward compatibility

with future PICmicro™ products, do

not use this instruction.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 65

PIC16C55X

XORLW Exclusive OR Literal with W

Syntax: [ label ]XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Encoding: 11 1010 kkkk kkkk

Description: The contents of the W register are

XOR’ed with the eight bit literal 'k'.

The result is placed in the W register.

Words: 1

Cycles: 1

Example: XORLW 0xAF

Before Instruction

W = 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .XOR. (f) → (dest)

Status Affected: Z

Encoding: 00 0110 dfff ffff

Description: Exclusive OR the contents of the

W register with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Words: 1

Cycles: 1

Example XORWF REG 1

Before Instruction

REG = 0xAF

W=0xB5

After Instruction

REG = 0x1A

W=0xB5

PIC16C55X

DS40143D-page 66 Preliminary  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. Preliminary DS40143D-page 67

PIC16C55X

9.0 DEVELOPMENT SUPPORT

The PICmicro® microcontrollers are supported with a

full range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

-MPASM

TM Assembler

- MPLAB C17 and MPLAB C18 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

• Simulators

- MPLAB SIM Software Simulator

• Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- ICEPIC™ In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD

• Device Programmers

-PRO MATE

® II Universal Device Programmer

- PICSTART® Plus Entry-Level Development

Programmer

• Low Cost Demonstration Boards

- PICDEMTM 1 Demonstration Board

- PICDEM 2 Demonstration Board

- PICDEM 3 Demonstration Board

- PICDEM 17 Demonstration Board

-K

EELOQ® Demonstration Board

9.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. The MPLAB IDE is a Windows®-based

application that contains:

• An interface to debugging tools

- simulator

- programmer (sold separately)

- emulator (sold separately)

- in-circuit debugger (sold separately)

• A full-featured editor

• A project manager

• Customizable toolbar and key mapping

• A status bar

• On-line help

The MPLAB IDE allows you to:

• Edit your source files (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro emulator and simulator tools (auto-

matically updates all project information)

• Debug using:

- source files

- absolute listing file

- machine code

The ability to use MPLAB IDE with multiple debugging

tools allows users to easily switch from the cost-

effective simulator to a full-featured emulator with

minimal retraining.

9.2 MPASM Assembler

The MPASM assembler is a full-featured universal

macro assembler for all PICmicro MCU’s.

The MPASM assembler has a command line interface

and a Windows shell. It can be used as a stand-alone

application on a Windows 3.x or greater system, or it

can be used through MPLAB IDE. The MPASM assem-

bler generates relocatable object files for the MPLINK

object linker, Intel® standard HEX files, MAP files to

detail memory usage and symbol reference, an abso-

lute LST file that contains source lines and generated

machine code, and a COD file for debugging.

The MPASM assembler features include:

• Integration into MPLAB IDE projects.

• User-defined macros to streamline assembly

code.

• Conditional assembly for multi-purpose source

files.

• Directives that allow complete control over the

assembly process.

9.3 MPLAB C17 and MPLAB C18

C Compilers

The MPLAB C17 and MPLAB C18 Code Development

Systems are complete ANSI ‘C’ compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microcontrollers, respectively. These compilers provide

powerful integration capabilities and ease of use not

found with other compilers.

For easier source level debugging, the compilers pro-

vide symbol information that is compatible with the

MPLAB IDE memory display.

PIC16C55X

DS40143D-page 68 Preliminary  2002 Microchip Technology Inc.

9.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can also

link relocatable objects from pre-compiled libraries,

using directives from a linker script.

The MPLIB object librarian is a librarian for pre-

compiled code to be used with the MPLINK object

linker. When a routine from a library is called from

another source file, only the modules that contain that

routine will be linked in with the application. This allows

large libraries to be used efficiently in many different

applications. The MPLIB object librarian manages the

creation and modification of library files.

The MPLINK object linker features include:

• Integration with MPASM assembler and MPLAB

C17 and MPLAB C18 C compilers.

• Allows all memory areas to be defined as sections

to provide link-time flexibility.

The MPLIB object librarian features include:

• Easier linking because single libraries can be

included instead of many smaller files.

• Helps keep code maintainable by grouping

related modules together.

• Allows libraries to be created and modules to be

added, listed, replaced, deleted or extracted.

9.5 MPLAB SIM Software Simulator

The MPLAB SIM software simulator allows code devel-

opment in a PC-hosted environment by simulating the

PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user-defined key press, to any of the pins. The

execution can be performed in single step, execute

until break, or Trace mode.

The MPLAB SIM simulator fully supports symbolic

debugging using the MPLAB C17 and the MPLAB C18

C compilers and the MPASM assembler. The software

simulator offers the flexibility to develop and debug

code outside of the laboratory environment, making it

an excellent multi-project software development tool.

9.6 MPLAB ICE High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLAB ICE universal in-circuit emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PICmicro

microcontrollers (MCUs). Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment (IDE),

which allows editing, building, downloading and source

debugging from a single environment.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

features. Interchangeable processor modules allow the

system to be easily re configured for emulation of differ-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE in-circuit emulator system has been

designed as a real-time emulation system, with

advanced features that are generally found on more

expensive development tools. The PC platform and

Microsoft® Windows environment were chosen to best

make these features available to you, the end user.

9.7 ICEPIC In-Circuit Emulator

The ICEPIC low cost, in-circuit emulator is a solution

for the Microchip Technology PIC16C5X, PIC16C6X,

PIC16C7X and PIC16CXXX families of 8-bit One-

Time-Programmable (OTP) microcontrollers. The mod-

ular system can support different subsets of PIC16C5X

or PIC16CXXX products through the use of inter-

changeable personality modules, or daughter boards.

The emulator is capable of emulating without target

application circuitry being present.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 69

PIC16C55X

9.8 MPLAB ICD In-Circuit Debugger

Microchip's In-Circuit Debugger, MPLAB ICD, is a pow-

erful, low cost, run-time development tool. This tool is

based on the FLASH PICmicro MCUs and can be used

to develop for this and other PICmicro microcontrollers.

The MPLAB ICD utilizes the in-circuit debugging capa-

bility built into the FLASH devices. This feature, along

with Microchip's In-Circuit Serial ProgrammingTM proto-

col, offers cost-effective in-circuit FLASH debugging

from the graphical user interface of the MPLAB

Integrated Development Environment. This enables a

designer to develop and debug source code by watch-

ing variables, single-stepping and setting break points.

Running at full speed enables testing hardware in real-

time.

9.9 PRO MATE II Universal Device

Programmer

The PRO MATE II universal device programmer is a

full-featured programmer, capable of operating in

Stand-alone mode, as well as PC-hosted mode. The

PRO MATE II device programmer is CE compliant.

The PRO MATE II device programmer has program-

mable VDD and VPP supplies, which allow it to verify

programmed memory at VDD min and VDD max for max-

imum reliability. It has an LCD display for instructions

and error messages, keys to enter commands and a

modular detachable socket assembly to support various

package types. In Stand-alone mode, the PRO MATE II

device programmer can read, verify, or program

PICmicro devices. It can also set code protection in this

mode.

9.10 PICSTART Plus Entry Level

Development Programmer

The PICSTART Plus development programmer is an

easy-to-use, low cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient.

The PICSTART Plus development programmer sup-

ports all PICmicro devices with up to 40 pins. Larger pin

count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus development programmer is CE

compliant.

9.11 PICDEM 1 Low Cost PICmicro

Demonstration Board

The PICDEM 1 demonstration board is a simple board

which demonstrates the capabilities of several of

Microchip’s microcontrollers. The microcontrollers sup-

ported are: PIC16C5X (PIC16C54 to PIC16C58A),

PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,

PIC17C42, PIC17C43 and PIC17C44. All necessary

hardware and software is included to run basic demo

programs. The user can program the sample microcon-

trollers provided with the PICDEM 1 demonstration

board on a PRO MATE II device programmer, or a

PICSTART Plus development programmer, and easily

test firmware. The user can also connect the

PICDEM 1 demonstration board to the MPLAB ICE in-

circuit emulator and download the firmware to the emu-

lator for testing. A prototype area is available for the

user to build some additional hardware and connect it

to the microcontroller socket(s). Some of the features

include an RS-232 interface, a potentiometer for simu-

lated analog input, push button switches and eight

LEDs connected to PORTB.

9.12 PICDEM 2 Low Cost PIC16CXX

Demonstration Board

The PICDEM 2 demonstration board is a simple dem-

onstration board that supports the PIC16C62,

PIC16C64, PIC16C65, PIC16C73 and PIC16C74

microcontrollers. All the necessary hardware and soft-

ware is included to run the basic demonstration pro-

grams. The user can program the sample

microcontrollers provided with the PICDEM 2 demon-

stration board on a PRO MATE II device programmer,

or a PICSTART Plus development programmer, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may also be used with the PICDEM 2 demonstration

board to test firmware. A prototype area has been pro-

vided to the user for adding additional hardware and

connecting it to the microcontroller socket(s). Some of

the features include a RS-232 interface, push button

switches, a potentiometer for simulated analog input, a

serial EEPROM to demonstrate usage of the I2CTM bus

and separate headers for connection to an LCD

module and a keypad.

PIC16C55X

DS40143D-page 70 Preliminary  2002 Microchip Technology Inc.

9.13 PICDEM 3 Low Cost PIC16CXXX

Demonstration Board

The PICDEM 3 demonstration board is a simple dem-

onstration board that supports the PIC16C923 and

PIC16C924 in the PLCC package. It will also support

future 44-pin PLCC microcontrollers with an LCD Mod-

ule. All the necessary hardware and software is

included to run the basic demonstration programs. The

user can program the sample microcontrollers pro-

vided with the PICDEM 3 demonstration board on a

PRO MATE II device programmer, or a PICSTART Plus

development programmer with an adapter socket, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may also be used with the PICDEM 3 demonstration

board to test firmware. A prototype area has been pro-

vided to the user for adding hardware and connecting it

to the microcontroller socket(s). Some of the features

include a RS-232 interface, push button switches, a

potentiometer for simulated analog input, a thermistor

and separate headers for connection to an external

LCD module and a keypad. Also provided on the

PICDEM 3 demonstration board is a LCD panel, with 4

commons and 12 segments, that is capable of display-

ing time, temperature and day of the week. The

PICDEM 3 demonstration board provides an additional

RS-232 interface and Windows software for showing

the demultiplexed LCD signals on a PC. A simple serial

interface allows the user to construct a hardware

demultiplexer for the LCD signals.

9.14 PICDEM 17 Demonstration Board

The PICDEM 17 demonstration board is an evaluation

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. All neces-

sary hardware is included to run basic demo programs,

which are supplied on a 3.5-inch disk. A programmed

sample is included and the user may erase it and

program it with the other sample programs using the

PRO MATE II device programmer, or the PICSTART

Plus development programmer, and easily debug and

test the sample code. In addition, the PICDEM 17 dem-

onstration board supports downloading of programs to

and executing out of external FLASH memory on board.

The PICDEM 17 demonstration board is also usable

with the MPLAB ICE in-circuit emulator, or the

PICMASTER emulator and all of the sample programs

can be run and modified using either emulator. Addition-

ally, a generous prototype area is available for user

hardware.

9.15 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microchip’s HCS Secure Data Products. The HCS eval-

uation kit includes a LCD display to show changing

codes, a decoder to decode transmissions and a pro-

gramming interface to program test transmitters.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 71

PIC16C55X

TABLE 9-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12CXXX

PIC14000

PIC16C5X

PIC16C6X

PIC16CXXX

PIC16F62X

PIC16C7X

PIC16C7XX

PIC16C8X

PIC16F8XX

PIC16C9XX

PIC17C4X

PIC17C7XX

PIC18CXX2

PIC18FXXX

24CXX/

25CXX/

93CXX

HCSXXX

MCRFXXX

MCP2510

Software Tools

MPLAB® Integrated

Development Environment   

MPLAB® C17 C Compiler 

MPLAB® C18 C Compiler 

MPASMTM Assembler/

MPLINKTM Object Linker    

Emulators

MPLAB® ICE In-Circuit Emulator   

** 

ICEPICTM In-Circuit Emulator    

Debugger

MPLAB® ICD In-Circuit

Debugger **

Programmers

PICSTART® Plus Entry Level

Development Programmer   

** 

PRO MATE® II

Universal Device Programmer   

**   

Demo Boards and Eval Kits

PICDEMTM 1 Demonstration

Board 

†

PICDEMTM 2 Demonstration

Board ††

PICDEMTM 3 Demonstration

Board 

PICDEMTM 14A Demonstration

Board 

PICDEMTM 17 Demonstration

Board 

KEELOQ® Evaluation Kit 

KEELOQ® Transponder Kit 

microIDTM Programmer’s Kit 

125 kHz microIDTM

Developer’s Kit 

125 kHz Anticollision microIDTM

Developer’s Kit 

13.56 MHz Anticollision

microIDTM Developer’s Kit 

MCP2510 CAN Developer’s Kit 

* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.

** Contact Microchip Technology Inc. for availability date.

†

PIC16C55X

DS40143D-page 72 Preliminary  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. Preliminary DS40143D-page 73

PIC16C55X

10.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings †

Ambient Temperature under bias ...............................................................................................................-40° to +125°C

Storage Temperature ................................................................................................................................ -65° to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR) .......................................................-0.6V to VDD +0.6V

Voltage on VDD with respect to VSS ................................................................................................................. 0 to +7.5V

Voltage on MCLR with respect to VSS................................................................................................................0 to +14V

Total power Dissipation (Note 1)...............................................................................................................................1.0W

Maximum Current out of VSS pin ..........................................................................................................................300 mA

Maximum Current into VDD pin .............................................................................................................................250 mA

Input Clamp Current, IIK (VI < 0 or VI > VDD) ........................................................................................................ ±20 mA

Output Clamp Current, IOK (V0 < 0 or V0 > VDD)..................................................................................................±20 mA

Maximum Output Current sunk by any I/O pin........................................................................................................25 mA

Maximum Output Current sourced by any I/O pin...................................................................................................25 mA

Maximum Current sunk by PORTA, PORTB and PORTC ....................................................................................200 mA

Maximum Current sourced by PORTA, PORTB and PORTC ...............................................................................200 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16C55X

DS40143D-page 74 Preliminary  2002 Microchip Technology Inc.

FIGURE 10-1: PIC16LC554/557/558 VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C

(COMMERCIAL TEMPS)

FIGURE 10-2: PIC16LC554/557/558 VOLTAGE-FREQUENCY GRAPH,

-40°C ≤ TA < 0°C, +70°C < TA ≤ +125°C (OUTSIDE OF COMMERCIAL TEMPS)

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.

Please reference the Product Identification System section for the maximum rated speed of the parts.

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz)

VDD

(Volts)

2.0

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.

Please reference the Product Identification System section for the maximum rated speed of the parts.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 75

PIC16C55X

FIGURE 10-3: PIC16LC554/557/558 VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +85°C

FIGURE 10-4: PIC16LC554/557/558 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ 0°C

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz)

VDD

(Volts)

2.0

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.

Please reference the Product Identification System section for the maximum rated speed of the parts.

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz)

VDD

(Volts)

2.0

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.

Please reference the Product Identification System section for the maximum rated speed of the parts.

2.7

PIC16C55X

DS40143D-page 76 Preliminary  2002 Microchip Technology Inc.

10.1 DC Characteristics: PIC16C55X-04 (Commercial, Industrial, Extended)

PIC16C55X-20 (Commercial, Industrial, Extended)

PIC16LC55X-04(Commercial, Industrial, Extended)

DC Characteristics

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial and

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

VDD Supply Voltage

D001 16LC55X 3.0

2.5

—5.5

5.5

V XT and RC osc configuration

LP osc configuration

D001

D001A

16C55X 3.0

4.5

—

5.5

XT, RC and LP osc configuration

HS osc configuration

D002 VDR RAM Data Retention

Voltage(1)

— 1.5* — V Device in SLEEP mode

D003 VPOR VDD Start Voltage to

ensure Power-on Reset

—VSS — V See Section 6.4, Power-on Reset for

details

D004 SVDD VDD Rise Rate to ensure

Power-on Reset

0.05* — — V/ms See Section 6.4, Power-on Reset for

details

IDD Supply Current(2)

D010

D010A

16LC55X —

—

1.4

2.5

µA

XT and RC osc configuration

Fosc = 2.0 MHz, VDD = 3.0V, WDT

disabled(4)

LP osc configuration

Fosc = 32 kHz, VDD = 3.0V, WDT

disabled

D010

D010A

D013

16C55X —

—

1.8

9.0

3.3

µA

XT and RC osc configuration

FOSC = 4 MHz, VDD = 5.5V,

WDT disabled(4)

LP osc configuration,

PIC16C55X-04 only

FOSC = 32 kHz, VDD = 4.0V,

WDT disabled

HS osc configuration

FOSC = 20 MHz, VDD = 5.5V,

WDT disabled

* These parameters are characterized but not tested.

†Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active Operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins configured as input, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or VSS.

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-

mated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 77

PIC16C55X

D020 IPD Power-Down Current(3)

16LC55X — 0.7 2 µAVDD = 3.0V, WDT disabled

16C55X —1.0 2.5

µA

VDD = 4.0V, WDT disabled

(+85°C to +125°C)

∆IWDT WDT Current(5)

16LC55X — 6.0 15 µAVDD = 3.0V

16C55X —6.0 20 µA VDD = 4.0V

(+85°C to +125°C)

10.1 DC Characteristics: PIC16C55X-04 (Commercial, Industrial, Extended)

PIC16C55X-20 (Commercial, Industrial, Extended)

PIC16LC55X-04(Commercial, Industrial, Extended)

DC Characteristics

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial and

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

†Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active Operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins configured as input, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or VSS.

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-

mated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

PIC16C55X

DS40143D-page 78 Preliminary  2002 Microchip Technology Inc.

10.2 DC Characteristics: PIC16C55X (Commercial, Industrial, Extended)

PIC16LC55X(Commercial, Industrial, Extended)

DC Characteristics

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial and

-40°C ≤ TA ≤ +125°C for automotive

Operating voltage VDD range as described in DC spec Table 10-1

Param.

No. Sym Characteristic Min Typ† Max Unit Conditions

VIL Input Low Voltage

I/O ports

D030 with TTL buffer VSS —0.8V

0.15 VDD

VVDD = 4.5V to 5.5V

otherwise

D031 with Schmitt Trigger input VSS 0.2 VDD V

D032 MCLR, RA4/T0CKI,OSC1 (in

RC mode)

VSS —0.2VDD V(Note1)

D033 OSC1 (in XT* and HS) VSS —0.3VDD V

OSC1 (in LP*) VSS —0.6VDD-1.0 V

VIH Input High Voltage

I/O ports —

D040 with TTL buffer 2.0V

0.8 + 0.25 VDD

—

VDD

VDD = 4.5V to 5.5V

otherwise

D041 with Schmitt Trigger input 0.8V VDD

D042 MCLR RA4/T0CKI 0.8 VDD —VDD V

D043

D043A

OSC1 (XT*, HS and LP*)

OSC1 (in RC mode)

0.7 VDD

0.9 VDD

—VDD V

(Note1)

D070 IPURB PORTB weak pull-up current 50 200 400 µAVDD = 5.0V, VPIN = VSS

IIL Input Leakage Current(2)(3)

I/O ports (Except PORTA) ±1.0 µAVSS ≤ VPIN ≤ VDD, pin at hi-

impedance

D060 PORTA — — ±0.5 µAVss ≤ VPIN ≤ VDD, pin at hi-

impedance

D061 RA4/T0CKI — — ±1.0 µAVss ≤ VPIN ≤ VDD

D063 OSC1, MCLR ——±5.0 µAVss ≤ VPIN ≤ VDD, XT, HS and

LP osc configuration

VOL Output Low Voltage

D080 I/O ports — — 0.6 V IOL=8.5 mA, VDD=4.5V, -40° to

+85°C

——0.6VI

OL=7.0 mA, VDD=4.5V, +125°C

D083 OSC2/CLKOUT — — 0.6 V IOL=1.6 mA, VDD=4.5V, -40° to

+85°C

(RC only) — — 0.6 V IOL=1.2 mA, VDD=4.5V, +125°C

VOH Output High Voltage(3)

D090 I/O ports (Except RA4) VDD-0.7 — — V IOH=-3.0 mA, VDD=4.5V, -40° to

+85°C

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X be

driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent nor-

mal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin.

 2002 Microchip Technology Inc. Preliminary DS40143D-page 79

PIC16C55X

VOH Output High Voltage(3)

D090 I/O ports (Except RA4) VDD-0.7 — — V IOH=-3.0 mA, VDD=4.5V, -40° to

+85°C

VDD-0.7 — — V IOH=-2.5 mA,

VDD=4.5V, +125°C

D092 OSC2/CLKOUT VDD-0.7 — — V IOH=-1.3 mA, VDD=4.5V, -40° to

+85°C

(RC only) VDD-0.7 — — V IOH=-1.0 mA,

VDD=4.5V, +125°C

*VOD Open-Drain High Voltage 10* V RA4 pin

Capacitive Loading Specs on Output Pins

D100 COSC2 OSC2 pin 15 pF In XT, HS and LP modes when

external clock used to drive

OSC1.

D101 CIO All I/O pins/OSC2 (in RC

mode)

50 pF

10.2 DC Characteristics: PIC16C55X (Commercial, Industrial, Extended)

PIC16LC55X(Commercial, Industrial, Extended) (Continued)

DC Characteristics

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial and

-40°C ≤ TA ≤ +125°C for automotive

Operating voltage VDD range as described in DC spec Table 10-1

Param.

No. Sym Characteristic Min Typ† Max Unit Conditions

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X be

driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent nor-

mal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin.

PIC16C55X

DS40143D-page 80 Preliminary  2002 Microchip Technology Inc.

10.3 Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

FIGURE 10-5: LOAD CONDITIONS

1. TppS2ppS

2. TppS

F Frequency T Time

Lowercase subscripts (pp) and their meanings:

ck CLKOUT os OSC1

io I/O port t0 T0CKI

mc MCLR

Uppercase letters and their meanings:

F Fall P Period

H High R Rise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

VDD/2

Pin Pin

VSS VSS

RL=464Ω

CL= 50 pF for all pins except OSC2

15 pF for OSC2 output

Load condition 1 Load condition 2

 2002 Microchip Technology Inc. Preliminary DS40143D-page 81

PIC16C55X

10.4 Timing Diagrams and Specifications

FIGURE 10-6: EXTERNAL CLOCK TIMING

TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

Fos External CLKIN Frequency(1) DC — 4 MHz XT and RC osc mode, VDD=5.0V

DC — 20 MHz HS osc mode

DC — 200 kHz LP osc mode

Oscillator Frequency(1) DC — 4 MHz RC osc mode, VDD=5.0V

0.1 — 4 MHz XT osc mode

1 — 20 MHz HS osc mode

DC – 200 kHz LP osc mode

1Tosc External CLKIN Period(1) 250 — — ns XT and RC osc mode

50 — — ns HS osc mode

5——

µs LP osc mode

Oscillator Period(1) 250 — — ns RC osc mode

250 — 10,000 ns XT osc mode

50 — 1,000 ns HS osc mode

5——

µs LP osc mode

2 Tcy Instruction Cycle Time(1) 1.0 Fos/4 DC µsTCY=FOS/4

3* TosL,

TosH

External Clock in (OSC1) High or

Low Time

100* — — ns XT osc mode

2* — — µs LP osc mode

20* — — ns HS osc mode

4* TosR,

TosF

External Clock in (OSC1) Rise or

Fall Time

25* — — ns XT osc mode

50* — — ns LP osc mode

15* — — ns HS osc mode

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0 V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1 pin.

When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

PIC16C55X

DS40143D-page 82 Preliminary  2002 Microchip Technology Inc.

FIGURE 10-7: CLKOUT AND I/O TIMING

Note 1: All tests must be done with specified capacitance loads (Figure 10-5) 50 pF on I/O pins and CLKOUT.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

20, 21

19 18

old value new value

 2002 Microchip Technology Inc. Preliminary DS40143D-page 83

PIC16C55X

TABLE 10-2: CLKOUT AND I/O TIMING REQUIREMENTS

Parameter # Sym Characteristic Min Typ† Max Units

10* TosH2ckL OSC1↑ to CLKOUT↓ (1) —

—

200

400

11* TosH2ckH OSC1↑ to CLKOUT↑ (1) —

—

200

400

12* TckR CLKOUT rise time(1) —

—

100

200

13* TckF CLKOUT fall time(1) —

—

100

200

14* TckL2ioV CLKOUT ↓ to Port out valid(1) — — 20 ns

15* TioV2ckH Port in valid before CLKOUT ↑ (1) Tosc +200 ns

Tosc +400 ns

—

16* TckH2ioI Port in hold after CLKOUT ↑ (1) 0——ns

17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid —

—

50 150

300

18* TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid (I/O in

hold time)

100

200

—

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns

20* TioR Port output rise time —

—

21* TioF Port output fall time —

—

22* Tinp RB0/INT pin high or low time 25

—

23* Trbp RB<7:4> change interrupt high or low time Tcy — — ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

PIC16C55X

DS40143D-page 84 Preliminary  2002 Microchip Technology Inc.

FIGURE 10-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

TABLE 10-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2000 — — ns -40° to +85°C

31 Twdt Watchdog Timer Timeout Period

(No Prescaler)

7* 18 33* ms VDD = 5.0V, -40° to +85°C

32 Tost Oscillation Start-up Timer Period — 1024

TOSC

——TOSC = OSC1 period

33 Tpwrt Power-up Timer Period 28* 72 132* ms VDD = 5.0V, -40° to +85°C

34 TIOZ I/O hi-impedance from MCLR low — 2.0* µs

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

VDD

MCLR

Internal

POR

PWRT

Timeout

OSC

Timeout

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

 2002 Microchip Technology Inc. Preliminary DS40143D-page 85

PIC16C55X

FIGURE 10-9: TIMER0 CLOCK TIMING

TABLE 10-4: TIMER0 CLOCK REQUIREMENTS

FIGURE 10-10: LOAD CONDITIONS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20* — — ns

With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns

With Prescaler 10* — — ns

42 Tt0P T0CKI Period TCY + 40*

— — ns N = prescale value

(1, 2, 4, ..., 256)

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

RA4/T0CKI

TMR0

VDD/2

Pin Pin

VSS VSS

RL=464Ω

CL= 50 pF for all pins except OSC2

15 pF for OSC2 output

Load condition 1 Load condition 2

PIC16C55X

DS40143D-page 86 Preliminary  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. Preliminary DS40143D-page 87

PIC16C55X

11.0 PACKAGING INFORMATION

11.1 Package Marking Information

28-Lead SSOP

XXXXXXXXXXXX

YYWWNNN

Example

0025 CBA

PIC16C557

-04I / SS123

18-Lead PDIP

XXXXXXXXXXXXXXXXX

YYWWNNN

Example

9823 CBA

PIC16C558

-04I / P456

20-Lead SSOP

YYWWNNN

XXXXXXXXXXX

Example

-04/SS218

0020 CBP

PIC16C558

XXXXXXXXXXX

28-Lead PDIP

XXXXXXXXXXXXXXXXX

YYWWNNN

Example

9823 CBA

PIC16C557

-04I / P456

Legend: XX...X Customer specific information*

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters

for customer specific information.

*Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

PIC16C55X

DS40143D-page 88 Preliminary  2002 Microchip Technology Inc.

Package Marking Information (Cont’d)

18-Lead SOIC (.300”)

XXXXXXXXXXXX

YYWWNNN

Example

9818 CDK

PIC16C558

-04I / S0218

XXXXXXXXXXXX

28-Lead SOIC (.300”)

XXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

9823 CBA

PIC16C557

-04I / P456

XXXXXXXXXXXXXXXXXXXX

18-Lead CERDIP Windowed Example

XXXXXXXX

YYWWNNN

16C558

/JW

9801 CBA

28-Lead CERDIP Windowed Example

XXXXXXXXXXXXXX

YYWWNNN

16C557

/JW

9801 CBA

 2002 Microchip Technology Inc. Preliminary DS40143D-page 89

PIC16C55X

18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

1510515105

Mold Draft Angle Bottom

1510515105

Mold Draft Angle Top

10.929.407.87.430.370.310

Overall Row Spacing §

0.560.460.36.022.018.014BLower Lead Width

1.781.461.14.070.058.045B1Upper Lead Width

0.380.290.20.015.012.008

Lead Thickness

3.433.303.18.135.130.125LTip to Seating Plane

22.9922.8022.61.905.898.890DOverall Length

6.606.356.10.260.250.240

Molded Package Width

8.267.947.62.325.313.300EShoulder to Shoulder Width

0.38.015

Base to Seating Plane

3.683.302.92.145.130.115A2Molded Package Thickness

4.323.943.56.170.155.140ATop to Seating Plane

2.54.100

Pitch

1818

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES*Units

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-007

§ Significant Characteristic

PIC16C55X

DS40143D-page 90 Preliminary  2002 Microchip Technology Inc.

28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)

1510515105

Mold Draft Angle Bottom

1510515105

Mold Draft Angle Top

10.928.898.13.430.350.320

Overall Row Spacing §

0.560.480.41.022.019.016BLower Lead Width

1.651.331.02.065.053.040B1Upper Lead Width

0.380.290.20.015.012.008

Lead Thickness

3.433.303.18.135.130.125LTip to Seating Plane

35.1834.6734.161.3851.3651.345DOverall Length

7.497.246.99.295.285.275E1Molded Package Width

8.267.877.62.325.310.300EShoulder to Shoulder Width

0.38.015A1Base to Seating Plane

3.433.303.18.135.130.125A2Molded Package Thickness

4.063.813.56.160.150.140ATop to Seating Plane

2.54.100

Pitch

2828

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES*Units

Notes:

JEDEC Equivalent: MO-095

Drawing No. C04-070

* Controlling Parameter

Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

§ Significant Characteristic

 2002 Microchip Technology Inc. Preliminary DS40143D-page 91

PIC16C55X

18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

Foot Angle φ048048

1512015120

Mold Draft Angle Bottom

1512015120

Mold Draft Angle Top

0.510.420.36.020.017.014BLead Width

0.300.270.23.012.011.009

Lead Thickness

1.270.840.41.050.033.016LFoot Length

0.740.500.25.029.020.010hChamfer Distance

11.7311.5311.33.462.454.446DOverall Length

7.597.497.39.299.295.291E1Molded Package Width

10.6710.3410.01.420.407.394EOverall Width

0.300.200.10.012.008.004A1Standoff §

2.392.312.24.094.091.088

Molded Package Thickness

2.642.502.36.104.099.093AOverall Height

1.27.050

Pitch

1818

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-051

§ Significant Characteristic

PIC16C55X

DS40143D-page 92 Preliminary  2002 Microchip Technology Inc.

28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

Foot Angle Top φ048048

1512015120

Mold Draft Angle Bottom

1512015120

Mold Draft Angle Top

0.510.420.36.020.017.014BLead Width

0.330.280.23.013.011.009

Lead Thickness

1.270.840.41.050.033.016LFoot Length

0.740.500.25.029.020.010hChamfer Distance

18.0817.8717.65.712.704.695DOverall Length

7.597.497.32.299.295.288E1Molded Package Width

10.6710.3410.01.420.407.394EOverall Width

0.300.200.10.012.008.004A1Standoff §

2.392.312.24.094.091.088A2Molded Package Thickness

2.642.502.36.104.099.093AOverall Height

1.27.050

Pitch

2828

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

§ Significant Characteristic

 2002 Microchip Technology Inc. Preliminary DS40143D-page 93

PIC16C55X

18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)

3.30 3.56 3.81

5.335.084.83.210.200.190W2Window Length

.150.140.130

Window Width

10.809.788.76.425.385.345

Overall Row Spacing §

0.530.470.41.021.019.016BLower Lead Width

1.521.401.27.060.055.050B1Upper Lead Width

0.300.250.20.012.010.008

Lead Thickness

3.813.493.18.150.138.125LTip to Seating Plane

23.3722.8622.35.920.900.880DOverall Length

7.497.377.24.295.290.285E1Ceramic Pkg. Width

8.267.947.62.325.313.300EShoulder to Shoulder Width

0.760.570.38.030.023.015

Standoff

4.194.063.94.165.160.155A2Ceramic Package Height

4.954.644.32.195.183.170ATop to Seating Plane

2.54.100

Pitch

1818

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES*Units

* Controlling Parameter

§ Significant Characteristic

JEDEC Equivalent: MO-036

Drawing No. C04-010

PIC16C55X

DS40143D-page 94 Preliminary  2002 Microchip Technology Inc.

28-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)

3.30 3.56 3.81

7.877.627.37.310.300.290

Window Length

.150.140.130W1Window Width

10.809.788.76.425.385.345

Overall Row Spacing §

0.530.470.41.021.019.016BLower Lead Width

1.651.461.27.065.058.050

Upper Lead Width

0.300.250.20.012.010.008

Lead Thickness

3.683.563.43.145.140.135LTip to Seating Plane

37.7237.0236.321.4851.4581.430DOverall Length

7.497.377.24.295.290.285E1Ceramic Pkg. Width

8.267.947.62.325.313.300EShoulder to Shoulder Width

0.760.570.38.030.023.015A1Standoff

4.194.063.94.165.160.155

Ceramic Package Height

4.954.644.32.195.183.170ATop to Seating Plane

2.54.100

Pitch

2828

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES*Units

eB p

* Controlling Parameter

§ Significant Characteristic

JEDEC Equivalent: MO-058

Drawing No. C04-080

 2002 Microchip Technology Inc. Preliminary DS40143D-page 95

PIC16C55X

20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)

10501050

Mold Draft Angle Bottom

10501050

Mold Draft Angle Top

0.380.320.25.015.013.010BLead Width

203.20101.600.00840

Foot Angle

0.250.180.10.010.007.004

Lead Thickness

0.940.750.56.037.030.022LFoot Length

7.347.207.06.289.284.278DOverall Length

5.385.255.11.212.207.201

Molded Package Width

8.187.857.59.322.309.299EOverall Width

0.250.150.05.010.006.002A1Standoff §

1.831.731.63.072.068.064A2Molded Package Thickness

1.981.851.73.078.073.068AOverall Height

0.65.026

Pitch

2020

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES*Units

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-150

Drawing No. C04-072

§ Significant Characteristic

PIC16C55X

DS40143D-page 96 Preliminary  2002 Microchip Technology Inc.

28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-150

Drawing No. C04-073

10501050Mold Draft Angle Bottom

10501050

Mold Draft Angle Top

0.380.320.25.015.013.010BLead Width

203.20101.600.00840

Foot Angle

0.250.180.10.010.007.004

Lead Thickness

0.940.750.56.037.030.022LFoot Length

10.3410.2010.06.407.402.396DOverall Length

5.385.255.11.212.207.201

Molded Package Width

8.107.857.59.319.309.299EOverall Width

0.250.150.05.010.006.002A1Standoff §

1.831.731.63.072.068.064A2Molded Package Thickness

1.981.851.73.078.073.068AOverall Height

0.65.026

Pitch

2828

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERS*INCHESUnits

§ Significant Characteristic

 2002 Microchip Technology Inc. Preliminary DS40143D-page 97

PIC16C55X

APPENDIX A: ENHANCEMENTS

The following are the list of enhancements over the

PIC16C5X microcontroller family:

1. Instruction word length is increased to 14 bits.

This allows larger page sizes both in program

memory (4K now as opposed to 512 before) and

bytes before).

2. A PC high latch register (PCLATH) is added to

handle program memory paging. PA2, PA1, PA0

bits are removed from STATUS register.

3. Data memory paging is slightly redefined.

STATUS register is modified.

4. Four new instructions have been added:

RETURN, RETFIE, ADDLW, and SUBLW.

Two instructions TRIS and OPTION are being

phased out although they are kept for

compatibility with PIC16C5X.

5. OPTION and TRIS registers are made

addressable.

6. Interrupt capability is added. Interrupt vector is

at 0004h.

7. Stack size is increased to 8 deep.

8. RESET vector is changed to 0000h.

9. RESET of all registers is revised. Three different

RESET (and wake-up) types are recognized.

Registers are reset differently.

10. Wake-up from SLEEP through interrupt is

added.

11. Two separate timers, Oscillator Start-up Timer

(OST) and Power-up Timer (PWRT) are

included for more reliable power-up. These

timers are invoked selectively to avoid

unnecessary delays on power-up and wake-up.

12. PORTB has weak pull-ups and interrupt-on-

change feature.

13. Timer0 clock input, T0CKI pin is also a port pin

(RA4/T0CKI) and has a TRIS bit.

14. FSR is made a full 8-bit register.

15. “In-circuit programming” is made possible. The

user can program PIC16C55X devices using

only five pins: VDD, VSS, VPP, RB6 (clock) and

RB7 (data in/out).

16. PCON status register is added with a Power-on

Reset (POR) status bit.

17. Code protection scheme is enhanced such that

portions of the program memory can be

protected, while the remainder is unprotected.

18. PORTA inputs are now Schmitt Trigger inputs.

APPENDIX B: COMPATIBILITY

To convert code written for PIC16C5X to PIC16C55X,

the user should take the following steps:

1. Remove any program memory page select

operations (PA2, PA1, PA0 bits) for CALL, GOTO.

2. Revisit any computed jump operations (write to

PC or add to PC, etc.) to make sure page bits

are set properly under the new scheme.

3. Eliminate any data memory page switching.

Redefine data variables to reallocate them.

4. Verify all writes to STATUS, OPTION, and FSR

registers since these have changed.

5. Change RESET vector to 0000h.

PIC16C55X

DS40143D-page 98 Preliminary  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. Preliminary DS40143D-page 99

PIC16C55X

INDEX

ADDLW Instruction ............................................................. 55

ADDWF Instruction ............................................................. 55

ANDLW Instruction ............................................................. 55

ANDWF Instruction ............................................................. 55

Architectural Overview .......................................................... 9

Assembler

MPASM Assembler ..................................................... 67

BCF Instruction ................................................................... 56

Block Diagram

TIMER0....................................................................... 47

TMR0/WDT PRESCALER .......................................... 50

BSF Instruction ................................................................... 56

BTFSC Instruction............................................................... 56

BTFSS Instruction............................................................... 57

CALL Instruction ................................................................. 57

Clocking Scheme/Instruction Cycle .................................... 12

CLRF Instruction ................................................................. 57

CLRW Instruction................................................................ 58

CLRWDT Instruction ........................................................... 58

Code Protection .................................................................. 46

COMF Instruction................................................................ 58

Configuration Bits................................................................ 31

Data Memory Organization ................................................. 13

DECF Instruction................................................................. 58

DECFSZ Instruction ............................................................ 59

Development Support ......................................................... 67

Errata .................................................................................... 3

External Crystal Oscillator Circuit ....................................... 34

General purpose Register File ............................................ 13

GOTO Instruction................................................................ 59

I/O Ports.............................................................................. 23

I/O Programming Considerations........................................ 28

ICEPIC In-Circuit Emulator ................................................. 68

ID Locations ........................................................................ 46

INCF Instruction .................................................................. 59

INCFSZ Instruction ............................................................. 60

In-Circuit Serial Programming............................................. 46

Indirect Addressing, INDF and FSR Registers ................... 21

Instruction Flow/Pipelining .................................................. 12

Instruction Set

ADDLW ....................................................................... 55

ADDWF....................................................................... 55

ANDLW ....................................................................... 55

ANDWF....................................................................... 55

BCF............................................................................. 56

BSF ............................................................................. 56

BTFSC ........................................................................ 56

BTFSS ........................................................................ 57

CALL ........................................................................... 57

CLRF........................................................................... 57

CLRW ......................................................................... 58

CLRWDT .................................................................... 58

COMF ......................................................................... 58

DECF.......................................................................... 58

DECFSZ ..................................................................... 59

GOTO ......................................................................... 59

INCF ........................................................................... 59

INCFSZ....................................................................... 60

IORLW ........................................................................ 60

IORWF........................................................................ 60

MOVF ......................................................................... 61

MOVLW ...................................................................... 60

MOVWF...................................................................... 61

NOP............................................................................ 61

OPTION...................................................................... 61

RETFIE....................................................................... 62

RETLW ....................................................................... 62

RETURN..................................................................... 62

RLF............................................................................. 62

RRF ............................................................................ 63

SLEEP ........................................................................ 63

SUBLW ....................................................................... 63

SUBWF....................................................................... 64

SWAPF ....................................................................... 64

TRIS ........................................................................... 64

XORLW....................................................................... 65

XORWF ...................................................................... 65

Instruction Set Summary .................................................... 53

INT Interrupt ....................................................................... 42

INTCON Register................................................................ 19

Interrupts ............................................................................ 41

IORLW Instruction .............................................................. 60

IORWF Instruction .............................................................. 60

KEELOQ Evaluation and Programming Tools...................... 70

MOVF Instruction................................................................ 61

MOVLW Instruction............................................................. 60

MOVWF Instruction ............................................................ 61

MPLAB C17 and MPLAB C18 C Compilers ....................... 67

MPLAB ICD In-Circuit Debugger ........................................ 69

MPLAB ICE High Performance Universal In-Circuit Emulator

with MPLAB IDE ................................................................. 68

MPLAB Integrated Development Environment Software.... 67

MPLINK Object Linker/MPLIB Object Librarian.................. 68

NOP Instruction .................................................................. 61

One-Time-Programmable (OTP) Devices ............................ 7

OPTION Instruction ............................................................ 61

OPTION Register................................................................ 18

Oscillator Configurations..................................................... 33

Oscillator Start-up Timer (OST).......................................... 36

PCL and PCLATH............................................................... 21

PCON Register................................................................... 20

PICDEM 1 Low Cost PICmicro Demonstration Board ........ 69

PICDEM 17 Demonstration Board...................................... 70

PICDEM 2 Low Cost PIC16CXX Demonstration Board ..... 69

PICDEM 3 Low Cost PIC16CXXX Demonstration Board... 70

PIC16C55X

DS40143D-page 100 Preliminary  2002 Microchip Technology Inc.

PICSTART Plus Entry Level Development Programmer .... 69

Port RB Interrupt ................................................................. 42

PORTA................................................................................ 23

PORTB.......................................................................... 25, 27

Power Control/Status Register (PCON) .............................. 37

Power-Down Mode (SLEEP)............................................... 45

Power-On Reset (POR) ...................................................... 36

Power-up Timer (PWRT)..................................................... 36

Prescaler ............................................................................. 49

PRO MATE II Universal Device Programmer ..................... 69

Program Memory Organization ........................................... 13

Quick-Turnaround-Production (QTP) Devices ...................... 7

RC Oscillator ....................................................................... 34

Reset................................................................................... 35

RETFIE Instruction.............................................................. 62

RETLW Instruction .............................................................. 62

RETURN Instruction............................................................ 62

RLF Instruction.................................................................... 62

RRF Instruction ................................................................... 63

Serialized Quick-Turnaround-Production (SQTP) Devices ... 7

SLEEP Instruction ............................................................... 63

Software Simulator (MPLAB SIM)....................................... 68

Special Features of the CPU............................................... 31

Special Function Registers ................................................. 15

Stack ................................................................................... 21

Status Register.................................................................... 17

SUBLW Instruction.............................................................. 63

SUBWF Instruction.............................................................. 64

SWAPF Instruction.............................................................. 64

Timer0

TIMER0....................................................................... 47

TIMER0 (TMR0) Interrupt ........................................... 47

TIMER0 (TMR0) Module............................................. 47

TMR0 with External Clock........................................... 49

Timer1

Switching Prescaler Assignment................................. 51

Timing Diagrams and Specifications................................... 81

TMR0 Interrupt .................................................................... 42

TRIS Instruction .................................................................. 64

TRISA.................................................................................. 23

TRISB............................................................................ 25, 27

Watchdog Timer (WDT) ...................................................... 43

WWW, On-Line Support........................................................ 3

XORLW Instruction ............................................................. 65

XORWF Instruction ............................................................. 65

 2002 Microchip Technology Inc. Preliminary DS40143D-page 101

PIC16C55X

SYSTEMS INFORMATION AND

UPGRADE HOT LINE

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip's development systems software products.

Plus, this line provides information on how customers

can receive the most current upgrade kits.The Hot Line

Numbers are:

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ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

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The web site is used by Microchip as a means to make

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and a web browser, such as Netscape® or Microsoft®

Internet Explorer. Files are also available for FTP

download from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available at the following

URL:

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The file transfer site is available by using an FTP ser-

vice to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User's Guides, Articles and Sample Programs. A vari-

ety of Microchip specific business information is also

available, including listings of Microchip sales offices,

distributors and factory representatives. Other data

available for consideration is:

• Latest Microchip Press Releases

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• Links to other useful web sites related to

Microchip Products

• Conferences for products, Development Systems,

technical information and more

• Listing of seminars and events

092002

PIC16C55X

DS40143D-page 102 Preliminary  2002 Microchip Technology Inc.

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

To: Technical Publications Manager

RE: Reader Response

Total Pages Sent ________

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DS40143D

PIC16C55X

 2002 Microchip Technology Inc. Preliminary DS40143D-page 103

PIC16C55X

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of

each oscillator type.

Sales and Support

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device PIC17C756: Standard VDD range

PIC17C756T: (Tape and Reel)

PIC17LC756: Extended VDD range

Temperature Range - = 0°C to +70°C

I = -40°C to +85°C

Package CL = Windowed LCC

PT = TQFP

L = PLCC

Pattern QTP, SQTP, ROM Code (factory specified) or

Special Requirements. Blank for OTP and

Windowed devices.

Examples:

a) PIC17C756–16L Commercial Temp.,

PLCC package, 16 MHz,

normal VDD limits

b) PIC17LC756–08/PT Commercial Temp.,

TQFP package, 8MHz,

extended VDD limits

c) PIC17C756–33I/PT Industrial Temp.,

TQFP package, 33 MHz,

normal VDD limits

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

PIC16C55X

DS40143D-page 104 Preliminary  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. Preliminary DS40143D-page 105

PIC16C55X

NOTES:

DS40143D-page 106 Preliminary  2002 Microchip Technology Inc.

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