1
Motorola Small–Signal Transistors, FETs and Diodes Device Data
N–Channel
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain–Source Voltage VDS 25 Vdc
Gate–Source Voltage VGS 25 Vdc
Gate Current IG10 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR–5 Board(1)
TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance, Junction to Ambient R
q
JA 556 °C/W
Junction and Storage Temperature TJ, Tstg –55 to +150 °C
DEVICE MARKING
MMBFJ309LT1 = 6U; MMBFJ310LT1 = 6T
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Gate–Source Breakdown Voltage (IG = –1.0 µAdc, VDS = 0) V(BR)GSS –25 — — Vdc
Gate Reverse Current (VGS = –15 Vdc)
Gate Reverse Current (VGS = –15 Vdc, TA = 125°C) IGSS —
——
—–1.0
–1.0 nAdc
µAdc
Gate Source Cutoff Voltage MMBFJ309
(VDS = 10 Vdc, ID = 1.0 nAdc) MMBFJ310 VGS(off) –1.0
–2.0 —
—–4.0
–6.5 Vdc
ON CHARACTERISTICS
Zero–Gate–Voltage Drain Current MMBFJ309
(VDS = 10 Vdc, VGS = 0) MMBFJ310 IDSS 12
24 —
—30
60 mAdc
Gate–Source Forward Voltage (IG = 1.0 mAdc, VDS = 0) VGS(f) — — 1.0 Vdc
SMALL–SIGNAL CHARACTERISTICS
Forward T ransfer Admittance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) |Yfs|8.0 — 18 mmhos
Output Admittance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) |yos| — — 250 µmhos
Input Capacitance (VGS = –10 Vdc, VDS = 0 Vdc, f = 1.0 MHz) Ciss — — 5.0 pF
Reverse Transfer Capacitance (VGS = –10 Vdc, VDS = 0 Vdc, f = 1.0 MHz) Crss — — 2.5 pF
Equivalent Short–Circuit Input Noise Voltage
(VDS = 10 Vdc, ID = 10 mAdc, f = 100 Hz) en— 10 — nV
ń
Hz
Ǹ
1. FR–5 = 1.0
0.75
0.062 in.
Thermal Clad is a trademark of the Bergquist Company
Order this document
by MMBFJ309LT1/D
SEMICONDUCTOR TECHNICAL DATA
12
3
CASE 318–08, STYLE 10
SOT–23 (T O–236AB)
Motorola, Inc. 1997
2 SOURCE
3
GATE
1 DRAIN
2 Motorola Small–Signal Transistors, FETs and Diodes Device Data
C1 = C2 = 0.8 – 10 pF, JFD #MVM010W.
C3 = C4 = 8.35 pF Erie #539–002D.
C5 = C6 = 5000 pF Erie (2443–000).
C7 = 1000 pF, Allen Bradley #F A5C.
RFC = 0.33 µH Miller #9230–30.
L1 = One T urn #16 Cu, 1/4″ I.D. (Air Core).
L2P = One T urn #16 Cu, 1/4″ I.D. (Air Core).
L2S = One T urn #16 Cu, 1/4″ I.D. (Air Core).
50
Ω
SOURCE 50
Ω
LOAD
U310
C3
C2
C6
C7
C4
1.0 k RFC
L1 L2PL2S
+VDD
C1
C5
Figure 1. 450 MHz Common–Gate Amplifier Test Circuit
70
60
50
40
30
20
, SA TURATION DRAIN CURRENT (mA)
–5.0 –4.0 –3.0 –2.0 –1.0 0
ID – VGS, GATE–SOURCE VOLTAGE (VOLTS)
IDSS
10
0
70
60
50
40
30
20
10
, DRAIN CURRENT (mA)ID
IDSS – VGS, GATE–SOURCE CUTOFF VOLTAGE (VOLTS)
Figure 2. Drain Current and Transfer
Characteristics versus Gate–Source Voltage
VDS = 10 V
IDSS
+25
°
C
T
A = –55
°
C
+25
°
C
+25
°
C
–55
°
C
+150
°
C
+150
°
C
VGS, GATE–SOURCE VOLTAGE (VOLTS)
5.0 4.0 3.0 2.0 1.0 0
35
30
25
20
15
10
5.0
0
, FORWARD TRANSCONDUCTANCE (mmhos)Yfs
Figure 3. Forward Transconductance
versus Gate–Source Voltage
VDS = 10 V
f = 1.0 MHz TA = –55
°
C+25
°
C
+150
°
C+25
°
C
–55
°
C
+150
°
C
ID, DRAIN CURRENT (mA)
100 k
10 k
1.0 k
100
1.0 k
100
10
1.0
0.01 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100
, FORWARD TRANSCONDUCTANCE ( mhos)Yfs
µ
, OUTPUT ADMITTANCE ( mhos)Yos
µ
VGS(off) = –2.3 V =
VGS(off) = –5.7 V =
Figure 4. Common–Source Output
Admittance and Forward Transconductance
versus Drain Current
Yfs Yfs
Yos
VGS, GATE SOURCE VOL TAGE (VOLTS)
5.0 4.0 3.0 2.0 1.0 06.07.08.09.010
CAPACITANCE (pF)
10
7.0
4.0
1.0
0
120
96
72
48
24
0
, ON RESISTANCE (OHMS)RDS
RDS
Cgs
Cgd
Figure 5. On Resistance and Junction
Capacitance versus Gate–Source Voltage
3
Motorola Small–Signal Transistors, FETs and Diodes Device Data
|Y11|, |Y21|, |Y22 | (mmhos)
Y12(mmhos)
30
24
18
12
6.0
01000100 200 300 500 700
f, FREQUENCY (MHz)
3.0
2.4
1.8
1.2
0.6
|S21|, |S11|
0.45
0.39
0.33
0.27
0.21
0.15
0.85
0.79
0.73
0.67
0.61
0.55
|S12|, |S22|
0.060
0.048
0.036
0.024
0.012
1.00
0.98
0.96
0.94
0.92
0.90
1000100 200 300 500 700
f, FREQUENCY (MHz)
Figure 6. Common–Gate Y Parameter
Magnitude versus Frequency Figure 7. Common–Gate S Parameter
Magnitude versus Frequency
f, FREQUENCY (MHz)ID, DRAIN CURRENT (mA)
NF, NOISE FIGURE (dB)
NF, NOISE FIGURE (dB)
G , POWER GAIN (dB)
pg
G , POWER GAIN (dB)
pg
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
4.0 6.0 8.0 10 12 14 16 18 20 22 24
24
21
18
15
12
9.0
6.0
3.0
0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
050 100 200 300 500 700 1000
26
22
18
14
10
6.0
2.0
VDS = 10 V
ID = 10 mA
TA = 25
°
CY11
Y21
Y22
Y12
S22
S21
S11
S12
Gpg
NF
VDS = 10 V
ID = 10 mA
TA = 25
°
C
VDD = 20 V
f = 450 MHz
BW
≈
10 MHz
CIRCUIT IN FIGURE 1
VDS = 10 V
ID = 10 mA
TA = 25
°
C
CIRCUIT IN FIGURE 1
Gpg
NF
f, FREQUENCY (MHz)
θ
21,
θ
11
50
°
40
°
30
°
20
°
10
°
0
°
180
°
170
°
160
°
150
°
140
°
130
°
θ
12,
θ
22
–20
°
–40
°
–80
°
–120
°
–160
°
–200
°
–20
°
–60
°
–100
°
–140
°
–180
°
87
°
86
°
85
°
84
°
83
°
82
°
1000100 200 300 500 700
Figure 8. Common–Gate Y Parameter
Phase–Angle versus Frequency
f, FREQUENCY (MHz)
θ
11,
θ
12
120
°
100
°
80
°
60
°
40
°
20
°
–20
°
–40
°
–60
°
–80
°
–100
°
–120
°
θ
21,
θ
22
0
–40
°
–80
°
–20
°
–60
°
–100
°
1000100 200 300 500 700
Figure 9. S Parameter Phase–Angle
versus Frequency
θ
22
θ
21
θ
12
θ
11 VDS = 10 V
ID = 10 mA
TA = 25
°
C
θ
11
θ
21
θ
22
θ
21
θ
11
θ
12 VDS = 10 V
ID = 10 mA
TA = 25
°
C
Figure 10. Noise Figure and
Power Gain versus Drain Current Figure 11. Noise Figure and Power Gain
versus Frequency
4 Motorola Small–Signal Transistors, FETs and Diodes Device Data
Figure 12. 450 MHz IMD Evaluation Amplifier
BW (3 dB) – 36.5 MHz
ID – 10 mAdc
VDS – 20 Vdc
Device case grounded
IM test tones – f1 = 449.5 MHz, f2 = 450.5 MHz
C1 = 1–10 pF Johanson Air variable trimmer.
C2, C5 = 100 pF feed thru button capacitor.
C3, C4, C6 = 0.5–6 pF Johanson Air variable
trimmer.
L1 = 1/8″ x 1/32″ x 1–5/8″ copper bar.
L2, L4 = Ferroxcube Vk200 choke.
L3 = 1/8″ x 1/32″ x 1–7/8″ copper bar.
INPUT
RS = 50
Ω
C1
C2
L1
L2
VS
S
G
D
SHIELD
C3
U310
C4
VD
L3
C5
L4
C6
OUTPUT
RL = 50
Ω
Amplifier power gain and IMD products are a function of the load impedance. For the amplifier design shown above with C4 and
C6 adjusted to reflect a load to the drain resulting in a nominal power gain of 9 dB, the 3rd order intercept point (IP) value is
29 dBm. Adjusting C4, C6 to provide larger load values will result in higher gain, smaller bandwidth and lower IP values. For
example, a nominal gain of 13 dB can be achieved with an intercept point of 19 dBm.
Example of intercept point plot use:
Assume two in–band signals of –20 dBm at the amplifier input.
They will result in a 3rd order IMD signal at the output of
–90 dBm. Also, each signal level at the output will be
–11 dBm, showing an amplifier gain of 9.0 dB and an
intermodulation ratio (IMR) capability of 79 dB. The gain and
IMR values apply only for signal levels below comparison.
Figure 13. Two Tone 3rd Order Intercept Point
–20
–40
–60
–80
–100
–120
OUTPUT POWER PER TONE (dBm)
–120 +20
–100 –80 –60
INPUT POWER PER TONE (dBm)
0
+20
+40
–40 –20 0
3RD ORDER INTERCEPT POINT
FUNDAMENTAL OUTPUT
3RD ORDER IMD OUTPUT
U310 JFET
VDS = 20 Vdc
ID = 10 mAdc
F1 = 449.5 MHz
F2 = 450.5 MHz
5
Motorola Small–Signal Transistors, FETs and Diodes Device Data
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by TJ(max), the maximum rated junction temperature of the
die, RθJA, the thermal resistance from the device junction to
ambient, and the operating temperature, TA. Using the
values provided on the data sheet for the SOT–23 package,
PD can be calculated as follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T A of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad. Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•Always preheat the device.
•The delta temperature between the preheat and
soldering should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
•The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
•After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
6 Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE DIMENSIONS
DJ
K
L
A
C
BS
H
GV
3
12
CASE 318–08
ISSUE AE
SOT–23 (TO–236AB)
DIM
AMIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0180 0.0236 0.45 0.60
L0.0350 0.0401 0.89 1.02
S0.0830 0.0984 2.10 2.50
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Af firmative Action Employer.
Mfax is a trademark of Motorola, Inc.
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