MCP1632 High-Speed, Low-Side PWM Controller Features: Description: * High-Speed PWM Controller with Integrated Low-Side MOSFET Driver * Multiple Switching Frequency Options (fSW): - 300 kHz - 600 kHz * Adjustable Reference Voltage Generator * Adjustable Soft Start * Internal Slope Compensation * Shutdown Input Pin (EN) * Low Operating Current: < 5 mA (typical) * Undervoltage Lockout (UVLO) Protection * Output Short Circuit Protection * Overtemperature Protection * Operating Temperature Range: - -40C to +125C The MCP1632 high-speed PWM controller is a pulse-width modulator developed for stand-alone power supply applications. The MCP1632 includes a high-speed analog control loop, a logic-level MOSFET driver, an internal oscillator, a reference voltage generator, and internal slope compensation. This high level of integration makes it an ideal solution for standalone SMPS applications. MCP1632 is suitable for use in topologies requiring a low-side MOSFET control, such as Boost, Flyback, SEPIC, uk, etc. Typical applications include battery chargers, intelligent power systems, brick DC-DC converters, LED drivers. Due to its low power consumption, the MCP1632 PWM controller is recommended for battery-operated applications. Applications: * * * * Switch Mode Power Supplies Brick DC-DC Converters Battery Charger Applications LED Drivers Related Literature: * "MCP1632 300 kHz Boost Converter Demo Board User's Guide", Microchip Technology Inc., DS20005252A, 2013 The MCP1632 offers a Peak Current mode control in order to achieve consistent performance regardless of the topology of the power train or the operating conditions. In addition, the MCP1632 can implement the Voltage Mode Control for cost-sensitive solutions. The MCP1632 PWM controller can be easily interfaced with PIC microcontrollers in order to develop an intelligent power solution. Additional features include: UVLO, overtemperature and overcurrent protection, shutdown capability (EN pin) and an adjustable soft start option. Package Type 8-Lead DFN (2 mm x 3 mm) 8 VREF COMP 1 FB 2 CS 3 EN 4 2013 Microchip Technology Inc. EP 9 8-Lead MSOP COMP 1 8 VREF 7 Vin FB 2 6 VEXT CS 3 6 VEXT 5 GND EN 4 5 GND 7 VIN DS20005254A-page 1 MCP1632 Functional Block Diagram VIN Shutdown Circuit EN SS Reset VIN UVLO Overtemperature Oscillator 300/600 kHz CLK VEXT 10 k: S Q R Q VDRIVE RAMP 6 k: +1 CS Blanking 100 ns CS GND VIN + - COMP PWM Comp Latch Truth Table VIN - FB 2R EA + VIN 2.7V Reference Voltage R S R Q 0 0 Qn 0 1 1 1 0 0 1 1 1 50 A VREF SS Reset DS20005254A-page 2 2013 Microchip Technology Inc. MCP1632 Typical Application Circuit - Peak Current Mode Control VIN VOUT VCC VREF VEXT EN MCP1632 CSS CS RR COMP FB GND Typical Application Circuit - Voltage Mode Control VIN VOUT VCC VREF VEXT EN MCP1632 CSS RR CS COMP FB GND 2013 Microchip Technology Inc. DS20005254A-page 3 MCP1632 1.0 Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings VDD...................................................................................6.0V Maximum Voltage on Any Pin . (VGND - 0.3)V to (VIN + 0.3)V VEXT Short Circuit Current ...........................Internally Limited Storage Temperature.....................................-65C to +150C Maximum Junction Temperature, TJ ........................... +150C Continuous Operating Temperature Range ..-40C to +125C ESD protection on all pins, HBM 2 kV AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, VIN = 3.0V to 5.5V, FOSC = 300 kHz, CIN = 0.1 F, VIN for typical values = 5.0V, TA = -40C to +125C. Parameters Sym. Min. Typ. Max. Units Conditions Input Operating Voltage VIN 3.0 -- 5.5 V Input Quiescent Current I(VIN) -- 5 7.5 mA IEXT = 0 mA Input Shutdown Current I(VIN)SHDN -- -- 2 A EN = 0V Input Voltage EN Input EN Input Voltage Low ENLOW -- -- 0.8 V EN Input Voltage High ENHIGH 75 -- -- % of VIN -- -- 190 210 s EN goes from low to high (Note 1) 40 60 s EN goes from high to low (Note 1) 250 300 350 kHz 510 600 690 Delay Time Internal Oscillator Internal Oscillator Range FOSC Two options Refer to Section 4.8 "Internal Oscillator". Reference Voltage Section Reference Voltage Input Range VREF 0 -- VIN V Note 1 Refer to Section 4.7 "Reference Voltage Generator" for details. Internal Constant Current Generator IREF 48 50 52 A Refer to Section 4.7 "Reference Voltage Generator" for details. Error Amplifier VOS -4 0.1 +4 mV PSRR 65 80 -- dB VIN = 3.0V to 5.0V, VCM = 1.2V (Note 1) VCM GND - 0.3 -- VIN V Note 1 CMRR 60 80 -- dB VIN = 5V, VCM = 0V to 2.5V (Note 1) Open-Loop Voltage Gain AVOL 80 95 -- dB RL = 5 k to VIN/2, 100 mV < VEAOUT < VIN - 100 mV, VCM = 1.2V (Note 1) Low-Level Output VOL -- 25 50 mV RL = 5 k to VIN/2 GBWP 3.5 5 -- MHz VIN = 5V (Note 1) ISINK 4 8 -- mA VIN = 5V, VREF = 1.2V, VFB = 1.4V, VCOMP = 2.0V Input Offset Voltage Error Amplifier Common-Mode Input Range Common-Mode Rejection Ratio Gain Bandwidth Product Error Amplifier Sink Current Note 1: Ensured by design. Not production tested. DS20005254A-page 4 2013 Microchip Technology Inc. MCP1632 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, VIN = 3.0V to 5.5V, FOSC = 300 kHz, CIN = 0.1 F, VIN for typical values = 5.0V, TA = -40C to +125C. Parameters Error Amplifier Source Current Sym. Min. Typ. Max. Units ISOURCE 4 6 -- mA VCS_MAX 0.8 0.9 0.97 V Conditions VIN = 5V, VREF = 1.2V, VFB = 1.0V, VCOMP = 2.0V, Absolute Value Current Sense Input Maximum Current Sense Signal Blanking Time Set by maximum error amplifier clamp voltage, divided by 3 (Note 1) TBLANK 80 100 130 ns Note 1 TCS_VEXT -- -- 35 ns Excluding the blanking time (Note 1) ICS_B -- -0.1 -- A Note 1 Minimum Duty Cycle DCMIN -- -- 0 % VFB = VREF + 0.1V, VCS = GND (Note 1) Maximum Duty Cycle DCMAX 80 85 95 % VRAMP 0.8 0.9 1 VPP Refer to Section 4.6 "Slope Compensation" for details. DC Offset Low -- 0.15 0.32 0.45 V Refer to Section 4.6 "Slope Compensation" for details. DC Offset High -- 1.12 1.22 1.32 V Refer to Section 4.6 "Slope Compensation" for details. ZRG 5.5 6 6.5 k Refer to Section 4.6 "Slope Compensation" for details. RDSon P-channel RDSon_P -- 10 30 RDSon N-channel RDSon_N -- 7 30 VEXT Rise Time TRISE -- -- 18 ns CL = 100 pF Typical for VIN = 3V (Note 1) VEXT Fall Time TFALL -- -- 18 ns CL = 100 pF Typical for VIN = 3V (Note 1) Undervoltage Lockout UVLO 2.6 -- 2.9 V VIN falling, VEXT low state when in UVLO Undervoltage Lockout Hysteresis UVLOHYS 50 110 180 mV Thermal Shutdown TSHD -- 150 -- C Note 1 Thermal Shutdown Hysteresis TSHD_HYS -- 20 -- C Note 1 Delay from CS to VEXT Current Sense Input Bias Current PWM Section Slope Compensation Ramp Generator Ramp Amplitude Ramp Generator Output Impedance Internal Driver Protection Features Note 1: Ensured by design. Not production tested. 2013 Microchip Technology Inc. DS20005254A-page 5 MCP1632 TEMPERATURE SPECIFICATIONS Electrical Specifications: VIN = 3.0V to 5.5V, FOSC = 600 kHz, CIN = 0.1 F. TA = -40C to +125C. Parameters Sym. Min. Typ. Max. Units Conditions Operating Junction Temperature Range TA -40 -- +125 C Storage Temperature Range TA -65 -- +150 C TJ -- -- +150 C Thermal Resistance, 8L-DFN (2 mm x 3 mm) JA -- 75 -- C/W Typical 4-layer board with two interconnecting vias. Thermal Resistance, 8L-MSOP JA -- 211 -- C/W Typical 4-layer board. Temperature Ranges Maximum Junction Temperature Steady state Transient Thermal Package Resistances DS20005254A-page 6 2013 Microchip Technology Inc. MCP1632 2.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: 0.9 Relative Oscillator Frequency Variation (%) Input Quiescent Current (A) Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. EN = Low 0.8 0.7 0.6 fSW = 600 kHz 0.5 0.4 0.3 fSW = 300 kHz 0.2 0.1 2.0 fSW = 300 kHz 0.0 -2.0 fSW = 600 kHz -4.0 -6.0 -8.0 -10.0 0.0 2.5 3.5 4.5 Input Voltage (V) -50 5.5 FIGURE 2-1: Input Quiescent Current vs. Input Voltage (EN = Low). 0 50 100 Junction Temperature (C) 150 FIGURE 2-4: Relative Oscillator Frequency Variation vs. Junction Temperature. 50.5 8.0 EN = High 7.0 50.4 50.3 6.0 5.0 VREF Current (A) Input Quiescent Current (mA) 4.0 fSW = 600 kHz 4.0 3.0 fSW = 300 kHz 2.0 1.0 50.2 50.1 50 49.9 49.8 49.7 49.6 0.0 49.5 2.5 3.5 4.5 Input Voltage (V) 5.5 FIGURE 2-2: Input Quiescent Current vs. Input Voltage (EN = High). 2.5 FIGURE 2-5: Voltage. 3.5 4.5 Input Voltage (V) 5.5 VREF Current vs. Input 50.8 2.0 50.6 fSW = 300 kHz 0.0 VREF Current (A) Relative Oscillator Frequency Variation (%) 51 4.0 -2.0 -4.0 fSW = 600 kHz -6.0 -8.0 50.4 50.2 50 49.8 49.6 49.4 49.2 -10.0 2.5 3.5 4.5 Input Voltage (V) FIGURE 2-3: Relative Oscillator Frequency Variation vs. Input Voltage. 2013 Microchip Technology Inc. 5.5 49 -50 FIGURE 2-6: Temperature. 0 50 100 Junction Temperature (C) 150 VREF Current vs. Junction DS20005254A-page 7 MCP1632 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 5 NMOS Pair 0.1 CLOAD = 100 pF VEXT Fall Time (ns) Error Amplifier Offset Voltage (mV) 0.2 0 -0.1 -0.2 -0.3 PMOS Pair 4 3 -0.4 -0.5 2 -50 0 50 100 Junction Temperature (C) 150 2.5 FIGURE 2-10: Voltage. FIGURE 2-7: Error Amplifier Offset Voltage vs. Temperature. 5.5 VEXT Fall Time vs. Input 45.0 Relative VEXT N-Channel MOSFET RDSon Variation (%) Error Amplifier Offset Voltage (mV) 0.6 0.4 0.2 NMOS Pair 0 -0.2 -0.4 -0.6 PMOS Pair -0.8 -1 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 -5.0 2.5 3.5 4.5 Input Voltage (V) 5.5 FIGURE 2-8: Error Amplifier Offset Voltage vs. Input Voltage. 2.5 Relative VEXT P-Channel MOSFET RDSon Variation (%) CLOAD = 100 pF 4 3 2 2.5 FIGURE 2-9: Voltage. DS20005254A-page 8 3.5 4.5 Input Voltage (V) 3.5 4.5 Input Voltage (V) 5.5 FIGURE 2-11: Relative VEXT N-Channel MOSFET RDSon Variation vs. Input Voltage. 5 VEXT Rise Time (ns) 3.5 4.5 Input Voltage (V) 5.5 VEXT Rise Time vs. Input 45.0 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 -5.0 -10.0 2.5 3.5 4.5 Input Voltage (V) 5.5 FIGURE 2-12: Relative VEXT P-Channel MOSFET RDSon Variation vs. Input Voltage. 2013 Microchip Technology Inc. MCP1632 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 3.00 UVLO Threshold (V) 2.95 VIN Rising 2.90 2.85 2.80 2.75 VIN Falling 2.70 2.65 2.60 -50 0 50 100 Junction Temperature (C) FIGURE 2-13: Temperature. 150 UVLO Threshold vs. Relative VEXT N-Channel MOSFET RDSon Variation (%) 25.0 20.0 15.0 10.0 5.0 0.0 -5.0 -10.0 -15.0 -50 0 50 100 Junction Temperature (C) 150 FIGURE 2-14: Relative VEXT N-Channel MOSFET RDSon Variation vs. Junction Temperature. Relative VEXT P-Channel MOSFET RDSon Variation (%) 25.0 20.0 15.0 10.0 5.0 0.0 -5.0 -10.0 -15.0 -50 0 50 100 Junction Temperature (C) 150 FIGURE 2-15: Relative VEXT P-Channel MOSFET RDSon Variation vs. Junction Temperature. 2013 Microchip Technology Inc. DS20005254A-page 9 MCP1632 NOTES: DS20005254A-page 10 2013 Microchip Technology Inc. MCP1632 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE DFN/MSOP Name 1 COMP 3.1 Function Error Amplifier Output 2 FB Error Amplifier Inverting Input 3 CS Current Sense Input 4 EN Enable Input 5 GND Circuit Ground 6 VEXT External Driver Output 7 VIN 8 VREF 9 EP Input Bias Reference Voltage Input/Internal Constant Current Generator Output Exposed Thermal Pad (EP); must be connected to GND Error Amplifier Output (COMP) COMP is the internal error amplifier output pin. External compensation is connected from the FB pin to the COMP pin for control-loop stabilization. Type II or III compensation networks must be used depending on the application. An internal voltage clamp is used to limit the maximum COMP pin voltage to 2.7V (typical). This clamp is used to set the maximum peak current in the power system switch by setting a maximum limit on the CS input for Peak Current Mode control systems. 3.2 Error Amplifier Inverting Input (FB) FB is the internal error amplifier inverting input pin. The output (voltage or current) is sensed and fed back to the FB pin for regulation. Inverting or negative feedback is used. 3.3 Current Sense Input (CS) This is the input for the switch current used for Peak Current Mode control. A blanking period of 100 ns (typical) for CS signal is provided to avoid leading edge spikes that can cause false PWM reset. The normal PWM duty cycle will be terminated when the voltage on the CS pin (including the slope compensation ramp) is equal to the output of the error amplifier divided by 3. For Current Mode operation, the CS pin will control the PWM output on a cycle-by-cycle basis. The internal error amplifier output is clamped to 2.7V (nominal) and divided by 3, so the maximum voltage of the CS pin is 0.9V. By limiting the inverting pin of the high-speed comparator to 0.9V, a current sense limit is established for all input bias voltage conditions (cycle-by-cycle overcurrent protection). To avoid the instability of the Peak Current Mode control when the duty cycle is higher than 50%, a slope compensation ramp generator is internally provided. This circuit will add to the CS signal an artificially generated ramp to avoid 2013 Microchip Technology Inc. sub-harmonic oscillations. The amplitude of the slope compensation ramp is adjustable with one external resistor. If this pin is left open, the PWM Controller will operate in Voltage Mode Control. In this mode, the external switching MOSFET transistor is not protected against overcurrent conditions. Certain limitations related to the stability of the closed-loop system must be taken into account by the designer when the part operates in Voltage Mode Control. Refer to Section 5.2 "Operation in Voltage Mode Control" for details about the operation in Voltage Mode Control. 3.4 Enable Input (EN) When this pin is connected to GND (logic "Low") for more than 50 s (typical), the chip will go into Shutdown state. A logic "High" enables the normal operation of the MCP1632 device. When the device is disabled, the VEXT output is held low. Do not let the EN pin float. If not used, connect EN to VIN through a 10 k resistor. 3.5 Circuit Ground (GND) Connect the circuit ground to the GND pin. For most applications, this should be connected to the analog (quiet) ground plane. Effort should be made to minimize the noise on this ground, as it can adversely affect the cycle-by-cycle comparison between the CS input and the error amplifier output. 3.6 External Driver Output (VEXT) VEXT is the internal MOSFET driver output pin, used to drive the external transistor. For high-power or high-side drives, this output should be connected to the logic-level input of an appropriate MOSFET driver. For low-power, low-side applications, the VEXT pin can be used to directly drive the gate of an N-channel MOSFET. DS20005254A-page 11 MCP1632 3.7 Input Bias (VIN) VIN is the input voltage pin. Connect the input voltage source to the VIN pin. For normal operation, the voltage on the VIN pin should range from +3.0V to +5.5V. A bypass capacitor of at least 0.1 F should be connected between the VIN pin and the GND pin. This decoupling capacitor must be located as close as possible to the controller package. 3.8 Reference Voltage Input/Internal Constant Current Generator Output (VREF) This pin is the output of the internal Constant Current Generator (50 A typical). An external resistor must be connected between this pin and GND. The current flowing in this resistor will set the reference voltage. Optionally, a capacitor may also be connected between this pin and GND to set the soft start ramp behavior. This pin may be overdriven by an external voltage source, enabling the reference voltage to be controlled externally. Refer to Section 4.7 "Reference Voltage Generator" for details. DS20005254A-page 12 2013 Microchip Technology Inc. MCP1632 4.0 DETAILED DESCRIPTION 4.1 Device Overview The MCP1632 device is comprised of an internal oscillator, an internal constant current generator, a high-speed comparator, a high-bandwidth amplifier, an internal ramp generator for slope compensation and logic gates, and is intended to be used to develop a stand-alone switch-mode power supply. There are two (orderable) switching frequency options for this device: 300 kHz or 600 kHz. Refer to Functional Block Diagram for details about the internal functional blocks. 4.2 PWM Circuitry MCP1632 implements a typical Peak Current Mode control loop. The VEXT output of the MCP1632 device is determined by the output level of the internal high-speed comparator and the level of the internal CLK signal. When the CLK signal level is high, the PWM output (VEXT) is forced low, limiting the maximum duty cycle to approximately 85% (typical). When the CLK signal is low, the PWM output is determined by the output level of the internal high-speed comparator. During UVLO, the VEXT pin is held in low state. During overtemperature operation, the VEXT pin is high-impedance (10 k to ground, typical). 4.3 Normal Cycle-by-Cycle Control The beginning of a PWM cycle is defined by the internal CLK signal (a transition from high to low). Refer to Figure 4-1 for the detailed timing operation of the MCP1632 PWM controller. For normal operation, the state of the high-speed comparator output (R) is low and the Q output of the latch is low. On the high-to-low transition of the CLK signal, the SR inputs to the high-speed latch are both low and the Q output will remain unchanged (low). The output of the OR gate (VDRIVE) will transition from high to low, turning on the P-Channel drive transistor in the output stage of the PWM. This will change the PWM output (VEXT) from low to high, turning on the power train MOSFET and ramping current in the power train magnetic device. The sensed current in the magnetic device is fed into the CS input, shown as a ramp, and increases linearly until it reaches the same level as the divided down output of the error amplifier at the non-inverting input of the high-speed comparator. The comparator output (R) changes state (low to high) and resets the PWM latch. The Q output transition from low to high turns off the VEXT drive to the external MOSFET driver, thus terminating the current conduction cycle. The CLK signal will transition from low to high while the VEXT pin remains unchanged. If the CS input pin never reaches the same level as the error amplifier output, the low-to-high transition on the CLK signal terminates the current switching cycle. This would be considered as the maximum duty cycle. In either case, while the 2013 Microchip Technology Inc. CLK signal is high, the VEXT drive pin is low, turning off the external power train switch. The next switching cycle will start on another transition of the CLK signal from high to low. 4.4 Error Amplifier/Comparator Current Limit Function The internal amplifier is used to create an error output signal that is determined by the VREF input pin and the power supply output voltage fed back into the FB pin. The error amplifier output is rail-to-rail and is clamped by a precision 2.7V internal voltage source. The output of the error amplifier is then divided down 3:1 and connected to the inverting input of the high-speed comparator. The maximum output of the error amplifier is 2.7V, so the maximum input to the inverting pin of the high-speed comparator is 0.9V. As the output load current demand increases, the error amplifier output increases too, causing the inverting input pin of the high-speed comparator to increase. Eventually, the output of the error amplifier will hit the 2.7V clamp, limiting the input of the high-speed comparator to 0.9V maximum. Even if the FB input continues to decrease, calling for more current, the inverting input is limited to 0.9V. By limiting the inverting input to 0.9V, the current sense (CS) input is limited to 0.9V, thus limiting the current that flows in the main switch. Limiting the maximum peak current in the switch prevents the destruction of the semiconductor device and the saturation of the inductor during overloads. The resistor divider placed at the output of the error amplifier decreases the gain of the control loop by 9.5 dB. The designer must take into account this gain reduction during the compensation loop process. The error amplifier is rail-to-rail at the input and the common-mode range includes the GND and VIN potentials. 4.5 0% Duty Cycle Operation The duty cycle of the VEXT output is capable of reaching 0% when the FB pin (inverting error amplifier) is held higher than the voltage present on the VREF (Reference Voltage) pin. This is accomplished by the rail-to-rail output capability of the error amplifier and the offset voltage of the high-speed comparator. The minimum error amplifier output voltage, divided by 3, is less than the offset voltage of the high-speed comparator. In case the output voltage of the converter is above the desired regulation point, the FB input will be above the VREF input and the error amplifier will be pulled to the bottom rail (GND). This low voltage is divided down 3:1 by the 2R and 1R resistor, and is connected to the input of the high-speed comparator. This voltage will be low enough so that there is no triggering of the comparator, allowing narrow pulse widths at VEXT. DS20005254A-page 13 MCP1632 CLK /S Ramp Signal EA Out ISENSE R/ Comp Out Q VDRIVE VEXT FIGURE 4-1: 4.6 PWM Timing Diagram. Slope Compensation In order to prevent sub-harmonic oscillations that occur when a Peak Current Mode converter exceeds a 50% duty cycle, the MCP1632 provides an internal ramp generator that can be used for slope compensation. Refer to Figure 4-2 for details about the slope generator circuit. The amplitude of the generated ramp signal is 0.9 VPP (typical) and the DC offset value is 770 mV (typical). The impedance of the internal ramp generator (RG) is 6 ktypical. The amplitude of the slope compensation ramp can be adjusted by modifying the value of the RSLOPE resistor. Refer to Figure 4-3 for details about the slope compensation ramp signal applied to CS pin. The parameters of the slope compensation ramp signal can be calculated with the provided equations. The MCP1632 device is equipped with a blanking circuit for the CS pin in order to prevent any false resets of the RS latch due to noise. However, for certain applications, it is recommended to place a small value capacitor (CFILTER) between the CS pin and GND to provide additional filtering for the current sense signal. The recommended value ranges from 10 pF to 30 pF. Use caution, because a higher value may affect the slope compensation ramp. DS20005254A-page 14 Oscillator 300/600 kHz Ramp 0.9 VPP L +1 VEXT RG 6 k: CS To PWM Comparator FIGURE 4-2: Circuit. Q RSLOPE CFILTER (Optional) RSENSE Slope Compensation 2013 Microchip Technology Inc. MCP1632 Amplitude (V) Amplitude (V) VIN VREF 0.9*VREF DCHIGH 50 A Slope (V) VREF VREF RVREF CSS DCLOW Time(s) Time R SLOPE Slope V PP = 0.9 V PP -------------------------------------RSLOPE + RG R R SLOPE DC V = 0.32 V -------------------------------------LOW R +R SLOPE G R SLOPE DCHIGH V = 1.22 V -------------------------------------R SLOPE + R G FIGURE 4-3: (CS) Pin. 4.7 Slope Compensation Signal Reference Voltage Generator The internal precision constant current generator and an external resistor connected between the VREF pin and GND form the reference voltage generator. Refer to Figure 4-4 for details. Optionally, a capacitor (CSS) can be connected in parallel with RVREF to activate the soft start function that will minimize overshoots of the output voltage during start-up. The equations in Figure 4-4 calculate the value of the resistor (RVREF) for a given reference voltage and the value of the soft start capacitor (CSS) based on the necessary time to reach 90% of the final value for VREF. An internal circuit of the MCP1632 device will discharge the capacitor during the shutdown period. This capacitor must be of good quality, with low leakage currents, in order to avoid any errors that can affect the reference voltage. The reference voltage should not exceed 80% of the bias input voltage (VIN pin) in order to avoid any errors that affect the internal constant current generator. An external low-noise, low-impedance source can be used to overdrive the VREF pin in order to control the reference voltage. In this case, the resistor/capacitor group connected to GND is not necessary, and the soft start profile must be controlled by the external reference voltage generator. 2013 Microchip Technology Inc. VREF V V REF = -----------------------50 A t s CSS F = ------------------------------------------2.3 R VREF FIGURE 4-4: Generator. 4.8 Reference Voltage Internal Oscillator The MCP1632 PWM controller provides two (orderable) switching frequency options: 300 kHz and 600 kHz. 4.9 Undervoltage Lockout (UVLO) When the input voltage (VIN) is less than the UVLO threshold, the VEXT is held in low state. This will ensure that, if the voltage is not adequate to power the MCP1632 device, the main power supply switch will be held in off state. In order to prevent oscillations when the input voltage is near the UVLO threshold, the UVLO circuit offers 100 mV (typical) hysteresis. Typically, the MCP1632 device will not start until the input voltage at VIN is between 2.8V and 2.9V (typical). 4.10 Overtemperature Protection To protect the VEXT output if shorted to VIN or GND, the VEXT output of the MCP1632 device will be high-impedance if the junction temperature is above the thermal shutdown threshold. An internal 10 k pull-down resistor is connected from VEXT to ground to provide some pull-down during overtemperature conditions. The protection is set to 150C (typical), with a hysteresis of 20C. DS20005254A-page 15 MCP1632 NOTES: DS20005254A-page 16 2013 Microchip Technology Inc. MCP1632 5.0 APPLICATION CIRCUITS 5.1 Typical Applications The MCP1632 PWM controller can be used for applications that require low-side MOSFET control, such as Boost, Buck-Boost, Flyback, SEPIC or uk converters. By using an external high-side MOSFET driver (e.g. MCP14628), the MCP1632 device is able to control the buck converter. The MCP1632 PWM controller can be easily interfaced with a microcontroller in order to develop intelligent solutions, such as battery chargers or LED drivers. Figure 5-1 depicts the typical boost converter controlled by MCP1632. The input voltage applied on the VIN pin of the MCP1632 device should be kept below 5.5V. If the converter must operate with input voltages higher than 5.5V, a linear voltage regulator can be used to bias the MCP1632 controller. The Peak Current Mode control used in this case will ensure consistent performance over a wide range of operating conditions. The Q1 MOSFET is protected against overcurrent by internally limiting the maximum voltage at the output of the error amplifier of the controller. If the voltage applied on the CS pin exceeds 0.9V, the MCP1632 device will reduce the duty cycle in order to prevent overcurrent in Q1 MOSFET. The maximum drain peak current in Q1 can be calculated using Equation 5-1. The slope compensation ramp amplitude may limit the maximum peak current and must be considered when calculating this parameter. The DC offset of the slope compensation ramp (DCHIGH) is calculated using the equations provided in Figure 4-3. Note that the boost converter is not protected against the output short circuit. EQUATION 5-1: I 0.9V - D DC HIGH V Max A = -------------------------------------------------------------Peak R SENSE + VIN - CIN L1 LDO D1 + VOUT R3 VIN R1 VREF Q1 VEXT EN MCP1632 CSS COUT RSLOPE CS RVREF R2 COMP RSENSE FB GND FIGURE 5-1: MCP1632 Boost Converter. 2013 Microchip Technology Inc. DS20005254A-page 17 MCP1632 The single-ended primary inductor converter (SEPIC) used to drive an LED string is presented in Figure 5-2. This converter offers buck-boost functionality and is protected against the output short circuit. The inductors can share the same magnetic core (coupled inductors); in this case, the mutual inductance doubles the value of the inductor, reducing the ripple of the current. The LED string can be dimmed by driving the EN pin (PWM dimming) or by adjusting the value of the RVREF resistor (current dimming). The maximum allowable peak current into Q1 MOSFET can be calculated using Equation 5-1. The SEPIC converter exhibits poor dynamic performance and is recommended only for applications with low step response demands, like LED drivers or battery chargers. + VIN - CIN L1A LDO C1 CC R1 D1 VIN VREF L1B Q1 VEXT COUT EN MCP1632 C2 CSS RSLOPE CS RVREF COMP C3 RSENSE R2 RS FB GND R3 FIGURE 5-2: DS20005254A-page 18 MCP1632 SEPIC Converter. 2013 Microchip Technology Inc. 2013 Microchip Technology Inc. A typical charger application for one- or two-cell Li-Ion batteries is presented in Figure 5-3. The PIC microcontroller handles all the necessary functions of the charger and the MCP1632 device controls the power train. Using the SEPIC converter allows developing a universal charger where the input voltage can be higher or lower than the battery voltage. The microcontroller can control the reference voltage across certain limits using its internal high-frequency PWM generator and the external circuit consisting of D2 and R1. This circuit can be replaced with a digital-to-analog converter (DAC) for a better range and accuracy of the reference voltage control. The charging current is monitored using a low-side shunt (RS) and an inverting amplifier. The floating voltage of the charger is controlled by MCP1632 and can be adjusted by varying the value of the RVREF resistor or the ratio of the feedback divider (R5, R6). Additional protection features can be implemented in the microcontroller's firmware. + VIN - CIN L1A LDO C1 CC VCC VSENSE AN1 D1 VIN R5 EN I/O R1 D2 CSS MCP1632 C2 Q1 VEXT VREF PIC Micro PWM Status Battery RSLOPE R6 COMP C3 R7 COUT VSENSE CS RVREF I/O L1B RSENSE R8 RS R2 FB AN2 GND R3 + FIGURE 5-3: Battery Charger Circuit. MCP1632 DS20005254A-page 19 R4 CSENSE MCP1632 5.2 Operation in Voltage Mode Control The MCP1632 PWM controller can operate in Voltage Mode Control using the internal slope compensation ramp to generate the PWM signal. The current sense resistor is not necessary for this application, thus the overall efficiency of the converter can be improved. Refer to Typical Application Circuit - Voltage Mode Control. Certain limitations occur in this operating mode. The compensation network for Voltage Mode Control must be of Type III, increasing the number of components.The closed-loop system is now a second order system and stability can be difficult to achieve over a wide range of operating conditions. The position of the dominant pole (double pole) in boost-derived converters varies with the operating conditions (input/output voltages); maintaining acceptable phase and gain margins across the entire operating range of the converter becomes a difficult task in this case. Note that there is no inherent protection mechanism that can limit the inductor's current during transients or overloads. A resistor placed between the CS pin and GND allows adjusting the maximum duty cycle by controlling the amplitude of the ramp signal. Refer to Figure 5-4 for details. If the RDC Adj resistor is not placed, the maximum duty cycle is set to approximately 60% (typical). The duty cycle can be increased up to 85% (typical) by adjusting the value of the RDC Adj resistor. The designer must limit the maximum operating duty cycle of the converter to a safe value by adjusting the value of this resistor. The DC offset of the ramp enables operation with 0% duty cycle if the output of the error amplifier divided by 3 is lower than DCLOW. The Voltage Mode Control should be used only for systems with low input voltages, low DC conversion ratios and limited dynamics of the load (e.g., LED drivers or battery chargers). Oscillator 300/600 kHz L + - EA 2R 2.7V R +1 RAMP 0.9 VPP VEXT Q RG 6 k: CS PWM + FIGURE 5-4: DS20005254A-page 20 RDC Adj Voltage Mode Operation Details. 2013 Microchip Technology Inc. MCP1632 5.3 PCB Layout Recommendations The PCB layout is critical for switch-mode power supplies. When developing the PCB, the designer must follow the general rules for switching converters in order to achieve consistent performance. The guidelines include: * Identify the high-current, high-frequency loops before starting the PCB design. Figure 5-5 depicts these loops for boost converters. I1 and I2 are the main currents of the boost converter. The IRR is the current produced by the reverse recovery of the output rectifier D1. The IRR current is an important source of noise/EMI. * Minimize the area of the high-current loops. Use copper planes or large traces for high-current connections in order to minimize the parasitic inductances. + VIN - * Four-layer PCBs with internal ground plane offer the best performance for switch-mode power supplies. For cost-sensitive applications, two-layer PCBs can be used. In this case, the bottom layer must be used like a ground plane. * Use separate grounds for small-signal and power signals. These grounds must be connected (when possible) in a single point located near the GND pin of the MCP1632 controller. * Keep the current sense (CS) and feedback (FB) signals away from noisy nodes, such as the drain of the main switch (Q1). * Locate the compensation network components near the MCP1632 case. I1 CIN L1 I2 D1 + VOUT - VIN Q1 VREF VEXT IDR EN COUT MCP1632 RSLOPE CS RSENSE COMP IRR FB GND FIGURE 5-5: The Boost Converter's Current Loops. 2013 Microchip Technology Inc. DS20005254A-page 21 MCP1632 NOTES: DS20005254A-page 22 2013 Microchip Technology Inc. MCP1632 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead DFN (2x3x0.9 mm) 8-Lead MSOP (3x3 mm) Example Part Number Code MCP1632-AAE/MC ACD MCP1632-BAE/MC ACY MCP1632T-AAE/MC ACD MCP1632T-BAE/MC ACY ACD 349 25 Example 1632AA 349256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2013 Microchip Technology Inc. DS20005254A-page 23 MCP1632 /HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH 0& [[PP%RG\>')1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ e D b N N L K E2 E EXPOSED PAD NOTE 1 NOTE 1 2 1 1 2 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ 6WDQGRII $ &RQWDFW7KLFNQHVV $ 5() 2YHUDOO/HQJWK ' %6& 2YHUDOO:LGWK ( ([SRVHG3DG/HQJWK ' ([SRVHG3DG:LGWK ( E &RQWDFW/HQJWK / &RQWDFWWR([SRVHG3DG . &RQWDFW:LGWK %6& %6& 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHPD\KDYHRQHRUPRUHH[SRVHGWLHEDUVDWHQGV 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ && DS20005254A-page 24 2013 Microchip Technology Inc. MCP1632 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc. DS20005254A-page 25 MCP1632 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005254A-page 26 2013 Microchip Technology Inc. MCP1632 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc. DS20005254A-page 27 MCP1632 8-Lead Plastic Micro Small Outline Package (UA) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005254A-page 28 2013 Microchip Technology Inc. MCP1632 APPENDIX A: REVISION HISTORY Revision A (December 2013) * Original Release of this Document. 2013 Microchip Technology Inc. DS20005254A-page 29 MCP1632 NOTES: DS20005254A-page 30 2013 Microchip Technology Inc. MCP1632 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X /XX Device Frequency Temperature Range Package Device: MCP1632: High-speed, low-side PWM controller MCP1632T: High-speed, low-side PWM controller (Tape and Reel) Examples: a) b) c) d) Frequency: AA BA = = 300 kHz 600 kHz Temperature Range: E = -40C to +125C Package: MC = MS = Plastic Dual Flat, No Lead - 2x3x0.9 mm body (DFN) Plastic Micro Small Outline a) b) c) d) 2013 Microchip Technology Inc. MCP1632-AAE/MC: Extended temperature, 8LD 2x3 DFN package MCP1632T-AAE/MC: Tape and Reel, Extended temperature, 8LD 2x3 DFN package MCP1632-BAE/MC: Extended temperature, 8LD 2x3 DFN package MCP1632T-BAE/MC: Tape and Reel, Extended temperature, 8LD 2x3 DFN package MCP1632-AAE/MS: Extended temperature, 8LD MSOP package MCP1632T-AAE/MS: Tape and Reel, Extended temperature, 8LD MSOP package MCP1632-BAE/MS: Extended temperature, 8LD MSOP package MCP1632T-BAE/MS: Tape and Reel, Extended temperature, 8LD MSOP package DS20005254A-page 31 MCP1632 NOTES: DS20005254A-page 32 2013 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62077-770-1 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2013 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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