Features
■-80/-85dBc 2nd/3rd HD at 20MHz
■-3dB bandwidth of 170MHz
■0.1% settling in 22ns
■Complete overdrive protection
■2400V/µs slew rate
■3MΩinput resistance
■Output may be current limited
■Direct replacement for CLC207
Applications
■Fast, precision A/D conversion
■Automatic test equipment
■Input/output amplifiers
■Photodiode, CCD preamps
■High-speed modems, radios
■Line drivers
General Description
The KH207 is a wideband, low distortion operational
amplifier designed specifically for applications requiring
both high speed and wide dynamic range. Utilizing
a proprietary current feedback architecture, the
KH207 offers performance far superior to that of
conventional voltage feedback op amps.
The most attractive feature of the KH207 is its
extremely low distortion: -80/-85dBc 2nd/3rd harmonics
at 20MHz (2Vpp, RL = 200Ω). The KH207 also provides
-3dB bandwidth of 170MHz at a gain of +20, settles to
0.1% in 22ns and slews at a rate of 2400V/µs. The
combination of these features positions the KH207 as
the right choice for high speed applications requiring
exceptional signal purity.
High speed, high resolution A/D and D/A converter
systems requiring low distortion operation will find
the KH207 an excellent choice. Wide dynamic range
systems such as radar and communication receivers
will find that the KH207’s low harmonic distortion and
low noise make it an attractive high speed solution.
The addition of the KH207 to the KH205/206 Series
of high speed operational amplifiers broadens the
selection of features available from which to choose.
The KH205 offers low power operation, the KH206
offers higher drive operation, and the KH207 offers
operation with extremely low distortion, all of which
are pin compatible and overdrive protected.
The KH207 is constructed using thin film resistor/bipolar
transistor technology, and is available in the following
versions:
KH207AI -25°C to +85°C 12-pin TO-8 can
KH207AK -55°C to +125°C 12-pin TO-8 can, features
burn-in & hermetic testing
KH207AM -55°C to +125°C 12-pin TO-8 can,
environmentally
screened and electrically
tested to MIL-STD-883
KH207HXC -55°C to +125°C SMD#: 5962-9097701HXC
KH207HXA -55°C to +125°C SMD#: 5962-9097701HXA
KH207
Low Distortion Wideband Op Amp
www.fairchildsemi.com
REV. 1A February 2001
Typical Performance
Gain Setting
Parameter +7 +20 +50 -1 -20 -50 Units
-3dB bandwidth 220 170 80 220 130 80 MHz
rise time 1.7 2.2 4.7 1.7 2.9 4.7 ns
slew rate 2.4 2.4 2.4 2.4 2.4 2.4 V/ns
settling time (to 0.1%) 22 22 20 21 20 19 ns
Supply
Voltage
2000Ω
8
Rf
7
GND
9
-VCC
2
NC
3
GND
1
+VCC
6
V+
5
V-
4
NC
10
-VCC
Vo
+VCC
11
12
6
6
Collector
Supply
Output
Collector
Supply
Supply
Voltage
Internal
Feedback
Not Connected
Case
ground
Non-Inverting
Input
Inverting
Input
Not
Connected
Case and
bias ground
+
-
Bottom View
Pin 8 provides access to a 2000Ωfeed-
back resistor which can be connected to
the output or left open if an external feed-
back resistor is desired.
DATA SHEET KH207
2REV. 1A February 2001
PARAMETERS CONDITIONS TYP MIN & MAX RATINGS UNITS SYM
Ambient Temperature KH207AI +25°C -25°C +25°C +85°C
Ambient Temperature KH207AK/AM/HXC/HXA +25°C -55°C +25°C +125°C
FREQUENCY DOMAIN RESPONSE
✝-3dB bandwidth Vo<2Vpp 170 >140 >140 >125 MHz SSBW
large-signal bandwidth Vo<10Vpp 100 >72 >80 >80 MHz FPBW
gain flatness Vo<2Vpp
✝peaking 0.1 to 35MHz 0 <0.3 <0.3 <0.5 dB GFPL
✝peaking >35MHz 0 <0.8 <0.5 <0.8 dB GFPH
✝rolloff at 70MHz –<0.8 <0.8 <0.8 dB GFR
group delay to 70MHz 3.0 ± .2 –––ns GD
linear phase deviation to 50MHz 0.8 <3.0 <2.0 <3.0 °LPD
TIME DOMAIN RESPONSE
rise and fall time 2V step 2.2 <2.6 <2.6 <3.0 ns TRS
10V step 4.8 <5.5 <5.5 <5.5 ns TRL
settling time to 0.1% 10V step, note 2 22 <27 <27 <27 ns TS
to 0.05% 10V step, note 2 24 <30 <30 <30 ns TSP
overshoot 5V step 7 <14 <14 <14 % OS
slew rate 20Vpp at 50MHz 2.4 >1.8 >2.0 >2.0 V/ns SR
NOISE AND DISTORTION RESPONSE
✝2nd harmonic distortion ✝ 2Vpp, 20MHz, RL= 200Ω-80 <-68 <-76 <-76 dBc HD2
2Vpp, 20MHz, RL= 100Ω-69 <-64 <-64 <-64 dBc HD2
✝3rd harmonic distortion ✝ 2Vpp, 20MHz, RL= 200Ω-85 <-76 <-76 <-76 dBc HD3
2Vpp, 20MHz, RL= 100Ω-69 <-64 <-64 <-64 dBc HD3
equivalent input noise
voltage >100kHz 1.6 <1.8 <1.8 <1.8 nV/√Hz VN
inverting current >100kHz 20 <23 <23 <23 pA/√Hz ICN
non-inverting current >100kHz 2.2 <2.5 <2.5 <2.5 pA/√Hz NCN
noise floor >100kHz -158 <-157 <-157 <-157 dBm(1Hz) SNF
integrated noise 1kHz to 150MHz 33 <38 <38 <38 µV INV
integrated noise 5MHz to 150MHz 33 <38 <38 <38 µV INV
STATIC, DC PERFORMANCE
* input offset voltage 3.5 <8.0 <8.0 <11.0 mV VIO
average temperature coefficient 11 <25 <25 <25 µV/°C DVIO
* input bias current non-inverting 3.0 <25 <15 <15 µA IBN
average temperature coefficient 15 <100 <100 <100 nA/°C DIBN
* input bias current inverting 2.0 <22 <10 <25 µA IBI
average temperature coefficient 20 <150 <150 <150 nA/°C DIBI
* power supply rejection ratio 69 >55 >55 >55 dB PSRR
common mode rejection ratio 60 >50 >50 >50 dB CMRR
* supply current no load 25 <27 <27 <29 mA ICC
MISCELLANEOUS PERFORMANCE
non-inverting input resistance DC 3.0 >1.0 >1.0 >1.0 MΩRIN
non-inverting input capacitance 70MHz 5.0 <7.0 <7.0 <7.0 pF CIN
output impedance DC –<0.1 <0.1 <0.1 ΩRO
output voltage range no load ±12 >±11 >±11 >±11 V VO
internal feedback resistor 2.0 –––kΩRF
absolute tolerance ––<0.2 –%RFA
temperature coefficient ––-100 ±40 –ppm/°C RFTC
inverting input current self limit 2.2 <3.0 <3.0 <3.2 mA ICL
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings Recommended Operating Conditions
VCC ±20V VCC ±5V to ±15V
Io±150mA Io±100mA
common mode input voltage, Vo|VCC| > 15V ±(29 - |VCC|)V common mode input voltage ±(|VCC| -5)V
|VCC| ≤15V ±(|VCC| -1)V gain range +7 to +50, -1 to -50
differential input voltage ±3V note 1: * AI/AK/AM/HXC/HXA 100% tested at +25°C
thermal resistance (see thermal model) ✝AK/AM/HXC/HXA 100% tested at +25°C and sample
junction temperature +175°C tested at -55°C and +125°C
operating temperature AI: -25°C to +85°C✝AI sample tested at +25°C
AK/AM/HXC/HXA: -55°C to +125°Cnote 2: Settling time specifications require the use of an external
storage temperature -65°C to +150°C feedback resistor (2kΩ).
lead temperature (soldering 10s) +300°C
KH207 Electrical Characteristics (Av= +20V, VCC = ±15V, RL= 200Ω, Rf= 2kΩ; unless specified)
KH207 DATA SHEET
REV. 1A February 2001 3
KH207 Typical Performance Characteristics (TA= +25°C, Av= +20, VCC = ±15V, Rf= 20Ω,R
L= 200Ω; unless specified)
Non-Inverting Frequency Response
Normalized Magnitude (1dB/div)
Phase (45°/div)
Frequency (MHz)
0 20 40 60 80 100 120 140 160 180 200
Gain
Phase
Av = +7
Av = +20
Av = +50
Av = +7
Av = +20
Av = +50
Inverting Frequency Response
Normalized Magnitude (1dB/div)
Phase (45°/div)
Frequency (MHz)
0 20 40 60 80 100 120 140 160 180 200
Gain
Phase
Av = -1
Av = -7
Av = -1
Av = -7
Av = -20
Av = -50
Av = -20
Av = -50
Frequency Response vs. External Rf
Relative Gain (5dB/div)
Frequency (MHz)
0 20 40 60 80 100 120 140 160 180 200
Rf = 1.5kΩ
Av = +7
Av = +50
Av = +20
Rf = 2kΩ
Rf = 3kΩ
Rf = 1.5kΩ
Rf = 2kΩ
Rf = 3kΩRf = 1.5kΩRf = 2kΩ
Rf = 3kΩ
Large Signal Gain and Phase
Magnitude (1dB/div)
Phase (45°/div)
Frequency (MHz)
0 153045607590105120135
150
Vo = 10Vpp
Gain
Phase
Relative Bandwidth vs. VCC
Relative Bandwidth
±VCC (V)
4 6 8 10 12 14 16
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Gain and Phase for Various Loads
Magnitude (1dB/div)
Phase (45°/div)
Frequency (MHz)
0 20 40 60 80 100 120 140 160 180 200
RL = 50Ω
RL = 100Ω
RL = 200Ω
RL = 1kΩ
RL = 1kΩ
RL = 200Ω
RL = 100Ω
RL = 50Ω
Gain
Phase
Small Signal Pulse Response
Output Voltage (0.4V/div)
Time (5ns/div)
Av = +20
Av = -20
Large Signal Pulse Response
Output Voltage (2V/div)
Time (5ns/div)
Av = +20
Av = -20
Settling Time
Settling Error (%)
Time (5ns/div)
10V step
Rf = 2kΩ (external)
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
2nd and 3rd Harmonic Distortion
Distortion (dBc)
Frequency (MHz)
-40
-75
-70
-65
-60
-55
-50
-45
-90
110 100
-80
-85
2nd
3rd
2nd Harmonic Distortion, RL = 100Ω
Distortion (dBc)
Frequency (MHz)
-20
-70
-60
-50
-40
-30
-90
110 100
-80
8Vpp
16Vpp
4Vpp
2Vpp
1Vpp
3rd Harmonic Distortion, RL = 100Ω
Distortion (dBc)
Frequency (MHz)
-20
-70
-60
-50
-40
-30
-90
110 100
-80
8Vpp
16Vpp
4Vpp
2Vpp
1Vpp
Equivalent Input Noise
Noise Voltage (nV√Hz)
Frequency (Hz)
100
10
1
Noise Current (pA√Hz)
100
10
1
102103104105106107108
Inverting Current 20pA√Hz
Non-Inverting Current 2.2pA√Hz
Voltage 1.6nV/√Hz
2-Tone, 3rd Order Intermod. Intercept
Interdept Point (dBm)
Frequency (MHz)
45
40
35
30
25
20
15
0 10203040 5060708090100
50Ω
50Ω
Pout
CMRR and PSRR
PSRR and CMRR (dB)
Frequency (Hz)
0
20
40
60
80
100
100 1k 100M10k 100k 1M 10M
PSRR
CMRR
DATA SHEET KH207
4REV. 1A February 2001
Current Feedback Amplifiers
Some of the key features of current feedback technology
are:
■Independence of AC bandwidth and voltage gain
■Adjustable frequency response with feedback resistor
■High slew rate
■Fast settling
Current feedback operation can be described using a simple
equation. The voltage gain for a non-inverting or inverting
current feedback amplifier is approximated by Equation 1.
Equation 1
where:
■Avis the closed loop DC voltage gain
■Rfis the feedback resistor
■Z(jω) is the CLC205’s open loop transimpedance
gain
■is the loop gain
The denominator of Equation 1 is approximately equal to
1 at low frequencies. Near the -3dB corner frequency, the
interaction between Rfand Z(jω) dominates the circuit
performance. The value of the feedback resistor has a
large affect on the circuits performance. Increasing Rf
has the following affects:
■Decreases loop gain
■Decreases bandwidth
■Reduces gain peaking
■Lowers pulse response overshoot
■Affects frequency response phase linearity
Overdrive Protection
Unlike most other high-speed op amps, the KH207 is not
damaged by saturation caused by overdriving input
signals (where Vin x gain > max. Vo). The KH207 self
limits the current at the inverting input when the output is
saturated (see the inverting input current self limit
specification); this ensures that the amplifier will not be
damaged due to excessive internal currents during overdrive.
For protection against input signals which would exceed
either the maximum differential or common mode input
voltage, the diode clamp circuits below may be used.
Figure 1: Diode Clamp Circuits for Common Mode
and Differential Mode Protection
Short Circuit Protection
Damage caused by short circuits at the output may be
prevented by limiting the output current to safe levels.
The most simple current limit circuit calls for placing
resistors between the output stage collector supplies and
the output stage collectors (pins 12 and 10). The value of
this resistor is determined by:
where IIis the desired limit current and RIis the minimum
expected load resistance (0Ωfor a short to ground).
Bypass capacitors of 0.01µF on should be used on the
collectors as in Figures 2 and 3.
Figure 2: Recommended Non-Inverting Gain Circuit
Figure 3: Recommended Inverting Gain Circuit
A more sophisticated current limit circuit which provides
a limit current independent of RIis shown in Figure 4 on
page 5.
With the component values indicated, current limiting
occurs at 50mA. For other values of current limit (II),
select RCto equal Vbe/lI. Where Vbe is the base to
emitter voltage drop of Q3 (or Q4) at a current of [2VCC –
1.4] / Rx, where Rx ≤[(2VCC – 1.4) / II] Bmin.
Also, Bmin is the minimum beta of Q1 (or Q2) at a current
of II. Since the limit current depends on Vbe, which is
temperature dependent, the limit current is likewise
temperature dependent.
differential protection
KH207
+
-
common mode
protection
Rg
+Vcc
Vin
Vo
-Vcc
RV
IR
CC
II
=−
33Ω
+15V
.1
3.9 .01
Capactance in µF
1
12 8
3,7 200Ω
10
11
33Ω
.01
.1
3.9
-15V
9
+
-
KH207 Vo
Rf = 2000Ω (internal)
6
Vin
5
Ri
50Ω
Rg
A1
R
R
v
f
g
=+
33Ω
+15V
.1
3.9 .01
Capactance in µF
1
12 8
5
Vin 3,7 200Ω
10
Ri
11
33Ω
.01
.1
3.9
-15V
9
+
-
KH207 Vo
Rf = 2000Ω (internal)
6
50Ω
Rg
For Zin = 50Ω, select Rg||Ri = 50Ω
A-R
R
vf
g
=
V
V
A
1R
Zj
o
in
v
f
=
+
()
ω
Zj
Rf
ω
()
KH207 DATA SHEET
REV. 1A February 2001 5
Figure 4: Active Current Limit Circuit (50mA)
Controlling Bandwidth and Passband Response
In most applications, a feedback resistor value of 2kΩ
will provide optimum performance; nonetheless, some
applications may require a resistor of some other value.
The response versus Rfplot on the previous page shows
how decreasing Rfwill increase bandwidth (and frequency
response peaking, which may lead to instability).
Conversely, large values of feedback resistance tend to
roll off the response.
The best settling time performance requires the use of an
external feedback resistor (use of the internal resistor
results in a 0.1% to 0.2% settling tail). The settling
performance may be improved slightly by adding a
capacitance of 0.4pF in parallel with the feedback
resistor (settling time specifications reflect performance
with an external feedback resistor but with no external
capacitance).
Thermal Model
Noise Analysis
Approximate noise figure can be determined for the
KH207 using the Equivalent Input Noise plot on page 3
and the equations shown below.
kT = 4.00 x 10-21 Joules at 290°K
Vnis spot noise voltage (V/√Hz)
inis non-inverting spot noise current (A/√Hz)
iiis inverting spot noise current (A/√Hz)
Figure 5: Noise Figure Diagram and Equations
(Noise Figure is for the Network Inside this Box.)
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the KH207 will
improve stability and settling performance.
Transmission Line Matching
One method for matching the characteristic impedance
(Zo) of a transmission line or cable is to place the
appropriate resistor at the input or output of the amplifier.
Figure 6 shows typical inverting and non-inverting circuit
configurations for matching transmission lines.
Figure 6: Transmission Line Matching
Non-inverting gain applications:
■Connect Rgdirectly to ground.
■Make R1, R2, R6, and R7equal to Zo.
■Use R3to isolate the amplifier from reactive
loading caused by the transmission line,
or by parasitics.
Rs
Rn
Ro
Rf
Rg
KH207
+
-
FR
R
R
kT iV
R
Ri
RA
where R RR
RR AR
R
s
n
s
nn
p
fi
pv
p
sn
sn vf
g
=++⋅++
=+=+
10 1 4
1
22
2
22
22
log
;
Q3
(2N3906)
Rx
14.3kΩ
Q4
(2N3904)
0.01ΩF
0.01ΩF
+Vcc
Rc
12Ω
Q1
(MJE170)
Q2
(MJE180)
Rc
12Ω
-Vcc
to pin 10
to pin 12
Pcircuit = [(+VCC) – (-VCC)]2/ 1.77kΩ
Pxxx = [(±VCC) – Vout –(Icol) (Rcol + 6)] (Icol)
(% duty cycle)
(For positive Voand VCC, this is the power in the npn output stage.)
(For negative Voand VCC, this is the power in the pnp output stage.)
θca = 65°C/W in still air without a heatsink.
35°C/W in still air without a Thermalloy 2268.
15°C/W in 300ft/min air with a Thermalloy 2268
(Thermalloy 2240 works equally well.)
Icol = Vout/Rload or 3mA, whichever is greater.
(Include feedback R in Rload.)
Rcol is a resistor (33Ωrecommended) between the xxx collector and ±VCC.
Tj (pnp) = Ppnp (100 + θca) + (Pcir + Pnpn)θca + Ta, similar for Tj (npn).
Tj (cir) = Pcir (17.5 + θca) + (Ppnp + Pnpn)θca + Ta.
+
-
Tambient
θca
Tcase
17.5°C/W
Tj(circuit)
Pcircuit
100°C/W
Tj(npn)
Pnpn
100°C/W
Ppnp
Tj(pnp)
KH207
+
-
R3Z0
R6
Vo
Z0
R1
R2
+
-
Rg
Z0
R4
R5
V1
V2+
-
Rf
C6
R7
DATA SHEET KH207
6REV. 1A February 2001
Inverting gain applications:
■Connect R3directly to ground.
■Make the resistors R4, R6, and R7equal to Zo.
■Make R5II Rg= Zo.
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C6to match the output transmission line over a
greater frequency range. C6compensates for the increase
of the amplifier’s output impedance with frequency.
Dynamic Range (Intermods)
For RF applications, the KH207 specifies a third
order intercept of 26dBm at 60MHz and Po = 10dBm. A
2-Tone, 3rd Order IMD Intercept plot is found in the
Typical Performance Characteristics section. The out-
put power level is taken at the load. Third-order harmon-
ic distortion is calculated with the formula:
HD 3rd = 2 •(IP3o– Po)
where:
■IP3o= third-order output intercept, dBm at
the load.
■Po= output power level, dBm at the load.
■HD 3rd = third-order distortion from the
fundamental, -dBc.
■dBm is the power in mW, at the load,
expressed in dB.
Realized third-order output distortion is highly
dependent upon the external circuit. Some of the
common external circuit choices that improve 3rd order
distortion are:
■short and equal return paths from the load
to the supplies.
■de-coupling capacitors of the correct value.
■higher load resistance.
■a lower ratio of the output swing to the
power supply voltage.
Printed Circuit Layout
As with any high frequency device, a good PCB layout
will enhance the performance of the KH207. Good
ground plane construction and power supply bypassing
close to the package are critical to achieving full perfor-
mance. In the non-inverting configuration, the amplifier is
sensitive to stray capacitance to ground at the inverting
input. Hence, the inverting node connections should be
small with minimal stray capacitance to the ground plane
or other nodes. Shunt capacitance across the feedback
resistor should not be used to compensate for this effect.
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
■Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
■Place the 6.8µF capacitors within 0.75
inches of the power pins.
■Place the 0.1µF capacitors less than 0.1
inches from the power pins.
■Remove the ground plane under and
around the part, especially near the input
and output pins to reduce parasitic
capacitance.
■Minimize all trace lengths to reduce series
inductances.
■Use flush-mount printed circuit board pins
for prototyping, never use high profile DIP
sockets.
An evaluation PC board (part number 730009) for the
KH207 is available to aid in device testing.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT
OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for
surgical implant into the body, or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support device or system whose
failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
KH207 Package Dimensions
DATA SHEET KH207
www.fairchildsemi.com © 2001 Fairchild Semiconductor Corporation
SYMBOL INCHES MILIMETERS
Minimun Maximum Minimum Maximum
A 0.142 0.181 3.61 4.60
φb 0.016 0.019 0.41 0.48
φD 0.595 0.605 15.11 15.37
φD10.543 0.555 13.79 14.10
e 0.400 BSC 10.16 BSC
e10.200 BSC 5.08 BSC
e20.100 BSC 2.54 BSC
F 0.016 0.030 0.41 0.76
k 0.026 0.036 0.66 0.91
k10.026 0.036 0.66 0.91
L 0.310 0.340 7.87 8.64
α45° BSC 45° BSC
NOTES:
Seal: cap weld
Lead finish: gold per MIL-M-38510
Package composition:
Package: metal
Lid: Type A per MIL-M-38510
87 9
23 1
5
6
4
11
10
12
k1
e
φDD
1
TO-8
e1
e2
kα
L
A
F
φb
