CD40175BCN - Fairchild Semiconductor

October 1987

Revised March 2002

CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad D-Type Flip-Flop

CD40174BC • CD40175BC

Hex D-Type Flip-Flop • Quad D-Type Flip-Flop

General Description

The CD4 01 74B C con si sts o f si x po siti ve- ed ge trig ger ed D-

typ e f li p -fl o ps ; th e tr ue ou tpu t s fr om eac h f li p -f lo p a re ex ter -

nally available. The CD40175BC consists of four positive-

edge tri ggered D- type flip-fl ops; both the true an d compl e-

me nt outputs from each flip-flop are externally available.

All flip-flo ps are contr olled by a com mon clock and a com-

mon clear. Information at the D inputs meeting the set-up

time requirements is transferred to the Q outputs on the

positive-g oi ng ed ge of the clock pul s e. T he clea ri ng op er a-

tion, en abled by a ne gative pulse at Clear inpu t, clears all

Q outputs to logical “0” and Q s (CD40175BC only) to logi-

cal “1”.

All inputs are protected from static discharge by diode

clamps to VDD and VSS.

Features

■Wide supply voltage range: 3V to 15V

■High noise immunity: 0.45 VDD (typ.)

■Low power TTL compatibility:

fan out of 2 driving 74L or 1 driving 74 LS

■Equivalent to MC14174B, MC14175B

■Equivalent to MM74C174, MM74C175

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the ordering code.

Connection Diagrams

CD40174B

Top View

CD40175B

Top View

Order Number Package Number Package Description

CD40174BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD40174BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

CD40175BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD40175BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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CD40174BC • CD40175BC

Truth Table

H = HIGH Level

L = LOW Lev el

X = Irrel ev a nt

↑ = Transition from LOW-to-HIGH level

NC = No change

Note 1: Q for CD40175B only

Inputs Outputs

Clear Clock D Q Q

(Note 1)

LXXLH

H↑HHL

H↑LLH

HHXNCNC

HLXNCNC

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CD40174BC • CD40175BC

Absolute Maximum Ratings(Note 2)

(Note 3) Recommended Operating

Conditions (Note 3)

Note 2: “Absolute Maximum Ratings” are those va lues beyond which the

safety of the device cannot be guaranteed. They are not meant to imply

that the de vices shou ld be ope rated at the se limits . The tables of “Recom-

mended Operating Conditions” and “Electrical Charac t eristics” pro v ide con-

ditions f or actual device o peration.

Note 3: VSS = 0V unles s ot herwise s pecified .

DC Electrical Characteristics (Note 3)

CD40174BC/CD40175BC

Note 4: IOH and IOL are tested one output at a ti m e.

DC Supply Voltage (VDD)−0.5V to +18V

Input Voltage (VIN)−0.5V to VDD +0.5 VDC

Stora ge Tem per atu re R ang e (TS)−65°C to +150°C

Power Di ssipa ti on (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seco nds) 260 °C

DC Supply Voltage (VDD) 3V to 15 VDC

Input Voltage (VIN) 0V to VDD VDC

Operating Temperature Range (TA)−55°C to +125°C

Symbol Parameter Conditions −55°C+25°C+125°CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device VDD = 5V, VIN = VDD or VSS 1.0 1.0 30 µACurrent VDD = 10V, VIN = VDD or VSS 2.0 2.0 60

VDD = 15V, VIN = VDD or VSS 4.0 4.0 120

VOL LOW Level Output VDD = 5V 0.05 0.05 0.05 VVoltage VDD = 10V |IO| < 1 µA 0.05 0.05 0.05

VDD = 15V 0.05 0.05 0.05

VOH HIGH Level Output VDD = 5V 4.95 4.95 5 4.95 VVoltage VDD = 10V |IO| < 1 µA 9.95 9.95 10 9.95

VDD = 15V 14.95 14.95 15 14.95

VIL LOW Level Input VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 VVoltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0

VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0

VIH HIGH Level Input VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 VVoltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0

VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0

IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mACurrent (Note 4) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9

VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4

IOH HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 mACurrent (Note 4) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9

VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4

IIN Input Current VDD = 15V, VIN = 0V 0.1 −10−50.1 −1.0 µA

VDD = 15V, VIN = 15V −0.1 10−5−0.1 1.0

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CD40174BC • CD40175BC

AC Electrical Characteristics (Note 5)

TA = 25°C, CL = 50 pF, RL = 200k and tr = tf = 20 ns, unless otherwise specified

Note 5: AC Parameters are guara nt eed by DC c orrelat ed testing.

Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application

note, AN-90.

Symbol Parameter Conditions Min Typ Max Units

tPHL, tPLH Propagation Delay Time to a VDD = 5V 190 300 nsLogical “0” or Logical “1” from VDD = 10V 75 110

Clock to Q or Q (CD40175 Only) VDD = 15V 60 90

tPHL Propagation Delay Time to a VDD = 5V 180 300 nsLogical “0” from Clear to Q VDD = 10V 70 110

VDD = 15V 60 90

tPLH Propagation Delay Time to a Logical VDD = 5V 230 400 ns“1” from Clear to Q (CD40175 Only) VDD = 10V 90 150

VDD = 15V 75 120

tSU Time Prior to Clock Pulse that VDD = 5V 45 100 nsData must be Present VDD = 10V 15 40

VDD = 15V 13 35

tHTime after Clock Pulse that VDD = 5V −11 0 nsData Must be Held VDD = 10V −40

VDD = 15V −30

tTHL, tTLH Transition Time VDD = 5V 100 200 nsVDD = 10V 50 100

VDD = 15V 40 80

tWH, tWL Minimum Clock Pulse Width VDD = 5V 130 250 nsVDD = 10V 45 100

VDD = 15V 40 80

tWL Minimum Clear Pulse Width VDD = 5V 120 250 nsVDD = 10V 45 100

VDD = 15V 40 80

tRCL Maximum Clock Rise Time VDD = 5V 15 µsVDD = 10V 5.0

VDD = 15V 5.0

tfCL Maximum Clock Fall Time VDD = 5V 15 50 µsVDD = 10V 5.0 50

VDD = 15V 5.0 50

fCL Maximum Clock Frequency VDD = 5V 2.0 3.5 MHzVDD = 10V 5.0 10

VDD = 15V 6.0 12

CIN Input Capacitance Clear Input 10 15 pF

Other Input 5.0 7.5

CPD Power Dissipation Per Package (Note 6) 130 pF

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CD40174BC • CD40175BC

Switching Time Waveforms

tr = tf = 20 ns

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CD40174BC • CD40175BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

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CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad D-Type Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assume an y responsibility for u se of any circuitry described, no circuit patent license s are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.