ST72324Bxx 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI Features Memories 8 to 32 Kbyte dual voltage High Density Flash (HDFlash) or ROM with readout protection capability. In-application programming and Incircuit programming for HDFlash devices 384 bytes to 1 Kbyte RAM HDFlash endurance: 1 kcycle at 55 C, data retention 40 years at 85 C Clock, reset and supply management LQFP32 7x7 SDIP32 400 mil SDIP42 600 mil 4 timers Enhanced low voltage supervisor (LVD) with programmable reset thresholds and auxiliary voltage detector (AVD) with interrupt capability Clock sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input PLL for 2x frequency multiplication 4 power saving modes: Slow, Wait, Active-halt, and Halt Interrupt management LQFP44 10 x 10 Main clock controller with real-time base, Beep and clock-out capabilities Configurable watchdog timer 16-bit Timer A with 1 input capture, 1 output compare, ext. clock input, PWM and pulse generator modes 16-bit Timer B with 2 input captures, 2 output compares, PWM and pulse generator modes 2 communication interfaces Nested interrupt controller. 10 interrupt vectors plus TRAP and RESET. 9/6 ext. interrupt lines (on 4 vectors) SPI synchronous serial interface SCI asynchronous serial interface Up to 32 I/O ports 1 analog peripheral (low current coupling) 32/24 multifunctional bidirectional I/Os, 22/17 alternate function lines, 12/10 high sink outputs Development tools Table 1. In-circuit testing capability Device summary Device Memory RAM (stack) ST72324BK2 Flash/ROM 8 Kbytes 384 (256) bytes ST72324BK4 Flash/ROM 16 Kbytes 512 (256) bytes ST72324BK6 Flash/ROM 32 Kbytes 1024 (256) bytes ST72324BJ2 Flash/ROM 8 Kbytes 384 (256) bytes ST72324BJ4 Flash/ROM 16 Kbytes 512 (256) bytes ST72324BJ6 Flash/ROM 32 Kbytes 1024 (256) bytes March 2009 10-bit ADC with up to 12 input ports Rev 7 Voltage range 3.8 to 5.5 V Temp. range up to -40 to 125 C Package LQFP32 7x7/ SDIP32 LQFP44 10x10/ SDIP42 1/193 www.st.com 1 Contents ST72324Bxx Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.1 4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7.1 5 6 2/193 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Flash Control/Status Register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.4 Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.5 Stack Pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 PLL (phase locked loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ST72324Bxx Contents 6.3.3 6.4 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4.1 6.5 6.6 6.5.1 LVD (low voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5.2 AVD (auxiliary voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.5.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 39 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2.1 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.2 Different interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2.3 Non-maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2.4 Maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.5 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.6 8 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.6.1 7 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.5.2 Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 46 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6.1 I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6.2 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 49 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.4 Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.4.1 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3/193 Contents ST72324Bxx 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.5.1 10 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1 10.2 10.3 4/193 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.4 How to program the Watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.1.6 Hardware Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.1.7 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 68 10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.1.9 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 69 10.2.1 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.2.2 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.3 Real-time clock (RTC) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.2.7 MCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ST72324Bxx Contents 10.3.7 10.4 10.5 10.6 11 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.4.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.4.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.4.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.4.8 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 10.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.5.7 SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10.6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.6.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.6.6 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.1 11.2 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 11.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5/193 Contents 12 ST72324Bxx Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.1 12.2 12.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.4 LVD/AVD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.5 12.6 12.7 12.8 12.9 6/193 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.4.1 Operating conditions with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.4.2 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 145 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.5.1 ROM current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.5.2 Flash current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.5.3 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.5.4 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.6.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.6.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.6.3 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 150 12.6.4 RC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 12.6.5 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.7.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.7.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.8.1 Functional electromagnetic susceptibility (EMS) . . . . . . . . . . . . . . . . . 155 12.8.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 157 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.9.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.9.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ST72324Bxx Contents 12.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.10.2 ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.11 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.11.1 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.12 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 166 12.12.1 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12.13 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.13.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 170 12.13.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 12.13.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.3 14 13.2.1 LQFP44 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.2.2 SDIP42 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.2.3 LQFP32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.2.4 SDIP32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Device configuration and ordering information . . . . . . . . . . . . . . . . . 178 14.1 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 14.1.1 14.2 ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.2.1 14.3 14.4 15 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.3.2 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.3.3 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.3.4 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.3.5 Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 184 ST7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1 All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7/193 Contents ST72324Bxx 15.2 15.3 16 8/193 15.1.1 Safe connection of OSC1/OSC2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1.2 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1.3 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15.1.4 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 187 15.1.5 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.1.6 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 188 15.1.7 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 8/16 Kbyte Flash devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.2.1 39-pulse ICC entry mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.2.2 Negative current injection on pin PB0 . . . . . . . . . . . . . . . . . . . . . . . . . 189 8/16 Kbyte ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.3.1 Readout protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.3.2 I/O Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 ST72324Bxx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Arithmetic management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Software interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupt software priority selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Effect of low power modes on SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AVD interrupt control/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 CPU CC register interrupt bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ISPRx interrupt vector correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Interrupt sensitivity - ei2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Interrupt sensitivity - ei3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Interrupt sensitivity - ei0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Interrupt sensitivity - ei1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MCC/RTC low power mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 I/O port interrupt control/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Effect of lower power modes on Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 MCC/RTC interrupt control/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 MCCBCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Beep frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Input capture byte distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Output compare byte distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 16-bit timer interrupt control/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9/193 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. 10/193 ST72324Bxx CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 CR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 CSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SPI interrupt control/wakeup capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 SPI master mode SCK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SCI interrupt control/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 SCIBRR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SCIETPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Effect of low power modes on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Instructions supporting direct, indexed, indirect and indirect indexed addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Relative direct and indirect instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Operating conditions with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 AVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 ROM current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Flash current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Oscillators, PLL and LVD current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Crystal and ceramic resonator oscillators (8/16 Kbyte Flash and ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Crystal and ceramic resonator oscillators (32 Kbyte Flash and ROM devices) . . . . . . . . 151 OSCRANGE selection for typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 RC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 ST72324Bxx Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. List of tables PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Dual voltage HDFlash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 42-pin dual in line package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 32-pin dual in-line package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Package selection (OPT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11/193 List of figures ST72324Bxx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 12/193 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 44-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 42-pin SDIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 32-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 32-pin SDIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Priority decision process flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Exact timeout duration (tmin and tmax). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 One pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 One Pulse mode timing example(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Pulse width modulation mode timing example with two output compare functions(1)(2) . . 86 ST72324Bxx Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. List of figures Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Data clock timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Clearing the WCOL bit (Write collision flag) software sequence . . . . . . . . . . . . . . . . . . . 103 Single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Bit sampling in Reception mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 fCPU max versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Typical application with a crystal or ceramic resonator (8/16 Kbyte Flash and ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Typical application with a crystal or ceramic resonator (32 Kbyte Flash and ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Typical fOSC(RCINT) vs TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Integrated PLL jitter vs signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Unused I/O pins configured as input(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Typical IPU vs. VDD with VIN = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Typical VOL at VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Typical VOL at VDD = 5 V (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Typical VOH at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Typical VOL vs. VDD (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Typical VOL vs. VDD (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Typical VOH vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Two typical applications with ICCSEL/VPP pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 SPI slave timing diagram with CPHA = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 SPI slave timing diagram with CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 SPI master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 RAIN max. vs fADC with CAIN = 0 pF(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Recommended CAIN and RAIN values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 44-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 42-pin plastic dual in-line package, shrink 600-mil width . . . . . . . . . . . . . . . . . . . . . . . . . 173 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 32-pin plastic dual in-line package, shrink 400-mil width . . . . . . . . . . . . . . . . . . . . . . . . . 175 ST72324Bxx ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13/193 Description 1 ST72324Bxx Description The ST72324Bxx devices are members of the ST7 microcontroller family designed for midrange applications running from 3.8 to 5.5 V. Different package options offer up to 32 I/O pins. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code. The on-chip peripherals include an A/D converter, two general purpose timers, an SPI interface and an SCI interface. For power economy, the microcontroller can switch dynamically into, Slow, Wait, Active-halt or Halt mode when the application is in idle or stand-by state. Typical applications include consumer, home, office and industrial products. Figure 1. Device block diagram 8-bit CORE ALU RESET VPP CONTROL RAM (384 - 1024 bytes) VSS VDD LVD OSC1 OSC2 OSC WATCHDOG PORT F TIMER A BEEP ADDRESS AND DATA BUS MCC/RTC/BEEP PF7:6, 4, 2:0 (6 bits on J devices) (5 bits on K devices) Program memory (8 - 32 Kbytes) PORT A PORT B PA7:3 (5 bits on J devices) (4 bits on K devices) PB4:0 (5 bits on J devices) (3 bits on K devices) PORT E PE1:0 (2 bits) PORT C SCI TIMER B PORT D PD5:0 (6 bits on J devices) (2 bits on K devices) VAREF VSSA 14/193 SPI 10-bit ADC PC7:0 (8 bits) ST72324Bxx Pin description 44-pin LQFP package pinout PE0/TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP/ICCSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) Figure 2. RDI / PE1 PB0 PB1 PB2 PB3 (HS) PB4 AIN0/PD0 AIN1/PD1 AIN2/PD2 AIN3/PD3 AIN4/PD4 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 ei0 31 ei2 4 30 5 29 ei3 6 28 7 27 8 26 9 25 ei1 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 VSS_1 VDD_1 PA3 (HS) PC7/SS/AIN15 PC6/SCK/ICCCLK PC5/MOSI/AIN14 PC4 / MISO/ICCDATA PC3 (HS)/ICAP1_B PC2 (HS)/ICAP2_B PC1/OCMP1_B/AIN13 PC0/OCMP2_B/AIN12 AIN5/PD5 VAREF VSSA MCO/AIN8/PF0 BEEP/(HS) PF1 (HS) PF2 OCMP1_A/AIN10/PF4 ICAP1_A/(HS) PF6 EXTCLK_A/(HS) PF7 VDD_0 VSS_0 2 Pin description (HS) 20 mA high sink capability eix associated external interrupt vector Figure 3. 42-pin SDIP package pinout (HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN5 / PD5 VAREF VSSA MCO / AIN8 / PF0 BEEP / (HS) PF1 (HS) PF2 AIN10 / OCMP1_A / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 AIN12 / OCMP2_B / PC0 AIN13 / OCMP1_B / PC1 ICAP2_B/ (HS) PC2 ICAP1_B / (HS) PC3 ICCDATA / MISO / PC4 AIN14 / MOSI / PC5 1 ei3 2 3 4 5 6 7 8 9 10 11 ei1 12 13 14 15 16 17 18 19 20 21 ei2 ei0 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 PB3 PB2 PB1 PB0 PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP / ICCSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) VSS_1 VDD_1 PA3 (HS) PC7 / SS / AIN15 PC6 / SCK / ICCCLK (HS) 20 mA high sink capability eix associated external interrupt vector 15/193 Pin description 32-pin LQFP package pinout PD1/AIN1 PD0/AIN0 PB4 (HS) PB3 PB0 PE1/RDI PE0/TDO VDD_2 Figure 4. ST72324Bxx 32 31 30 29 28 27 26 25 24 1 ei3 ei2 23 2 22 3 ei1 21 4 20 5 19 6 18 7 ei0 17 8 9 10 11 12 13 14 15 16 OSC1 OSC2 VSS_2 RESET VPP/ICCSEL PA7 (HS) PA6 (HS) PA4 (HS) AIN13/OCMP1_B/PC1 ICAP2_B/(HS) PC2 ICAP1_B/(HS) PC3 ICCDATA/MISO/PC4 AIN14/MOSI/PC5 ICCCLK/SCK/PC6 AIN15/SS/PC7 (HS) PA3 VAREF VSSA MCO/AIN8/PF0 BEEP/(HS) PF1 OCMP1_A/AIN10/PF4 ICAP1_A/(HS) PF6 EXTCLK_A/(HS) PF7 AIN12/OCMP2_B/PC0 Figure 5. (HS) 20 mA high sink capability eix associated external interrupt vector 32-pin SDIP package pinout (HS) PB4 1 ei3 32 ei2 PB3 AIN0 / PD0 2 31 PB0 AIN1 / PD1 3 30 PE1 / RDI VAREF 4 29 PE0 / TDO VSSA 5 28 VDD_2 MCO / AIN8 / PF0 6 27 OSC1 ei1 BEEP / (HS) PF1 7 26 OSC2 OCMP1_A / AIN10 / PF4 8 25 VSS_2 ICAP1_A / (HS) PF6 9 24 RESET EXTCLK_A / (HS) PF7 10 23 VPP / ICCSEL AIN12 / OCMP2_B / PC0 11 22 PA7 (HS) AIN13 / OCMP1_B / PC1 12 21 PA6 (HS) ICAP2_B / (HS) PC2 13 20 PA4 (HS) ICAP1_B / (HS) PC3 14 19 PA3 (HS) ICCDATA/ MISO / PC4 15 18 PC7 / SS / AIN15 AIN14 / MOSI / PC5 16 17 PC6 / SCK / ICCCLK ei0 (HS) 20mA high sink capability eix associated external interrupt vector See Section 12: Electrical characteristics on page 141 for external pin connection guidelines. Refer to Section 9: I/O ports on page 58 for more details on the software configuration of the I/O ports. The reset configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. 16/193 ST72324Bxx Pin description Legend / Abbreviations for Table 2: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7DD CT = CMOS 0.3VDD/0.7DD with input trigger Output level: HS = 20 mA high sink (on N-buffer only) Port and control configuration: Input: float = floating, wpu = weak pull-up, int = interrupt(a), ana = analog ports Output: OD = open drain(b), PP = push-pull Device pin description Level SDIP32 1 30 1 PB4 (HS) I/O CT HS X 7 2 31 2 PD0/AIN0 I/O CT X X 8 3 32 3 PD1/AIN1 I/O CT X 9 4 PD2/AIN2 I/O CT 10 5 PD3/AIN3 11 6 12 Alternate Function X Port B4 X X X Port D0 ADC Analog Input 0 X X X X Port D1 ADC Analog Input 1 X X X X X Port D2 ADC Analog Input 2 I/O CT X X X X X Port D3 ADC Analog Input 3 PD4/AIN4 I/O CT X X X X X Port D4 ADC Analog Input 4 7 PD5/AIN5 I/O CT X X X X X Port D5 8 4 VAREF(1) S Analog Reference Voltage for ADC S Analog Ground Voltage 1 9 2 5 15 10 3 6 PF0/MCO/AIN8 I/O CT X ei1 16 11 4 7 PF1 (HS)/BEEP I/O CT HS X PF2 (HS) X 17 12 I/O CT HS int X ei3 VSSA(1) 14 Output PP wpu float Input Main function (after reset) OD 13 Output LQFP32 6 Pin Name Input SDIP42 Port LQFP44 Type Pin No. ana Table 2. ADC Analog Input 5 ADC Analog Input 8 X X Port F0 Main clock out (fCPU) ei1 X X Port F1 Beep signal output ei1 X X Port F2 X X Port F4 Timer A Output Compare 1 X ADC Analog Input 10 18 13 5 8 PF4/OCMP1_A/ I/O CT AIN10 X X 19 14 6 9 PF6 (HS)/ICAP1_A I/O CT HS X X X X Port F6 Timer A Input Capture 1 20 15 7 10 PF7 (HS)/ EXTCLK_A I/O CT HS X X X X Port F7 Timer A External Clock Source X a. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. b. In the open drain output column, `T' defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 9: I/O ports and Section 12.9: I/O port pin characteristics for more details. 17/193 Pin description Device pin description (continued) Port PP OD Output ana int wpu Input float Output Pin Name Type Level SDIP32 LQFP32 SDIP42 LQFP44 Pin No. Input Table 2. ST72324Bxx Main function (after reset) Alternate Function 21 VDD_0(1) S Digital Main Supply Voltage 22 (1) S Digital Ground Voltage VSS_0 23 16 8 11 PC0/OCMP2_B I/O CT /AIN12 X X X X X Port C0 Timer B Output Compare 2 ADC Analog Input 12 24 17 9 12 PC1/OCMP1_B I/O CT /AIN13 X X X X X Port C1 Timer B Output Compare 1 ADC Analog Input 13 25 18 10 13 PC2 (HS)/ ICAP2_B I/O CT HS X X X X Port C2 Timer B Input Capture 2 26 19 11 14 PC3 (HS)/ ICAP1_B I/O CT HS X X X X Port C3 Timer B Input Capture 1 27 20 12 15 PC4/MISO/ICC DATA I/O CT X X X X Port C4 SPI Master In / Slave Out Data ICC Data Input 28 21 13 16 PC5/MOSI/ AIN14 I/O CT X X X X Port C5 SPI Master Out / Slave In Data ADC Analog Input 14 29 22 14 17 PC6/SCK/ ICCCLK I/O CT X X X X Port C6 SPI Serial Clock ICC Clock Output 30 23 15 18 PC7/SS/AIN15 I/O CT X X X X Port C7 SPI Slave Select (active low) ADC Analog Input 15 31 24 16 19 PA3 (HS) I/O CT HS X X X Port A3 X X ei 0 32 25 VDD_1(1) S Digital Main Supply Voltage 33 26 (1) S Digital Ground Voltage VSS_1 34 27 17 20 PA4 (HS) I/O CT HS X X X X Port A4 35 28 PA5 (HS) I/O CT HS X X X X Port A5 36 29 18 21 PA6 (HS) I/O CT HS X T Port A6 (2) 37 30 19 22 PA7 (HS) I/O CT HS X T Port A7 (2) 38 31 20 23 VPP /ICCSEL 39 32 21 24 RESET 40 33 22 25 VSS_2 18/193 (1) I I/O CT S Must be tied low. In the flash programming mode, this pin acts as the programming voltage input VPP. See Section 12.10.2 for more details. High voltage must not be applied to ROM devices. Top priority non maskable interrupt. Digital Ground Voltage ST72324Bxx Device pin description (continued) Port PP OD Output ana int wpu Input float Output Pin Name Type Level SDIP32 LQFP32 SDIP42 LQFP44 Pin No. Input Table 2. Pin description Main function (after reset) Alternate Function 41 34 23 26 OSC2(3) O Resonator oscillator inverter output 42 35 24 27 OSC1(3) I External clock input or Resonator oscillator inverter input 43 36 25 28 VDD_2(1) S Digital Main Supply Voltage 44 37 26 29 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out 1 38 27 30 PE1/RDI I/O CT X X X X Port E1 SCI Receive Data In 2 39 28 31 PB0 I/O CT X ei2 X X Port B0 Caution: Negative current injection not allowed on this pin(4) 3 40 PB1 I/O CT X ei2 X X Port B1 4 41 PB2 I/O CT X ei2 X X Port B2 5 42 29 32 PB3 I/O CT X X X Port B3 ei 2 1. It is mandatory to connect all available VDD and VREF pins to the supply voltage and all VSS and VSSA pins to ground. 2. On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1: Description and Section 12.6: Clock and timing characteristics for more details. 4. For details refer to Section 12.9.1 on page 158 19/193 Register and memory map 3 ST72324Bxx Register and memory map As shown in Figure 6, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 1024 bytes of RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors. Caution: Never access memory locations marked as `Reserved'. Accessing a reserved area can have unpredictable effects on the device. Figure 6. Memory map 0000h HW registers (see Table 3) 007Fh 0080h 0080h 00FFh 0100h RAM (1024, 512 or 384 bytes) 047Fh 0480h Reserved Short addressing RAM (zero page) 256 bytes stack 01FFh 0200h 16-bit addressing RAM 027Fh or 047Fh 7FFFh 8000h Program memory (32, 16 or 8 Kbytes) C000h FFDFh FFE0h Interrupt and reset vectors (see Table 25) FFFFh Table 3. 8000h 32 Kbytes 16 Kbytes E000h 8 Kbytes FFFFh Hardware register map Address Block 0000h 0001h 0002h Port A(1) PADR PADDR PAOR Port A data register Port A data direction register Port A option register 00h(2) 00h 00h R/W R/W R/W 0003h 0004h 0005h Port B(1) PBDR PBDDR PBOR Port B data register Port B data direction register Port B option register 00h(2) 00h 00h R/W R/W R/W Port C PCDR PCDDR PCOR Port C data register Port C data direction register Port C option register 00h(2) 00h 00h R/W R/W R/W 0006h 0007h 0008h Register label Register name Reset status Remarks 0009h 000Ah 000Bh Port D(1) PDADR PDDDR PDOR Port D data register Port D data direction register Port D option register 00h(2) 00h 00h R/W R/W R/W 000Ch 000Dh 000Eh Port E(1) PEDR PEDDR PEOR Port E data register Port E data direction register Port E option register 00h(2) 00h 00h R/W R/W(1) R/W(1) 20/193 ST72324Bxx Table 3. Address 000Fh 0010h 0011h Register and memory map Hardware register map (continued) Block Port F(1) Register label PFDR PFDDR PFOR 0012h to 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h SPI ITC 0029h Flash 002Ah Watchdog 002Bh SI 002Ch 002Dh MCC (2) Remarks 00h 00h 00h R/W R/W R/W SPIDR SPICR SPICSR SPI data I/O register SPI control register SPI control/status register xxh 0xh 00h R/W R/W R/W ISPR0 ISPR1 ISPR2 ISPR3 Interrupt software priority register 0 Interrupt software priority register 1 Interrupt software priority register 2 Interrupt software priority register 3 FFh FFh FFh FFh R/W R/W R/W R/W EICR External interrupt control register 00h R/W FCSR Flash control/status register 00h R/W WDGCR Watchdog control register 7Fh R/W SICSR System integrity control/status register 000x 000xb R/W MCCSR MCCBCR Main clock control/status register Main clock controller: beep control register 00h 00h R/W R/W 002Eh to 0030h 0040h Port F data register Port F data direction register Port F option register Reset status Reserved area (15 bytes) 0028h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Register name Reserved area (3 bytes) Timer A TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer A control register 2 Timer A control register 1 Timer A control/status register Timer A input capture 1 high register Timer A input capture 1 low register Timer A output compare 1 high register Timer A output compare 1 low register Timer A counter high register Timer A counter low register Timer A alternate counter high register Timer A alternate counter low register Timer A input capture 2 high register Timer A input capture 2 low register Timer A output compare 2 high register Timer A output compare 2 low register 00h 00h xxxx x0xxb xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read only Read only R/W R/W Read only Read only Read only Read only Read only Read only R/W R/W Reserved area (1 byte) 21/193 Register and memory map Table 3. Address 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h Hardware register map (continued) Block Timer B SCI Register label 0073h 007Fh Register name Reset status Remarks TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer B control register 2 Timer B control register 1 Timer B control/status register Timer B input capture 1 high register Timer B input capture 1 low register Timer B output compare 1 high register Timer B output compare 1 low register Timer B counter high register Timer B counter low register Timer B alternate counter high register Timer B alternate counter low register Timer B input capture 2 high register Timer B input capture 2 low register Timer B output compare 2 high register Timer B output compare 2 low register 00h 00h xxxx x0xxb xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read only Read only R/W R/W Read only Read only Read only Read only Read only Read only R/W R/W SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCI status register SCI data register SCI baud rate register SCI control register 1 SCI control register 2 SCI extended receive prescaler register Reserved area SCI extended transmit prescaler register C0h xxh 00h x000 0000b 00h 00h --00h Read only R/W R/W R/W R/W R/W 00h 00h 00h R/W Read only Read only SCIETPR 0058h to 006Fh 0070h 0071h 0072h ST72324Bxx R/W Reserved area (24 bytes) ADC ADCCSR ADCDRH ADCDRL Control/status register Data high register Data low register Reserved area (13 bytes) 1. The bits associated with unavailable pins must always keep their reset value. 2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. Legend: x = undefined, R/W = read/write 22/193 ST72324Bxx Flash program memory 4 Flash program memory 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming). The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main features 4.3 3 Flash programming modes: - Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. - ICP (in-circuit programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. - IAP (in-application programming). In this mode, all sectors, except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (in-circuit testing) for downloading and executing user application test patterns in RAM Readout protection Register Access Security System (RASS) to prevent accidental programming or erasing Structure The Flash memory is organized in sectors and can be used for both code and data storage. Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (seeTable 4). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 7). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh). Table 4. Sectors available in Flash devices Flash size Available sectors 4 Kbytes Sector 0 8 Kbytes Sectors 0, 1 >8 Kbytes Sectors 0, 1, 2 23/193 Flash program memory 4.3.1 ST72324Bxx Readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased. Readout protection selection depends on the device type: In Flash devices it is enabled and removed through the FMP_R bit in the option byte. In ROM devices it is enabled by mask option specified in the option list. Figure 7. Memory map and sector address 8K 16K 32K Flash memory size 7FFFh Sector 2 BFFFh DFFFh EFFFh FFFFh 24/193 8 Kbytes 24 Kbytes 4 Kbytes Sector 1 4 Kbytes Sector 0 ST72324Bxx 4.4 Flash program memory ICC interface ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 8). These pins are: - RESET: device reset - VSS: device power supply ground - ICCCLK: ICC output serial clock pin - ICCDATA: ICC input/output serial data pin - ICCSEL/VPP: programming voltage - OSC1 (or OSCIN): main clock input for external source (optional) - VDD: application board power supply (optional, see Figure 8, Note 3) Figure 8. Typical ICC interface Programming tool ICC connector Mandatory for 8/16 Kbyte Flash devices (see note 4) ICC cable (See note 3) 9 7 5 3 1 10 8 6 4 2 Application board ICC connector HE10 connector type Application reset source See note 2 10 k Application power supply ICCDATA RESET ICCCLK ST7 ICCSEL/VPP VSS OSC1 OSC2 VDD See note 1 Application I/O 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (PUSH-pull output or pull-up resistor <1 k). A schottky diode can be used to isolate the application reset circuit in this case. When using a classical RC network with R>1k or a reset management IC with open drain output and pull-up resistor >1 k, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual. 4. Pin 9 has to be connected to the OSC1 (OSCIN) pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multioscillator capability need to have OSC2 grounded in this case. Caution: External clock ICC entry mode is mandatory in ST72F324B 8/16 Kbyte Flash devices. In this case pin 9 must be connected to the OSC1 (OSCIN) pin of the ST7 and OSC2 must be grounded. 32 Kbyte Flash devices may use external clock or application clock ICC entry mode. 25/193 Flash program memory 4.5 ST72324Bxx ICP (in-circuit programming) To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 8). For more details on the pin locations, refer to the device pinout description. 4.6 IAP (in-application programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (such as user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored). For example, it is possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.7 Related documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.7.1 Flash Control/Status Register (FCSR) This register is reserved for use by programming tool software. It controls the Flash programming and erasing operations. Reset value:0000 0000 (00h) FCSR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 5. Flash control/status register address and reset value Address (Hex) 0029h 26/193 Register label 7 6 5 4 3 2 1 0 FCSR reset value 0 0 0 0 0 0 0 0 ST72324Bxx Central processing unit (CPU) 5 Central processing unit (CPU) 5.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation. 5.2 5.3 Main features Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power Halt and Wait modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts CPU registers The six CPU registers shown in Figure 9 are not present in the memory mapping and are accessed by specific instructions. Figure 9. CPU registers 7 0 Accumulator Reset value = XXh 7 0 X index register Reset value = XXh 7 0 Y index register Reset value = XXh 15 PCH 8 7 PCL 0 Program counter Reset value = reset vector @ FFFEh-FFFFh 7 0 1 1 I1 H I0 N Z C Reset value = 1 1 1 X 1 X X X 15 8 7 Condition code register 0 Stack pointer Reset value = stack higher address X = undefined value 27/193 Central processing unit (CPU) 5.3.1 ST72324Bxx Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 5.3.2 Index registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. 5.3.3 Program counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). 5.3.4 Condition Code register (CC) The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. CC Reset value: 111x1xxx 7 6 5 4 3 2 1 0 1 1 I1 H I0 N Z C R/W R/W R/W R/W R/W R/W R/W R/W Table 6. Arithmetic management bits BIt Name Function Half carry 4 2 28/193 H N This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1. This bit is accessed by the JRMI and JRPL instructions. ST72324Bxx Central processing unit (CPU) Table 6. Arithmetic management bits (continued) BIt Name 1 0 Function Z Zero (Arithmetic Management bit) This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. C Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the `bit test and branch', shift and rotate instructions. Table 7. Software interrupt bits BIt Name Function 5 I1 Software Interrupt Priority 1 The combination of the I1 and I0 bits determines the current interrupt software priority (see Table 8). 3 I0 Software Interrupt Priority 0 The combination of the I1 and I0 bits determines the current interrupt software priority (see Table 8). Table 8. Interrupt software priority selection Interrupt software priority Level 0 (main) Level I1 I0 Low 1 0 0 1 0 0 1 1 Level 1 Level 2 Level 3 (= interrupt disable) High These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See Section 7: Interrupts on page 41 for more details. 29/193 Central processing unit (CPU) 5.3.5 ST72324Bxx Stack Pointer register (SP) SP Reset value: 01 FFh 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 10). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by an LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 10. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. Figure 10. Stack manipulation example Call subroutine Push Y Interrupt event Pop Y RET or RSP IRET @ 0100h SP SP CC A CC A X X X PCH PCH PCL PCL PCL PCH PCH PCH PCH PCH PCL PCL PCL PCL PCL Stack Higher Address = 01FFh Stack Lower Address = 0100h 30/193 SP PCH SP @ 01FFh Y CC A SP SP ST72324Bxx Supply, reset and clock management 6 Supply, reset and clock management 6.1 Introduction The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 12. For more details, refer to dedicated parametric section. Main features 6.2 Optional Phase Locked Loop (PLL) for multiplying the frequency by 2 (not to be used with internal RC oscillator in order to respect the max. operating frequency) Multi-Oscillator clock management (MO) - 5 crystal/ceramic resonator oscillators - 1 Internal RC oscillator Reset Sequence Manager (RSM) System Integrity management (SI) - Main supply low voltage detection (LVD) - Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main supply PLL (phase locked loop) If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2. Caution: The PLL is not recommended for applications where timing accuracy is required. Furthermore, it must not be used with the internal RC oscillator. Figure 11. PLL block diagram fOSC PLL x 2 0 /2 1 fOSC2 PLL option bit 31/193 Supply, reset and clock management ST72324Bxx Figure 12. Clock, reset and supply block diagram Multioscillator (MO) OSC2 OSC1 fOSC fOSC2 PLL (option) Main Clock fCPU Controller with Real-time Clock (MCC/RTC) System integrity management Reset sequence manager (RSM) RESET AVD interrupt request Watchdog timer (WDG) SICSR 0 AVD AVD LVD F RF IE 0 0 0 WDG RF Low voltage detector (LVD) VSS VDD Auxiliary voltage detector (AVD) 6.3 Multi-oscillator (MO) The main clock of the ST7 can be generated by three different source types coming from the multi-oscillator block: an external source 4 crystal or ceramic resonator oscillators an internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 9. Refer to the electrical characteristics section for more details. Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (> 16 MHz.), putting the ST7 in an unsafe/undefined state. The product behavior must therefore be considered undefined when the OSC pins are left unconnected. 6.3.1 External clock source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. 32/193 ST72324Bxx 6.3.2 Supply, reset and clock management Crystal/ceramic oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of four oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 14.1 on page 179 for more details on the frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. Internal RC oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing. In this mode, the two oscillator pins have to be tied to ground. In order not to exceed the maximum operating frequency, the internal RC oscillator must not be used with the PLL. Table 9. ST7 clock sources Crystal/ceramic resonators External clock Hardware configuration Internal RC oscillator 6.3.3 OSC1 ST7 OSC2 External source OSC1 CL1 ST7 OSC2 Load capacitors CL2 ST7 OSC1 OSC2 33/193 Supply, reset and clock management 6.4 ST72324Bxx Reset sequence manager (RSM) The reset sequence manager includes three reset sources as shown in Figure 14: External reset source pulse Internal LVD reset Internal Watchdog reset These sources act on the RESET pin and it is always kept low during the delay phase. The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic reset sequence consists of three phases as shown in Figure 13: Caution: Active Phase depending on the reset source 256 or 4096 CPU clock cycle delay (selected by option byte) Reset vector fetch When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. The reset vector fetch phase duration is two clock cycles. Figure 13. Reset sequence phases RESET ACTIVE PHASE 6.4.1 INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See the Electrical characteristics section for more details. A reset signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 15). This detection is asynchronous and therefore the MCU can enter reset state even in Halt mode. 34/193 ST72324Bxx Supply, reset and clock management Figure 14. Reset block diagram VDD RON RESET Internal reset Filter Pulse generator Watchdog reset LVD reset The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. External power-on reset If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. Internal LVD reset Two different reset sequences caused by the internal LVD circuitry can be distinguished: Power-On reset Voltage Drop reset The device RESET pin acts as an output that is pulled low when VDD < VIT+ (rising edge) or VDD < VIT- (falling edge) as shown in Figure 15. The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets. Internal Watchdog reset The reset sequence generated by a internal Watchdog counter overflow is shown in Figure 15. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. 35/193 Supply, reset and clock management ST72324Bxx Figure 15. RESET sequences VDD VIT+(LVD) VIT-(LVD) LVD reset External reset Run Run Active phase Active phase Watchdog reset Run Active phase Run tw(RSTL)out th(RSTL)in External RESET source RESET pin Watchdog reset Watchdog underflow Internal reset (256 or 4096 TCPU) Vector fetch 6.5 System integrity management (SI) The system integrity management block contains the LVD and auxiliary voltage detector (AVD) functions. It is managed by the SICSR register. 6.5.1 LVD (low voltage detector) The LVD function generates a static reset when the VDD supply voltage is below a VITreference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD reset circuitry generates a reset when VDD is below: - VIT+ when VDD is rising - VIT- when VDD is falling The LVD function is illustrated in Figure 15. The voltage threshold can be configured by option byte to be low, medium or high. 36/193 ST72324Bxx Supply, reset and clock management Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: - under full software control - in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During an LVD reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Note: 1 The LVD allows the device to be used without any external reset circuitry. 2 If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8 V, device operation is not guaranteed. 3 The LVD is an optional function which can be selected by option byte. 4 It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from reset, to ensure the application functions properly. Figure 16. Low voltage detector vs reset VDD Vhys VIT+ VIT- RESET 6.5.2 AVD (auxiliary voltage detector) The AVD is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply. The VIT- reference value for falling voltage is lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real-time status bit (AVDF) in the SICSR register. This bit is read only. Caution: The AVD function is active only if the LVD is enabled through the option byte (see Section 14.1 on page 179). Monitoring the VDD main supply The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see Section 14.1 on page 179). If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 17. 37/193 Supply, reset and clock management ST72324Bxx The interrupt on the rising edge is used to inform the application that the VDD warning state is over. If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached. If trv is greater than 256 or 4096 cycles then: If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached. If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur. Figure 17. Using the AVD to monitor VDD VDD Early warning interrupt (power has dropped, MCU not not yet in reset) Vhyst VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD) AVDF bit trv Voltage rise time 0 1 Reset value 1 0 AVD Interrupt Request if AVDIE bit = 1 Interrupt process Interrupt process LVD RESET 6.5.3 Low power modes Table 10. Effect of low power modes on SI Mode 6.5.4 Description Wait No effect on SI. AVD interrupt causes the device to exit from Wait mode. Halt The CRSR register is frozen. Interrupts The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask in the CC register is reset (RIM instruction). M Table 11. 38/193 AVD interrupt control/wakeup capability Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No ST72324Bxx Supply, reset and clock management 6.6 SI registers 6.6.1 System integrity (SI) control/status register (SICSR) SICSR Reset value: 000x 000x (00h) 7 6 5 4 Res AVDIE AVDF LVDRF Reserved WDGRF - R/W RO R/W - R/W Table 12. Bit Name 7 - 3 2 1 0 SICSR register description Function Reserved, must be kept cleared AVDIE Voltage detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine 0: AVD interrupt disabled 1: AVD interrupt enabled 5 AVDF Voltage detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. Refer to Figure 17 and to Section 6.5.2: AVD (auxiliary voltage detector) for additional details. 0: VDD over VIT+(AVD) threshold 1: VDD under VIT-(AVD) threshold 4 LVD Reset flag This bit indicates that the last reset was generated by the LVD block. It is set by LVDRF hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by option byte, the LVDRF bit value is undefined. 6 3:1 0 - Reserved, must be kept cleared Watchdog Reset flag This bit indicates that the last reset was generated by the Watchdog peripheral. It is WDGRF set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF information, the flag description is given in Table 13. Table 13. Reset source flags Reset sources LVDRF WDGRF External RESET pin 0 0 Watchdog 0 1 LVD 1 X 39/193 Supply, reset and clock management ST72324Bxx Application notes The LVDRF flag is not cleared when another reset type occurs (external or watchdog); the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset cannot. Caution: 40/193 When the LVD is not activated with the associated option byte, the WDGRF flag can not be used in the application. ST72324Bxx Interrupts 7 Interrupts 7.1 Introduction The ST7 enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: - up to 4 software programmable nesting levels - up to 16 interrupt vectors fixed by hardware - 2 non-maskable events: reset, TRAP This interrupt management is based on: Bit 5 and bit 3 of the CPU CC register (I1:0) Interrupt software priority registers (ISPRx) Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller. 7.2 Masking and processing flow The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 14). The processing flow is shown in Figure 18. When an interrupt request has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table 25: Interrupt mapping for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. 41/193 Interrupts ST72324Bxx Table 14. Interrupt software priority levels Interrupt software priority Level I1 I0 Low 1 0 Level 1 0 1 Level 2 0 0 1 1 Level 0 (main) Level 3 (= interrupt disable) High Figure 18. Interrupt processing flowchart Pending Reset Y TRAP Interrupt Fetch next Instruction Y The interrupt stays pending "IRET" N RESTORE PC, X, A, CC from stack 7.2.1 Execute instruction N I1:0 Interrupt has a higher software priority than current one Interrupt has the same or a lower software priority than current one N Y Stack PC, X, A, CC load I1:0 from interrupt SW reg. load PC from interrupt vector Servicing pending interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 19 describes this decision process. Figure 19. Priority decision process flowchart PENDING INTERRUPTS Same SOFTWARE PRIORITY Different HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED 42/193 ST72324Bxx Interrupts When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: 7.2.2 1 The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. 2 Reset and TRAP can be considered as having the highest software priority in the decision process. Different interrupt vector sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (reset, TRAP) and the maskable type (external or from internal peripherals). 7.2.3 Non-maskable sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 18). After stacking the PC, X, A and CC registers (except for reset), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit Halt mode. TRAP (non-maskable software interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 18. Reset The reset source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the reset chapter for more details. 7.2.4 Maskable sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. External interrupts External interrupts allow the processor to Exit from Halt low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed. Peripheral interrupts Usually the peripheral interrupts cause the MCU to Exit from Halt mode except those mentioned in Table 25: Interrupt mapping. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the 43/193 Interrupts ST72324Bxx peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be serviced) is therefore lost if the clear sequence is executed. 7.3 Interrupts and low power modes All interrupts allow the processor to exit the Wait low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the Halt modes (see column Exit from Halt in Table 25: Interrupt mapping). When several pending interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt with Exit from Halt mode capability and it is selected through the same decision process shown in Figure 19. Note: If an interrupt, that is not able to exit from Halt mode, is pending with the highest priority when exiting Halt mode, this interrupt is serviced after the first one serviced. 7.4 Concurrent and nested management Figure 20 and Figure 21 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 21. The interrupt hardware priority is given in order from the lowest to the highest as follows: MAIN, IT4, IT3, IT2, IT1, IT0. Software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure. Hardware priority TRAP 3 IT0 IT1 IT1 IT2 IT3 RIM IT4 Main 11/10 44/193 I1 Main 10 I0 1 1 3 1 1 3 1 1 3 1 1 3 1 1 3 1 1 3/0 Used stack = 10 bytes Software priority level IT0 TRAP IT3 IT4 IT1 IT2 Figure 20. Concurrent interrupt management ST72324Bxx Interrupts I1 Hardware priority TRAP IT0 IT1 IT1 IT2 IT2 IT3 RIM IT4 IT4 Main 11 / 10 Main I0 3 1 1 3 1 1 2 0 0 1 0 1 3 1 1 3 1 1 Used stack = 20 bytes Software priority level IT0 TRAP IT3 IT4 IT1 IT2 Figure 21. Nested interrupt management 3/0 10 7.5 Interrupt registers 7.5.1 CPU CC register interrupt bits CPU CC Reset value: 111x 1010(xAh) 7 6 5 4 3 2 1 0 1 1 I1 H I0 N Z C R/W R/W R/W R/W R/W R/W R/W R/W Table 15. CPU CC register interrupt bits description Bit Name Function 5 I1 Software Interrupt Priority 1 3 I0 Software Interrupt Priority 0 Table 16. Interrupt software priority levels Interrupt software priority Level 0 (main) Level I1 I0 Low 1 0 0 1 0 0 1 1 Level 1 Level 2 Level 3 (= interrupt disable) (1) High 1. TRAP and RESET events can interrupt a level 3 program. These two bits indicate the current interrupt software priority (see Table 16) and are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see Table 18: Dedicated interrupt instruction set). 45/193 Interrupts 7.5.2 ST72324Bxx Interrupt software priority registers (ISPRx) ISPRx Reset value: 1111 1111 (FFh) 7 6 5 4 3 2 1 0 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0 ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4 ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 I1_13 I0_13 I1_12 I0_12 RO RO RO RO R/W R/W R/W R/W ISPR3 These four registers contain the interrupt software priority of each interrupt vector. Each interrupt vector (except reset and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondence is shown in the following Table 17. Table 17. ISPRx interrupt vector correspondence Vector address ISPRx bits FFFBh-FFFAh I1_0 and I0_0 bits FFF9h-FFF8h I1_1 and I0_1 bits ... ... FFE1h-FFE0h I1_13 and I0_13 bits Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is kept (for example, previous value = CFh, write = 64h, result = 44h). The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x). Table 18. Instruction 46/193 Dedicated interrupt instruction set(1) New description Function/example HALT Entering Halt mode IRET Interrupt routine return POP CC, A, X, PC JRM Jump if I1:0=11 (level 3) I1:0=11 ? JRNM Jump if I1:0<>11 I1:0<>11 ? I1 H 1 I1 I0 N Z C N Z C 0 H I0 ST72324Bxx Interrupts Table 18. Instruction Dedicated interrupt instruction set(1) (continued) New description Function/example Mem => CC I1 H I0 N Z C I1 H I0 N Z C POP CC POP CC from the Stack RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software TRAP 1 1 WFI Wait for interrupt 1 0 Software NMI 1. During the execution of an interrupt routine, the HALT, POP CC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. 47/193 Interrupts ST72324Bxx 7.6 External interrupts 7.6.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 22). This control allows up to four fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: Falling edge Rising edge Falling and rising edge Falling edge and low level Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the EICR. Figure 22. External interrupt control bits Port A3 interrupt PAOR.3 PADDR.3 EICR IS20 IS21 ei0 interrupt source Sensitivity control PA3 IPA BIT Port F [2:0] interrupts PFOR.2 PFDDR.2 PF2 Port B [3:0] interrupts PBOR.3 PBDDR.3 EICR IS20 IS21 Sensitivity control IS10 IS11 IPB BIT Port B4 interrupt PBOR.4 PBDDR.4 PB4 48/193 ei1 interrupt source EICR Sensitivity control PB3 PF2 PF1 PF0 PB3 PB2 PB1 PB0 ei2 interrupt source EICR IS10 IS11 Sensitivity control ei3 interrupt source ST72324Bxx 7.6.2 Interrupts External interrupt control register (EICR) EICR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 IS11 IS10 IPB IS21 IS20 IPA Reserved R/W R/W R/W R/W R/W R/W - Table 19. Bit 1 0 EICR register description Name Function ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: 7:6 IS1[1:0] - ei2 for port B [3:0] (see Table 20) - ei3 for port B4 (see Table 21) Bits 7 and 6 can only be written when I1 and I0 of the CC register are both set to 1 (level 3). 5 IPB Interrupt Polarity (for port B) This bit is used to invert the sensitivity of port B [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: 4:3 IS2[1:0] - ei0 for port A[3:0] (see Table 22) - ei1 for port F[2:0] (see Table 23) Bits 4 and 3 can only be written when I1 and I0 of the CC register are both set to 1 (level 3). 2 IPA 1:0 - Table 20. Interrupt Polarity (for port A) This bit is used to invert the sensitivity of port A [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion. 1: Sensitivity inversion. Reserved, must always be kept cleared Interrupt sensitivity - ei2 External interrupt sensitivity IS11 IS10 IPB bit = 0 IPB bit = 1 0 0 Falling edge and low level Rising edge and high level 0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only 1 1 Rising and falling edge 49/193 Interrupts ST72324Bxx Table 21. Interrupt sensitivity - ei3 IS11 IS10 External interrupt sensitivity 0 0 Falling edge and low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge Table 22. Interrupt sensitivity - ei0 External interrupt sensitivity IS21 IS20 IPA bit = 0 IPA bit = 1 0 0 Falling edge and low level Rising edge and high level 0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only 1 1 Table 23. Rising and falling edge Interrupt sensitivity - ei1 IS21 IS20 External interrupt sensitivity 0 0 Falling edge and low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge Table 24. Nested interrupts register map and reset values Address (Hex.) Register label 7 6 5 4 ei1 0024h ISPR0 reset value I1_3 1 ei0 I0_3 1 I1_2 1 3 ISPR1 reset value I1_7 1 50/193 0 I0_2 1 I1_1 1 I0_1 1 1 1 ei3 I0_7 1 I1_6 1 AVD 0026h 1 MCC + SI SPI 0025h 2 I0_6 1 SCI I1_5 1 ei2 I0_5 1 Timer B I1_4 1 I0_4 1 Timer A ISPR2 reset value I1_11 1 I0_11 1 I1_10 1 I0_10 1 I1_9 1 I0_9 1 I1_8 1 I0_8 1 0027h ISPR3 reset value 1 1 1 1 I1_13 1 I0_13 1 I1_12 1 I0_12 1 0028h EICR reset value IS11 0 IS10 0 IPB 0 IS21 0 IS20 0 IPA 0 0 0 ST72324Bxx Table 25. No. Interrupts Interrupt mapping Source block Reset Register Priority Exit from label order Halt/Active-halt Description Reset Address vector yes FFFEh-FFFFh no FFFCh-FFFDh N/A TRAP Software interrupt 0 Not used Main clock controller time base interrupt 1 MCC/RTC 2 ei0 External interrupt port A3..0 3 ei1 External interrupt port F2..0 FFFAh-FFFBh MCCSR Higher priority yes FFF8h-FFF9h yes FFF6h-FFF7h yes FFF4h-FFF5h N/A 4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h 5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h 6 Not used 7 SPI 8 Timer A 9 Timer B 10 11 SPI peripheral interrupts FFEEh-FFEFh SPICSR yes FFECh-FFEDh Timer A peripheral interrupts TASR no FFEAh-FFEBh Timer B peripheral interrupts TBSR no FFE8h-FFE9h SCI SCI peripheral interrupts SCISR no FFE6h-FFE7h AVD Auxiliary voltage detector interrupt SICSR no FFE4h-FFE5h Lower priority 51/193 Power saving modes 8 Power saving modes 8.1 Introduction ST72324Bxx To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 23): Slow, Wait (Slow Wait), Active-halt and Halt. After a reset the normal operating mode is selected by default (Run mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (fOSC2). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 23. Power saving mode transitions High Run Slow Wait Slow Wait Active Halt Halt Low Power consumption 8.2 Slow mode This mode has two targets: To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage. Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (fCPU). Note: 52/193 Slow-Wait mode is activated when entering the Wait mode while the device is already in Slow mode. ST72324Bxx Power saving modes Figure 24. Slow mode clock transitions fOSC2/2 fOSC2/4 fOSC2 fCPU MCCSR fOSC2 CP1:0 00 01 SMS Normal Run mode request New Slow frequency request 8.3 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced to `10', to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or reset service routine. The MCU will remain in Wait mode until a reset or an interrupt occurs, causing it to wake up. Refer to Figure 25. Figure 25. Wait mode flowchart WFI instruction Oscillator Peripherals CPU I[1:0] bits on on off 10 N Reset Y N Interrupt Y Oscillator Peripherals CPU I[1:0] bits on off on 10 256 or 4096 CPU clock cycle delay Oscillator Peripherals CPU I[1:0] bits on on on XX(1) Fetch reset vector or service interrupt 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. 53/193 Power saving modes 8.4 ST72324Bxx Active-halt and Halt modes Active-halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in Activehalt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in the MCCSR register). Table 26. MCC/RTC low power mode selection MCCSR OIE bit 8.4.1 Power saving mode entered when HALT instruction is executed 0 Halt mode 1 Active-halt mode Active-halt mode Active-halt mode is the lowest power consumption mode of the MCU with a real-time clock available. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see Section 10.2: Main clock controller with realtime clock and beeper (MCC/RTC) on page 69 for more details on the MCCSR register). The MCU can exit Active-halt mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 25: Interrupt mapping) or a reset. When exiting Active-halt mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 27). When entering Active-halt mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Active-halt mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wakeup time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in Active-halt mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering Active-halt mode while the Watchdog is active does not generate a reset. This means that the device cannot spend more than a defined delay in this power saving mode. Caution: When exiting Active-halt mode following an interrupt, OIE bit of MCCSR register must not be cleared before tDELAY after the interrupt occurs (tDELAY = 256 or 4096 tCPU delay depending on option byte). Otherwise, the ST7 enters Halt mode for the remaining tDELAY period. Figure 26. Active-halt timing overview Run Active Halt Halt instruction [MCCSR.OIE = 1] 256 or 4096 CPU cycle delay(1) Reset or interrupt Run Fetch vector 1. This delay occurs only if the MCU exits Active-halt mode by means of a reset. 54/193 ST72324Bxx Power saving modes Figure 27. Active-halt mode flowchart Halt instruction (MCCSR.OIE = 1) Oscillator Peripherals(1) CPU I[1:0] bits N N Interrupt(2) Y on off off 10 Reset Y Oscillator Peripherals CPU I[1:0] bits on off on XX(3) 256 or 4096 CPU clock cycle delay Oscillator Peripherals CPU I[1:0] bits on on on XX(3) Fetch reset vector or service interrupt 1. Peripheral clocked with an external clock source can still be active. 2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from Active-halt mode (such as external interrupt). Refer to Table 25: Interrupt mapping on page 51 for more details. 3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped. 8.4.2 Halt mode The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 10.2: Main clock controller with real-time clock and beeper (MCC/RTC) on page 69 for more details on the MCCSR register). The MCU can exit Halt mode on reception of either a specific interrupt (see Table 25: Interrupt mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 29). When entering Halt mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Halt mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with Halt mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog reset (see Section 14.1 on page 179) for more details. 55/193 Power saving modes ST72324Bxx Figure 28. Halt timing overview Run 256 or 4096 CPU cycle delay Halt Run Reset or interrupt Halt instruction [MCCSR.OIE = 0] Fetch vector Figure 29. Halt mode flowchart Halt instruction (MCCSR.OIE = 0) Enable WDGHALT(1) Watchdog Disable 0 1 Watchdog reset Oscillator Peripherals(2) CPU I[1:0] bits off off off 10 N Reset N Y Interrupt(3) Y Oscillator Peripherals CPU I[1:0] bits on off on XX(4) 256 or 4096 CPU clock cycle delay Oscillator Peripherals CPU I[1:0] bits on on on XX(4) Fetch reset vector or service interrupt 1. WDGHALT is an option bit. See Section 14.1 on page 179 for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 25: Interrupt mapping for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. 56/193 ST72324Bxx Power saving modes Halt mode recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. For the same reason, reinitialize the sensitivity level of each external interrupt as a precautionary measure. The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt). 57/193 I/O ports ST72324Bxx 9 I/O ports 9.1 Introduction The I/O ports offer different functional modes: transfer of data through digital inputs and outputs, and for specific pins: external interrupt generation, alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 Functional description Each port has two main registers: Data Register (DR) Data Direction Register (DDR) and one optional register: Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to Section 9.3: I/O port implementation on page 62). The generic I/O block diagram is shown in Figure 30. 9.2.1 Input modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Note: 58/193 1 Writing the DR register modifies the latch value but does not affect the pin status. 2 When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3 Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this might corrupt the DR content for I/Os configured as input. ST72324Bxx I/O ports External interrupt function When an I/O is configured as `Input with Interrupt', an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed. The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified. 9.2.2 Output modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. Table 27. 9.2.3 DR register value and output pin status DR Push-pull Open-drain 0 VSS VSS 1 VDD Floating Alternate functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. 59/193 I/O ports ST72324Bxx Figure 30. I/O port general block diagram Alternate output Register access 1 VDD 0 Alternate enable P-buffer (see table 24 below) Pull-up (see table 24 below) DR VDD DDR Pull-up condition Data bus OR Pad If implemented OR SEL N-buffer Diodes (see table 24 below) DDR SEL DR SEL Analog input CMOS Schmitt trigger 1 0 Alternate input External interrupt source (eix) Table 28. I/O port mode options Diodes Configuration mode Pull-up Floating with/without Interrupt Off(3) Pull-up with/without Interrupt On(4) Input P-buffer to VDD(1) to VSS(2) Off On Push-pull On On Off Output Open drain (logic level) True open drain Off NI NI NI(5) 1. The diode to VDD is not implemented in the true open drain pads. 2. A local protection between the pad and VSS is implemented to protect the device against positive stress. 3. Off = implemented not activated. 4. On = implemented and activated. 5. NI = not implemented 60/193 ST72324Bxx I/O ports Table 29. I/O port configurations Hardware configuration Not implemented in true open drain I/O ports DR register access VDD RPU Pull-up condition DR register W Data bus Pad R Alternate input External interrupt source (eix) Input(1) Interrupt condition Analog input Open-drain output(2) Not implemented in true open drain I/O ports RPU DR register Pad Alternate enable Not implemented in true open drain I/O ports PUSH-pull output(2) DR register access VDD R/W Data bus Alternate output DR register access VDD RPU DR R/W register Pad Alternate enable Data bus Alternate output 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content. Caution: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. 61/193 I/O ports ST72324Bxx Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. Warning: 9.3 The analog input voltage level must be within the limits stated in the absolute maximum ratings. I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 31. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 31. Interrupt I/O port state transitions 01 00 Input Input floating floating/pull-up (reset state) interrupt 10 11 Output open-drain Output push-pull XX 9.4 Low power modes Table 30. Effect of low power modes on I/O ports Mode 9.5 = DDR, OR Description Wait No effect on I/O ports. External interrupts cause the device to exit from Wait mode. Halt No effect on I/O ports. External interrupts cause the device to exit from Halt mode. Interrupts The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction). 62/193 ST72324Bxx I/O ports Table 31. 9.5.1 I/O port interrupt control/wakeup capability Interrupt event Event flag Enable Control bit Exit from Wait Exit from Halt External interrupt on selected external event - DDRx, ORx Yes Yes I/O port implementation The I/O port register configurations are summarized Table 32. Table 32. Port configuration Input (DDR = 0) Port OR = 0 PA7:6 Port A Output (DDR = 1) Pin name OR = 1 OR = 0 Floating OR = 1 True open-drain (high sink) PA5:4 Floating Pull-up Open drain Push-pull PA3 Floating Floating interrupt Open drain Push-pull PB3 Floating Floating interrupt Open drain Push-pull PB4, PB2:0 Floating Pull-up Open drain Push-pull Port C PC7:0 Floating Pull-up Open drain Push-pull Port D PD5:0 Floating Pull-up Open drain Push-pull Port E PE1:0 Floating Pull-up Open drain Push-pull PF7:6, 4 Floating Pull-up Open drain Push-pull PF2:0 Floating Pull-up Open drain Push-pull Port B Port F Table 33. I/O port register map and reset values Address (Hex.) Register label 7 6 5 4 3 2 1 0 Reset value of all I/O port registers 0 0 0 0 0 0 0 0 0000h PADR 0001h PADDR 0002h PAOR 0003h PBDR 0004h PBDDR 0005h PBOR 0006h PCDR 0007h PCDDR 0008h PCOR 0009h PDDR 000Ah PDDDR 000Bh PDOR MSB LSB MSB LSB MSB LSB MSB LSB 63/193 I/O ports ST72324Bxx Table 33. I/O port register map and reset values Address (Hex.) 64/193 Register label 000Ch PEDR 000Dh PEDDR 000Eh PEOR 000Fh PFDR 0010h PFDDR 0011h PFOR 7 6 5 4 3 2 1 0 MSB LSB MSB LSB ST72324Bxx On-chip peripherals 10 On-chip peripherals 10.1 Watchdog timer (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 10.1.2 10.1.3 Main features Programmable free-running downcounter Programmable reset Reset (if Watchdog activated) when the T6 bit reaches zero Optional reset on HALT instruction (configurable by option byte) Hardware Watchdog selectable by option byte Functional description The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is decremented every 16384 fOSC2 cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30s. The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the WDGCR register must be between FFh and C0h: The WDGA bit is set (Watchdog enabled) The T6 bit is set to prevent generating an immediate reset The T[5:0] bits contain the number of increments which represents the time delay before the Watchdog produces a reset (see Figure 33: Approximate timeout duration). The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see Figure 34). Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the Watchdog is activated, the HALT instruction generates a reset. 65/193 On-chip peripherals ST72324Bxx Figure 32. Watchdog block diagram Reset fOSC2 MCC/RTC Watchdog Control register (WDGCR) Div 64 WDGA T6 T5 T4 T2 T3 T1 T0 6-bit downcounter (CNT) 12-bit MCC RTC counter LSB MSB 11 10.1.4 6 5 0 WDG prescaler div 4 TB[1:0] bits (MCCSR register) How to program the Watchdog timeout Figure 33 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If more precision is needed, use the formulae in Figure 34. Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 33. Approximate timeout duration 3F 38 30 CNT value (Hex.) 28 20 18 10 08 00 1.5 18 34 50 65 82 Watchdog timeout (ms) @ 8 MHz. fOSC2 66/193 98 114 128 ST72324Bxx On-chip peripherals Figure 34. Exact timeout duration (tmin and tmax) WHERE: tmin0 = (LSB + 128) x 64 x tOSC2 tmax0 = 16384 x tOSC2 tOSC2 = 125 ns if fOSC2 = 8 MHz CNT = value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register TB1 bit (MCCSR reg.) TB0 bit (MCCSR reg.) Selected MCCSR timebase MSB LSB 0 0 2 ms 4 59 0 1 4 ms 8 53 1 0 10 ms 20 35 1 1 25 ms 49 54 To calculate the minimum Watchdog timeout (tmin): MSB IF CNT < ------------4 THEN t min = t min0 + 16384 x CNT x t osc2 4CNT 4CNT ELSE t = t + 16384 x CNT - ----------------- + ( 192 + LSB ) x 64 x ----------------min min0 MSB MSB x t osc2 To calculate the maximum Watchdog timeout (tmax): MSB IF CNT ------------4 THEN t max = t max0 + 16384 x CNT x t osc2 4CNT 4CNT ELSE t = t + 16384 x CNT - ----------------- + ( 192 + LSB ) x 64 x ----------------max max0 MSB MSB x t osc2 NOTE: In the above formulae, division results must be rounded down to the next integer value. EXAMPLE: With 2ms timeout selected in MCCSR register Value of T[5:0] bits in WDGCR register (Hex.) Min. Watchdog timeout (ms) tmin Max. Watchdog timeout (ms) tmax 00 1.496 2.048 3F 128 128.552 67/193 On-chip peripherals 10.1.5 ST72324Bxx Low power modes Table 34. Effect of lower power modes on Watchdog Mode Description Slow No effect on Watchdog Wait OIE bit in WDGHALT bit in MCCSR register option byte 0 0 No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset. If an external interrupt is received, the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations, see Section 10.1.7 below. 0 1 A reset is generated. x No reset is generated. The MCU enters Active-halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks. Halt 1 10.1.6 Hardware Watchdog option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the option byte description in Section 14.1: Flash devices. 10.1.7 Using Halt mode with the WDG (WDGHALT option) The following recommendation applies if Halt mode is used when the watchdog is enabled: Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected WDG reset immediately after waking up the microcontroller. 10.1.8 Interrupts None. 68/193 ST72324Bxx 10.1.9 On-chip peripherals Control register (WDGCR) WDGCR 7 Reset value: 0111 1111 (7Fh) 6 5 3 WDGA T[6:0] R/W R/W Table 35. Bit 2 1 0 WDGCR register description Name Function 7 Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. WDGA 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. 6:0 7-bit counter (MSB to LSB) These bits contain the value of the Watchdog counter, which is decremented every T[6:0] 16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 is cleared). Table 36. Watchdog timer register map and reset values Address (Hex.) Register label 002Ah 10.2 4 WDGCR reset value 7 6 5 4 3 2 1 0 WDGA 0 T6 1 T5 1 T4 1 T3 1 T2 1 T1 1 T0 1 Main clock controller with real-time clock and beeper (MCC/RTC) The main clock controller consists of three different functions: a programmable CPU clock prescaler a clock-out signal to supply external devices a real-time clock timer with interrupt capability Each function can be used independently and simultaneously. 10.2.1 Programmable CPU clock prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages Slow power saving mode (see Section 8.2: Slow mode on page 52 for more details). The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MCCSR register: CP[1:0] and SMS. 69/193 On-chip peripherals 10.2.2 ST72324Bxx Clock-out capability The clock-out capability is an alternate function of an I/O port pin that outputs the fCPU clock to drive external devices. It is controlled by the MCO bit in the MCCSR register. Caution: When selected, the clock out pin suspends the clock during Active-halt mode. 10.2.3 Real-time clock (RTC) timer The counter of the real-time clock timer allows an interrupt to be generated based on an accurate real-time clock. Four different time bases depending directly on fOSC2 are available. The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF. When the RTC interrupt is enabled (OIE bit set), the ST7 enters Active-halt mode when the HALT instruction is executed. See Section 8.4: Active-halt and Halt modes on page 54 for more details. 10.2.4 Beeper The beep function is controlled by the MCCBCR register. It can output three selectable frequencies on the Beep pin (I/O port alternate function). Figure 35. Main clock controller (MCC/RTC) block diagram BC1 BC0 MCCBCR Beep Beep signal selection MCO 12-bit MCC RTC counter Div 64 To Watchdog timer MCO CP1 CP0 SMS TB1 TB0 OIE OIF MCCSR fOSC2 Div 2, 4, 8, 16 MCC/RTC interrupt 1 0 70/193 fCPU CPU clock to CPU and peripherals ST72324Bxx 10.2.5 On-chip peripherals Low power modes Table 37. Effect of low power modes on MCC/RTC Mode Description Wait No effect on MCC/RTC peripheral. MCC/RTC interrupt causes the device to exit from Wait mode. No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt causes the device to exit from Active-halt mode. Active-halt MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with Exit from Halt capability. Halt 10.2.6 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction). Table 38. MCC/RTC interrupt control/wakeup capability Interrupt event Event flag Time base overflow event OIF Enable control bit Exit from Wait OIE Exit from Halt No(1) Yes 1. The MCC/RTC interrupt wakes up the MCU from Active-halt mode, not from Halt mode. 10.2.7 MCC registers MCC control/status register (MCCSR) ) MCCSR 7 6 5 4 3 2 1 0 MCO CP[1:0] SMS TB[1:0] OIE OIF R/W R/W R/W R/W R/W R/W Table 39. Bit 7 Reset value: 0000 0000 (00h) MCCSR register description Name Function MCO Main Clock Out selection This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O). 1: MCO alternate function enabled (fCPU on I/O port). Note: To reduce power consumption, the MCO function is not active in Active-halt mode. 71/193 On-chip peripherals ST72324Bxx Table 39. MCCSR register description (continued) Bit Name 6:5 CPU Clock Prescaler These bits select the CPU clock prescaler which is applied in different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software: CP[1:0] 00: fCPU in Slow mode = fOSC2/2 01: fCPU in Slow mode = fOSC2/4 10: fCPU in Slow mode = fOSC2/8 11: fCPU in Slow mode = fOSC2/16 4 3:2 1 SMS Function Slow Mode Select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC2. 1: Slow mode. fCPU is given by CP1, CP0. See Section 8.2: Slow mode and Section 10.2: Main clock controller with real-time clock and beeper (MCC/RTC) for more details. Time Base control These bits select the programmable divider time base. They are set and cleared by TB[1:0] software (see Table 40). A modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real-time clock. OIE Oscillator interrupt Enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from Active-halt mode. When this bit is set, calling the ST7 software HALT instruction enters the Active-halt power saving mode . 0 . OIF Table 40. Oscillator interrupt Flag This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached Caution: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. Time base selection Time base Counter prescaler 72/193 TB1 TB0 2 ms 0 0 8 ms 4 ms 0 1 80000 20 ms 10 ms 1 0 200000 50 ms 25 ms 1 1 fOSC2 = 4 MHz fOSC2 = 8 MHz 16000 4 ms 32000 ST72324Bxx On-chip peripherals MCC beep control register (MCCBCR) MCCBCR Reset value: 0000 0000 (00h) 7 6 Table 41. 5 4 3 2 1 0 Reserved BC[1:0] - R/W MCCBCR register description Bit Name 7:2 - Function Reserved, must be kept cleared Beep Control These 2 bits select the PF1 pin beep capability (see Table 42). The beep output 1:0 BC[1:0] signal is available in Active-halt mode but has to be disabled to reduce the consumption. Table 42. Beep frequency selection BC1 BC0 Beep mode with fOSC2 = 8 MHz 0 0 Off 0 1 ~2 kHz 1 0 ~1 kHz 1 1 ~500 Hz Table 43. Output Beep signal ~50% duty cycle Main clock controller register map and reset values Address Register label (Hex.) 7 6 5 4 3 2 1 0 002Bh SICSR Reset value 0 AVDIE 0 AVDF 0 LVDRF x 0 0 0 WDGRF x 002Ch MCCSR Reset value MCO 0 CP1 0 CP0 0 SMS 0 TB1 0 TB0 0 OIE 0 OIF 0 002Dh MCCBCR Reset value 0 0 0 0 0 0 BC1 0 BC0 0 73/193 On-chip peripherals ST72324Bxx 10.3 16-bit timer 10.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 10.3.2 Main features Programmable prescaler: fCPU divided by 2, 4 or 8 Overflow status flag and maskable interrupt External clock input (must be at least four times slower than the CPU clock speed) with the choice of active edge 1 or 2 output compare functions each with: - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt 1 or 2 input capture functions each with: - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt Pulse width modulation mode (PWM) One pulse mode Reduced power mode 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)(c) The timer block diagram is shown in Figure 36. c. 74/193 Some timer pins may not be available (not bonded) in some ST7 devices. Refer to Section 2: Pin description. When reading an input signal on a non-bonded pin, the value will always be `1'. ST72324Bxx 10.3.3 On-chip peripherals Functional description Counter The main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. Counter Register (CR) - Counter High Register (CHR) is the most significant byte (MSB) - Counter Low Register (CLR) is the least significant byte (LSB) Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MSB) - Alternate Counter Low Register (ACLR) is the least significant byte (LSB) These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 50. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency. 75/193 On-chip peripherals ST72324Bxx Figure 36. Timer block diagram ST7 internal bus fCPU MCU-peripheral interface 8 low 8 8 low 8 low 8 high 8 high EXEDG 8 low 8 high 8 high 8-bit buffer low 8 high 16 1/2 1/4 1/8 EXTCLK pin Output Compare register 2 Output Compare register 1 Counter register Alternate Counter register Input Capture register 1 Input Capture register 2 16 16 16 CC[1:0] Timer internal bus 16 Overflow Detect circuit Output Compare circuit 6 ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 16 Edge Detect circuit 1 ICAP1 pin Edge Detect circuit 2 ICAP2 pin Latch 1 OCMP1 pin Latch 2 OCMP2 0 (Control/Status register) CSR pin ICIE OCIE TOIE FOLV2FOLV1OLVL2 IEDG1OLVL1 OC1E OC2E OPM PWM CC1 (Control register 1) CR1 CC0 IEDG2EXEDG (Control register 2) CR2 (See note 1) Timer interrupt 1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 25: Interrupt mapping on page 51). 76/193 ST72324Bxx On-chip peripherals 16-bit read sequence The 16-bit read sequence (from either the Counter register or the Alternate Counter register) is illustrated in the following Figure 37. Figure 37. 16-bit read sequence Beginning of the sequence At t0 LSB is buffered Read MSB Other instructions At t0 +t Read LSB Returns the buffered LSB value at t0 Sequence completed The user must first read the MSB, afterwhich the LSB value is automatically buffered. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MSB several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LSB of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: The TOF bit of the SR register is set. A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: Note: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. The TOF bit is not cleared by access to the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by Wait mode. In Halt mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a reset). 77/193 On-chip peripherals ST72324Bxx External clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure 38. Counter timing diagram, internal clock divided by 2 CPU clock Internal reset Timer clock Counter register FFFD FFFE FFFF 0000 0001 0002 0003 Timer Overflow Flag (TOF) Figure 39. Counter timing diagram, internal clock divided by 4 CPU clock Internal reset Timer clock Counter register FFFC FFFD 0000 0001 Timer Overflow Flag (TOF) Figure 40. Counter timing diagram, internal clock divided by 8 CPU clock Internal reset Timer clock Counter register FFFC FFFD 0000 Timer Overflow Flag (TOF) Note: 78/193 The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running. ST72324Bxx On-chip peripherals Input capture In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R/IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see Figure 42). Table 44. Input capture byte distribution Register MS byte LS byte ICiR ICiHR ICiLR The ICiR registers are read-only registers. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure To use the input capture function select the following in the CR2 register: Select the timer clock (CC[1:0]) (see Table 50). Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). Select the following in the CR1 register: Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). When an input capture occurs: ICFi bit is set. The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 42). A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set 2. An access (read or write) to the ICiLR register 79/193 On-chip peripherals Note: ST72324Bxx 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2 The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3 The two input capture functions can be used together even if the timer also uses the two output compare functions. 4 In One pulse mode and PWM mode only Input Capture 2 can be used. 5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6 The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh). Figure 41. Input capture block diagram ICAP1 pin ICAP2 pin (Control register 1) CR1 Edge Detect circuit 2 Edge Detect circuit 1 ICIE IEDG1 (Status register) SR IC2R register IC1R register ICF1 0 ICF2 CC1 16-bit free running counter Figure 42. Input capture timing diagram Timer clock FF01 FF02 FF03 ICAPi pin ICAPi flag ICAPi register Note: The rising edge is the active edge. 80/193 0 (Control register 2) CR2 16-bit Counter register 0 FF03 CC0 IEDG2 ST72324Bxx On-chip peripherals Output compare In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCiE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare register 1 (OC1R) and Output Compare register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. Table 45. Output compare byte distribution Register MS byte LS byte OCiR OCiHR OCiLR These registers are readable and witable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure To use the Output Compare function, select the following in the CR2 register: Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. Select the timer clock (CC[1:0]) (see Table 50). And select the following in the CR1 register: Select the OLVLi bit to applied to the OCMPi pins after the match occurs. Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: OCFi bit is set The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset) A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR = t * fCPU PRESC Where: t = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table 50) 81/193 On-chip peripherals ST72324Bxx If the timer clock is an external clock, the formula is: OCiR = t * fEXT Where: t fEXT = Output compare period (in seconds) = External timer clock frequency (in hertz) Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: Note: Write to the OCiHR register (further compares are inhibited). Read the SR register (first step of the clearance of the OCFi bit, which may be already set). Write to the OCiLR register (enables the output compare function and clears the OCFi bit). 1 After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2 If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3 In both internal and external clock modes, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 44 on page 83 for an example with fCPU/2 and Figure 45 on page 83 for an example with fCPU/4). This behavior is the same in OPM or PWM mode. 4 The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5 The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Forced output compare capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. The FOLVLi bits have no effect in both one pulse mode and PWM mode. 82/193 ST72324Bxx On-chip peripherals Figure 43. Output compare block diagram 16-bit free running counter OC1E OC2E CC1 CC0 (Control Register 2) CR2 16-bit (Control Register 1) CR1 Output compare 16-bit circuit OCIE FOLV2FOLV1 OLVL2 OLVL1 16-bit Latch 1 Latch 2 OC1R register OCF1 OCF2 OC2R register 0 0 OCMP1 Pin OCMP2 Pin 0 (Status register) SR Figure 44. Output compare timing diagram, fTIMER = fCPU/2 Internal CPU clock Timer clock Counter register 2ECF 2ED0 Output Compare register i (OCRi) 2ED1 2ED2 2ED3 2ED4 2ED3 Output Compare flag i (OCFi) OCMPi pin (OLVLi = 1) Figure 45. Output compare timing diagram, fTIMER = fCPU/4 Internal CPU clock Timer clock Counter register Output Compare register i (OCRi) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3 Output Compare flag i (OCFi) OCMPi pin (OLVLi = 1) 83/193 On-chip peripherals ST72324Bxx One Pulse mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula below). 2. Select the following in the CR1 register: 3. - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 50). Figure 46. One pulse mode cycle When event occurs on ICAP1 ICR1 = Counter OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When counter = OC1R OCMP1 = OLVL1 Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 84/193 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. ST72324Bxx On-chip peripherals The OC1R register value required for a specific timing application can be calculated using the following formula: t f OCiR value = * CPU -5 PRESC Where: t = Pulse period (in seconds) fCPU = CPU clock frequnency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 50) If the timer clock is an external clock the formula is: OCiR = t * fEXT - 5 Where: t fEXT = Pulse period (in seconds) = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 47). Note: 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 3 If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin. 4 The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5 When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode. Figure 47. One Pulse mode timing example(1) Counter 2ED3 01F8 IC1R 01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD 2ED3 ICAP1 OCMP1 OLVL2 OLVL1 OLVL2 Compare1 1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 85/193 On-chip peripherals ST72324Bxx Figure 48. Pulse width modulation mode timing example with two output compare functions(1)(2) Counter 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 OLVL2 OCMP1 compare2 OLVL1 compare1 34E2 FFFC OLVL2 compare2 1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1 2. On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length. Pulse Width Modulation mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated. In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1). Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula below. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column. 3. Select the following in the CR1 register: 4. 86/193 - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC2R register. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 50). ST72324Bxx On-chip peripherals Figure 49. Pulse width modulation cycle When counter = OC1R OCMP1 = OLVL1 OCMP1 = OLVL2 When counter = OC2R counter is reset to FFFCh ICF1 bit is set If OLVL1 = 1 and OLVL2 = 0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1 = OLVL2, a continuous signal will be seen on the OCMP1 pin. The OC1R register value required for a specific timing application can be calculated using the following formula: t f OCiR value = * CPU -5 PRESC Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequnency (in Hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 50) If the timer clock is an external clock the formula is: OCiR = t * fEXT - 5 Where: t fEXT = Signal or pulse period (in seconds) = External timer clock frequency (in Hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (see Figure 48). Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. 3 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4 In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. 5 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 87/193 On-chip peripherals 10.3.4 ST72324Bxx Low power modes Table 46. Effect of low power modes on 16-bit timer Mode 10.3.5 Description Wait No effect on 16-bit timer. Timer interrupts cause the device to exit from Wait mode. Halt 16-bit timer registers are frozen. In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with Exit from Halt mode capability or from the counter reset value when the MCU is woken up by a reset. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with Exit from Halt mode capability, the ICFi bit is set, and the counter value present when exiting from Halt mode is captured into the ICiR register. Interrupts Table 47. 16-bit timer interrupt control/wakeup capability(1) Interrupt event Event flag Enable Control bit Exit from Wait Input Capture 1 event/counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Output Compare 1 event (not available in PWM mode) OCF1 Output Compare 2 event (not available in PWM mode) OCF2 Exit from Halt ICIE Yes No OCIE Timer Overflow event TOF TOIE 1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 7: Interrupts). These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in the CC register is reset (RIM instruction). 88/193 ST72324Bxx 10.3.6 On-chip peripherals Summary of timer modes Table 48. Summary of timer modes Timer resources Mode Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Input Capture (1 and/or 2) Output Compare (1 and/or 2) Not recommended(1) One Pulse mode No Not recommended(3) PWM mode Partially(2) No No 1. See note 4 in One Pulse mode on page 84. 2. See note 5 in One Pulse mode on page 84. 3. See note 4 in Pulse Width Modulation mode on page 86. 10.3.7 16-bit timer registers Each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. Control Register 1 (CR1) CR1 Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 R/W R/W R/W R/W R/W R/W R/W R/W M Table 49. Bit CR1 register description Name Function ICIE Input Capture Interrupt Enable 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. 6 OCIE Output Compare Interrupt Enable 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. 5 TOIE Timer Overflow Interrupt Enable 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. 7 89/193 On-chip peripherals Table 49. Bit ST72324Bxx CR1 register description (continued) Name Function 4 Forced Output compare 2 This bit is set and cleared by software. FOLV2 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. 3 Forced Output compare 1 This bit is set and cleared by software. FOLV1 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. 2 Output Level 2 This bit is copied to the OCMP2 pin whenever a successful comparison occurs with OLVL2 the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width modulation mode. 1 IEDG1 Input Edge 1 This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. 0 OLVL1 Output Level 1 The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. Control Register 2 (CR2) CR2 Reset value: 0000 0000 (00h) 7 6 5 4 OC1E OC2E OPM PWM R/W R/W R/W R/W M Table 50. Bit 7 6 90/193 Name 3 2 1 0 CC[1:0] IEDG2 EXEDG R/W R/W R/W CR2 register description Function OCIE Output compare 1 pin enable This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and One-Pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. OC2E Output compare 2 pin enable This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. ST72324Bxx On-chip peripherals Table 50. Bit 5 4 CR2 register description (continued) Name Function OPM One Pulse mode 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register. PWM Pulse width modulation 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Clock control The timer clock mode depends on these bits. 00: Timer clock = fCPU/4 01: Timer clock = fCPU/2 CC[1:0] 10: Timer clock = fCPU/8 11: Timer clock = external clock (where available) Note: If the external clock pin is not available, programming the external clock configuration stops the counter. 3:2 1 Input edge 2 This bit determines which type of level transition on the ICAP2 pin will trigger the IEDG2 capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. 0 External clock edge This bit determines which type of level transition on the external clock pin EXTCLK EXEDG will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register. Control/Status Register (CSR) CSR Reset value: xxxx x0xx (xxh) 7 6 5 4 3 2 ICF1 OCF1 TOF ICF2 OCF2 TIMD Reserved RO RO RO RO RO R/W - M Table 51. Bit Name 7 1 0 CSR register description Function Input capture flag 1 0: No input capture (reset value). ICF1 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. 91/193 On-chip peripherals Table 51. ST72324Bxx CSR register description (continued) Bit Name Function Output compare flag 1 0: No match (reset value). OCF1 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. 6 Timer overflow flag 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. 5 TOF 4 Input capture flag 2 0: No input capture (reset value). ICF2 1: An Input Capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. 3 Output compare flag 2 0: No match (reset value). OCF2 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. 2 Timer disable This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce TIMD power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: Timer enabled. 1: Timer prescaler, counter and outputs disabled. 1:0 - Reserved, must be kept cleared. Input capture 1 high register (IC1HR) This is an 8-bit register that contains the high part of the counter value (transferred by the input capture 1 event). IC1HR 7 Reset value: undefined 6 5 4 3 2 1 MSB RO 92/193 0 LSB RO RO RO RO RO RO RO ST72324Bxx On-chip peripherals Input capture 1 low register (IC1LR) This is an 8-bit register that contains the low part of the counter value (transferred by the input capture 1 event). IC1LR 7 Reset value: undefined 6 5 4 3 2 1 MSB RO 0 LSB RO RO RO RO RO RO RO Output compare 1 high register (OC1HR) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OC1HR 7 Reset value: 1000 0000 (80h) 6 5 4 3 2 1 MSB R/W 0 LSB R/W R/W R/W R/W R/W R/W R/W Output compare 1 low register (OC1LR) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OC1LR 7 Reset value: 0000 0000 (00h) 6 5 4 3 2 1 MSB R/W 0 LSB R/W R/W R/W R/W R/W R/W R/W Output compare 2 high register (OC2HR) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OC2HR 7 Reset value: 1000 0000 (80h) 6 5 4 3 2 1 MSB R/W 0 LSB R/W R/W R/W R/W R/W R/W R/W 93/193 On-chip peripherals ST72324Bxx Output compare 2 low register (OC2LR) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OC2LR 7 Reset value: 0000 0000 (00h) 6 5 4 3 2 1 MSB R/W 0 LSB R/W R/W R/W R/W R/W R/W R/W Counter high register (CHR) This is an 8-bit register that contains the high part of the counter value. CHR Reset value: 1111 1111 (FFh) 7 6 5 4 3 2 1 MSB RO 0 LSB RO RO RO RO RO RO RO Counter low register (CLR) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit. CLR Reset value: 1111 1100 (FCh) 7 6 5 4 3 2 1 MSB RO 0 LSB RO RO RO RO RO RO RO Alternate counter high register (ACHR) This is an 8-bit register that contains the high part of the counter value. ACHR 7 Reset value: 1111 1111 (FFh) 6 5 4 3 2 1 MSB RO 94/193 0 LSB RO RO RO RO RO RO RO ST72324Bxx On-chip peripherals Alternate counter low register (ACLR) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register. ACLR 7 Reset value: 1111 1100 (FCh) 6 5 4 3 2 1 0 MSB RO LSB RO RO RO RO RO RO RO Input capture 2 high register (IC2HR) This is an 8-bit register that contains the high part of the counter value (transferred by the Input Capture 2 event). 1C2HR 7 Reset value: undefined 6 5 4 3 2 1 0 MSB RO LSB RO RO RO RO RO RO RO Input capture 2 low register (IC2LR) This is an 8-bit register that contains the low part of the counter value (transferred by the Input Capture 2 event). 1C2LR 7 Reset value: undefined 6 5 4 3 2 1 0 MSB RO Table 52. LSB RO RO RO RO RO RO RO 16-bit timer register map and reset values Address (Hex.) Register label Timer A: 32 Timer B: 42 7 6 5 4 3 2 1 0 CR1 Reset value ICIE 0 OCIE 0 TOIE 0 FOLV2 0 FOLV1 0 OLVL2 0 IEDG1 0 OLVL1 0 Timer A: 31 Timer B: 41 CR2 Reset value OC1E 0 OC2E 0 OPM 0 PWM 0 CC1 0 CC0 0 IEDG2 0 EXEDG 0 Timer A: 33 Timer B: 43 CSR Reset value ICF1 x OCF1 x TOF x ICF2 x OCF2 x TIMD 0 x x Timer A: 34 Timer B: 44 IC1HR Reset value MSB x x x x x x x LSB x Timer A: 35 Timer B: 45 IC1LR Reset value MSB x x x x x x x LSB x 95/193 On-chip peripherals Table 52. ST72324Bxx 16-bit timer register map and reset values (continued) Address (Hex.) Register label Timer A: 36 Timer B: 46 7 6 5 4 3 2 1 0 OC1HR Reset value MSB 1 0 0 0 0 0 0 LSB 0 Timer A: 37 Timer B: 47 OC1LR Reset value MSB 0 0 0 0 0 0 0 LSB 0 Timer A: 3E Timer B: 4E OC2HR Reset value MSB 1 0 0 0 0 0 0 LSB 0 Timer A: 3F Timer B: 4F OC2LR Reset value MSB 0 0 0 0 0 0 0 LSB 0 Timer A: 38 Timer B: 48 CHR Reset value MSB 1 1 1 1 1 1 1 LSB 1 Timer A: 39 Timer B: 49 CLR Reset value MSB 1 1 1 1 1 1 0 LSB 0 Timer A: 3A Timer B: 4A ACHR Reset value MSB 1 1 1 1 1 1 1 LSB 1 Timer A: 3B Timer B: 4B ACLR Reset value MSB 1 1 1 1 1 1 0 LSB 0 Timer A: 3C Timer B: 4C IC2HR Reset value MSB x x x x x x x LSB x Timer A: 3D Timer B: 4D IC2LR Reset value MSB x x x x x x x LSB x 10.4 Serial peripheral interface (SPI) 10.4.1 Introduction The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves. However, the SPI interface can not be a master in a multi-master system. 10.4.2 Note: 96/193 Main features Full duplex synchronous transfers (on 3 lines) Simplex synchronous transfers (on 2 lines) Master or slave operation 6 master mode frequencies (fCPU/4 max.) fCPU/2 max. slave mode frequency (see note) SS Management by software or hardware Programmable clock polarity and phase End of transfer interrupt flag Write collision, Master mode fault and Overrun flags In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. ST72324Bxx 10.4.3 On-chip peripherals General description Figure 50 shows the serial peripheral interface (SPI) block diagram. The SPI has three registers: - SPI Control Register (SPICR) - SPI Control/Status Register (SPICSR) - SPI Data Register (SPIDR) The SPI is connected to external devices through four pins: - MISO: Master In / Slave Out data - MOSI: Master Out / Slave In data - SCK: Serial Clock out by SPI masters and input by SPI slaves - SS: Slave select: This input signal acts as a `chip select' to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master MCU. Figure 50. Serial peripheral interface block diagram Data/Address bus Read SPIDR Interrupt request Read Buffer MOSI 0 SPICSR 7 MISO 8-bit Shift Register SPIF WCOL OVR MODF SOD bit 0 SOD SSM SSI Write SS SPI state control SCK 7 1 0 SPICR 0 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 Master control Serial clock generator SS Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure 51. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). 97/193 On-chip peripherals ST72324Bxx The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node (in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 54) but master and slave must be programmed with the same timing mode. Figure 51. Single master/single slave application Master MSB Slave LSB 8-bit Shift Register SPI clock generator MSB MISO MISO MOSI MOSI SCK SS LSB 8-bit Shift Register SCK +5V SS Not used if SS is managed by software Slave select management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 53). In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register. In Master mode: - SS internal must be held high continuously Depending on the data/clock timing relationship, there are two cases in Slave mode (see Figure 52): If CPHA = 1 (data latched on second clock edge): - SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to VSS, or made free for standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR register) If CPHA = 0 (data latched on first clock edge): - 98/193 SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Write collision error (WCOL) on page 102). ST72324Bxx On-chip peripherals Figure 52. Generic SS timing diagram Byte 1 MOSI/MISO Byte 2 Byte 3 Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1) Figure 53. Hardware/software slave select management SSM bit SSI bit SS external pin 1 SS internal 0 Master mode operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0). How to operate the SPI in master mode To operate the SPI in master mode, perform the following steps in order: 1. 2. Write to the SPICR register: - Select the clock frequency by configuring the SPR[2:0] bits. - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 54 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. Write to the SPICSR register: - 3. Write to the SPICR register: - Caution: Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. Set the MSTR and SPE bits. Note: MSTR and SPE bits remain set only if SS is high. If the SPICSR register is not written first, the SPICR register setting (MSTR bit) might not be taken into account. The transmit sequence begins when software writes a byte in the SPIDR register. 99/193 On-chip peripherals ST72324Bxx Master mode transmit sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: Note: 1. An access to the SPICSR register while the SPIF bit is set. 2. A read to the SPIDR register. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Slave mode operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. 2. Write to the SPICSR register to perform the following actions: - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 54). The slave must have the same CPOL and CPHA settings as the master. - Manage the SS pin as described in Slave select management on page 98 and Figure 52. If CPHA = 1, SS must be held low continuously. If CPHA = 0, SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions. Slave mode transmit sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: Note: 100/193 1. An access to the SPICSR register while the SPIF bit is set. 2. A write or a read to the SPIDR register. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. ST72324Bxx On-chip peripherals The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Overrun condition (OVR) on page 102). 10.4.4 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (see Figure 54). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge Figure 54 shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK, MISO and MOSI pins are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Figure 54. Data clock timing diagram(1) CPHA = 1 SCK (CPOL = 1) SCK (CPOL = 0) MISO (from master) MSB Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 MOSI (from slave) MSB Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSB LSB SS (to slave) Capture strobe CPHA = 0 SCK (CPOL = 1) SCK (CPOL = 0) MISO (from master) MOSI (from slave) MSB MSB Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSB Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSB SS (to slave) Capture strobe 1. This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter. 101/193 On-chip peripherals 10.4.5 ST72324Bxx Error flags Master mode fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: - The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: Note: 1. A read access to the SPICSR register while the MODF bit is set. 2. A write to the SPICR register. To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. Overrun condition (OVR) An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte. When an Overrun occurs the OVR bit is set and an interrupt request is generated if the SPIE bit is set. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost. The OVR bit is cleared by reading the SPICSR register. Write collision error (WCOL) A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted and the software write is unsuccessful. Write collisions can occur both in master and slave mode. See also Slave select management on page 98. Note: A read collision will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). A software sequence clears the WCOL bit (see Figure 55). 102/193 ST72324Bxx On-chip peripherals Figure 55. Clearing the WCOL bit (Write collision flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SPICSR Result 2nd Step Read SPIDR SPIF = 0 WCOL = 0 Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step Read SPICSR Result 2nd Step Read SPIDR Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit. WCOL = 0 Single master systems A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 56). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. Note: To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission. For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register. Other transmission security methods can use ports for handshake lines or data bytes with command fields. Figure 56. Single master/multiple slave configuration SS SS SCK SCK MOSI MISO MOSI MISO MOSI SCK MISO Slave MCU Slave MCU Slave MCU Slave MCU SS SS SCK MOSI MISO MOSI MISO Master MCU 5V Ports SCK SS 103/193 On-chip peripherals 10.4.6 ST72324Bxx Low power modes Table 53. Effect of low power modes on SPI Mode Description Wait No effect on SPI. SPI interrupt events cause the device to exit from Wait mode. Halt SPI registers are frozen. In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with Exit from Halt mode capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the device. Using the SPI to wake up the MCU from Halt mode In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. Caution: The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. Therefore, if Slave selection is configured as external (see Slave select management on page 98), make sure the master drives a low level on the SS pin when the slave enters Halt mode. 10.4.7 Interrupts Table 54. SPI interrupt control/wakeup capability(1) Interrupt event Event flag SPI end of transfer event SPIF Master mode fault event MODF Enable control bit Exit from Wait Exit from Halt Yes SPIE Yes No Overrun error OVR 1. The SPI interrupt events are connected to the same interrupt vector (see Section 7: Interrupts). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 10.4.8 SPI registers SPI control register (SPICR) SPICR 104/193 Reset value: 0000 xxxx (0xh) 7 6 5 4 3 2 1 0 SPIE SPE SPR2 MSTR CPOL CPHA SPR[1:0] R/W R/W R/W R/W R/W R/W R/W ST72324Bxx On-chip peripherals Table 55. Bit 7 6 5 4 3 2 SPICR register description Name Function SPIE Serial Peripheral Interrupt Enable This bit is set and cleared by software. 0: Interrupt is inhibited. 1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register. SPE Serial Peripheral Output Enable This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS = 0 (see Master mode fault (MODF) on page 102). The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled SPR2 Divider Enable This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 56: SPI master mode SCK frequency. 0: Divider by 2 enabled 1: Divider by 2 disabled Note: This bit has no effect in slave mode. MSTR Master mode This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS = 0 (see Master mode fault (MODF) on page 102). 0: Slave mode 1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed. CPOL Clock Polarity This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. CPHA Clock Phase This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Note: The slave must have the same CPOL and CPHA settings as the master. Serial clock frequency These bits are set and cleared by software. Used with the SPR2 bit, they select 1:0 SPR[1:0] the baud rate of the SPI serial clock SCK output by the SPI in master mode (seeTable 56). Note: These 2 bits have no effect in slave mode. Table 56. SPI master mode SCK frequency Serial clock SPR2 SPR1 SPR0 fCPU/4 1 0 0 fCPU/8 0 0 0 105/193 On-chip peripherals ST72324Bxx Table 56. SPI master mode SCK frequency (continued) Serial clock SPR2 SPR1 SPR0 fCPU/16 0 0 1 fCPU/32 1 1 0 fCPU/64 0 1 0 fCPU/128 0 1 1 SPI control/status register (SPICSR) SPICSR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 SPIF WCOL OVR MODF Reserved SOD SSM SSI RO RO RO RO - R/W R/W R/W Table 57. Bit 7 6 5 4 3 106/193 SPICSR register description Name Function SPIF Serial peripheral data transfer flag This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared 1: Data transfer between the device and an external device has been completed. Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Write collision status This bit is set by hardware when a write to the SPIDR register is done during a WCOL transmit sequence. It is cleared by a software sequence (see Figure 55). 0: No write collision occurred 1: A write collision has been detected. OVR SPI Overrun error This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (see Overrun condition (OVR) on page 102). An interrupt is generated if SPIE = 1 in SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected Mode fault flag This bit is set by hardware when the SS pin is pulled low in master mode (see Master mode fault (MODF) on page 102). An SPI interrupt can be generated if SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An MODF access to the SPICR register while MODF = 1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected. - Reserved, must be kept cleared. ST72324Bxx On-chip peripherals Table 57. Bit SPICSR register description (continued) Name Function SOD SPI output disable This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode). 0: SPI output enabled (if SPE = 1). 1: SPI output disabled. SSM SS management This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Slave select management on page 98. 0: Hardware management (SS managed by external pin). 1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O). SSI SS Internal mode This bit is set and cleared by software. It acts as a `chip select' by controlling the level of the SS slave select signal when the SSM bit is set. 0: Slave selected. 1: Slave deselected. 2 1 0 SPI data I/O register (SPIDR) SPIDR Reset value: undefined 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte. Note: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Figure 50). 107/193 On-chip peripherals ST72324Bxx Table 58. SPI register map and reset values Address (Hex.) Register label 7 6 5 4 3 2 1 0 x x x x LSB x 0021h SPIDR Reset value MSB x x x 0022h SPICR Reset value SPIE 0 SPE 0 SPR2 0 MSTR CPOL CPHA SPR1 SPR0 0 x x x x 0023h SPICSR Reset value SPIF 0 WCOL 0 OVR 0 MODF 0 10.5 Serial communications interface (SCI) 10.5.1 Introduction 0 SOD 0 SSM 0 SSI 0 The serial communications interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 10.5.2 Main features Full duplex, asynchronous communications NRZ standard format (mark/space) Dual baud rate generator systems Independently programmable transmit and receive baud rates up to 500K baud. Programmable data word length (8 or 9 bits) Receive buffer full, Transmit buffer empty and End of Transmission flags 2 receiver wakeup modes Address bit (MSB) - Idle line Muting function for multiprocessor configurations Separate enable bits for Transmitter and Receiver 4 error detection flags 108/193 - - Overrun error - Noise error - Frame error - Parity error 5 interrupt sources with flags - Transmit data register empty - Transmission complete - Receive data register full - Idle line received - Overrun error detected ST72324Bxx 10.5.3 On-chip peripherals Parity control - Transmits parity bit - Checks parity of received data byte Reduced power consumption mode General description The interface is externally connected to another device by two pins (see Figure 58): TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level. RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through these pins, serial data is transmitted and received as frames comprising: an Idle Line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first a Stop bit indicating that the frame is complete This interface uses two types of baud rate generator: a conventional type for commonly-used baud rates an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies 109/193 On-chip peripherals ST72324Bxx Figure 57. SCI block diagram Write Read (Data Register) DR Received Data Register (RDR) Transmit Data Register (TDR) TDO Received Shift Register Transmit Shift Register RDI CR1 R8 Wake up unit Transmit control T8 SCID M WAKE PCE PS PIE Receiver clock Receiver control CR2 SR TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE SCI Interrupt control Transmitter clock fCPU Transmitter rate control /16 /PR BRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 Receiver rate control Conventional baud rate generator 110/193 PE ST72324Bxx 10.5.4 On-chip peripherals Functional description The block diagram of the serial control interface is shown in Figure 57. It contains six dedicated registers: 2 control registers (SCICR1 and SCICR2) a status register (SCISR) a baud rate register (SCIBRR) an extended prescaler receiver register (SCIERPR) an extended prescaler transmitter register (SCIETPR) Refer to the register descriptions in Section 10.5.7 for the definitions of each bit. Serial data format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 57). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of `1's followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving `0's for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra `1' bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator. Figure 58. Word length programming 9-bit word length (M bit is set) Possible Parity bit Data frame Start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 Next data frame Next Stop Start bit bit Start bit Idle frame Break frame Extra '1' Start bit 8-bit word length (M bit is reset) Possible Parity bit Data frame Start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 Stop bit 7 Bit Next data frame Next Start bit Idle frame Start bit Break frame Extra Start bit '1' 111/193 On-chip peripherals ST72324Bxx Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. Character transmission During an SCI transmission, data shifts out LSB first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 57). Procedure 1. Select the M bit to define the word length. 2. Select the desired baud rate using the SCIBRR and the SCIETPR registers. 3. Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission. 4. Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: The TDR register is empty. The data transfer is beginning. The next data can be written in the SCIDR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. Clearing the TC bit is performed by the following software sequence: Note: 112/193 1. An access to the SCISR register 2. A write to the SCIDR register The TDRE and TC bits are cleared by the same software sequence. ST72324Bxx On-chip peripherals Break characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 58). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore, the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte in the SCIDR. Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 57). Procedure 1. Select the M bit to define the word length. 2. Select the desired baud rate using the SCIBRR and the SCIERPR registers. 3. Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The error flags can be set if a frame error, noise or an overrun error has been detected during reception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SCISR register 2. A read to the SCIDR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break character When a break character is received, the SCI handles it as a framing error. Idle character When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register. 113/193 On-chip peripherals ST72324Bxx Overrun error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the RDR register as long as the RDRF bit is not cleared. When a overrun error occurs: The OR bit is set. The RDR content will not be lost. The shift register will be overwritten. An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation. Noise error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag from being set during start bit reception, there should be a valid edge detection as well as three valid samples. When noise is detected in a frame: The NF flag is set at the rising edge of the RDRF bit. Data is transferred from the Shift register to the SCIDR register. No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation. During reception, if a false start bit is detected (for example, 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received. Note: If the application Start bit is not long enough to match the above requirements, then the NF Flag may get set due to the short Start bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received. See also Noise error causes on page 119. 114/193 ST72324Bxx On-chip peripherals Figure 59. SCI baud rate and extended prescaler block diagram Extended prescaler transmitter rate control Transmitter clock SCIETPR Extended transmitter prescaler register SCIERPR Extended receiver prescaler register Receiver clock Extended prescaler receiver rate control Extended prescaler fCPU Transmitter rate control /16 /PR SCIBRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 Receiver rate control Conventional baud rate generator Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise. A break is received. When the framing error is detected: the FE bit is set by hardware Data is transferred from the Shift register to the SCIDR register. No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation. 115/193 On-chip peripherals ST72324Bxx Conventional baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: Tx = fCPU (16*PR)*TR Rx = fCPU (16*PR)*RR with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCI baud rate register (SCIBRR) on page 125. Example: If fCPU is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and receive baud rates are 38400 baud. Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. Extended baud rate generation The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional baud rate generator retains industry standard software compatibility. The extended baud rate generator block diagram is described in Figure 59. The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR register. The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value other than zero. The baud rates are calculated as follows: fCPU fCPU Rx = Tx = 16*ERPR*(PR*RR) 16*ETPR*(PR*TR) with: ETPR = 1,..,255, see SCI extended transmit prescaler division register (SCIETPR) on page 126. ERPR = 1,.. 255, see SCI extended receive prescaler division register (SCIERPR) on page 125. 116/193 ST72324Bxx On-chip peripherals Receiver muting and wakeup feature In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non-addressed receivers. The non-addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in sleep mode: All the reception status bits cannot be set. All the receive interrupts are inhibited. A muted receiver may be awakened by one of the following two ways: by Idle Line detection if the Wake bit is reset, by Address Mark detection if the Wake bit is set. A receiver wakes up by Idle Line detection when the Receive line has recognized an Idle Frame. Then the RWU bit is reset by hardware but the Idle bit is not set. A receiver wakes up by Address Mark detection when it received a `1' as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU = 1) and an address mark wakeup event occurs (RWU is reset) before the write operation, the RWU bit will be set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode. Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 59. Table 59. Frame formats(1)(2) M bit PCE bit SCI frame 0 0 | SB | 8 bit data | STB | 0 1 | SB | 7-bit data | PB | STB | 1 0 | SB | 9-bit data | STB | 1 1 | SB | 8-bit data PB | STB | 1. SB = Start bit, STB = Stop bit, and PB = Parity bit. 2. In case of wakeup by an address mark, the MSB bit of the data is taken into account and not the Parity bit. 117/193 On-chip peripherals ST72324Bxx Even parity The parity bit is calculated to obtain an even number of `1's inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit, for example, data = 00110101; 4 bits set => Parity bit will be 0 if Even parity is selected (PS bit = 0). Odd parity The parity bit is calculated to obtain an odd number of `1's inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit, for example, data = 00110101; 4 bits set => Parity bit will be 1 if Odd parity is selected (PS bit = 1). Transmission mode If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit. Reception mode If the PCE bit is set then the interface checks if the received data byte has an even number of `1's if even parity is selected (PS = 0) or an odd number of `1's if odd parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register. SCI clock tolerance During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: If the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be `1', but the Noise flag bit is set because the three samples values are not the same. Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. Note: 118/193 The internal sampling clock of the microcontroller samples the pin value on every falling edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit length is 64 s), then the 8th, 9th and 10th samples will be at 28 s, 32 s and 36 s respectively (the first sample starting ideally at 0 s). But if the falling edge of the internal clock occurs just before the pin value changes, the samples would then be out of sync by ~4 s. This means the entire bit length must be at least 40s (36 s for the 10th sample + 4 s for synchronization with the internal sampling clock). ST72324Bxx On-chip peripherals Clock deviation causes The causes which contribute to the total deviation are: - DTRA: Deviation due to transmitter error (local oscillator error of the transmitter or the transmitter is transmitting at a different baud rate). - DQUANT: Error due to the baud rate quantization of the receiver. - DREC: Deviation of the local oscillator of the receiver: This deviation can occur during the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message. - DTCL: Deviation due to the transmission line (generally due to the transceivers) All the deviations of the system should be added and compared to the SCI clock tolerance: DTRA + DQUANT + DREC + DTCL < 3.75% Noise error causes See also the description of Noise error in Receiver on page 113. Start bit The Noise Flag (NF) is set during start bit reception if one of the following conditions occurs: 1. A valid falling edge is not detected. A falling edge is considered to be valid if the three consecutive samples before the falling edge occurs are detected as `1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a `1'. 2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a `1'. Therefore, a valid Start bit must satisfy both the above conditions to prevent the Noise Flag from being set. Data bits The Noise Flag (NF) is set during normal data bit reception if the following condition occurs: During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. The majority of the 8th, 9th and 10th samples is considered as the bit value. Therefore, a valid Data bit must have samples 8, 9 and 10 at the same value to prevent the Noise Flag from being set. Figure 60. Bit sampling in Reception mode RDI line sampled values Sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6/16 7/16 7/16 One bit time 119/193 On-chip peripherals 10.5.5 ST72324Bxx Low power modes Table 60. Effect of low power modes on SCI Mode 10.5.6 Description Wait No effect on SCI. SCI interrupts cause the device to exit from Wait mode. Halt SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. Interrupts The SCI interrupt events are connected to the same interrupt vector. These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in the CC register is reset (RIM instruction). Table 61. SCI interrupt control/wakeup capability Interrupt event Event flag Enable control bit Exit from Wait Transmit data register empty Transmission complete Received data ready to be read Exit from Halt TDRE TIE Yes No TC TCIE Yes No Yes No Yes No RDRF RIE Overrun error detected OR Idle line detected Parity error 10.5.7 IDLE ILIE Yes No PE PIE Yes No SCI registers SCI status register (SCISR) SCISR 7 6 5 4 3 2 1 0 TDRE TC RDRF IDLE OR NF FE PE RO RO RO RO RO RO RO RO Table 62. Bit 7 120/193 Reset value: 1100 0000 (C0h) Name SCISR register description Function Transmit Data Register Empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register TDRE followed by a write to the SCIDR register). 0: Data is not transferred to the shift register. 1: Data is transferred to the shift register. Note: Data will not be transferred to the shift register unless the TDRE bit is cleared. ST72324Bxx On-chip peripherals Table 62. Bit 6 SCISR register description (continued) Name Function TC Transmission complete This bit is set by hardware when transmission of a frame containing data is complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Transmission is not complete 1: Transmission is complete Note: TC is not set after the transmission of a Preamble or a Break. 5 Received data ready flag This bit is set by hardware when the content of the RDR register has been transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 RDRF register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read 4 Idle line detect This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). IDLE 0: No idle line is detected 1: Idle line is detected Note: The IDLE bit is not reset until the RDRF bit has itself been set (that is, a new idle line occurs). 3 OR Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF = 1. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No overrun error 1: Overrun error is detected Note: When this bit is set RDR register content is not lost but the shift register is overwritten. NF Noise flag This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. FE Framing error This bit is set by hardware when a desynchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No framing error is detected 1: Framing error or break character is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both Frame Error and Overrun error, it is transferred and only the OR bit will be set. 2 1 121/193 On-chip peripherals Table 62. Bit ST72324Bxx SCISR register description (continued) Name Function PE Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register. 0: No parity error 1: Parity error 0 SCI Control Register 1 (SCICR1) SCICR1 7 6 5 4 3 2 1 0 R8 T8 SCID M WAKE PCE PS PIE R/W R/W R/W R/W R/W R/W R/W R/W Table 63. SCICR1 register description Bit Name 7 R8 Receive data bit 8 This bit is used to store the 9th bit of the received word when M = 1. 6 T8 Transmit data bit 8 This bit is used to store the 9th bit of the transmitted word when M = 1. Function 5 Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and SCID cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled 4 Word length This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 data bits, 1 Stop bit 1: 1 Start bit, 9 data bits, 1 Stop bit Note: The M bit must not be modified during a data transfer (both transmission and reception). 3 2 122/193 Reset value: x000 0000 (x0h) M Wakeup method This bit determines the SCI wakeup method, it is set or cleared by software. WAKE 0: Idle line 1: Address mark PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled ST72324Bxx On-chip peripherals Table 63. Bit SCICR1 register description (continued) Name PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity PIE Parity interrupt enable This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled 1 0 Function SCI control register 2 (SCICR2) SCICR2 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK R/W R/W R/W R/W R/W R/W R/W R/W Table 64. Bit 7 6 5 4 Reset value: 0000 0000 (00h) Name TIE TCIE SCICR2 register description Function Transmitter interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register. Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC = 1 in the SCISR register. RIE Receiver interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register. ILIE Idle line interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register. 123/193 On-chip peripherals Table 64. Bit ST72324Bxx SCICR2 register description (continued) Name Function TE Transmitter enable This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Notes: - During transmission, a `0' pulse on the TE bit (`0' followed by `1') sends a preamble (Idle line) after the current word. - When TE is set there is a 1 bit-time delay before the transmission starts. Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set). RE Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit Note: Before selecting Mute mode (setting the RWU bit), the SCI must first receive some data, otherwise it cannot function in Mute mode with wakeup by Idle line detection. RWU Receiver wakeup This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wakeup sequence is recognized. 0: Receiver in Active mode 1: Receiver in Mute mode SBK Send break This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted. 1: Break characters are transmitted. Note: If the SBK bit is set to `1' and then to `0', the transmitter will send a Break word at the end of the current word. 3 2 1 0 SCI data register (SCIDR) This register contains the received or transmitted data character, depending on whether it is read from or written to. SCIDR Reset value: undefined 7 6 5 4 3 2 1 0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 R/W R/W R/W R/W R/W R/W R/W R/W The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 57). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 57). 124/193 ST72324Bxx On-chip peripherals SCI baud rate register (SCIBRR) SCIBRR Reset value: 0000 0000 (00h) 7 6 4 3 2 1 SCP[1:0] SCT[2:0] SCR[2:0] R/W R/W R/W Table 65. Bit 5 0 SCIBRR register description Name Function First SCI prescaler These 2 prescaling bits allow several standard clock division ranges. 00: PR prescaling factor = 1 7:6 SCP[1:0] 01: PR prescaling factor = 3 10: PR prescaling factor = 4 11: PR prescaling factor = 13 SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division applied to the bus clock to yield the transmit rate clock in conventional baud rate generator mode. 000: TR dividing factor = 1 001: TR dividing factor = 2 5:3 SCT[2:0] 010: TR dividing factor = 4 011: TR dividing factor = 8 100: TR dividing factor = 16 101: TR dividing factor = 32 110: TR dividing factor = 64 111: TR dividing factor = 128 SCI Receiver rate divisor These 3 bits, in conjunction with the SCP[1:0] bits, define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 000: RR dividing factor = 1 001: RR dividing factor = 2 2:0 SCR[2:0] 010: RR dividing factor = 4 011: RR dividing factor = 8 100: RR dividing factor = 16 101: RR dividing factor = 32 110: RR dividing factor = 64 111: RR dividing factor = 128 SCI extended receive prescaler division register (SCIERPR) This register is used to set the Extended Prescaler rate division factor for the receive circuit. SCIERPR 7 Reset value: 0000 0000 (00h) 6 5 4 3 2 1 0 ERPR[7:0] R/W 125/193 On-chip peripherals Table 66. Bit ST72324Bxx SCIERPR register description Name Function 8-bit extended receive prescaler register The extended baud rate generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 ERPR[7:0] divider (see Figure 59) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset. 7:0 SCI extended transmit prescaler division register (SCIETPR) This register is used to set the External Prescaler rate division factor for the transmit circuit. SCIETPR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 ETPR[7:0] R/W Table 67. Bit 7:0 Table 68. SCIETPR register description Name Function ETPR[7:0] 8-bit Extended Transmit Prescaler Register The extended baud rate generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 59) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset. Baud rate selection Conditions Symbol Parameter fCPU fTx fRx Communication frequency Accuracy vs. Standard Prescaler ~0.16% Conventional mode TR (or RR) = 128, PR = 13 TR (or RR) = 32, PR = 13 TR (or RR) = 16, PR = 13 TR (or RR) = 8, PR = 13 TR (or RR) = 4, PR = 13 TR (or RR) = 16, PR = 3 TR (or RR) = 2, PR =13 TR (or RR) = 1, PR = 13 8 MHz ~0.79% 126/193 Extended mode ETPR (or ERPR) = 35, TR (or RR)= 1, PR = 1 Standard Baud rate 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 14400 ~14285.71 Unit Hz ST72324Bxx Table 69. On-chip peripherals SCI register map and reset values Address (Hex.) Register label 7 6 5 4 3 2 1 0 0050h SCISR Reset value TDRE 1 TC 1 RDRF 0 IDLE 0 OR 0 NF 0 FE 0 PE 0 0051h SCIDR Reset value MSB x x x x x x x LSB x 0052h SCIBRR Reset value SCP1 0 SCP0 0 SCT2 0 SCT1 0 SCT0 0 SCR2 0 SCR1 0 SCR0 0 0053h SCICR1 Reset value R8 x T8 0 SCID 0 M 0 WAKE 0 PCE 0 PS 0 PIE 0 0054h SCICR2 Reset value TIE 0 TCIE 0 RIE 0 ILIE 0 TE 0 RE 0 RWU 0 SBK 0 0055h SCIERPR Reset value MSB 0 0 0 0 0 0 0 LSB 0 0057h SCIPETPR Reset value MSB 0 0 0 0 0 0 0 LSB 0 127/193 On-chip peripherals ST72324Bxx 10.6 10-bit A/D converter (ADC) 10.6.1 Introduction The on-chip analog-to-digital converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 10-bit Data Register. The A/D converter is controlled through a Control/Status Register. 10.6.2 Main features 10-bit conversion Up to 16 channels with multiplexed input Linear successive approximation Data register (DR) which contains the results Conversion complete status flag On/off bit (to reduce consumption) The block diagram is shown in Figure 61. Figure 61. ADC block diagram fCPU Div 4 0 fADC 1 Div 2 EOC SPEED ADON 0 CH3 CH2 CH1 ADCCSR CH0 4 AIN0 AIN1 Analog to Digital Analog MUX Converter AINx ADCDRH D9 D8 ADCDRL 128/193 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 D0 ST72324Bxx 10.6.3 On-chip peripherals Functional description The conversion is monotonic, meaning that the result never decreases if the analog input does not increase. If the input voltage (VAIN) is greater than VAREF (high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the allotted time. A/D converter configuration The analog input ports must be configured as input, no pull-up, no interrupt. Refer to Section 9: I/O ports. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the ADCCSR register: Select the CS[3:0] bits to assign the analog channel to convert. Starting the conversion In the ADCCSR register: Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete: - the EOC bit is set by hardware - the result is in the ADCDR registers A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit. To read the 10 bits, perform the following steps: Note: 1. Poll the EOC bit. 2. Read the ADCDRL register 3. Read the ADCDRH register. This clears EOC automatically. The data is not latched, so both the low and the high data register must be read before the next conversion is complete. Therefore, it is recommended to disable interrupts while reading the conversion result. To read only 8 bits, perform the following steps: 1. Poll the EOC bit. 2. Read the ADCDRH register. This clears EOC automatically. 129/193 On-chip peripherals ST72324Bxx Changing the conversion channel The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel. 10.6.4 Low power modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed. . Table 70. Effect of low power modes on ADC Mode 10.6.5 Description Wait No effect on A/D converter. Halt A/D converter disabled. After wakeup from Halt mode, the A/D converter requires a stabilization time tSTAB (see Section 12: Electrical characteristics) before accurate conversions can be performed. Interrupts None. 10.6.6 ADC registers ADC control/status register (ADCCSR) ADCCSR 7 6 5 4 EOC SPEED ADON Reserved CH[3:0] RO R/W RW - RW Table 71. Bit 7 130/193 Reset value: 0000 0000 (00h) Name EOC 3 1 0 ADCCSR register description Function End of Conversion This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH register or writes to any bit of the ADCCSR register. 0: Conversion is not complete 1: Conversion complete 6 ADC clock selection This bit is set and cleared by software. SPEED 0: fADC = fCPU/4 1: fADC = fCPU/2 5 A/D Converter on This bit is set and cleared by software. 0: Disable ADC and stop conversion 1: Enable ADC and start conversion ADON 2 ST72324Bxx On-chip peripherals Table 71. Bit Name 4 - 3:0 ADCCSR register description (continued) Function Reserved, must be kept cleared. Channel selection These bits are set and cleared by software. They select the analog input to convert. 0000: Channel pin = AIN0 0001: Channel pin = AIN1 0010: Channel pin = AIN2 0011: Channel pin = AIN3 0100: Channel pin = AIN4 0101: Channel pin = AIN5 0110: Channel pin = AIN6 0111: Channel pin = AIN7 CH[3:0] 1000: Channel pin = AIN8 1001: Channel pin = AIN9 1010: Channel pin = AIN10 1011: Channel pin = AIN11 1100: Channel pin = AIN12 1101: Channel pin = AIN13 1110: Channel pin = AIN14 1111: Channel pin = AIN15 Note: The number of channels is device dependent. Refer to Section 2: Pin description. ADC data register high (ADCDRH) ADCDRH 7 Reset value: 0000 0000 (00h) 6 5 4 3 2 1 0 D[9:2] RO Table 72. Bit Name 7:0 D[9:2] ADCDRH register description Function MSB of converted analog value 131/193 On-chip peripherals ST72324Bxx ADC data register low (ADCDRL) ADCDRL 7 Reset value: 0000 0000 (00h) 6 Table 73. Bit Name 7:2 - 1:0 D[1:0] Table 74. 5 4 2 1 0 Reserved D[1:0] - RO ADCDRL register description Function Reserved. Forced by hardware to 0. LSB of converted analog value ADC register map and reset values Address (Hex.) Register label 132/193 3 7 6 5 4 3 2 1 0 0070h ADCCSR Reset value EOC 0 SPEED 0 ADON 0 0 CH3 0 CH2 0 CH1 0 CH0 0 0071h ADCDRH Reset value D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 0072h ADCDRL Reset value 0 0 0 0 0 0 D1 0 D0 0 ST72324Bxx Instruction set 11 Instruction set 11.1 CPU addressing modes The CPU features 17 different addressing modes which can be classified in 7 main groups (see Table 75). : Table 75. Addressing mode groups Addressing mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset byte,#5 The CPU Instruction Set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be divided in two submodes called long and short: Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. Short addressing mode is less powerful because it can generally only access page zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes. Table 76. CPU addressing mode overview Mode Syntax Destination Pointer address (Hex.) Pointer size (Hex.) Length (bytes) Inherent nop +0 Immediate ld A,#$55 +1 Short Direct ld A,$10 00..FF +1 Long Direct ld A,$1000 0000..FFFF +2 No offset Direct Indexed ld A,(X) 00..FF +0 Short Direct Indexed ld A,($10,X) 00..1FE +1 Long Direct Indexed ld A,($1000,X) 0000..FFFF +2 Short Indirect ld A,[$10] 00..FF 00..FF byte +2 Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2 Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2 Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2 133/193 Instruction set Table 76. ST72324Bxx CPU addressing mode overview (continued) Relative Direct jrne loop PC+/-127 Relative Indirect jrne [$10] PC+/-127 Bit Direct bset $10,#7 00..FF Bit Indirect bset [$10],#7 00..FF Bit Direct Relative btjt $10,#7,skip 00..FF Bit Indirect Relative btjt [$10],#7,skip 00..FF 11.1.1 +1 00..FF byte +2 +1 00..FF byte +2 +2 00..FF byte +3 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Table 77. Inherent instructions Instruction 11.1.2 Function NOP No operation TRAP S/W interrupt WFI Wait for interrupt (low power mode) HALT Halt oscillator (lowest power mode) RET Sub-routine return IRET Interrupt sub-routine return SIM Set interrupt mask (level 3) RIM Reset interrupt mask (level 0) SCF Set carry flag RCF Reset carry flag RSP Reset stack pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/decrement TNZ Test negative or zero CPL, NEG 1 or 2 complement MUL Byte multiplication SLL, SRL, SRA, RLC, RRC Shift and rotate operations SWAP Swap nibbles Immediate Immediate instructions have two bytes: The first byte contains the opcode and the second byte contains the operand value. 134/193 ST72324Bxx Instruction set . Table 78. Immediate instructions Instruction 11.1.3 Function LD Load CP Compare BCP Bit compare AND, OR, XOR Logical operations ADC, ADD, SUB, SBC Arithmetic operations Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requiring only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 11.1.4 Indexed (no offset, short, long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indexed addressing mode consists of three submodes: Indexed (no offset) There is no offset, (no extra byte after the opcode), and it allows 00 - FF addressing space. Indexed (short) The offset is a byte, thus requiring only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 11.1.5 Indirect (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes: 135/193 Instruction set ST72324Bxx Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 11.1.6 Indirect indexed (short, long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two submodes: Indirect indexed (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect indexed (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. I Table 79. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes Instructions Long and short Short only 136/193 Function LD Load CP Compare AND, OR, XOR Logical operations ADC, ADD, SUB, SBC Arithmetic additions/subtractions operations BCP Bit Compare CLR Clear INC, DEC Increment/decrement TNZ Test negative or zero CPL, NEG 1 or 2 complement BSET, BRES Bit operations BTJT, BTJF Bit test and jump operations SLL, SRL, SRA, RLC, RRC Shift and rotate operations SWAP Swap nibbles CALL, JP Call or jump sub-routine ST72324Bxx 11.1.7 Instruction set Relative mode (direct, indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it. . Table 80. Relative direct and indirect instructions and functions Available relative direct/indirect instructions Function JRxx Conditional Jump CALLR Call Relative The relative addressing mode consists of two submodes: Relative (direct) The offset follows the opcode. Relative (indirect) The offset is defined in the memory, the address of which follows the opcode. 11.2 Instruction groups The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Table 81. Instruction groups Group Instructions Load and transfer LD CLR Stack operation PUSH POP Increment/decrement INC DEC Compare and tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit operation BSET BRES Conditional bit test and branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional jump or call JRA JRT JRF JP CALL CALLR NOP Conditional branch JRxx Interruption management TRAP WFI HALT IRET Condition code flag modification SIM RIM SCF RCF RSP RET 137/193 Instruction set ST72324Bxx Using a prebyte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable the instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: 138/193 PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. ST72324Bxx Table 82. Instruction set Instruction set overview Mnemo Description Function/example Dst Src I1 H I0 N Z C ADC Add with Carry A=A+M+C A M H N Z C ADD Addition A=A+M A M H N Z C AND Logical And A=A.M A M N Z BCP Bit compare A, memory tst (A . M) A M N Z BRES Bit reset bres Byte, #3 M BSET Bit set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call sub-routine CALLR Call sub-routine relative CLR Clear CP Arithmetic Compare tst(Reg - M) reg CPL One Complement A = FFH-A DEC Decrement dec Y HALT Halt IRET Interrupt routine return Pop CC, A, X, PC INC Increment inc X JP Absolute Jump jp [TBL.w] JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. INT pin = 1 (ext. INT pin high) JRIL Jump if ext. INT pin = 0 (ext. INT pin low) JRH Jump if H = 1 H=1? JRNH Jump if H = 0 H=0? JRM Jump if I1:0 = 11 I1:0 = 11 ? JRNM Jump if I1:0 <> 11 I1:0 <> 11 ? JRMI Jump if N = 1 (minus) N=1? JRPL Jump if N = 0 (plus) N=0? JREQ Jump if Z = 1 (equal) Z=1? JRNE Jump if Z = 0 (not equal) Z=0? JRC Jump if C = 1 C=1? JRNC Jump if C = 0 C=0? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= reg, M 0 1 N Z C reg, M N Z 1 reg, M N Z N Z N Z M 1 I1 reg, M 0 H I0 C 139/193 Instruction set Table 82. ST72324Bxx Instruction set overview (continued) Mnemo Description Function/example Dst Src JRUGT Jump if (C + Z = 0) Unsigned > JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg MUL Multiply X,A = X * A A, X, Y X, Y, A NEG Negate (2's compl) neg $10 reg, M NOP No Operation OR OR operation A=A+M A M pop reg reg M POP Pop from the Stack pop CC CC M M reg, CC I1 H I0 N Z N Z 0 I1 H C 0 I0 N Z N Z N Z C C PUSH Push onto the Stack push Y RCF Reset carry flag C=0 RIM Enable Interrupts I1:0 = 10 (level 0) RLC Rotate Left true C C <= A <= C reg, M N Z C RRC Rotate Right true C C => A => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A=A-M-C N Z C SCF Set CARRY FLAG C=1 SIM Disable Interrupts I1:0 = 11 (level 3) SLA Shift Left Arithmetic C <= A <= 0 reg, M N Z C SLL Shift Left Logic C <= A <= 0 reg, M N Z C SRL Shift Right Logic 0 => A => C reg, M 0 Z C SRA Shift Right Arithmetic A7 => A => C reg, M N Z C SUB Subtraction A=A-M A N Z C SWAP SWAP nibbles A7-A4 <=> A3-A0 reg, M N Z TNZ Test for Neg and Zero tnz lbl1 N Z TRAP S/W TRAP S/W interrupt WFI Wait for Interrupt XOR Exclusive OR N Z 140/193 A = A XOR M 0 1 A 0 M 1 1 A 1 M M 1 1 1 0 ST72324Bxx Electrical characteristics 12 Electrical characteristics 12.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 12.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3). 12.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 5 V. They are given only as design guidelines and are not tested. 12.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 62. Figure 62. Pin loading conditions ST7 pin CL 141/193 Electrical characteristics 12.1.5 ST72324Bxx Pin input voltage The input voltage measurement on a pin of the device is described in Figure 63. Figure 63. Pin input voltage ST7 pin VIN 12.2 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 12.2.1 Voltage characteristics Table 83. Voltage characteristics Symbol Ratings Maximum value Unit VDD - VSS Supply voltage 6.5 VPP - VSS Programming voltage 13 Input voltage on true open drain pin VIN(1)(2) Input voltage on any other pin |VDDx| and |VSSx| Variations between different digital power pins |VSSA - VSSx| Variations between digital and analog ground pins VESD(HBM) Electrostatic discharge voltage (human body model) VESD(MM) Electrostatic discharge voltage (machine model) V VSS - 0.3 to 6.5 VSS - 0.3 to VDD + 0.3 50 mV 50 see Section 12.8.3 on page 157 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7 k for RESET, 10 k for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS. 2. IINJ(PIN) must never be exceeded. This is implicitly ensured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected. 142/193 ST72324Bxx 12.2.2 Electrical characteristics Current characteristics Table 84. Current characteristics Symbol Ratings IVDD Total current into VDD power lines (source)(1) IVSS Total current out of VSS ground lines (sink)(1) IIO Max value Unit 32-pin devices 75 44-pin devices 150 32-pin devices 75 44-pin devices 150 Output current sunk by any standard I/O and control pin 20 Output current sunk by any high sink I/O pin 40 Output current source by any I/Os and control pin - 25 Injected current on VPP pin 5 Injected current on RESET pin 5 Injected current on OSC1 and OSC2 pins 5 Injected current on ROM and 32 Kbyte Flash devices PB0 pin 5 Injected current on 8/16 Kbyte Flash devices PB0 pin +5 mA IINJ(PIN)(2)(3) Injected current on any other IINJ(PIN) (2) pin(4)(5) Total injected current (sum of all I/O and control 5 pins)(4) 25 1. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected. 3. Negative injection degrades the analog performance of the device. See note in Section 12.13.3: ADC accuracy on page 171. If the current injection limits given in Table 106: General characteristics on page 158 are exceeded, general device malfunction may result. 4. When several inputs are submitted to a current injection, the maximum SIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with SIINJ(PIN) maximum current injection on four I/O port pins of the device. 5. True open drain I/O port pins do not accept positive injection. 12.2.3 Thermal characteristics Table 85. Symbol TSTG TJ Thermal characteristics Ratings Storage temperature range Value Unit -65 to +150 C Maximum junction temperature (see Section 13.3: Thermal characteristics) 143/193 Electrical characteristics 12.3 ST72324Bxx Operating conditions Table 86. Operating conditions Symbol fCPU Parameter Conditions Min Max Unit 0 8 MHz 3.8 5.5 4.5 5.5 1-suffix version 0 70 5-suffix version -10 85 6-suffix version -40 85 7-suffix version -40 105 3-suffix version -40 125 Internal clock frequency Operating voltage (except Flash Write/Erase) VDD TA V Operating Voltage for Flash Write/Erase Ambient temperature range VPP = 11.4 to 12.6 V Figure 64. fCPU max versus VDD fCPU [MHz] Functionality guaranteed in this area (unless otherwise specified in the tables of parametric data) 8 Functionality not guaranteed in this area 6 4 2 1 0 3.5 3.8 4.0 4.5 5.5 Supply voltage [V] Note: Some temperature ranges are only available with a specific package and memory size. Refer to Section 14: Device configuration and ordering information. Warning: 144/193 Do not connect 12 V to VPP before VDD is powered on, as this may damage the device. C ST72324Bxx Electrical characteristics 12.4 LVD/AVD characteristics 12.4.1 Operating conditions with LVD Subject to general operating conditions for TA. Table 87. Operating conditions with LVD Symbol Parameter Conditions Typ Max 4.0(1) 4.2 4.5 VD level = med. in option byte 3.55 3.75 4.0(1) VD level = low in option byte(2) 2.95(1) 3.15 3.35(1) VD level = high in option byte 3.8 4.0 4.25(1) 3.55 3.75(1) 2.8(1) 3.0 3.15(1) 150 200 250 (2) VIT-(LVD) Reset generation threshold (VDD fall) VD level = med. in option byte(2) 3.35(1) VD level = low in option byte(2) Vhys(LVD) LVD voltage threshold hysteresis(1) VIT+(LVD)-VIT-(LVD) Flash devices VtPOR VDD rise time(1) 8/16 Kbyte ROM devices Filtered glitch delay on VDD(1) V mV 100ms/V 6s/V 20ms/V ms/V 32 Kbyte ROM devices tg(VDD) Unit (1) VD level = high in option byte VIT+(LVD) Reset release threshold (VDD rise) Min Not detected by the LVD 40 ns 1. Data based on characterization results, tested in production for ROM devices only. 2. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. 12.4.2 Auxiliary voltage detector (AVD) thresholds Subject to general operating conditions for TA. Table 88. Symbol AVD thresholds Parameter 1 0 AVDF flag toggle threshold VIT+(AVD) (VDD rise) VIT-(AVD) 0 1 AVDF flag toggle threshold (VDD fall) Vhys(AVD) AVD voltage threshold hysteresis VIT- Voltage drop between AVD flag set and LVD reset activated Conditions Min Typ Max VD level = high in option byte 4.4(1) 4.6 4.9 VD level = med. in option byte 3.95(1) 4.15 4.4(1) VD level = low in option byte 3.4(1) 3.6 3.8(1) VD level = high in option byte 4.2 4.4 4.65(1) VD level = med. in option byte 3.75(1) 4.0 4.2(1) VD level = low in option byte 3.2(1) 3.4 3.6(1) VIT+(AVD)-VIT-(AVD) 200 VIT-(AVD)-VIT-(LVD) 450 Unit V mV 1. Data based on characterization results, tested in production for ROM devices only. 145/193 Electrical characteristics 12.5 ST72324Bxx Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current values must be added (except for Halt mode for which the clock is stopped). 12.5.1 ROM current consumption Table 89. ROM current consumption Symbol 32 Kbyte ROM devices 16/8 Kbyte ROM devices Typ Max(1) Typ Max(1) fOSC = 2 MHz, fCPU = 1 MHz fOSC = 4 MHz, fCPU = 2 MHz fOSC = 8 MHz, fCPU = 4 MHz fOSC = 16 MHz, fCPU = 8 MHz 0.55 1.10 2.20 4.38 0.87 1.75 3.5 7.0 0.46 0.93 1.9 3.7 0.69 1.4 2.7 5.5 mA fOSC = 2 MHz, fCPU = 62.5 kHz fOSC = 4 MHz, fCPU = 125 kHz fOSC = 8 MHz, fCPU = 250 kHz fOSC = 16 MHz, fCPU = 500 kHz 53 100 194 380 87 175 350 700 30 70 150 310 60 120 250 500 A Supply current in Wait mode fOSC = 2 MHz, fCPU = 1 MHz fOSC = 4 MHz, fCPU = 2 MHz fOSC = 8 MHz, fCPU = 4 MHz fOSC = 16 MHz, fCPU = 8 MHz 0.31 0.61 1.22 2.44 0.5 1.0 2.0 4.0 0.22 0.45 0.91 1.82 0.37 0.75 1.5 3 mA Supply current in Slow Wait mode(2) fOSC = 2 MHz, fCPU = 62.5 kHz fOSC = 4 MHz, fCPU = 125 kHz fOSC = 8 MHz, fCPU = 250 kHz fOSC = 16 MHz, fCPU = 500 kHz 36 69 133 260 63 125 250 500 20 40 90 190 40 90 180 350 -40 C < TA < +85 C <1 10 <1 10 -40 C < TA < +125 C <1 50 <1 50 fOSC = 2 MHz fOSC = 4 MHz fOSC = 8 MHz fOSC = 16 MHz 15 28 55 107 20 38 75 200 11 22 43 85 15 30 60 150 Parameter Supply current in Run Conditions mode(2) Supply current in Slow mode(2) (2) IDD Supply current in Halt mode(3) Supply current in Active-halt mode(4) Unit A 1. Data based on characterization results, tested in production at VDD max. and fCPU max. 2. Measurements are done in the following conditions: - Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash is 50%. - All I/O pins in input mode with a static value at VDD or VSS (no load) - All peripherals in reset state - LVD disabled. - Clock input (OSC1) driven by external square wave - In Slow and Slow Wait modes, fCPU is based on fOSC divided by 32 To obtain the total current consumption of the device, add the clock source (Section 12.6.3) and the peripheral power consumption (Section 12.5.4). 3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load), LVD disabled. Data based on characterization results, tested in production at VDD max. and fCPU max. 4. Data based on characterization results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the total current consumption of the device, add the clock source consumption (Section 12.6.3). 146/193 ST72324Bxx Electrical characteristics 12.5.2 Flash current consumption Table 90. Flash current consumption Symbol Parameter Conditions 32 Kbyte Flash 16/8 Kbyte Flash Unit Typ Max(1) Typ Max Supply current in Run mode fOSC = 2 MHz, fCPU = 1 MHz fOSC = 4 MHz, fCPU = 2 MHz fOSC = 8 MHz, fCPU = 4 MHz fOSC = 16 MHz, fCPU = 8 MHz 1.3 2.0 3.6 7.1 3.0 5.0 8.0 15.0 1 1.4 2.4 4.4 2.3 3.5 5.3 7.0 Supply current in Slow mode(2) fOSC = 2 MHz, fCPU = 62.5 kHz fOSC = 4 MHz, fCPU = 125 kHz fOSC = 8 MHz, fCPU = 250 kHz fOSC = 16 MHz, fCPU = 500 kHz 0.6 0.7 0.8 1.1 2.7 3.0 3.6 4.0 0.48 0.53 0.63 0.80 1 1.1 1.2 1.4 Supply current in Wait mode fOSC = 2 MHz, fCPU = 1 MHz fOSC = 4 MHz, fCPU = 2 MHz fOSC = 8 MHz, fCPU = 4 MHz fOSC = 16 MHz, fCPU = 8 MHz 0.8 1.2 2.0 3.5 3.0 4.0 5.0 7.0 0.6 0.9 1.3 2.3 1.8 2.2 2.6 3.6 Supply current in Slow Wait mode(2) 580 fOSC = 2 MHz, fCPU = 62.5 kHz 650 fOSC = 4 MHz, fCPU = 125 kHz 770 fOSC = 8 MHz, fCPU = 250 kHz fOSC = 16 MHz, fCPU = 500 kHz 1050 1200 1300 1800 2000 430 470 530 660 950 1000 1050 1200 (2) (2) IDD Supply current in Halt mode(3) Supply current in Active-halt mode(4) (1) -40C < TA < +85C <1 10 <1 10 -40C < TA < +125C 5 50 <1 50 365 380 410 500 475 500 550 650 315 330 360 460 425 450 500 600 fOSC = 2 MHz fOSC = 4 MHz fOSC = 8 MHz fOSC = 16 MHz mA A 1. Data based on characterization results, tested in production at VDD max. and fCPU max. 2. Measurements are done in the following conditions: - Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash is 50%. - All I/O pins in input mode with a static value at VDD or VSS (no load) - All peripherals in reset state - LVD disabled - Clock input (OSC1) driven by external square wave - In Slow and Slow Wait modes, fCPU is based on fOSC divided by 32 - To obtain the total current consumption of the device, add the clock source (Section 12.6.3) and the peripheral power consumption (Section 12.5.4). 3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load), LVD disabled. Data based on characterization results, tested in production at VDD max. and fCPU max. 4. Data based on characterization results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the total current consumption of the device, add the clock source consumption (Section 12.6.3). 147/193 Electrical characteristics 12.5.3 ST72324Bxx Supply and clock managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current values must be added (except for Halt mode). Table 91. Oscillators, PLL and LVD current consumption Symbol Parameter Conditions Typ IDD(RCINT) Supply current of internal RC oscillator IDD(RES) Supply current of resonator oscillator(1)(2) IDD(PLL) PLL supply current IDD(LVD) LVD supply current Max Unit 625 see Section 12.6.3 on page 150 A 360 VDD = 5V 150 300 1. Data based on characterization results done with the external components specified in Section 12.6.3, not tested in production. 2. As the oscillator is based on a current source, the consumption does not depend on the voltage. 12.5.4 On-chip peripherals . Table 92. On-chip peripherals current consumption Symbol Parameter Conditions IDD(TIM) 16-bit timer supply current(1) IDD(SPI) SPI supply current(2) IDD(SCI) SCI supply current(3) Typ Unit 50 TA = 25 C, fCPU = 4 MHz, VDD = 5.0 V A 400 IDD(ADC) ADC supply current when converting(4) 1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer counter stopped (only TIMD bit set). Data valid for one timer. 2. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent SPI master communication at maximum speed (data sent equal to 55h). This measurement includes the pad toggling consumption. 3. Data based on a differential IDD measurement between SCI low power state (SCID = 1) and a permanent SCI data transmit sequence. 4. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. 148/193 ST72324Bxx 12.6 Electrical characteristics Clock and timing characteristics Subject to general operating conditions for VDD, fCPU, and TA. 12.6.1 General timings Table 93. General timings Symbol Parameter Conditions tc(INST) Instruction cycle time tv(IT) fCPU = 8 MHz Interrupt reaction time tv(IT) = tc(INST) + 10(2) fCPU = 8 MHz Min Typ(1) Max Unit 2 3 12 tCPU 250 375 1500 ns 10 22 tCPU 1.25 2.75 s 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 12.6.2 External clock source Table 94. External clock source Symbol Parameter Conditions Min Typ Max VOSC1H OSC1 input pin high level voltage VDD-1 VDD VOSC1L OSC1 input pin low level voltage VSS VSS+1 tw(OSC1H) OSC1 high or low time(1) tw(OSC1L) tr(OSC1) tf(OSC1) Ilkg See Figure 65. Unit V 5 ns OSC1 rise or fall time(1) 15 OSC1 input leakage current VSS < VIN < VDD 1 A 1. Data based on design simulation and/or technology characteristics, not tested in production. Figure 65. Typical application with an external clock source 90% VOSC1H 10% VOSC1L tr(OSC1) tf(OSC1) OSC2 External clock source tw(OSC1H) tw(OSC1L) Not connected internally fOSC OSC1 Ilkg ST72XXX 149/193 Electrical characteristics 12.6.3 ST72324Bxx Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). 8/16 Kbyte Flash and ROM devices Table 95. Symbol fOSC Crystal and ceramic resonator oscillators (8/16 Kbyte Flash and ROM devices) Parameter Oscillator frequency(1) Conditions LP: low power oscillator MP: medium power oscillator MS: medium speed oscillator HS: high speed oscillator RF Feedback resistor(2) CL1 CL2 Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (RS)(3) RS = 200 RS = 200 RS = 200 RS = 100 OSC2 driving current VDD = 5V, VIN = VSS LP oscillator MP oscillator MS oscillator HS oscillator i2 LP oscillator MP oscillator MS oscillator HS oscillator Min Typ Max Unit 1 >2 >4 >8 2 4 8 16 MHz 20 40 k 22 22 18 15 56 46 33 33 pF 80 160 310 610 150 250 460 910 A 1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value. Refer to crystal/ceramic resonator manufacturer for more details. 2. Data based on characterization results, not tested in production. The relatively low value of the RF resistor, offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the microcontroller is used in tough humidity conditions. 3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25 pF range (typ.) designed for high-frequency applications and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance). 150/193 ST72324Bxx Electrical characteristics Figure 66. Typical application with a crystal or ceramic resonator (8/16 Kbyte Flash and ROM devices) When resonator with integrated capacitors i2 fOSC CL1 OSC1 Resonator CL2 RF OSC2 ST72XXX 32 Kbyte Flash and ROM devices Table 96. Crystal and ceramic resonator oscillators (32 Kbyte Flash and ROM devices) Symbol fOSC Parameter Conditions Oscillator frequency(1) resistor(2) RF Feedback CL1 CL2 Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (RS)(3) fOSC = 1 to 2 MHz fOSC = 2 to 4 MHz fOSC = 4 to 8 MHz fOSC = 8 to 16 MHz OSC2 driving current VDD = 5V, VIN = VSS LP oscillator MP oscillator MS oscillator HS oscillator i2 Min Typ Max Unit 1 16 MHz 20 40 k 20 20 15 15 60 50 35 35 pF 80 160 310 610 150 250 460 910 A 1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value. Refer to crystal/ceramic resonator manufacturer for more details. 2. Data based on characterization results, not tested in production. The relatively low value of the RF resistor, offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the microcontroller is used in tough humidity conditions. 3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5-pF to 25-pF range (typ.) designed for high-frequency applications and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance). 151/193 Electrical characteristics ST72324Bxx Figure 67. Typical application with a crystal or ceramic resonator (32 Kbyte Flash and ROM devices) When resonator with integrated capacitors fOSC CL1 OSC1 Linear amplifier RF CL2 Feedback loop i2 VDD/2 ref Resonator Power down logic OSC2 ST72XXX Table 97. OSCRANGE selection for typical resonators Typical ceramic resonators(1) Supplier fOSC (MHz) Recommended OSCRANGE option bit configuration Reference 2 CSTCC2M00G56A-R0 MP mode(2) 4 CSTCR4M00G55B-R0 MS mode 8 CSTCE8M00G52A-R0 HS mode 16 CSTCE16M0V51A-R0 HS mode Murata 1. Resonator characteristics given by the ceramic resonator manufacturer. 2. LP mode is not recommended for 2 MHz resonator because the peak to peak amplitude is too small (>0.8 V). For more information on these resonators, please consult www.murata.com. 12.6.4 RC oscillators Table 98. Symbol fOSC (RCINT) RC oscillators Parameter Conditions Internal RC oscillator frequency (see Figure 68) TA = 25 C, VDD = 5 V Figure 68. Typical fOSC(RCINT) vs TA fOSC(RCINT) (MHz) 4 Vdd = 5V 3.8 Vdd = 5.5V 3.6 3.4 3.2 3 -45 0 25 TA(C) 152/193 70 130 Min Typ Max Unit 2 3.5 5.6 MHz ST72324Bxx Electrical characteristics Note: To reduce disturbance to the RC oscillator, it is recommended to place decoupling capacitors between VDD and VSS as shown in Figure 87 on page 170. 12.6.5 PLL characteristics Table 99. PLL characteristics Symbol Parameter Conditions fOSC PLL input frequency range fCPU/fCPU Instantaneous PLL jitter(1) Min Typ 2 fOSC = 4 MHz 0.7 Max Unit 4 MHz 2 % 1. Data characterized but not tested The user must take the PLL jitter into account in the application (for example in serial communication or sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the PLL jitter. Figure 69 shows the PLL jitter integrated on application signals in the range 125 kHz to 2 MHz. At frequencies of less than 125 kHz, the jitter is negligible. Figure 69. Integrated PLL jitter vs signal frequency(1) +/-Jitter (%) 1.2 Max 1 Typ 0.8 0.6 0.4 0.2 0 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz Application Frequency 1. Measurement conditions: fCPU = 8 MHz 12.7 Memory characteristics 12.7.1 RAM and hardware registers Table 100. RAM and hardware registers Symbol VRM Parameter Data retention mode(1) Conditions Halt mode (or reset) Min Typ Max 1.6 Unit V 1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under reset) or in hardware registers (only in Halt mode). Not tested in production. 153/193 Electrical characteristics 12.7.2 ST72324Bxx Flash memory Table 101. Dual voltage HDFlash memory Symbol Parameter Conditions 8 Write/Erase mode 1 8 11.4 12.6 VPP Programming voltage(2) 4.5 V < VDD < 5.5 V IDD Supply current(3) Write/Erase IPP VPP current(3) tVPP Internal VPP stabilization time NRW TPROG TERASE Write erase cycles Max(1) 0 Operating frequency Data retention Typ Read mode fCPU tRET Min(1) Unit MHz <10 V A Read (VPP = 12 V) 200 A Write/Erase 30 mA 10 s TA = 85 C 40 TA = 105 C 15 TA = 125 C 7 TA=85 C 100 cycles TA=55 C 1000 cycles Programming or erasing temperature range -40 years 25 85 C 1. Data based on characterization results, not tested in production. 2. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons. 3. Data based on simulation results, not tested in production. 154/193 ST72324Bxx 12.8 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 12.8.1 Functional electromagnetic susceptibility (EMS) Based on a simple running application on the product (toggling two LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results given in Table 102 on page 156 are based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). 155/193 Electrical characteristics ST72324Bxx Table 102. EMS test results Symbol VFESD VFFTB 12.8.2 Parameter Conditions Level/class 32 Kbyte Flash or ROM device: VDD = 5 V, TA = +25 C, fOSC = 8 MHz conforms to IEC 1000-4-2 3B 8 or 16 Kbyte ROM device: Voltage limits to be applied on any I/O pin to VDD = 5 V, TA = +25C, fOSC = 8 MHz induce a functional disturbance conforms to IEC 1000-4-2 4A 8 or 16 Kbyte Flash device: VDD = 5 V, TA = +25 C, fOSC = 8 MHz conforms to IEC 1000-4-2 4B VDD = 5 V, TA = +25 C, fOSC = 8 MHz conforms to IEC 1000-4-4 4A Fast transient voltage burst limits to be applied through 100 pF on VDD and VDD pins to induce a functional disturbance Electromagnetic interference (EMI) Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 103. EMI emissions Symbol SEMI Parameter Conditions VDD = 5 V (2) TA = +25 C Peak level conforming to SAE J 1752/3 Device/package(1) Monitored frequency band 16/8 MHz 0.1 MHz to 30 MHz 12 18 30 MHz to 130 MHz 8/16 Kbyte Flash LQFP32 and LQFP44 130 MHz to 1 GHz 19 25 15 22 SAE EMI Level 3 3.5 0.1 MHz to 30 MHz 13 14 30 MHz to 130 MHz 32 Kbyte Flash LQFP32 and LQFP44 130 MHz to 1 GHz 20 25 16 21 SAE EMI Level 3.0 3.5 0.1 MHz to 30 MHz 12 15 30 MHz to 130 MHz 8/16 Kbyte ROM LQFP32 and LQFP44 130 MHz to 1 GHz 23 26 15 20 SAE EMI Level 3.0 3.5 0.1 MHz to 30 MHz 17 21 30 MHz to 130 MHz 32 Kbyte ROM LQFP32 and LQFP44 130 MHz to 1 GHz 24 30 18 23 3.0 3.5 1. Refer to application note AN1709 for data on other package types. 156/193 Unit 8/4 MHz SAE EMI Level 2. Not tested in production. Max vs [fOSC/fCPU] dBV - dBV - dBV - dBV - ST72324Bxx 12.8.3 Electrical characteristics Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: human body model and machine model. This test conforms to the JESD22-A114A/A115A standard. Table 104. Absolute maximum ratings Symbol Ratings Conditions VESD(HBM) Electrostatic discharge voltage (human body model) VESD(CDM) Electrostatic discharge voltage (charged device model) Maximum value(1) Unit 2000 TA = +25 C V 750 1. Data based on characterization results, not tested in production. Static latch-up LU: two complementary static tests are required on 6 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. Table 105. Electrical sensitivities Symbol LU Parameter Static latch-up class Conditions TA = +25 C TA = +85 C TA = +125 C Test specification Class JESD 78 II level A 157/193 Electrical characteristics ST72324Bxx 12.9 I/O port pin characteristics 12.9.1 General characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Table 106. General characteristics Symbol Parameter Conditions VIL Input low level voltage (standard voltage devices)(1) VIH Input high level voltage(1) Vhys Schmitt trigger voltage hysteresis(2) Min Typ Max Unit 0.3xVDD V 0.7xVDD 0.7 Injected current on I/O pins other than pin PB0(4) 4 IINJ(PIN) (3) Injected current on ROM and 32 Kbyte Flash devices pin PB0 VDD = 5 V Injected current on 8/16 Kbyte Flash devices pin PB0 mA 0 +4 Total injected current (sum of all I/O and control pins) VDD = 5 V 25 Ilkg Input leakage current VSS < VIN < VDD 1 IS Static current consumption induced by each floating input pin Floating input mode(5)(6) RPU Weak pull-up equivalent resistor(7) VIN = VSS, VDD = 5 V CIO I/O pin capacitance IINJ(PIN)(3) A 200 50 120 250 5 time(1) tf(IO)out Output high to low level fall tr(IO)out Output low to high level rise time(1) tw(IT)in External interrupt pulse time(8) mA k pF 25 CL = 50 pF between 10% and 90% ns 25 1 tCPU 1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to the IINJ(PIN) specification. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. Refer to Section 12.2.2 on page 143 for more details. 4. No negative current injection allowed on 8/16 Kbyte Flash devices 5. Static peak current value taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in production. This value depends on VDD and temperature values. 6. The Schmitt trigger that is connected to every I/O port is disabled for analog inputs only when ADON bit is ON and the particular ADC channel is selected (with port configured in input floating mode). When the ADON bit is OFF, static current consumption may result. This can be avoided by keeping the input voltage of this pin close to VDD or VSS. 7. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 71). 8. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source. 158/193 ST72324Bxx Electrical characteristics Figure 70. Unused I/O pins configured as input(1) VDD ST7XXX 10 k 10 k Unused I/O port Unused I/O port ST7XXX 1. I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC robustness and lower cost. Figure 71. Typical IPU vs. VDD with VIN = VSS 90 Ta=1 40C 80 Ta=9 5C 70 Ta=2 5C Ta=-45 C Ipu(uA) 60 50 40 30 20 10 0 2 12.9.2 2.5 3 3.5 4 4.5 Vdd(V) 5 5.5 6 Output driving current Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Table 107. Output driving current Symbol Parameter Conditions Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 72) VOL(1) VOH(2) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 73 and Figure 75) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 74 and Figure 77) VDD = 5V Min Max IIO = +5 mA 1.2 IIO = +2 mA 0.5 IIO = +20 mA TA < 85 C TA > 85 C 1.3 1.5 IIO = +8 mA 0.6 IIO = -5 mA, TA < 85 C TA > 85 C VDD - 1.4 VDD - 1.6 IIO = -2 mA VDD - 0.7 Unit V 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH. 159/193 Electrical characteristics ST72324Bxx Figure 72. Typical VOL at VDD = 5 V (standard ports) 1.4 1.2 Vol (V) at Vdd=5V 1 0.8 0.6 Ta =140C " 0.4 Ta =95C Ta =25C 0.2 Ta =-45 C 0 0 0.005 5 0.01 10 0.015 15 (mA) IIOIio(A) Figure 73. Typical VOL at VDD = 5 V (high-sink ports) 1 0.9 Vol(V) at Vdd=5V 0.8 0.7 0.6 0.5 0.4 Ta= 140 C 0.3 Ta= 95 C 0.2 Ta= 25 C 0.1 Ta= -45C 0 0 0.01 30 20 10 0.02 IIO (mA) Iio(A) 0.03 Figure 74. Typical VOH at VDD = 5 V 5.5 Vdd-Voh (V) at Vdd=5V 5 4.5 4 3.5 V dd= 5V 1 40C m in 3 V dd= 5v 95C m in V dd= 5v 25C m in 2.5 2 V dd= 5v -4 5C m in -10 -0.01 -8 -6 -4 -0.008 -0.006 -0.004 IIO (mA) Iio (A) 160/193 -2 -0.002 0 0 ST72324Bxx Electrical characteristics Figure 75. Typical VOL vs. VDD (standard ports) 1 0.45 Ta= -4 5C 0.9 Ta= 95C 0.7 Ta=2 5C Ta=9 5C 0.35 Ta= 140 C Vol(V) at Iio=2mA Vol(V ) at Iio=5m A 0.8 Ta=-4 5C 0.4 Ta= 25C 0.6 0.5 0.4 0.3 Ta=1 40C 0.3 0.25 0.2 0.15 0.2 0.1 0.1 0.05 0 2 2.5 3 3.5 4 4.5 5 5.5 0 6 2 Vdd(V) 2.5 3 3.5 4 4.5 5 5.5 6 Vdd(V) Figure 76. Typical VOL vs. VDD (high-sink ports) 1 .6 0 .6 Ta = 140 C 1 .4 0 .5 Ta =95 C 1 .2 Ta =25 C Ta =-45C Vol(V ) at Iio=20m A Vol(V ) at Iio=8m A 0 .4 0 .3 0 .2 1 0 .8 0 .6 Ta= 14 0C 0 .4 Ta=9 5C 0 .1 Ta=2 5C 0 .2 Ta=-45 C 0 0 2 2.5 3 3.5 4 4.5 5 5.5 2 6 2.5 3 3.5 4 4.5 5 5.5 6 V dd(V ) V dd (V ) Figure 77. Typical VOH vs. VDD 5.5 6 Ta= -4 5C 5 4.5 Vdd-Voh(V) at Iio=-5mA Vdd-Voh(V) at Iio=-2m A 5 4 3.5 Ta= -4 5C 3 Ta= 25C Ta= 25C Ta= 95C 4 Ta= 140C 3 2 Ta= 95C 2.5 1 Ta= 140C 2 2 2.5 3 3.5 4 Vdd(V) 4.5 5 5.5 6 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vdd(V) 161/193 Electrical characteristics ST72324Bxx 12.10 Control pin characteristics 12.10.1 Asynchronous RESET pin Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Table 108. Asynchronous RESET pin Symbol VIL Parameter Conditions Typ Input low level voltage(1) (1) VIH Input high level voltage Vhys Schmitt trigger voltage hysteresis(2) voltage(3) Output low level IIO Driving current on RESET pin Weak pull-up equivalent resistor tw(RSTL)out Generated reset pulse duration th(RSTL)in External reset pulse hold tg(RSTL)in duration(6) Filtered glitch Max Unit 0.3xVDD V 0.5 V 0.7xVDD VOL RON Min 2.5 VDD = 5 V, IIO = +2 mA 0.2 2 mA VDD = 5V 20 30 120 k Internal reset sources 20 30 42(4) s time(5) 2.5 s 200 ns 1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. 3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 4. Data guaranteed by design, not tested in production. 5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the RESET pin with a duration below th(RSTL)in can be ignored. 6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy environments. 162/193 ST72324Bxx Electrical characteristics RESET pin protection when LVD is enabled When the LVD is enabled, it is recommended to protect the RESET pin as shown in Figure 78 and follow these guidelines: 1. The reset network protects the device against parasitic resets. 2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). 3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section 12.10.1. Otherwise the reset will not be taken into account internally. 4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified for IINJ(RESET) in Section 12.2.2 on page 143. 5. When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pulldown capacitor is recommended to filter noise on the reset line. 6. In case a capacitive power supply is used, it is recommended to connect a 1M ohm pull-down resistor to the RESET pin to discharge any residual voltage induced by this capacitive power supply (this will add 5 A to the power consumption of the MCU). Tips when using the LVD: Check that all recommendations related to reset circuit have been applied (see section above) Check that the power supply is properly decoupled (100 nF + 10 F close to the MCU). Refer to AN1709. If this cannot be done, it is recommended to put a 100 nF + 1 M Ohm pull-down on the RESET pin. The capacitors connected on the RESET pin and also the power supply are key to avoiding any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: Replace 10 nF pull-down on the RESET pin with a 5 F to 20 F capacitor. Figure 78. RESET pin protection when LVD is enabled VDD Recommended Optional (note 6) External reset ST72XXX RON Internal reset Filter 0.01 F 1 M Pulse generator Watchdog LVD reset 163/193 Electrical characteristics ST72324Bxx RESET pin protection when LVD is disabled When the LVD is disabled, it is recommended to protect the RESET pin as shown in Figure 79 and follow these guidelines: 1. The reset network protects the device against parasitic resets. 2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). 3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section 12.10.1. Otherwise the reset will not be taken into account internally. 4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified for IINJ(RESET) in Section 12.2.2 on page 143. Figure 79. RESET pin protection when LVD is disabled VDD ST72XXX VDD 4.7k User external reset circuit RON Internal reset Filter 0.01F Pulse generator Required 164/193 Watchdog ST72324Bxx 12.10.2 Electrical characteristics ICCSEL/VPP pin Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Table 109. ICCSEL/VPP pin Symbol VIL Parameter Conditions Input low level voltage(1) VIH Input high level voltage Ilkg Input leakage current (1) Min Max Flash versions VSS 0.2 ROM versions VSS 0.3 x VDD Flash versions VDD - 0.1 12.6 ROM versions 0.7 x VDD VDD VIN = VSS Unit V 1 A 1. Data based on design simulation and/or technology characteristics, not tested in production. Figure 80. Two typical applications with ICCSEL/VPP pin(1) ICCSEL/VPP VPP Programming tool 10k ST72XXX ST72XXX 1. When ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS. 12.11 Timer peripheral characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). Data based on design simulation and/or characterization results, not tested in production. 12.11.1 16-bit timer Table 110. 16-bit timer Symbol Parameter tw(ICAP)in Input capture pulse time tres(PWM) PWM resolution time fCPU = 8 MHz fEXT Timer external clock frequency fPWM PWM repetition rate ResPWM Conditions Min Max Unit 1 tCPU 2 tCPU 250 ns 0 PWM resolution Typ fCPU/4 MHz 16 bit 165/193 Electrical characteristics ST72324Bxx 12.12 Communication interface characteristics 12.12.1 Serial peripheral interface (SPI) The following characteristics are ubject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. The data is based on design simulation and/or characterization results, not tested in production. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. Refer to the I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Table 111. SPI characteristics Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(SS)(1) th(SS) (1) Parameter SPI clock frequency Conditions Min Max Master fCPU = 8 MHz fCPU/128 = 0.0625 fCPU/4 = 2 Slave fCPU = 8 MHz 0 fCPU/2 = 4 SPI clock rise and fall time Slave tCPU + 50 SS hold time Slave 120 Master Slave 100 90 tsu(MI)(1) tsu(SI)(1) Data input setup time Master Slave 100 100 th(MI)(1) th(SI)(1) Data input hold time Master Slave 100 100 ta(SO)(1) Data output access time Slave 0 tdis(SO)(1) Data output disable time Slave tv(SO) (1) 120 120 Slave (after enable edge) Data output hold time tv(MO)(1) Data output valid time th(MO)(1) Data output hold time 0 120 Master (after enable edge) 0 1. Data based on design simulation and/or characterization results, not tested in production. 2. Depends on fCPU. For example, if fCPU = 8 MHz, then tCPU = 1 / fCPU = 125 ns and tsu(SS) = 175 ns. 166/193 ns 240 Data output valid time th(SO)(1) MHz see I/O port pin description SS setup time(2) tw(SCKH)(1) SCK high and low time tw(SCKL)(1) Unit ST72324Bxx Electrical characteristics Figure 81. SPI slave timing diagram with CPHA = 0(1) SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) MISO OUTPUT See note 2 tdis(SO) tf(SCK) tr(SCK) Bit 6 OUT MSB OUT tsu(SI) th(SO) tv(SO) LSB OUT See note 2 th(SI) MSB IN MOSI INPUT LSB IN Bit 1 IN 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. Figure 82. SPI slave timing diagram with CPHA = 1(1) SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) MISO OUTPUT see note 2 MSB OUT HZ tsu(SI) MOSI INPUT tv(SO) th(SO) Bit 6 OUT tf(SCK) tr(SCK) LSB OUT tdis(SO) see note 2 th(SI) MSB IN Bit 1 IN LSB IN 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 167/193 Electrical characteristics ST72324Bxx Figure 83. SPI master timing diagram(1) SS INPUT tc(SCK) SCK INPUT CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 CPHA = 1 CPOL = 0 CPHA = 1 CPOL = 1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) tsu(MI) MISO INPUT MSB IN BIT6 IN tv(MO) th(MO) MSB OUT MOSI OUTPUT See note 2 LSB IN LSB OUT BIT6 OUT See note 2 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 12.13 10-bit ADC characteristics Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Table 112. 10-bit ADC characteristics Symbol fADC VAREF VAIN Ilkg Parameter ADC clock frequency Analog reference voltage Conversion voltage 0.7*VDD < VAREF < VDD range(1) Input leakage current for analog input(2) RAIN External input impedance CAIN External capacitor on analog input fAIN Variation freq. of analog input signal CADC Internal sample and hold capacitor 168/193 Conditions Min Typ Max Unit 0.4 2 MHz 3.8 VDD VSSA VAREF -40 C < TA < + 85 C Other TA ranges 12 V 250 nA 1 A See figures 84 and 85 k pF Hz pF ST72324Bxx Electrical characteristics Table 112. 10-bit ADC characteristics (continued) Symbol tADC Parameter Conditions Min Typ Max Unit Conversion time (Sample + Hold) fCPU = 8 MHz, Speed = 0, fADC = 2 MHz 7.5 s No. of sample capacitor loading cycles No. of Hold conversion cycles 4 11 1/fADC 1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 2. Injecting negative current on adjacent pins may result in increased leakage currents. Software filtering of the converted analog value is recommended. Figure 84. RAIN max. vs fADC with CAIN = 0 pF(1) 45 Max. R AIN (Kohm) 40 2 MHz 35 30 1 MHz 25 20 15 10 5 0 0 10 30 70 CPARASITIC (pF) 1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced. Figure 85. Recommended CAIN and RAIN values(1) 1000 Cain 10 nF Cain 22 nF Max. R AIN (Kohm) 100 Cain 47 nF 10 1 0.1 0.01 0.1 1 10 fAIN(KHz) 1. This graph shows that, depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and decreased to allow the use of a larger serial resistor (RAIN). Figure 86. Typical A/D converter application VDD RAIN AINx VAIN CAIN ST72XXX VT 0.6 V VT 0.6 V 2 k (max) Ilkg 10-bit A/D conversion CADC 12 pF 169/193 Electrical characteristics 12.13.1 ST72324Bxx Analog power supply and reference pins Depending on the MCU pin count, the package may feature separate VAREF and VSSA analog power supply pins. These pins supply power to the A/D converter cell and function as the high and low reference voltages for the conversion. In some packages, VAREF and VSSA pins are not available (refer to Section 2 on page 15). In this case the analog supply and reference pads are internally bonded to the VDD and VSS pins. Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see Section 12.13.2: General PCB design guidelines). 12.13.2 General PCB design guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. Use separate digital and analog planes. The analog ground plane should be connected to the digital ground plane via a single point on the PCB. Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1F and optionally, if needed 10 pF capacitors as close as possible to the ST7 power supply pins and a 1 to 10 F capacitor close to the power source (see Figure 87). The analog and digital power supplies should be connected in a star network. Do not use a resistor, as VAREF is used as a reference voltage by the A/D converter and any resistance would cause a voltage drop and a loss of accuracy. Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs on the same I/O port as the A/D input being converted. Figure 87. Power supply filtering ST72XXX 1 to 10 F 0.1 F VSS ST7 digital noise filtering VDD VDD Power supply source 0.1 F VAREF External noise filtering VSSA 170/193 ST72324Bxx 12.13.3 Electrical characteristics ADC accuracy Table 113. ADC accuracy Max(1) Parameter Conditions |ET| Total unadjusted error(2) |EO| (2) Offset error |EG| Gain error (2) |ED| Differential linearity error |EL| Integral linearity error(2) (2) VDD = 5 V(2) Symbol CPU in run mode @ fADC 2 MHz Typ ROM and 8/16 Kbyte Flash 32 Kbyte Flash 3 4 6 2 3 5 0.5 3 4.5 1 2 Unit LSB 2 3 1. Data based on characterization results, monitored in production to guarantee 99.73% within max value from -40C to 125 C ( 3 distribution limits). 2. ADC accuracy vs. negative injection current: Injecting negative current may reduce the accuracy of the conversion being performed on another analog input. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 12.9 does not affect the ADC accuracy. Figure 88. ADC accuracy characteristics Digital result ADCDR EG 1023 1022 1021 1LSB IDEAL V -V AREF SSA = -------------------------------------------1024 (2) ET 7 (3) (1) 6 5 4 EO EL 3 ED 2 VSSA ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 1 LSBIDEAL 1 0 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) End point correlation line. 1 2 3 4 5 6 7 1021 1023 VAREF Vin (LSBIDEAL) 171/193 Package characteristics ST72324Bxx 13 Package characteristics 13.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 13.2 Package mechanical data 13.2.1 LQFP44 package mechanical data Figure 89. 44-pin low profile quad flat package outline D D1 A A2 A1 b e E1 E c L1 L h Table 114. 44-pin low profile quad flat package mechanical data inches (1) mm Dim. Min Typ A 172/193 Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.30 C 0.09 Max 0.0630 0.15 0.0020 0.0059 1.40 1.45 0.0531 0.0551 0.0571 0.37 0.45 0.0118 0.0146 0.0177 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 ST72324Bxx Package characteristics Table 114. 44-pin low profile quad flat package mechanical data (continued) inches (1) mm Dim. Min Typ Max Min Typ E1 10.00 0.3937 e 0.80 0.0315 Max 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 Number of pins N 44 1. Values in inches are converted from mm and rounded to 4 decimal digits. 13.2.2 SDIP42 package mechanical data Figure 90. 42-pin plastic dual in-line package, shrink 600-mil width E A2 A1 b2 b A L c E1 e eA eB D E 0.015 GAGE PLANE eC eB Table 115. 42-pin dual in line package mechanical data inches (1) mm Dim. Min Typ A Max Min Typ 5.08 Max 0.2000 A1 0.51 0.0201 A2 3.05 3.81 4.57 0.1201 0.1500 0.1799 b 0.38 0.46 0.56 0.0150 0.0181 0.0220 b2 0.89 1.02 1.14 0.0350 0.0402 0.0449 c 0.23 0.25 0.38 0.0091 0.0098 0.0150 D 36.58 36.83 37.08 1.4402 1.4500 1.4598 173/193 Package characteristics ST72324Bxx Table 115. 42-pin dual in line package mechanical data inches (1) mm Dim. Min E 15.24 E1 12.70 Typ 13.72 Max Min 16.00 0.6000 14.48 0.5000 Typ Max 0.6299 0.5402 e 1.78 0.0701 eA 15.24 0.6000 0.5701 eB 18.54 0.7299 eC 1.52 0.0598 L 2.54 3.30 3.56 0.1000 0.1299 0.1402 Number of pins N 42 1. Values in inches are converted from mm and rounded to 4 decimal digits. 13.2.3 LQFP32 package mechanical data Figure 91. 32-pin low profile quad flat package outline D A D1 A2 A1 e E1 E b c L1 L h Table 116. 32-pin low profile quad flat package mechanical data inches (1) mm Dim. Min Typ A 174/193 Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.30 C 0.09 Max 0.0630 0.15 0.0020 0.0059 1.40 1.45 0.0531 0.0551 0.0571 0.37 0.45 0.0118 0.0146 0.0177 0.20 0.0035 0.0079 D 9.00 0.3543 D1 7.00 0.2756 ST72324Bxx Package characteristics Table 116. 32-pin low profile quad flat package mechanical data (continued) inches (1) mm Dim. Min Typ Max Min Typ E 9.00 0.3543 E1 7.00 0.2756 e 0.80 0.0315 Max 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 Number of pins N 32 1. Values in inches are converted from mm and rounded to 4 decimal digits. 13.2.4 SDIP32 package mechanical data Figure 92. 32-pin plastic dual in-line package, shrink 400-mil width E eC A2 A A1 L E1 C b b2 e eA eB D Table 117. 32-pin dual in-line package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A 3.56 3.76 5.08 0.1402 0.1480 0.2000 A1 0.51 A2 3.05 3.56 4.57 0.1201 0.1402 0.1799 b 0.36 0.46 0.58 0.0142 0.0181 0.0228 b1 0.76 1.02 1.40 0.0299 0.0402 0.0551 C 0.20 0.25 0.36 0.0079 0.0098 0.0142 D 27.43 28.45 1.0799 0.0201 1.1201 175/193 Package characteristics ST72324Bxx Table 117. 32-pin dual in-line package mechanical data (continued) inches(1) mm Dim. Min Typ Max Min Typ Max E 9.91 10.41 11.05 0.3902 0.4098 0.4350 E1 7.62 8.89 9.40 0.3000 0.3500 0.3701 e 1.78 0.0701 eA 10.16 0.4000 eB 12.70 0.5000 eC 1.40 0.0551 L 2.54 3.05 3.81 0.1000 Number of pins N 42 1. Values in inches are converted from mm and rounded to 4 decimal digits. 176/193 0.1201 0.1500 ST72324Bxx 13.3 Package characteristics Thermal characteristics Table 118. Thermal characteristics Symbol RthJA PD TJmax Ratings Value Unit Package thermal resistance (junction to ambient): LQFP44 10x10 LQFP32 7x7 DIP42 600mil SDIP32 200mil 52 70 55 50 C/W Power dissipation(1) 500 mW 150 C (2) Maximum junction temperature 1. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA. The power dissipation of an application can be defined by the user with the formula: PD = PINT + PPORT where PINT is the chip internal power (IDD x VDD) and PPORT is the port power dissipation depending on the ports used in the application. 2. The maximum chip-junction temperature is based on technology characteristics. 177/193 Device configuration and ordering information 14 ST72324Bxx Device configuration and ordering information Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (ROM/FASTROM). ST72324Bxx devices are ROM versions. ST72P324B devices are Factory Advanced Service Technique ROM (FASTROM) versions: They are factory-programmed HDFlash devices. Flash devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code supplied by the customer. This implies that Flash devices have to be configured by the customer using the Option bytes while the ROM devices are factory-configured. Figure 93. ST72324Bxx ordering information scheme Example: ST72 F 324B K 2 B 5 Family ST7 microcontroller family Version F = Flash P = FASTROM Blank = ROM Sub-family 324B No. of pins K = 32 J = 42 or 44 Memory size 2 = 8 Kbytes 4 = 16 Kbytes 6 = 32 Kbytes Package B = DIP 1) M = SO U = DFN Temperature range 1 = 0 to +70 C 5 = -10 to +85 C 6 = -40 to +85 C 7 = -40 to +105 C 3 = -40 to +125 C For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please contact the ST sales office nearest to you. 178/193 ST72324Bxx Device configuration and ordering information 14.1 Flash devices 14.1.1 Flash configuration Table 119. Flash option bytes 5 4 WDG 3 1 VD Res Default 2 HALT SW 1 1 1 Reserved 1 0 0 0 1 1 0 7 PKG1 1 See note 1 6 5 1 4 3 2 1 0 OSCRANGE 1 0 2 1 0 PLLOFF 6 RSTC 7 Static option byte 1 FMP_R Static option byte 0 1 0 0 1 1 1 OSCTYPE 1. Depends on device type as defined in Table 122: Package selection (OPT7) on page 181. The option bytes allow the hardware configuration of the microcontroller to be selected. They have no address in the memory map and can be accessed only in programming mode (for example using a standard ST7 programming tool). The default content of the Flash is fixed to FFh. To program directly the Flash devices using ICP, Flash devices are shipped to customers with the internal RC clock source. In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list). Table 120. Option byte 0 bit description Bit OPT7 Name WDG HALT OPT6 WDG SW OPT5 - OPT4:3 VD[1:0] OPT2:1 - Function Watchdog reset on Halt This option bit determines if a reset is generated when entering Halt mode while the Watchdog is active. 0: No reset generation when entering Halt mode 1: Reset generation when entering Halt mode Hardware or software Watchdog This option bit selects the Watchdog type. 0: Hardware (Watchdog always enabled) 1: Software (Watchdog to be enabled by software) Reserved, must be kept at default value. Voltage detection These option bits enable the voltage detection block (LVD and AVD) with a selected threshold for the LVD and AVD. 00: Selected LVD = Highest threshold (VDD~4V). 01: Selected LVD = Medium threshold (VDD~3.5V). 10: Selected LVD = Lowest threshold (VDD~3V). 11: LVD and AVD off Caution: If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed. For details on the AVD and LVD threshold levels refer to Section 12.4.1 on page 145. Reserved, must be kept at default value 179/193 Device configuration and ordering information ST72324Bxx Table 120. Option byte 0 bit description (continued) Bit OPT0 Name Function FMP_R Flash memory readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected causes the whole user memory to be erased first, afterwhich the device can be reprogrammed. Refer to Section 4.3.1 on page 24 and the ST7 Flash Programming Reference Manual for more details. 0: Readout protection enabled 1: Readout protection disabled Table 121. Option byte 1 bit description Bit OPT7 OPT6 OPT5:4 Name Function PKG1 Pin package selection bit This option bit selects the package (see Table 122). Note: On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. RSTC Reset clock cycle selection This option bit selects the number of CPU cycles applied during the reset phase and when exiting Halt mode. For resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time. 0: Reset phase with 4096 CPU cycles 1: Reset phase with 256 CPU cycles OSCTYPE[1:0] Oscillator type These option bits select the ST7 main clock source type. 00: Clock source = Resonator oscillator 01: Reserved 10: Clock source = Internal RC oscillator 11: Clock source = External source Oscillator range When the resonator oscillator type is selected, these option bits select the resonator oscillator current source corresponding to the frequency range of the used resonator. When the external clock source is OPT3:1 OSCRANGE[2:0] selected, these bits are set to medium power (2 ~ 4 MHz). 000: Typ. frequency range (LP) = 1 ~ 2 MHz 001: Typ. frequency range (MP) = 2 ~ 4 MHz 010: Typ. frequency range (MS) = 4 ~ 8 MHz 011: Typ. frequency range (HS) = 8 ~ 16 MHz 180/193 ST72324Bxx Device configuration and ordering information Table 121. Option byte 1 bit description (continued) Bit OPT0 Name Function PLL OFF PLL activation This option bit activates the PLL which allows multiplication by two of the main input clock frequency. The PLL must not be used with the internal RC oscillator. The PLL is guaranteed only with an input frequency between 2 and 4 MHz. 0: PLL x2 enabled 1: PLL x2 disabled Caution: The PLL can be enabled only if the "OSCRANGE" (OPT3:1) bits are configured to "MP - 2~4 MHz". Otherwise, the device functionality is not guaranteed. Table 122. Package selection (OPT7) Version Selected package PKG1 J LQFP44/SDIP42 1 K LQFP32/SDIP32 0 14.2 ROM devices 14.2.1 Transfer of customer code Customer code is made up of the ROM/FASTROM contents and the list of the selected options (if any). The ROM/FASTROM contents are to be sent with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh. Complete the appended ST72324Bxx MICROCONTROLLER OPTION LIST on page 182 to communicate the selected options to STMicroelectronics. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. Figure 93: ST72324Bxx ordering information scheme on page 178 serves as a guide for ordering. The STMicroelectronics sales organization will be pleased to provide detailed information on contractual points. Caution: The readout protection binary value is inverted between ROM and Flash products. The option byte checksum differs between ROM and Flash. 181/193 Device configuration and ordering information ST72324Bxx ST72324Bxx MICROCONTROLLER OPTION LIST (Last update: March 2009) Customer: ................................... Address: ................................... ................................... Contact: ................................... Phone No: ................................... Reference/ROM Code* : . . . . . . . . . . . . . . . . . . . . . . . . . . . *The ROM code name is assigned by STMicroelectronics. ROM code must be sent in .S19 format. .Hex extension cannot be processed. Device type/memory size/package (check only one option): --------------------------------------------------------------------| ROM DEVICE: 32K --------------------------------------------------------------------LQFP32: | [] DIP32: | [] LQFP44 : | [] DIP42: | [] ----------------------------------------------------------------------DIE FORM: | 32K ----------------------------------------------------------------------32-pin: | [] 44-pin: | [] Conditioning (check only one option): -----------------------------------------------------------------------Packaged product -----------------------------------------------------------------------LQFP: [ ] Tape & reel [ ] Tray DIP: [ ] Tube | | | | | | | | ------------------------------------16K ------------------------------------[] [] [] [] --------------------------------------16K --------------------------------------[] [] | ------------------------------------8K ------------------------------------- | | | | [] [] [] [] -------------------------------------| 8K --------------------------------------| [] | [] | ----------------------------------------------------Die product (dice tested at 25 C only) | ----------------------------------------------------| [ ] Tape & Reel | [ ] Inked wafer | [ ] Sawn wafer on sticky foil Power supply range: [ ] 3.8 to 5.5 V Temp. range (do not check for die product). [] [] [] [] [] 0 C to +70 C -10 C to +85 C -40 C to +85 C -40 C to +105 C -40 C to +125 C Special marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ " (LQFP32 7 char., other pkg. 10 char. max) Authorized characters are letters, digits, '.', '-', '/' and spaces only. Clock source selection: [ ] Resonator: [ ] LP: Low power resonator (1 to 2 MHz) [ ] MP: Medium power resonator (2 to 4 MHz) [ ] MS: Medium speed resonator (4 to 8 MHz) [ ] HS: High speed resonator (8 to 16 MHz) [ ] Internal RC [ ] External clock PLL LVD Reset [ ] Disabled Reset Delay [ ] Disabled [ ] High threshold [ ] 256 Cycles Watchdog selection: Watchdog Reset on Halt: [ ] Software activation [ ] Reset [ ] Hardware activation [ ] No Reset Readout protection: [ ] Disabled [ ] Enabled Date Signature [ ] Enabled [ ] Med. threshold [ ] Low threshold [ ] 4096 Cycles ................................ ................................ Caution: The readout protection binary value is inverted between ROM and Flash products. The option byte checksum will differ between ROM and Flash. 182/193 ST72324Bxx 14.3 Development tools 14.3.1 Introduction Device configuration and ordering information Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 14.3.2 Evaluation tools and starter kits ST offers complete, affordable starter kits and full-featured evaluation boards that allow you to evaluate microcontroller features and quickly start developing ST7 applications. Starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your application. ST evaluation boards are open-design, embedded systems, which are developed and documented to serve as references for your application design. They include sample application software to help you demonstrate, learn about and implement your ST7's features. 14.3.3 Development and debugging tools Application development for ST7 is supported by fully optimizing C Compilers and the ST7 Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated development environments in order to facilitate the debugging and fine-tuning of your application. The Cosmic C Compiler is available in a free version that outputs up to 16 Kbytes of code. The range of hardware tools includes cost effective ST7-DVP3 series emulators. These tools are supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7 integrated development environment (IDE) with high-level language debugger, editor, project manager and integrated programming interface. 14.3.4 Programming tools During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the RLink provide in-circuit programming capability for programming the Flash microcontroller on your application board. ST also provides dedicated a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as ST7 socket boards which provide all the sockets required for programming any of the devices in a specific ST7 subfamily on a platform that can be used with any tool with incircuit programming capability for ST7. For production programming of ST7 devices, ST's third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment. For additional ordering codes for spare parts, accessories and tools available for the ST7 (including from third party manufacturers), refer to the online product selector at www.st.com/mcu. 183/193 Device configuration and ordering information ST72324Bxx Table 123. STMicroelectronics development tools Emulation Supported products ST7 DVP3 series Emulator ST72324BJ, ST72F324BJ ST72324BK, ST72F324BK ST7MDT20DVP3 Programming ST7 EMU3 series Emulator Active probe and TEB ST7MDT20J-EMU3 ST7MDT20J-TEB Connection kit ST7MDT20T44/DVP ICC socket board ST7SB20J/xx(1) ST7MDT20T32/DVP 1. Add suffix /EU, /UK, /US for the power supply of your region. 14.3.5 Socket and emulator adapter information For information on the type of socket that is supplied with the emulator, refer to the suggested list of sockets in Table 124. Note: Before designing the board layout, it is recommended to check the overall dimensions of the socket as they may be greater than the dimensions of the device. For footprint and other mechanical information about these sockets and adapters, refer to the manufacturer's datasheet (www.yamaichi.de for LQFP44 10x10 and www.ironwoodelectronics.com for LQFP32 7x7). Table 124. Suggested list of socket types Device 14.4 Socket (supplied with ST7MDT20J-EMU3) Emulator adapter (supplied with ST7MDT20J-EMU3) LQFP32 7X7 IRONWOOD SF-QFE32SA-L-01 IRONWOOD SK-UGA06/32A-01 LQFP44 10X10 YAMAICHI IC149-044-*52-*5 YAMAICHI ICP-044-5 ST7 Application notes All relevant ST7 application notes can be found on www.st.com. 184/193 ST72324Bxx 15 Known limitations 15.1 All Flash and ROM devices 15.1.1 Safe connection of OSC1/OSC2 pins Known limitations The OSC1 and/or OSC2 pins must not be left unconnected, otherwise the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (> 16 MHz), putting the ST7 in an unsafe/undefined state. Refer to Section 6.3 on page 32. 15.1.2 External interrupt missed To avoid any risk of generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either DDR and OR. Any input signal edge during this period will not be detected and will not generate an interrupt. This case can typically occur if the application refreshes the port configuration registers at intervals during runtime. Workaround The workaround is based on software checking the level on the interrupt pin before and after writing to the PxOR or PxDDR registers. If there is a level change (depending on the sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction with three extra PUSH instructions before executing the interrupt routine (this is to make the call compatible with the IRET instruction at the end of the interrupt service routine). But detection of the level change does not make sure that edge occurs during the critical one cycle duration and the interrupt has been missed. This may lead to occurrence of same interrupt twice (one hardware and another with software call). To avoid this, a semaphore is set to `1' before checking the level change. The semaphore is changed to level '0' inside the interrupt routine. When a level change is detected, the semaphore status is checked and if it is `1' this means that the last interrupt has been missed. In this case, the interrupt routine is invoked with the call instruction. There is another possible case that is, if writing to PxOR or PxDDR is done with global interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to `1' when the level change is detected. Detecting a missed interrupt is done after the global interrupts are enabled (interrupt mask bit reset) and by checking the status of the semaphore. If it is `1' this means that the last interrupt was missed and the interrupt routine is invoked with the call instruction. To implement the workaround, the following software sequence is to be followed for writing into the PxOR/PxDDR registers. The example is for Port PF1 with falling edge interrupt sensitivity. The software sequence is given for both cases (global interrupt disabled/enabled). 185/193 Known limitations ST72324Bxx Case 1: Writing to PxOR or PxDDR with global interrupts enabled: LD A,#01 LD sema,A; set the semaphore to '1' LD A,PFDR AND A,#02 LD X,A; store the level before writing to PxOR/PxDDR LD A,#$90 LD PFDDR,A ; Write to PFDDR LD A,#$ff LD PFOR,A ; Write to PFOR LD A,PFDR AND A,#02 LD Y,A; store the level after writing to PxOR/PxDDR LD A,X; check for falling edge cp A,#02 jrne OUT TNZ Y jrne OUT LD A,sema ; check the semaphore status if edge is detected CP A,#01 jrne OUT call call_routine ; call the interrupt routine OUT:LD A,#00 LD sema,A .call_routine ; entry to call_routine PUSH A PUSH X PUSH CC .ext1_rt ; entry to interrupt routine LD A,#00 LD sema,A IRET Case 2: Writing to PxOR or PxDDR with global interrupts disabled: SIM ; set the interrupt mask LD A,PFDR AND A,#$02 LD X,A ; store the level before writing to PxOR/PxDDR LD A,#$90 LD PFDDR,A ; Write into PFDDR LD A,#$ff LD PFOR,A ; Write to PFOR LD A,PFDR AND A,#$02 LD Y,A ; store the level after writing to PxOR/PxDDR LD A,X ; check for falling edge cp A,#$02 jrne OUT TNZ Y jrne OUT LD A,#$01 LD sema,A ; set the semaphore to '1' if edge is detected 186/193 ST72324Bxx Known limitations RIM ; reset the interrupt mask LD A,sema ; check the semaphore status CP A,#$01 jrne OUT call call_routine ; call the interrupt routine RIM OUT:RIM JP while_loop .call_routine ; entry to call_routine PUSH A PUSH X PUSH CC .ext1_rt ; entry to interrupt routine LD A,#$00 LD sema,A IRET 15.1.3 Unexpected reset fetch If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt controller does not recognize the source of the interrupt and, by default, passes the reset vector address to the CPU. Workaround To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction. 15.1.4 Clearing active interrupts outside interrupt routine When an active interrupt request occurs at the same time as the related flag is being cleared, an unwanted reset may occur. Note: Clearing the related interrupt mask will not generate an unwanted reset. Concurrent interrupt context The symptom does not occur when the interrupts are handled normally, that is, when: The interrupt flag is cleared within its own interrupt routine The interrupt flag is cleared within any interrupt routine The interrupt flag is cleared in any part of the code while this interrupt is disabled If these conditions are not met, the symptom can be avoided by implementing the following sequence: Perform SIM and RIM operation before and after resetting an active interrupt request. Example: - SIM - Reset interrupt flag - RIM 187/193 Known limitations ST72324Bxx Nested interrupt context The symptom does not occur when the interrupts are handled normally, that is, when: The interrupt flag is cleared within its own interrupt routine The interrupt flag is cleared within any interrupt routine with higher or identical priority level The interrupt flag is cleared in any part of the code while this interrupt is disabled If these conditions are not met, the symptom can be avoided by implementing the following sequence: 15.1.5 - PUSH CC - SIM - Reset interrupt flag - POP CC 16-bit timer PWM mode In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on the OLVL1 and OLVL2 settings. 15.1.6 TIMD set simultaneously with OC interrupt If the 16-bit timer is disabled at the same time the output compare event occurs then output compare flag gets locked and cannot be cleared before the timer is enabled again. Impact on the application If output compare interrupt is enabled, then the output compare flag cannot be cleared in the timer interrupt routine. Consequently the interrupt service routine is called repeatedly. Workaround Disable the timer interrupt before disabling the timer. Again while enabling, first enable the timer then the timer interrupts. 15.1.7 Perform the following to disable the timer: - TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt - TACSR I or TBCSR I = 0x40; // Disable the timer Perform the following to enable the timer again: - TACSR & or TBCSR & = ~0x40; // Enable the timer - TACR1 or TBCR1 = 0x40; // Enable the compare interrupt SCI wrong break duration Description A single break character is sent by setting and resetting the SBK bit in the SCICR2 register. In some cases, the break character may have a longer duration than expected: 188/193 20 bits instead of 10 bits if M = 0 22 bits instead of 11 bits if M = 1 ST72324Bxx Known limitations In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin. This may lead to generate one break more than expected. Occurrence The occurrence of the problem is random and proportional to the baud rate. With a transmit frequency of 19200 baud (fCPU = 8MHz and SCIBRR = 0xC9), the wrong break duration occurrence is around 1%. Workaround If this wrong duration is not compliant with the communication protocol in the application, software can request that an Idle line be generated before the break character. In this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. This can be ensured by temporarily disabling interrupts. The exact sequence is: 1. Disable interrupts 2. Reset and set TE (IDLE request) 3. Set and reset SBK (break request) 4. Re-enable interrupts 15.2 8/16 Kbyte Flash devices only 15.2.1 39-pulse ICC entry mode ICC mode entry using ST7 application clock (39 pulses) is not supported. External clock mode must be used (36 pulses). Refer to the ST7 Flash Programming Reference Manual. 15.2.2 Negative current injection on pin PB0 Negative current injection on pin PB0 degrades the performance of the device and is not allowed on this pin. 15.3 8/16 Kbyte ROM devices only 15.3.1 Readout protection with LVD Readout protection is not supported if the LVD is enabled. 15.3.2 I/O Port A and F configuration When using an external quartz crystal or ceramic resonator, a few fOSC2 clock periods may be lost when the signal pattern in Table 125 occurs. This is because this pattern causes the device to enter test mode and return to user mode after a few clock periods. User program execution and I/O status are not changed, only a few clock cycles are lost. This happens with either one of the following configurations PA3 = 0, PF4 = 1, PF1 = 0 while PLL option is disabled and PF0 is toggling PA3 = 0, PF4 = 1, PF1 = 0, PF0 = 1 while PLL option is enabled This is detailed in Table 125. 189/193 Known limitations ST72324Bxx Table 125. Port A and F configuration PLL PA3 PF4 PF1 PF0 Clock disturbance Off 0 1 0 Toggling Maximum 2 clock cycles lost at each rising or falling edge of PF0 On 0 1 0 1 Maximum 1 clock cycle lost out of every 16 As a consequence, for cycle-accurate operations, these configurations are prohibited in either input or output mode. Workaround To avoid this from occurring, it is recommended to connect one of these pins to GND (PF4 or PF0) or VDD (PA3 or PF1). 190/193 ST72324Bxx 16 Revision history Revision history Table 126. Document revision history Date 05-May-2004 30-Mar-2005 12-Sep-2005 06-Feb-2006 Revision 2.0 Changes Merged ST72F324 Flash with ST72324B ROM datasheet. Vt POR max modified in Section 12.4 on page 145 Added Figure 79 on page 164 Modified VAREF min in "10-bit ADC characteristics" on page 168 Modified I INJ for PB0 in Section 12.9 on page 158 Added "Clearing active interrupts outside interrupt routine" on page 187 Modified "32K ROM DEVICES ONLY" on page 165 3 Removed Clock Security System (CSS) throughout document Added notes on ST72F324B 8K/16K Flash devices in Table 27 Corrected MCO description in Section 10.2 on page 69 Modified VtPOR in Section 12.4 on page 145 Static current consumption modified in Section 12.9 on page 158 Updated footnote and Figure 78 on page 163 and Figure 79 on page 164 Modified Soldering information in Section 13.6 Updated Section 14 on page 178 Added Table 27 Modified Figure 8 on page 25 and note 4 in "Flash program memory" on page 23 Added limitation on ICC entry mode with 39 pulses to "Known limitations" on page 185 Added Section 16 on page 166 for ST72F324B 8K/16K Flash devices Modified "Internal Sales Types on box label" in Table 29 on page 157 4 Removed notes related to ST72F324, refer to datasheet rev 3 for specifications on older devices. Note: This datasheet rev refers only to ST72F324B and ST72324B. Changed character transmission procedure in Section on page 112 Updated Vt POR max in Section 12.4 on page 145 Updated Current Consumption for in Section 12.5 on page 146 Added oscillator diagram and table to Section 12.6.3 on page 150 Increased Data retention max. parameter in Section 12.7.2 on page 154 Updated ordering Section 14.3 on page 155 and Section 14.5 on page 157 Updated Development tools Section 14.3 on page 183 Added "external interrupt missed" in Section 15.1 on page 185 5 Added description of SICSR register at address 2Bh in Table 3 on page 20 Changed description on port PF2 to add internal pull-up in Section 9.5.1 on page 63 Highlighted note in SPI "Master mode operation" on page 99 Changed "Static latch-up" on page 157 Added note 5 on analog input static current consumption "General characteristics" on page 158 Updated notes in "Thermal characteristics" on page 177 191/193 Revision history ST72324Bxx Table 126. Document revision history (continued) Date 10-Oct-2007 17-Mar-2009 192/193 Revision Changes 6 Removed references to automotive versions (these are covered by separate ST72324B-Auto datasheet). Changed Flash endurance to 1 Kcycles at 55C Replaced TQFP with LQFP in package outline and device summary on page 1 Figure 1 on page 14: Replaced 60 Kbytes with 32 Kbytes in program memory block Replaced TQFP with LQFP in Figure 2 on page 15, in Figure 4 on page 16 and in Table 2 on page 17 Changed note 3 in Section 9.2.1 on page 58 Changed Section 10.1.3 on page 65 Changed Master mode operation on page 99 Added unit of measure to LVD supply current in Section 12.5.3 on page 148 Replaced TQFP with LQFP in Section 12.8.2 on page 156 Changed note 4 in Section 12.9.1 on page 158 Changed Figure 78 on page 163 Removed EMC protective circuitry in Figure 79 on page 164 (device works correctly without these components) Changed titles of Figure 89 on page 172 and Figure 91 on page 174 Replaced TQFP with LQFP in Section 13.3 on page 177 Changed Section 13.6 on page 171 Replaced TQFP with LQFP in Section 14.1 on page 179, in Table 122 on page 181, in Section Table 122. on page 182 and in Section 14.3.5 on page 184 7 Removed soldering information section. In Section 10.6.3: Functional description on page 129, modified "Starting the conversion" paragraph: added " or a write to any bit of the ADCCSR register". Modified tRET values in Table 101: Dual voltage HDFlash memory on page 154 . Section 13.2: Package mechanical data on page 172 modified (values in inches rounded to 4 decimal digits). Modified Section 12.8.3: Absolute maximum ratings (electrical sensitivity) on page 157 (removed DLU and VESD (MM)). Added Section 13.1: ECOPACK on page 172. Modified "Device configuration and ordering information" on page 178. ST72324Bxx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. 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