NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM 200 pin Unbuffered DDR2 SO-DIMM Based on DDR2-533/667/800 32Mx16/64Mx8 SDRAM B-Die Features * 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) * 32Mx64 and 64Mx64 Unbuffered DDR2 SO-DIMM based on 32Mx16 DDR2 SDRAM B-Die devices. * 128Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx8 DDR2 SDRAM B-Die devices. * Performance: Speed Sort DIMM Latency PC24200 PC25300 PC26400 37B 3C 25C * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: - DIMM Latency: 3, 4, 5 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 13/10/1 Addressing (256MB) 13/10/2 Addressing (512MB) 14/10/2 Addressing (1GB) * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect * Gold contacts * SDRAMs in 84-ball BGA Package (256MB&512MB) * SDRAMs in 60-ball BGA Package (1GB) * RoHS compliance Unit 4 5 5 fCK Clock Frequency 266 333 400 tCK Clock Cycle 3.75 3 2.5 ns fDQ DQ Burst Frequency 533 667 800 MHz MHz * Intended for 266MHz, 333MHz, and 400MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8V 0.1V * SDRAMs have 4 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges Description NT256T64UH4B0FN, NT512T64UH8B0FN, and NT1GT64U8HB0BN are unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as one rank of 32x64 (256MB), two ranks of 64x64 (512MB), and two ranks of 128x64(1GB) high-speed memory array. Modules use four 32Mx16 (256MB) and eight 32Mx16 (512MB) 84-ball BGA packaged devices. Modules use sixteen 64Mx8 (1GB) 60-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a space-saving footprint. The DIMM is intended for use in applications operating of 266MHz/333MHz/400MHz clock speeds and achieves high-speed data transfer rates of 533MHz/667MHz/800MHz. Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.0 06/2006 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Ordering Information Part Number Speed Organization Power Leads 1.8V Gold Note NT256T64UH4B0FN -25C DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 5) 32Mx64 NT256T64UH4B0FN -3C DDR2-667 PC2-5300 333MHz (3ns @ CL = 5) NT256T64UH4B0FN -37B DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4) NT512T64UH8B0FN -25C DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 5) 64Mx64 NT512T64UH8B0FN -3C DDR2-667 PC2-5300 333MHz (3ns @ CL = 5) NT512T64UH8B0FN -37B DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4) NT1GT64U8HB0BN -25C DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 5) NT1GT64U8HB0BN -3C DDR2-667 PC2-5300 333MHz (3ns @ CL = 5) NT1GT64U8HB0BN -37B DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4) REV 1.0 06/2006 128Mx64 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Pin Description CK0, CK1, , Differential Clock Inputs CKE0, CKE1 DQ0-DQ63 Clock Enable DQS0-DQS7 Row Address Strobe Bidirectional data strobes - Column Address Strobe Differential data strobes DM0-DM7 Write Enable , Data input/output Chip Selects Input Data Masks VDD Power (1.8V) VREF Ref. Voltage for SSTL_18 inputs A0-A13 Row Address Inputs A0-A9 Column Address Inputs VSS Column Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output ODT0, ODT1 Active termination control lines SA0, SA1 A10/AP NC VDDSPD Serial EEPROM positive power supply Ground Serial Presence Detect Address Inputs No Connect Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47 5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 9 VSS 10 DM0 59 VSS 60 VSS 109 12 VSS 61 DQ24 62 DQ28 111 DQS0 14 DQ6 63 DQ25 64 DQ29 113 15 VSS 16 DQ7 65 VSS 66 VSS 115 17 DQ2 18 VSS 67 DM3 68 19 DQ3 20 DQ12 69 NC 70 21 VSS 22 DQ13 71 VSS 72 23 DQ8 24 VSS 73 DQ26 25 DQ9 26 DM1 75 DQ27 27 VSS 28 VSS 77 30 CK0 11 13 29 31 VSS 156 VSS DQ48 158 DQ52 DQ53 159 DQ49 160 112 VDD 161 VSS 162 VSS 114 ODT0 163 NC 164 CK1 116 A13 165 VSS 118 VDD 167 117 VDD DQS3 119 ODT1 120 NC 169 VSS 121 VSS 122 VSS 171 74 DQ30 123 DQ32 124 DQ36 76 DQ31 125 DQ33 126 DQ37 VSS 78 VSS 127 VSS 128 VSS 79 CKE0 80 CKE1 129 81 VDD 82 VDD 131 166 168 VSS DQS6 170 DM6 VSS 172 VSS 173 DQ50 174 DQ54 175 DQ51 176 DQ55 177 VSS 178 VSS 130 DM4 179 DQ56 180 DQ60 DQS4 132 VSS 181 DQ57 182 DQ61 133 VSS 134 DQ38 183 VSS 184 VSS 135 DQ34 136 DQ39 185 DM7 186 VDD 137 DQ35 138 VSS 187 VSS 188 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63 96 VDD 145 VSS 146 195 SDA 196 VSS A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1 DQS1 32 33 VSS 34 VSS 83 NC 84 NC 35 DQ10 36 DQ14 85 NC 86 NC 37 DQ11 38 DQ15 87 VDD 88 39 VSS 40 VSS 89 A12 41 VSS 42 VSS 91 A9 43 DQ16 44 DQ20 93 A8 45 DQ17 46 DQ21 95 VDD 47 VSS 48 VSS 97 50 NC 99 49 110 VDD 155 157 DQS7 Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.0 06/2006 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Input/Output Functional Description Symbol Type Polarity Function CK0, CK1 (SSTL) The positive line of the differential pair of system clock inputs which drives the input to the Positive on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the rising Edge edge of their associated clocks. , (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to the Edge on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, to be executed by the SDRAM. , , VREF Supply , , define the operation Reference voltage for SSTL-18 inputs ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. A0 - A9 A10/AP A11, A13 (SSTL) - DQ0 - DQ63 (SSTL) Active High VDD, VSS Supply DQS0 - DQS7 - (SSTL) DM0 - DM7 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Power and ground for the DDR2 SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. VDDSPD REV 1.0 06/2006 Supply Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Functional Block Diagram (256MB - 1 Rank, 32Mx16 DDR2 SDRAMs) ( / , = < ( > ? / , ( = < > ? ( / , = < > ? ; / (/ ( . . . . ./ ., .= .< ; / , = < > ? ( . . . . ./ ., .= .< 6 6 ( .> .? . . . . . / . , , (, / / / / // /, /= /< 6 6 ( .> .? . . . . . / . , ( . . . . ./ ., .= .< = (= /> /? , , , , ,/ ,, ( . . . . ./ ., .= .< 6 6 ( .> .? . . . . . / . , < (< ,= ,< ,> ,? = = = = 6 6 ( .> .? . . . . . / . , ; ; 4 (% 4 4 4 4 / 5 5 REV 1.0 06/2006 ) (% " % (% (% ) " % (% !! !" #$ # %& ' #$% ( ) #" %$*% # %%$" ( %%#" % + ,- .$ % %# *&" &#" % 0!" " 1& 2 34 .65 0. 734 8 70 34 % "# 9: #" 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Functional Block Diagram (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) REV 1.0 06/2006 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Functional Block Diagram (1GB - 2 Ranks, 64Mx8 DDR2 SDRAMs) / (/ ( . . . . ./ ., .= .< / , = < ( . . . . ./ ., .= .< / , = < > ? > ( . . . . ./ ., .= .< / ( . . . . ./ ., .= .< , ( . . . . ./ ., .= .< = ( . . . . ./ ., .= .< / < ( . . . . ./ ., .= .< , , (, ( . . . . ./ ., .= .< > ? / , ( . . . . ./ ., .= .< / / / / // /, /= /< ? ( . . . . ./ ., .= .< = ( (= ( . . . . ./ ., .= .< = < > ? ( . . . . ./ ., .= .< /> /? , , , , ,/ ,, ( . . . . ./ ., .= .< < ( (< ( . . . . ./ ., .= .< / , = < > ? ; ; ( . . . . ./ ., .= .< ; ; 4 4 4 4 4 ) ) . 5 . 5 7"# % 4 REV 1.0 06/2006 ) 4 ) 4 . 54 . 54 ,= ,< ,> ,? = = = = (% , (% , (% , (% , (% , (% < (% > , (% < (% > , ( . . . . ./ ., .= .< # *4 % ,2 , ,2 7"# / 2 #" . ' &$ #$ '# ( ) #" %$*% # % %$" %%#" % .$ % + ,/ ; @2 @2 2 2 %%#" % , .$ %+ ,, %% &" #" %%#" % .$ % + ,- 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Serial Presence Detect (256MB - 1 Rank, 32Mx16 DDR2 SDRAMs) (Part 1 of 2) Byte SPD Entry Value Description -37B -3C -25C Serial PD Data Entry (Hex.) Note -37B -3C 128 80 256 08 -25C 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of DIMM Ranks, Package, and Height 6 Data Width of Assembly 7 Reserved 8 Voltage Interface Level of this Assembly 9 DDR2 SDRAM Device Cycle Time at CL=5 3.75ns 3ns 2.5ns 3D 30 25 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 0.5ns 0.45ns 0.40ns 50 45 40 11 DIMM Configuration Type Non-Parity 00 12 Refresh Rate/Type 7.8As/self 82 13 Primary DDR2 SDRAM Width X16 10 14 Error Checking DDR2 SDRAM Device Width N/A 00 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 DDR2 SDRAM Device Attributes: Number of Device Banks 18 DDR2 SDRAM Device Attributes: 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes DDR2-SDRAM 08 13 0D 10 0A 1 rank, Height=30mm 60 X64 40 Undefined 00 SSTL_1.8V 05 Undefined 00 4,8 0C 4 04 3,4,5 38 <3.80mm 01 SODIMM (67.6mm) 04 Normal DIMM 00 Support weak driver, 50 ODT, and PASR 07 Latencies Supported 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 3.75ns 3D 24 Maximum Data Access Time from Clock at CL=4 0.5ns 50 25 Minimum Clock Cycle Time at CL=3 5ns 50 26 Maximum Data Access Time from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum 30 Minimum Active to Precharge Time (tRAS) 31 Module Rank Density 32 Address and Command Setup Time Before Clock (tIS) 0.25ns 0.175ns 25 20 17 33 Address and Command Hold Time After Clock (tIH) 0.375ns 0.275ns 0.25ns 37 27 25 34 Data Input Setup Time Before Clock (tDS) 0.10ns 0.05ns 10 10 05 35 Data Input Hold Time After Clock (tDH) 0.225ns 0.175ns 0.125ns 22 17 12 36 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Reserved Undefined 00 40 12.5ns 3C 10ns delay (tRCD) Extension of Byte 41 tRC and Byte 42 tRFC REV 1.0 06/2006 to 15ns 15ns 32 28 12.5ns 3C 32 45ns 2D 256MB 40 0.2ns 0.10ns 00: The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 30: The number below a decimal point of tRC is 5, tRFC is less than 256ns. 00 30 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Serial Presence Detect (256MB - 1 Rank, 32Mx16 DDR2 SDRAMs) (Part 2 of 2) Byte SPD Entry Value Description -37B -3C -37B -25C Minimum Core Cycle Time (tRC) 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 43 Maximum Clock Cycle Time (tCK) 8.0ns 44 Max. DQS-DQ Skew Factor (tQHS) 0.30ns 0.24ns 0.20ns 1E 18 14 45 Read Data Hold Skew Factor (tQHS) 0.40ns 0.34ns 0.30ns 28 22 1E 46 PLL Relock Time 47 Tcasemax DT4R4W Delta 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 7.85C 8.41C 9.42C 47 4F 5F 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 4.48C 5.61C 5.72C 2D 39 3A 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 4.82C 5.61C 6.73C 21 26 2D 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 3.14C 3.7C 4.37C 3F 4A 58 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 12.33C 14.57C 17.38C 3E 4A 58 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 16.82C 17.94C 19.62C 22 24 28 57 DRAM Case Temperature Rise from Ambient due to Bank 17.94C Interleave Reads with Auto-Precharge (DT7) 19.06C 24 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Reversion 63 Checksum for Byte 0-62 95C 0C Module Manufacturing Location Reserved Module part number: NT256T64UH4B0FN-37B NT256T64UH4B0FN-3C NT256T64UH4B0FN-25C REV 1.0 06/2006 39 80 00 95C 0C 50 59C/W 53 50 76 0.78C 35 1.01C 29 1.2 72 92-255 95C 1.2C Note 69 Checksum Data Manufacturer's JEDEC ID Code Note: 1. 3C N/A 64-71 Module Part number 57.5ns -3C 41 73-91 60ns -25C Serial PD Data Entry (Hex.) 27 12 08 FC 17 NANYA 7F7F7F0B00000000 Manufacturing code -- Module Part Number in ASCII -- undefined -- 1 4E543235365436345548344230464E2D333742 4E543235365436345548344230464E2D334320 4E543235365436345548344230464E2D323543 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Serial Presence Detect (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) (Part 1 of 2) Byte SPD Entry Value Description -3C -37B 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 -25C Serial PD Data Entry (Hexadecimal) -37B -3C 128 80 256 08 DDR2-SDRAM 08 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Rank, Package, and Height 2 rank, Height=30mm 61 6 Data Width of this Assembly 7 Reserved 8 Voltage Interface Level of this Assembly 9 DDR2 SDRAM Device Cycle Time at CL=5 3.75ns 10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.5ns 11 DIMM Configuration Type Non-Parity 00 12 Refresh Rate/Type 7.8As/self 82 13 Primary DDR2 SDRAM Width X16 10 14 Error Checking DDR2 SDRAM Device Width NA 00 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 DDR2 SDRAM Device Attributes: Number of Device Banks 18 DDR2 SDRAM Device Attributes: 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes X64 40 Undefined 00 SSTL_1.8V -25C 05 3 ns 2.5ns 3D 30 25 0.45ns 0.40ns 50 45 40 Undefined 00 4,8 0C 4 04 3,4,5 38 Latencies Supported <3.80mm 01 SODIMM (67.6mm) 04 Normal DIMM 00 Support weak driver, 50 ODT, and PASR 07 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 3.75ns 3D 24 Maximum Data Access Time from Clock at CL=4 0.5ns 50 25 Minimum Clock Cycle Time at CL=3 5ns 50 26 Maximum Data Access Time from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum RAS to CAS delay (tRCD) 30 Minimum RAS Pulse Width (tRAS) 31 Module Bank Density per Rank 32 Address and Command Setup Time Before Clock (tIS) 0.25ns 0.2ns 0.175ns 25 20 17 33 Address and Command Hold Time After Clock (tIH) 0.375ns 0.275ns 0.25ns 37 27 25 34 Data Input Setup Time Before Clock (tDS) 0.1ns 0.1 ns 0.05ns 10 10 05 35 Data Input Hold Time After Clock (tDH) 0.175ns 0.125ns 22 17 12 36 Write Recovery Time (tWR) 15ns 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Reserved Undefined 00 40 15ns REV 1.0 3C 12.5ns 3C 32 2D 256MB 0.225ns 32 28 45ns 40 00: The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 30: The number below a decimal point of tRC is 5, tRFC is less than 256ns. Extension of Byte 41 tRC and Byte 42 tRFC 06/2006 12.5ns 10ns 15ns Note 3C 00 30 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Serial Presence Detect (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) (Part 2 of 2) Byte SPD Entry Value Description -37B -3C 60ns -25C Serial PD Data Entry (Hexadecimal) -37B 57.5ns -3C 41 Minimum Core Cycle Time (tRC) 3C 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 39 44 Max. DQS-DQ Skew Factor (tDQS) 0.30ns 0.24ns 0.20ns 1E 18 14 45 Read Data Hold Skew Factor (tQHS) 0.40ns 0.34ns 0.30ns 28 22 1E 46 PLL Relock Time 47 Tcasemax DT4R4W Delta 95C 0C 95C 1.2C 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 7.85C 8.41C 9.42C 47 4F 5F 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 4.48C 5.61C 5.72C 2D 39 3A 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 4.82C 5.61C 6.73C 21 26 2D 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 3.14C 3.7C 4.37C 3F 4A 58 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 1.01C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 12.33C 14.57C 17.38C 3E 4A 58 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 16.82C 17.94C 19.62C 22 24 28 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 17.94C 24 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum for Byte 0-62 105ns 69 8ns 80 N/A 00 95C 0C 50 59C/W 53 50 76 0.78C 35 19.06C 29 1.2 Checksum Data 27 12 09 FD 18 64-71 Manufacturer's JEDEC ID Code NANYA 7F7F7F0B00000000 72 Module Manufacturing Location Manufacturing code -- 73-91 Module Part number 92-255 Reserved Note: 1. Module part number: NT512T64UH8A0FN-37B NT512T64UH8A0FN-3C NT512T64UH8A0FN-25C REV 1.0 06/2006 Note -25C Module Part Number in ASCII -- Undefined -- 1 4E543531325436345548384230464E2D333742 4E543531325436345548384230464E2D334320 4E543531325436345548384230464E2D323543 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Serial Presence Detect (1GB - 2 Ranks, 64Mx8 DDR2 SDRAMs) (Part 1 of 2) Byte SPD Entry Value Description -37B -3C -25C Serial PD Data Entry (Hexadecimal) -37B -3C 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of DIMM Ranks 6 Data Width of Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8 9 DDR2 SDRAM Device Cycle Time at CL=5 3.75ns 3ns 2.5ns 3D 30 25 10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.50ns 0.45ns 0.40ns 50 45 40 11 DIMM Configuration Type Non-Parity 00 12 Refresh Rate/Type 7.8us/self 82 13 Primary DDR2 SDRAM Width X8 08 14 Error Checking DDR2 SDRAM Device Width NA 00 15 Reserved Undefined 00 16 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 3/4/5 38 19 DIMM Mechanical Characteristics <4.10mm 01 20 DDR2 SDRAM DIMM Type Information Regular SODIMM (67.6mm) 04 21 DDR2 SDRAM Module Attributes: Normal DIMM 00 Support weak driver, 50 ODT, and PASR 07 3D DDR2-SDRAM 08 14 0E 10 0A 2 rank, Height = 30mm 61 05 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 3.75ns 24 Maximum Data Access Time from Clock at CL=4 0.5ns 50 25 Minimum Clock Cycle Time at CL=3 5ns 50 26 Maximum Data Access Time from Clock at CL=3 27 Minimum Row Precharge Time (tRP) 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum RAS to CAS delay (tRCD) 30 Minimum RAS Pulse Width (tRAS) 31 Module Bank Density 32 Address and Command Setup Time Before Clock (tIS) 0.25ns 0.20ns 0.175ns 25 20 17 33 Address and Command Hold Time After Clock (tIH) 0.375ns 0.275ns 0.25ns 37 27 25 34 Data Input Setup Time Before Clock (tDS) 0.10ns 0.05ns 10 10 05 35 Data Input Hold Time After Clock (tDH) 0.225ns 0.175ns 0.125ns 22 17 12 36 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5 ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Reserved Undefined 00 40 Extension of Byte 41 tRC and Byte 42 tRFC REV 1.0 06/2006 0.6ns 15ns 60 12.5ns 3C 12.5ns 3C 7.5ns 15ns 32 1E 45ns 32 2D 512MB 0.10ns Note -25C 80 00: The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 30: The number below a decimal point of tRC is 5, tRFC is less than 256ns. 00 30 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Serial Presence Detect (1GB - 2 Ranks, 64Mx8 DDR2 SDRAMs) (Part 2 of 2) Byte SPD Entry Value Description -37B -3C -25C -37B 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.30ns 0.24ns 0.20ns 1E 18 14 45 Read Data Hold Skew Factor (tQHS) 0.40ns 0.34ns 0.30ns 28 22 1E 46 PLL Relock Time 47 Tcasemax DT4R4W Delta 95C 0C 95C 1.2C 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 8.11C 8.69C 9.74C 4B 53 63 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 4.64C 5.8C 5.91C 2F 3A 3C 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 0.81C 52 DRAM Case Temperature Rise from Ambient due to Active 4.98C Standby (DT3N) 5.8C 6.95C 22 27 2F 53 DRAM Case Temperature Rise from Ambient due to Active 3.25C Power-Down with Fast PDN Exit (DT3P fast) 3.82C 4.52C 41 4D 5B 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 1.04C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 12.75C 15.07C 17.96C 40 4C 5C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 17.39C 18.54C 20.28C 23 26 29 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 18.54C 26 28 28 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 1.2 12 63 Checksum for Byte 0-62 Checksum Data 64-71 Manufacturer's JEDEC ID Code NANYA 7F7F7F0B00000000 105ns REV 1.0 00 95C 0C 50 61C/W 53 50 7A 37 2A 19.7C 4D 41 Manufacturing code -- Module Part Number in ASCII -- Undefined -- 92-255 Reserved 06/2006 80 N/A 19.7C 39 69 8ns Module Manufacturing Location Note: 1. Module PN: NT1GT64U8HB0BN-37B NT1GT64U8HB0BN-3C NT1GT64U8HB0BN-25C 3C Note -25C Minimum Core Cycle Time (tRC) 73-91 Module Part Number 57.5ns -3C 41 72 60ns Serial PD Data Entry (Hexadecimal) 5F 1 4E5431475436345538484230424E2D33374220 4E5431475436345538484230424E2D33432020 4E5431475436345538484230424E2D32354320 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Environmental Requirements Symbol Rating Units Operating Temperature (ambient) 0 to 65 C HOPR Operating Humidity (relative) 10 to 90 % TSTG Storage Temperature -50 to 100 C HSTG Storage Humidity (without condensation) 5 to 95 % 105 to 69 kPa TOPR Parameter Barometric pressure (operating & storage) up to 9850ft. Note: Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Absolute Maximum DC Ratings Symbol Rating Units Voltage on VDD pins relative to Vss -1.0 to +2.3 V VDDQ Voltage on VDDQ pins relative to Vss -0.5 to +2.3 V VDDL Voltage on VDDL pins relative to Vss -0.5 to +2.3 V VDD VIN, VOUT TSTG Parameter Voltage on I/O pins relative to Vss -0.5 to +2.3 V Storage Temperature (Plastic) -55 to +100 C Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage temperature is the case surface temperature on the center/top side of the DRAM. Operating temperature Conditions Symbol TCASE Note: 1. 2. Parameter Operating Temperature (Ambient) Rating Units Note 0 to 95 C 1 Case temperature is measured at top and center side of any DRAMs. tCASE > 85C tREFI = 3.9 As DC Electrical Characteristics and Operating Conditions Symbol Parameter Min Max Units Notes VDD Supply Voltage 1.7 1.9 V 1 VDDL DLL Supply Voltage 1.7 1.9 V 1 VDDQ Output Supply Voltage 1.7 1.9 V 1 0 0 V 0.49VDDQ 0.51VDDQ V 1, 2 VREF - 0.04 VREF + 0.04 V 3 VSS, VSSQ VREF VTT Supply Voltage, I/O Supply Voltage Input Reference Voltage Termination Voltage Note: 1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However, VDDQ must be less than or equal to VDD under all conditions. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device. REV 1.0 06/2006 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM ODT DC Electrical Characteristics Parameter/Condition Symbol Min. Nom. Max. Units Note Rtt effective impedance value for EMRS(A6,A2)=0,1; 75ohm Rtt1(eff) 60 75 90 ohm 1 Rtt effective impedance value for EMRS(A6,A2)=1,0; 150ohm Rtt2(eff) 120 150 180 ohm 1 Rtt effective impedance value for EMRS(A6,A2)=1,1; 50ohm Rtt3(eff) 40 50 60 ohm 1 Deviation of VM with respect to VDDQ/2 Delta VM -6 +6 % 1 Note1: Test condition for Rtt measurements. Input AC/DC logic level Symbol Parameter VIH (AC) Input High (Logic1) Voltage VIL (AC) Input Low (Logic0) Voltage VIH (DC) Input High (Logic1) Voltage VIL (DC) Input Low (Logic0) Voltage REV 1.0 06/2006 DDR2-533 DDR2-667 DDR-800 Units Min. Max. Min. Max. Min. Max. VREF + 0.250 - VREF + 0.200 - VREF + 0.200 - V - VREF 0.250 - VREF 0.200 - VREF 0.200 V VREF + 0.125 VDDQ + 0.3 VREF + 0.125 VDDQ + 0.3 VREF + 0.125 VDDQ + 0.3 V -0.3 VREF 0.125 -0.3 VREF 0.125 -0.3 VREF 0.125 V 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) PC2-4300 PC2-5300 PC2-6400 (-37B) (-3C) (-25C) Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 280 300 336 mA Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 320 360 400 mA IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 28 28 28 mA IDD2Q Precharge quiet standby current 140 160 180 mA IDD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 160 200 204 mA IDD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=0 112 132 156 mA IDD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=1 36 36 36 mA IDD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 172 200 240 mA IDD4R Operating Current: one bank; Burst = 4; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA 440 520 620 mA Operating Current: one bank; Burst = 4; writes; continuous burst; address IDD4W and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) 440 560 620 mA Symbol Parameter/Condition IDD0 IDD1 Unit IDD5B Burst Refresh Current: tRFC = tRFC (MIN) 600 640 580 mA IDD5D Distributed Refresh Current: tRFC = tREF 36 36 36 mA Self-Refresh Current: CKE 0.2V 28 28 28 mA 680 mA IDD6 Operating Current: four bank; four bank interleaving with BL = 4, address 640 680 IDD7 and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 06/2006 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (512MB, 2 Ranks, 32Mx16 DDR2 SDRAMs) PC2-4300 PC2-5300 PC2-6400 (-37B) (-3C) (-25C) Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 452 500 576 mA Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 492 560 640 mA IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 56 56 56 mA IDD2Q Precharge quiet standby current 280 320 360 mA IDD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 320 400 408 mA IDD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=0 224 264 312 mA IDD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=1 72 72 72 mA IDD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 344 400 480 mA IDD4R Operating Current: one bank; Burst = 4; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA 612 720 860 mA Operating Current: one bank; Burst = 4; writes; continuous burst; address IDD4W and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) 612 760 860 mA Symbol Parameter/Condition IDD0 IDD1 Unit IDD5B Burst Refresh Current: tRC = tRFC (MIN) 772 840 820 mA IDD5D Distributed Refresh Current: tRFC = tREF 476 596 656 mA Self-Refresh Current: CKE 0.2V 56 56 56 mA 920 mA IDD6 Operating Current: four bank; four bank interleaving with BL = 4, address 812 880 IDD7 and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 06/2006 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) PC2-4300 PC2-5300 PC2-6400 (-37B) (-3C) (-25C) Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 840 920 1032 mA Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 920 1040 1160 mA IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 112 112 112 mA IDD2Q Precharge quiet standby current 560 640 720 mA IDD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 640 800 816 mA IDD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=0 448 528 624 mA IDD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=1 144 144 144 mA IDD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 344 400 480 mA IDD4R Operating Current: one bank; Burst = 4; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA 1160 1360 1600 mA Operating Current: one bank; Burst = 4; writes; continuous burst; address IDD4W and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) 1160 1440 1600 mA Symbol Parameter/Condition IDD0 IDD1 Unit IDD5B Burst Refresh Current: tRC = tRFC (MIN) 1544 1680 1640 mA IDD5D Distributed Refresh Current: tRFC = tREF 952 1192 1312 mA Self-Refresh Current: CKE 0.2V 112 112 112 mA 1720 mA IDD6 Operating Current: four bank; four bank interleaving with BL = 4, address 1560 1680 IDD7 and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 06/2006 18 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol -37B Parameter -3C -25C Unit Min. Max. Min. Max. Min. Max. DQ output access time from CK/ -0.5 +0.5 -0.45 +0.45 -0.4 +0.4 ns DQS output access time from CK/ -0.45 +0.45 -0.4 +0.4 -0.35 +0.35 ns tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCL CK low-level width 0.45 tAC tDQSCK 0.55 0.45 0.55 0.45 0.55 tCK tCH or tCL - tCH or tCL - tCH or tCL - tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCK Clock Cycle Time 3.75 8 3 8 2.5 8 ns tDH DQ and DM input hold time 225 - 175 - 125 - ps tDS DQ and DM input setup time 100 - 100 - 50 - ps tIPW Input pulse width 0.6 - 0.6 - 0.6 - tCK DQ and DM input pulse width (each input) 0.35 - 0.35 - 0.35 - tCK tAC max - tAC max - tDIPW tHZ Data-out high-impedance time from CK/ - tAC max ns tLZ(DQ) Data-out low-impedance time from CK/ 2tAC min tAC max 2tAC min tAC max 2tAC min tAC max ns tLZ(DQS) DQS low-impedance time from CK/ tAC min tAC max tAC max ns - 0.30 - 0.2 ns - tDQSQ DQS-DQ skew (DQS & associated DQ signals) - 0.24 0.4 - 0.34 - 0.3 ns Data output hold time from DQS tHP tQHS - tHP tQHS - tHP tQHS - ns Write command to 1st DQS latching transition -0.25 0.25 -0.25 0.25 -0.25 0.25 tCK tDQSH DQS input high pulse width 0.35 - 0.35 - 0.35 - tCK tDQSL DQS input low pulse width 0.35 - 0.35 - 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - 0.2 - tCK tMRD Mode register set command cycle time 2 - 2 - 2 - tCK tQHS tQH tDQSS Data hold Skew Factor tAC min tAC max tAC min tWPST Write postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK tWPRE Write preamble 0.35 - 0.35 - 0.35 - tCK tIH Address and control input hold time 0.375 - 0.275 - 0.250 ns tIS Address and control input setup time 0.25 - 0.2 - 0.175 ns tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.4 0.6 0.4 0.6 tCK - tIS + tCK + tIH - ns tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tRFC Refresh to active/Refresh command time REV 1.0 06/2006 tIS + tCK + tIH 105 - tIS + tCK + tIH 105 105 Notes ns 19 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol tREFI tRRD tCCD -37B Parameter Min. -3C Max. Min. -25C Max. Min. Max. Unit Average Periodic Refresh Interval (85C < TCASE B 95C) 3.9 3.9 3.9 As Average Periodic Refresh Interval (0C B TCASE B 85C) 7.8 7.8 7.8 As Active bank A to Active bank B command to tWR Write recovery time WR Write recovery time with Auto-Precharge 7.5 - 7.5 - 7.5 - ns 2 - 2 - 2 - tCK 15 - 15 - 15 - ns tWR/tCK tWR/tCK tWR/tCK - WR +tRP - WR +tRP - tCK 7.5 - 7.5 - ns ns tDAL Auto precharge write recovery + precharge time WR +tRP tWTR Internal write to read command delay 7.5 - tRTP Internal read to precharge command delay 7.5 - 7.5 - 7.5 - ns tXSNR Exit self refresh to a Non-read command tRFC +10 - tRFC +10 - tRFC +10 - ns tXSRD Exit self refresh to a Read command 200 - 200 - 200 - tCK Exit precharge power down to any Non- read command 2 - 2 - 2 - tCK tXARD Exit active power down to read command 2 - 2 - 2 - tCK tXARDS Exit active power down to read command 6-AL - 7-AL - 8-AL - tCK tXP Notes tCKE CKE minimum pulse width 3 - 3 - 3 - tCK tOIT OCD drive mode output delay 0 12 0 12 0 12 ns 2 2 2 2 2 tCK tAC(max) ns ODT tAOND tAON tAONPD tAOFD tAOF ODT turn-on delay ODT turn-on ODT turn-on (Power down mode) 2 tAC (min) tAC (max) +1 tAC(min) tAC(max) tAC(min) +0.7 +0.7 2tCK + 2tCK + t t 2tCK + tAC(min) +2 tAC(max) AC(min) tAC(max) AC(min) +2 +2 tAC(max)+1 +1 +1 ODT turn-off delay 2.5 ODT turn-off tAC(min) 2.5 2.5 2.5 2.5 2.5 ns tCK tAC(max) tAC(max) tAC(max)+ t t +0.6 AC(min) +0.6 AC(min) 0.6 ns 2.5tCK + tAC(min) tAC(min) 2.5tCK + +2 tAC(max) +2 tAC(max)+1 +1 ns 2.5tCK + tAOFPD ODT turn-off (Power down mode) tAC(min) +2 t AC(max) +1 tANPD ODT to power down entry latency 3 - 3 - 3 - tCK tAXPD ODT power down exit latency 8 - 8 - 8 - tCK tRAS Row Active Time 45 70000 45 70000 45 70000 ns tRCD RAS to CAS delay 15 - 15 - 12.5 ns tRC Row Cycle Time 60 - 60 - 57.5 ns tRP Row Precharge Time 15 - 15 - 12.5 ns Speed Grade Definition REV 1.0 06/2006 20 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Package Dimensions (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) .75 =< = = = 0 C3 > ? , / ?? / # # ; / /< / /, < ; ) > ( C + # # ; /, + 7"# 4 6 #%4 ( %" % = #*& #$#" & %"!+ ,: %%"#$ % %# # # %0 &$ %3 Note: Device position and scale are only for reference. REV 1.0 06/2006 21 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Package Dimensions (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) .75 =< = = / = = 0 C3 > ? , / ?? / # # ; / /< / < /, ; ) + > ( C + /, = + 7"# 4 6 #%4 ( %" % #*& #$#" & %"!+ ,, / # ; ,( C # ,: %%"#$ % %# # # %0 &$ %3 Note: Device position and scale are only for reference. REV 1.0 06/2006 22 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Package Dimensions (1GB - 2 Ranks, 32Mx8 DDR2 SDRAMs) FRONT 67.60 30.00 20.00 6.00 4.00 63.60 (2X) 1.80 1 2.15 39 41 11.40 199 Detail A Detail B 4.20 47.40 2.70 2.45 SIDE BACK 3.80 MAX 1.00+/- 0.10 Detail B 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail A Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) Note: Device position and scale are only for reference. REV 1.0 06/2006 23 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM Revision Log Rev Date Modification 0.1 01/2006 Preliminary Release 0.2 03/2006 Add PC2-6400 (DDR2-800MHz) 1.0 06/2006 Official Release Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Printed in Taiwan (c)2006 REV 1.0 06/2006 24 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.