18-Mbit QDR™-II SRAM 4-Word
Burst Architecture
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05620 Rev. *C Revised June 27, 2006
Features
• Separate Independent Read and Write data ports
— Supports concurrent transactions
• 300-MHz clock for high bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 600 MHz) at 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output dat a (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Wr ite ports
• Separate Port Selects for depth exp ansion
• Synchronous internally self-timed writes
• Available in x 8, x 9, x 18, and x 36 configurations
• Full data coherency providing most current data
•Core V
DD = 1.8 (±0.1V); I/O VDDQ = 1.4V to VDD
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Offered in both lead-free and non-lead free packages
• Variable drive HSTL output buffers
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1311BV18 – 2M x 8
CY7C1911BV18 – 2M x 9
CY7C1313BV18 – 1M x 18
CY7C1315BV18 – 512K x 36
Functional Description
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and
CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data input s and dat a output s to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR-II Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and W rite ports are equi pped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 8-bit words (CY7C1311BV18) or 9-bit
words (CY7C1911BV18) or 18-bit words (CY7C1313BV18) or
36-bit words (CY7C1315BV18) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K and
K and C and C), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All dat a outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit
Maximum Operating Frequency 300 278 250 200 167 MHz
Maximum Operating Current 550 530 500 450 400 mA
[+] Feedback
C
Y7
C
1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Document Number: 38-05620 Rev. *C Page 2 of 28
Logic Block Diagram (CY7C1311BV18)
512K x 8 Array
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
19
8
32
8
NWS[1:0]
VREF
Write Add. Decode
Write
Reg
16
A(18:0)
19
C
C
512K x 8 Array
512K x 8 Array
512K x 8 Array
Write
Reg Write
Reg Write
Reg
8
CQ
CQ
DOFF
Logic Block Diagram (CY7C1911BV18)
512K x 9 Array
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
9
36
9
BWS[0]
VREF
Write Add. Decode
Write
Reg
18
A(18:0)
19
C
C
512K x 9 Array
512K x 9 Array
512K x 9 Array
Write
Reg Write
Reg Write
Reg
9
CQ
CQ
DOFF
[+] Feedback
C
Y7
C
1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Document Number: 38-05620 Rev. *C Page 3 of 28
Logic Block Diagram (CY7C1313BV18)
256K x 18 Array
CLK
A(17:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
18
72
18
BWS[1:0]
VREF
Write Add. Decode
Write
Reg
36
A(17:0)
18
C
C
256K x 18 Array
256K x 18 Array
256K x 18 Array
Write
Reg Write
Reg Write
Reg
18
CQ
CQ
DOFF
Logic Block Diagram (CY7C1315BV18)
128K x 36 Array
CLK
A(16:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
17
36
144
36
BWS[3:0]
VREF
Write Add. Decode
Write
Reg
72
A(16:0)
17
C
C
128K x 36 Array
128K x 36 Array
128K x 36 Array
Write
Reg Write
Reg Write
Reg
36
CQ
CQ
DOFF
[+] Feedback
C
Y7
C
1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Document Number: 38-05620 Rev. *C Page 4 of 28
Pin Configurations
CY7C1311BV18 (2M x 8)
234567
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M A NWS1 K
WPS NC/144M
NC NC
NC
NC
NC
TDO
NC
NC
D5
NC
NC
NC
TCK
NC
NC A NC/288M K NWS0
VSS ANCA
NC VSS
VSS VSS VSS
VDD
A
VSS
VSS
VSS
VDD
Q4
NC
VDDQ
NC
NC
NC
NC
Q7
A
VDDQ VSS
VDDQ VDD VDD
Q5 VDDQ VDD
VDDQ VDD
VDDQ VDD VSS
VDD
VDDQ
VDDQ VSS
VSS VSS VSS
A
A
C
VSS
A A
A
D4 VSS
NC VSS
NC
NC VREF
VSS VDD
VSS VSS
A
VSS
C
NC Q6
NC D7
D6
VDD
A
891011
NC
ANC/36M
RPS CQ
A NC NC Q3
VSS NC NC D3
NC
VSS NC Q2
NC
NC
NC
VREF
NC NC
VDDQ NC
VDDQ NC NC
VDDQ VDDQ
VDDQ D1VDDQ NC Q1
NC
VDDQ
VDDQ NC
VSS NC D0
NC
TDITMS
VSS
ANC
A
NC
D2
NC ZQ
NC Q0
NC
NC
NC
NC
A
NC/144M
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1911BV18 (2M x 9)
234567
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M A NC K
WPS NC/144M
NC NC
NC
NC
NC
TDO
NC
NC
D6
NC
NC
NC
TCK
NC
NC A NC/288M K BWS0
VSS ANCA
NC VSS
VSS VSS VSS
VDD
A
VSS
VSS
VSS
VDD
Q5
NC
VDDQ
NC
NC
NC
NC
Q8
A
VDDQ VSS
VDDQ VDD VDD
Q6 VDDQ VDD
VDDQ VDD
VDDQ VDD VSS
VDD
VDDQ
VDDQ VSS
VSS VSS VSS
A
A
C
VSS
A A
A
D5 VSS
NC VSS
NC
NC VREF
VSS VDD
VSS VSS
A
VSS
C
NC Q7
NC D8
D7
VDD
A
891011
Q0
A NC/36MRPS CQ
A NC NC Q4
VSS NC NC D4
NC
VSS NC Q3
NC
NC
NC
VREF
NC NC
VDDQ NC
VDDQ NC NC
VDDQ VDDQ
VDDQ D2VDDQ NC Q2
NC
VDDQ
VDDQ NC
VSS NC D1
NC
TDITMS
VSS
ANC
A
NC
D3
NC ZQ
NC Q1
NC
NC
D0
NC
A
NC
NC
[+] Feedback
C
Y7
C
1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Document Number: 38-05620 Rev. *C Page 5 of 28
Pin Configurations (continued)
CY7C1313BV18 (1M x 18)
234567
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
RA
CQ
NC
NC
NC
NC
DOFF
NC
NC/144M NC/36M BWS1KWPS NC/288M
Q9 D9
NC
NC
NC
TDO
NC
NC
D13
NC
NC
NC
TCK
NC
D10 A NC K BWS0
VSS ANCA
Q10 VSS
VSS VSS VSS
VDD
A
VSS
VSS
VSS
VDD
Q11
D12
VDDQ
D14
Q14
D16
Q16
Q17
A
VDDQ VSS
VDDQ VDD VDD
Q13 VDDQ VDD
VDDQ VDD
VDDQ VDD VSS
VDD
VDDQ
VDDQ VSS
VSS VSS VSS
A
A
VSS
A A
A
D11 VSS
NC VSS
Q12
NC VREF
VSS VDD
VSS VSS
A
VSS
C
NC Q15
NC D17
D15
VDD
A
891011
Q0
A NC/72MRPS CQ
A NC NC Q8
VSS NC Q7 D8
NC
VSS NC Q6
D5
NC
NC
VREF
NC Q3
VDDQ NC
VDDQ NC Q5
VDDQ VDDQ
VDDQ D4VDDQ NC Q4
NC
VDDQ
VDDQ NC
VSS NC D2
NC
TDITMS
VSS
ANC
A
D7
D6
NC ZQ
D3 Q2
D1
Q1
D0
NC
A
C
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
23456
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
Q27
D27
D28
D34
DOFF
Q33
NC/288M NC/72M BWS2KWPS BWS1
Q18 D18
Q30
D31
D33
TDO
Q28
D29
D22
D32
Q34
Q31
TCK
D35
D19 A BWS3KBWS0
VSS ANCA
Q19 VSS
VSS VSS VSS
VDD
A
VSS
VSS
VSS
VDD
Q20
D21
VDDQ
D23
Q23
D25
Q25
Q26
A
VDDQ VSS
VDDQ VDD VDD
Q22 VDDQ VDD
VDDQ VDD
VDDQ VDD VSS
VDD
VDDQ
VDDQ VSS
VSS VSS VSS
A
A
C
VSS
A A
A
D20 VSS
Q29 VSS
Q21
D30 VREF
VSS VDD
VSS VSS
A
VSS
C
Q32 Q24
Q35 D26
D24
VDD
A
891011
Q0
NC/36M
NC/144M
RPS CQ
A D17 Q17 Q8
VSS D16 Q7 D8
Q16
VSS D15 Q6
D5
D9
Q14
VREF
Q11 Q3
VDDQ Q15
VDDQ D14 Q5
VDDQ VDDQ
VDDQ D4VDDQ D12 Q4
Q12
VDDQ
VDDQ D11
VSS D10 D2
Q10
TDITMS
VSS
AQ9
A
D7
D6
D13 ZQ
D3 Q2
D1
Q1
D0
Q13
A
CY7C1315BV18 (512K x 36)
[+] Feedback
C
Y7
C
1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Document Number: 38-05620 Rev. *C Page 6 of 28
Pin Definitions
Pin Name I/O Pin Description
D[x:0] Input-
Synchronous Data input sign als, sampled on the rising edge of K and K clocks during valid write opera-
tions.
CY7C1311BV18 − D[7:0]
CY7C1911BV18 − D[8:0]
CY7C1313BV18 − D[17:0]
CY7C1315BV18 − D[35:0]
WPS Input-
Synchronous Write Port Select, active LOW . Sampled on the rising edge of the K clock. When asserted active,
a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the W rite port
will cause D[x:0] to be ignored.
NWS0,
NWS1,Input-
Synchronous Nibble Write Select 0, 1 − active LOW.(CY7C1311BV18 Only) Sampled on the rising edge of
the K and K clocks during W rite operations. Used to select which nibble is written into t he device
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous Byte Write Select 0, 1, 2, and 3 − active LOW . Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1911BV18 − BWS0 controls D[8:0]
CY7C1313BV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1315BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and
BWS3 controls D[35:27].
All the Byte Write Select s are sampled on the same edge as the dat a . Deselecting a Byte W rite
Select will cause the corresponding byte of data to be ignored and not written into the device.
A Input-
Synchronous Address Input s. Sampled on the rising edge of the K clock during active Read and W rite opera-
tions. These address inputs are multiplexed for both Read and Write operations. Internally, the
device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1311BV18, 2M x 9 (4 arrays
each of 512K x 9) for CY7C1911BV18,1M x 18 (4 arrays each of 256K x 18) for CY7C1313BV18
and 512K x 36 (4 arrays each of 128K x 36) for CY7C1315BV18. Therefore, only 19 address
inputs are needed to access the entire memory array of CY7C1311BV18 and CY7C1 911BV18,
18 address inputs for CY7C1313BV18 and 17 address inputs for CY7C1315BV18. These input s
are ignored when the appropriate port is deselected.
Q[x:0] Outputs-
Synchronous Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K. when in single clock mode. When the Read port is deselected, Q[x:0] are automatically
tri-stated.
CY7C1311BV18 − Q[7:0]
CY7C1911BV18 − Q[8:0]
CY7C1313BV18 − Q[17:0]
CY7C1315BV18 − Q[35:0]
RPS Input-
Synchronous Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the C clock. Each Read access consists of a burst of
four sequential transfers.
C Input-
Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device . C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
CInput-
Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device . C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
K Input-
Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q [x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
KInput-
Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
[+] Feedback
C
Y7
C
1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Document Number: 38-05620 Rev. *C Page 7 of 28
Functional Overview
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18,
CY7C1315BV18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write por t s, the QDR-I I completely eli minates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of four 8-bit data transfers in the case of
CY7C1311BV18, four 9-bit data transfers in the case of
CY7C1911BV18, four 18-bit data transfers in the case of
CY7C1313BV18, and four 36-bit data in the case of
CY7C1315BV18 transfers in two clock cycles.
Accesses for both ports are initiated on the Positive Input
Clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the output clocks (C and C or K and K when
in single clock mode).
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data output s (Q[x:0]) output s pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single-clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1313BV18 is described in the following sections. The
same basic descriptions apply to CY7C1311BV18,
CY7C1911BV18, and CY7C1315BV18.
Read Operations
The CY7C1313BV18 is organized internally as 4 arrays of
256K x 18. Accesses are completed in a burst of four
sequential 18-bit data words. R ead operations are initi ated by
asserting RPS active at the rising edge of the Positive Input
Clock (K). The address presented to Address inputs are stored
in the Read address register. Following the next K clock rise,
the corresponding lowest order 18-bit word of data is driven
onto the Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data
CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF Input DLL T urn Off - active LOW . Connecting this pin to ground will turn of f the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
TDO Output TDO for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.
NC N/A Not connected to the die. Can be tied to any voltage level.
NC/36M N/A Not connected to the die. Can be tied to any voltage level.
NC/72M N/A Not connected to the die. Can be tied to any voltage level.
NC/144M N/A Not connected to the die. Can be tied to any voltage level.
NC/288M N/A Not connected to the die. Can be tied to any voltage level.
VREF Input-
Reference Reference V oltage Input. S tatic input used to set the reference level for HSTL inputs and outputs
as well as AC measurement points.
VDD Power Supply Power supply inputs to the core of the device.
VSS Ground Ground for the device.
VDDQ Power Supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name I/O Pin Description
[+] Feedback
C
Y7
C
1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Document Number: 38-05620 Rev. *C Page 8 of 28
will be valid 0.45 ns from the rising edge of t he output clock (C
or C or (K or K when in single-clock mode)). In order to
maintain the internal logic, each read access must be allowed
to complete. Each Read access consists of four 18-bit data
words and takes 2 clock cycles to complete. Therefore, Read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Read request. Read accesses can be initiated on
every other K clock rise. Doing so will pipeline the data flow
such that data is transferred out of the device on every rising
edge of the output clocks (C and C or K and K when in
single-clock mode).
When the read port is deselected, the CY7C1313BV18 will first
complete the pending Read transactions. Synchronous
internal circuitry will automatically tri-state the outputs following
the next rising ed ge of t he Posit ive Outp ut Clock (C). Thi s will
allow for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored
into the lower 18-bit Write Dat a register , provided BWS[1:0] are
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K) the information presented to D[17:0]
is also stored into the Write Data register, provided BWS[1:0]
are both asserted active. This process continues for one more
cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the Positive Input Clock (K). Doing
so will pipeline the data flow such that 18 bits of data can be
transferred into the device on every rising edge of the input
clocks (K and K).
When deselected, the W rite por t will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1313BV18.
A Write operation is initiated as described in the Write Opera-
tions section above. The bytes that are written are determined
by BWS0 and BWS1, which are sampled with each set of 18-bit
data words. Asserting the appropriate Byte Write Select input
during the data portion of a Write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1313BV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power on. This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1313BV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the transaction
on the other port. If the ports access the same location when a
Read follows a Write in successive clock cycles, the SRAM will
deliver the most recent information associated with the
specified address location. This includes forwarding data from
a Write cycle that was initiated on the previous K clock rise.
Read accesses and Write access must be scheduled such that
one transaction is initiated on any clock cycle. If both port s are
selected on the same K clock rise, the arbitration depends on
the previous state of the SRAM. If both ports were deselected,
the Read port will take priority. If a Read was initiated on the
previous cycle, the Write port will assume priority (since Read
operations can not be initiated on consecutive cycles). If a
Write was initiated on the previous cycle, the Read port will
assume priority (since Write operations can not be initiated on
consecutive cycles). Therefore, asserting both port selects
active from a deselected state will result in alternating
Read/Write operations being initiated, with the first access
being a Read.
Depth Expansion
The CY7C1313BV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are free running
clocks and are synchronized to the output clock of the QDR-II.
In the single clock mode, CQ is generated with respect to K
and CQ is generated with respect to K. The timings for the
echo clocks are shown in the AC Timing table.
[+] Feedback
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DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency . D uring power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented. The DLL may be
disabled by applying ground to the D OFF pin. For i nformation
refer to the application note ‘DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+.’
Application Example[11]
Truth Tab le[12, 13, 14, 15, 16, 17]
Operation K RPS WPS DQ DQ DQ DQ
Write Cycle:
Load address on the
rising edge of K; input
write data on two
consecutive K and K
rising edges.
L-H H[8] L[9] D(A) at K(t + 1) ↑D(A + 1) at K(t + 1) ↑D(A + 2) at K(t + 2) ↑D(A + 3) at K(t + 2) ↑
Read Cycle:
Load address on the
rising edge of K; wait
one and a half cycle;
read data on two
consecutive C and C
rising edges.
L-H L[9] X Q(A) at C(t + 1) ↑Q(A + 1) at C(t + 2) ↑Q(A + 2) at C(t + 2)↑Q(A + 3) at C(t + 3) ↑
NOP: No Operation L-H H H D = X
Q = High-Z D = X
Q = High-Z D = X
Q = High-Z D = X
Q = High-Z
Standby: Clock
Stopped Stopped X X Previous State Previous State Previous State Previous State
Notes:
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a Read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the
“t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read or Write request.
Vt = Vddq/2
CC#
D
AKCC#
D
AK
BUS
MASTER
(CPU
or
ASIC)
SRAM #1 SRAM #4
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K# R = 50ohms
R = 250ohms
R = 250ohms
R
P
S
#
W
P
S
#
B
W
S
#
R
P
S
#
W
P
S
#
B
W
S
#
Vt
Vt
Vt
R
R
R
ZQ
CQ/CQ#
Q
K#
ZQ
CQ/CQ#
Q
K#
CLKIN/CLKIN#
[+] Feedback
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Write Cycle Descriptions (CY7C1311BV18 and CY7C1313BV18) [2, 10]
BWS0/NWS0BWS1/NWS1KK Comments
L L L–H – During the Data portion of a Write sequence:
CY7C1311BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1313BV18 − both bytes (D[17:0]) are written into the device.
L L – L-H During the Data portion of a Write sequence:
CY7C1311BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1313BV18 − both bytes (D[17:0]) are written into the device.
L H L–H – During the Data portion of a Write sequence :
CY7C1311BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will
remain unaltered,
CY7C1313BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will
remain unaltered.
L H – L–H During the Data portion of a Write sequence :
CY7C1311BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will
remain unaltered,
CY7C1313BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will
remain unaltered.
H L L–H – During the Data portion of a Write sequence :
CY7C1311BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1313BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will
remain unaltered.
H L – L–H During the Data portion of a Write sequence :
CY7C1311BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1313BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will
remain unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
Note:
10.Assumes a W rite cycle was initiated per the Write Port Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, B WS2 and BWS3 can be altered on different
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
[+] Feedback
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Write Cycle Descriptions(CY7C1315BV18)[2, 10]
BWS0BWS1BWS2BWS3KK Comments
L L L L L–H – During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
L L L L – L–H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
L H H H L–H – During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
L H H H – L–H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
H L H H L–H – During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
H L H H – L–H During the Dat a portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
H H L H L–H – During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
H H L H – L–H During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
H H H L L–H During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
H H H L – L–H During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
H H H H L–H – No data is written into the device during this portion of a write operation.
H H H H – L–H No data is written into the device during this portion of a write operation.
Write Cycle Descriptions (CY7C1911BV18)[2, 10]
BWS0KK
L L–H – During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device.
L – L–H During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device.
H L–H – No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.
[+] Feedback
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IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller , TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in T AP Control ler Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting da ta through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bump s
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR st ate. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
[+] Feedback
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is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input s and output pins is cap-
tured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is ca ptured, it is possible to shif t out the data by
putting the T AP into the Shi ft-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tristate”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
[+] Feedback
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Note:
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
TAP Controller State Diagram[11]
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
01
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
0
[+] Feedback
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TAP Controller Block Diagram
TAP Electrica l Charac teristics Over the Operating Range[12, 15, 16]
Parameter Description Test Conditions Min. Max. Unit
VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V
VOH2 Output HIGH Voltage IOH = −100 µA1.6 V
VOL1 Output LOW Voltage IOL = 2.0 mA 0.4 V
VOL2 Output LOW Voltage IOL = 100 µA0.2V
VIH Input HIGH Voltage 0.65VDD VDD + 0.3 V
VIL Input LOW Voltage –0.3 0.35VDD V
IXInput and Output Load Current GND ≤ VI ≤ VDD –5 5 µA
TAP AC Switching Characteristics Over the Operating Range [13, 14]
Parameter Description Min. Max. Unit
tTCYC TCK Clock Cycle Time 50 ns
tTF TCK Clock Frequency 20 MHz
tTH TCK Clock HIGH 20 ns
tTL TCK Clock LOW 20 ns
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise 5 ns
tTDIS TDI Set-up to TCK Clock Rise 5 ns
tCS Capture Set-up to TCK Rise 5 ns
Hold Times
tTMSH TMS Hold after TCK Clock Rise 5 ns
tTDIH TDI Hold after Clock Rise 5 ns
Notes:
12.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
13.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
14.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
15.Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).
16.All Voltage referenced to Ground.
0
012..
29
3031
Boundary Scan Register
Identification Register
012..
.
.106
012
Instruction Register
Bypass Register
Selection
Circuitry Selection
Circuitry
TAP Controller
TDI TDO
TCK
TMS
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tCH Capture Hold after Clock Rise 5 ns
Output Times
tTDOV TCK Clock LOW to TDO Valid 10 ns
tTDOX TCK Clock LOW to TDO Invalid 0 ns
TAP AC Switching Characteristics Over the Operating Range [13, 14] (continued)
Parameter Description Min. Max. Unit
TAP Timing and Test Conditions[14]
(a)
TDO
CL= 20 pF
Z0= 50Ω
GND
0.9V
50Ω
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
tTCYC
tTMSH
tTL
tTH
tTMSS
tTDIS tTDIH
tTDOV tTDOX
TDO
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Identification Register Definitions
Instruction Field Value DescriptionCY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
Revision Number (31:29) 000 000 000 000 V ersion
number.
C y p r e s s D ev i c e I D ( 2 8 : 1 2 ) 1 1010011011000101 1 10100 1 1011001101 1 1010011011010101 11010011011100101 Defines the
type of SRAM.
Cy p re s s JE D E C I D ( 11 : 1) 000001 10100 000001 10100 00000110100 00000110100 Allows unique
identification of
SRAM vendor.
ID Register Presence (0) 1 1 1 1 Indicates the
presence of an
ID register.
Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary Scan 107
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the Input/Output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRA M operation.
SAMPLE Z 010 Captures the Input/Output contents. Places the bo undary scan register
between TDI and TDO. Forces all SRAM output drivers to a High-Z
state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan
register between TDI and TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYP ASS 1 11 Places the byp ass register between TDI and TDO. This operation does
not affect SRAM operation.
[+] Feedback
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Boundary Scan O rde r
Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID
0 6R 27 11H 54 7B 81 3G
1 6P 28 10G 55 6B 82 2G
26N 299G 566A 831J
3 7P 30 11F 57 5B 84 2J
4 7N 31 11G 58 5A 85 3K
57R 329F 594A 863J
6 8R 33 10F 60 5C 87 2K
7 8P 34 11E 61 4B 88 1K
8 9R 35 10E 62 3A 89 2L
9 11P 36 10D 63 1H 90 3L
10 10P 37 9E 64 1A 91 1M
11 10N 38 10C 65 2B 92 1L
12 9P 39 11D 66 3B 93 3N
13 10M 40 9C 67 1C 94 3M
14 11N 41 9D 68 1B 95 1N
15 9M 42 11B 69 3D 96 2M
16 9N 43 11C 70 3C 97 3P
17 11L 44 9B 71 1D 98 2N
18 11M 45 10B 72 2C 99 2P
19 9L 46 11A 73 3E 100 1P
20 10L 47 Internal 74 2D 101 3R
21 11K 48 9A 75 2E 102 4R
22 10K 49 8B 76 1E 103 4P
23 9J 50 7C 77 2F 104 5P
24 9K 51 6C 78 3F 105 5N
25 10J 52 8A 79 1G 106 5R
26 11J 53 7A 80 1F
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CY7C1911BV18
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Document Number: 38-05620 Rev. *C Page 19 of 28
Power-Up Sequence in QDR-II SRAM[17, 18]
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
• Apply power and drive DOFF LOW (All other input s can be
HIGH or LOW)
— Apply VDD before VDDQ
— Apply VDDQ before VREF or at the same time as VREF
• After the power and clock (K, K, C, C) are stable take DOFF
HIGH
• The additional 1024 cycles of clocks are required for the
DLL to lock
DLL Constraints
• DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as
tKC Var
• The DLL will function at frequencies down to 80 MHz
• If the input clock is unstable and the DLL is enabled, then
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior
Notes:
17.It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
18.During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
Power-up Waveforms
> 1024 Stable clock
Start Normal
Operation
DOFF
Stable(< +/- 0.1V DC per 50ns )
Fix High (or tied to VDDQ)
K
K
DDQ
DD
VV
/DDQ
DD
VV
/
Clock Start (Clock Starts after Stable)
DDQ
DD
VV
/
~
~
~
~
Unstable Clock
[+] Feedback
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Document Number: 38-05620 Rev. *C Page 20 of 28
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage on VDD Relative to GND........–0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND......–0.5V to +VDD
DC Applied to Outputs in High-Z .........–0.5V to VDDQ + 0.3V
DC Input Voltage[15]...............................–0.5V to VDD + 0.3V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient
Temperature (TA)V
DD[21] VDDQ[21]
Com’l 0°C to +70°C 1.8 ± 0.1V 1.4V to VDD
Ind’l –40°C to +85°C
Electrical Characteristics Over the Operating Range[16]
DC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ. Max. Unit
VDD Power Supply Voltage 1.7 1.8 1.9 V
VDDQ I/O Supply Voltage 1.4 1.5 VDD V
VOH Output HIGH Voltage Note 19 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V
VOL Output LOW Voltage Note 20 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V
VOH(LOW) Output HIGH Voltage IOH = −0.1 mA, Nominal Impedance VDDQ – 0.2 VDDQ V
VOL(LOW) Output LOW Voltage IOL = 0.1 mA, Nominal Impedance VSS 0.2 V
VIH Input HIGH Voltage[15] VREF + 0.1 VDDQ + 0.3 V
VIL Input LOW Voltage[15] –0.3 VREF – 0.1 V
IXInput Leakage Current GND ≤ VI ≤ VDDQ −55µA
IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled −55µA
VREF Input Reference Voltage[22] Typical Value = 0.75V 0.68 0.75 0.95 V
IDD VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC 167 MHz 400 mA
200 MHz 450 mA
250 MHz 500 mA
278 MHz 530 mA
300 MHz 550 mA
ISB1 Automatic Power-down
Current Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
VIN ≤ VIL
f = fMAX = 1/tCYC,
Inputs Static
167 MHz 200 mA
200 MHz 220 mA
250 MHz 240 mA
278 MHz 250 mA
300 MHz 260 mA
AC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ. Max. Unit
VIH Input HIGH Voltage VREF + 0.2 – – V
VIL Input LOW Voltage – – VREF – 0.2 V
Capacitance[23]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
5pF
CCLK Clock Input Capacitance 6pF
COOutput Capacitance 7pF
Notes:
19.Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350 Ωs.
20.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350 Ωs.
21.Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH< VDD and VDDQ< VDD.
22.VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
23.Tested initially and after any design or process change that may affect these parameters.
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Document Number: 38-05620 Rev. *C Page 21 of 28
Note:
24.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
Thermal Resistance[23]
Parameter Description Test Conditions 165 FBGA
Package Unit
ΘJA Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods and procedures for
measuring thermal impedance, per EIA/JESD51. 28.51 °C/W
ΘJC Thermal Resistance
(Junction to Case) 5.91 °C/W
AC Test Loads and Waveforms
1.25V
0.25V
R = 50Ω
5pF
ALL INPUT PULSES
Device RL= 50Ω
Z0= 50Ω
VREF = 0.75V
VREF = 0.75V
[24]
0.75V
Under
Test
0.75V
Device
Under
Test
OUTPUT
0.75V
VREF
VREF
OUTPUT
ZQ
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
Ω
(b)
RQ =
250
Ω
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Document Number: 38-05620 Rev. *C Page 22 of 28
Switching Characteristics Over the Operating Range[24,26]
Cypress
Parameter Consortium
Parameter Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tPOWER VDD(Typical) to the First
Access[25] 11111ms
tCYC tKHKH K Clock and C Clock Cycle
Time 3.30 5.25 3.60 5.25 4.0 5.25 5.0 6.3 6.0 8.4 ns
tKH tKHKL Input Clock (K/K; C/C)
HIGH 1.32 – 1.4 – 1.6 – 2.0 2.4 – ns
tKL tKLKH Input Clock (K/K; C/C)
LOW 1.32 – 1.4 – 1.6 – 2.0 – 2.4 – ns
tKHKHtKHKHK Clock Rise to K Clock
Rise and C to C Rise
(rising edge to rising edge)
1.49 – 1.6 – 1.8 – 2.2 – 2.7 – ns
tKHCH tKHCH K/K Clock Rise to C/C
Clock Rise (rising edge to
rising edge)
0.0 1.45 0.0 1.55 0.0 1.8 0.0 2.2 0.0 2.7 ns
Set-up Times
tSA tAVKH Address Set-up to K Clock
Rise 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
tSC tIVKH Control Set-up to K Clock
Rise (RPS, WPS)0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
tSCDDR tIVKH Double Data Rate Control
Set-up to Clock (K, K) Rise
(BWS0, BWS1, BWS2,
BWS3)
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
tSD[27] tDVKH D[X:0] Set-up to Clock
(K/K) Rise 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Hold Times
tHA tKHAX Address Hold after K
Clock Rise 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
tHC tKHIX Control Hold after K Clock
Rise (RPS, WPS)0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
tHCDDR tKHIX Double Data Rate Control
Hold after Clock (K, K)
Rise (BWS0, BWS1,
BWS2, BWS3)
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
tHD tKHDX D[X:0] Hold after Clock
(K/K) Rise 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Output Times
tCO tCHQV C/C Clock Rise (or K/K in
single clock mode) to Data
Valid
0.45 0.45 – 0.45 – 0.45 – 0.50 ns
tDOH tCHQX Data Output Hold after
Output C/C Clock Rise
(Active to Active)
–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
tCCQO tCHCQV C/C Clock Rise to Echo
Clock Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
Notes:
25.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation
can be initiated.
26.All devices can operate at clock frequencies as low as 1 19 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency ,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
27.For D2 data signal on CY7C1911BV18 device, tSD is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
[+] Feedback
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Document Number: 38-05620 Rev. *C Page 23 of 28
tCQOH tCHCQX Echo Clock Hold after C/C
Clock Rise –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
tCQD tCQHQV Echo Clock High to Data
Valid 0.27 0.27 – 0.30 – 0.35 – 0.40 ns
tCQDOH tCQHQX Echo Clock High to Data
Invalid –0.27 – –0.27 – –0.30 – –0.35 – –0.40 – ns
tCHZ tCHQZ Clock (C/C)
Rise to High-Z
(Active to High-Z)[28, 29]
– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tCLZ tCHQX1 Clock (C/C) Rise to
Low-Z[28, 29] –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
DLL Timing
tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 – 0.20 ns
tKC lock tKC lock DLL Lock Time (K, C) 1024 – 1024 – 1024 – 1024 – 1024 – Cycles
tKC Reset tKC Reset K Static to DLL Reset 30 30 30 30 30 ns
Notes:
28.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
29.At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Switching Characteristics Over the Operating Range[24,26] (continued)
Cypress
Parameter Consortium
Parameter Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
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Document Number: 38-05620 Rev. *C Page 24 of 28
Switching Waveforms[30, 31, 32]
Read/Write/Deselect Sequence
Notes:
30.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
31.Output are disabled (High-Z) one clock cycle after a NOP.
32.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole
diagram.
K
12345
67
RPS
WPS
A
Q
D
C
C
READ READWRITE WRITE
NOP NOP
DON’T CARE UNDEFINED
CQ
CQ
K
A0 A1
tKH tKHKH
tKL tCYC
ttHC
tSA tHA
A2
SC tt
HCSC
A3
tKHCH
tKHCH
tCQD
tCLZ
DOH
tCHZ
t
ttKL
tCYC
tCCQO
tCCQO
tCQOH
tCQOH
KHKH KH
Q00 Q03
Q01 Q02 Q20 Q23
Q21 Q22
tCO tCQDOH
t
D10 D11 D12 D13
tSD
tHD
tSD
tHD
D30 D31 D32 D33
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1311BV18
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Document Number: 38-05620 Rev. *C Page 25 of 28
Ordering Information
Not all of the speed, pa ckage and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
167 CY7C1311BV18-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
CY7C1911BV18-167BZC
CY7C1313BV18-167BZC
CY7C1315BV18-167BZC
CY7C1311BV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-167BZXC
CY7C1313BV18-167BZXC
CY7C1315BV18-167BZXC
CY7C1311BV18-167BZI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1911BV18-167BZI
CY7C1313BV18-167BZI
CY7C1315BV18-167BZI
CY7C1311BV18-167BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-167BZXI
CY7C1313BV18-167BZXI
CY7C1315BV18-167BZXI
200 CY7C1311BV18-200BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
CY7C1911BV18-200BZC
CY7C1313BV18-200BZC
CY7C1315BV18-200BZC
CY7C1311BV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-200BZXC
CY7C1313BV18-200BZXC
CY7C1315BV18-200BZXC
CY7C1311BV18-200BZI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1911BV18-200BZI
CY7C1313BV18-200BZI
CY7C1315BV18-200BZI
CY7C1311BV18-200BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-200BZXI
CY7C1313BV18-200BZXI
CY7C1315BV18-200BZXI
250 CY7C1311BV18-250BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
CY7C1911BV18-250BZC
CY7C1313BV18-250BZC
CY7C1315BV18-250BZC
CY7C1311BV18-250BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-250BZXC
CY7C1313BV18-250BZXC
CY7C1315BV18-250BZXC
[+] Feedback
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Y7
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1311BV18
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Document Number: 38-05620 Rev. *C Page 26 of 28
250 CY7C1311BV18-250BZI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1911BV18-250BZI
CY7C1313BV18-250BZI
CY7C1315BV18-250BZI
CY7C1311BV18-250BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-250BZXI
CY7C1313BV18-250BZXI
CY7C1315BV18-250BZXI
278 CY7C1311BV18-278BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
CY7C1911BV18-278BZC
CY7C1313BV18-278BZC
CY7C1315BV18-278BZC
CY7C1311BV18-278BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-278BZXC
CY7C1313BV18-278BZXC
CY7C1315BV18-278BZXC
CY7C1311BV18-278BZI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1911BV18-278BZI
CY7C1313BV18-278BZI
CY7C1315BV18-278BZI
CY7C1311BV18-278BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-278BZXI
CY7C1313BV18-278BZXI
CY7C1315BV18-278BZXI
300 CY7C1311BV18-300BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
CY7C1911BV18-300BZC
CY7C1313BV18-300BZC
CY7C1315BV18-300BZC
CY7C1311BV18-300BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-300BZXC
CY7C1313BV18-300BZXC
CY7C1315BV18-300BZXC
CY7C1311BV18-300BZI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1911BV18-300BZI
CY7C1313BV18-300BZI
CY7C1315BV18-300BZI
CY7C1311BV18-300BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-300BZXI
CY7C1313BV18-300BZXI
CY7C1315BV18-300BZXI
Ordering Information (continued)
Not all of the speed, pa ckage and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
[+] Feedback
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Y7
C
1311BV18
CY7C1911BV18
CY7C1313BV18
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Document Number: 38-05620 Rev. *C Page 27 of 28
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuit r y embodied in a Cypress product. No r does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life sup port, life saving, critical con trol or safety applicatio ns, unless pursuant to an express writ ten agreement with Cypress. F urthermore, Cypress does not auth orize its
products for use as critical components in life-support systems wh ere a malfunction or failure ma y reasonably be exp ected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application impli es that the manufa ctur er assumes all risk of such use and in doing so indemnifies Cypress against all charges.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT,NEC, and Samsung
technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagram
A
1
PIN 1 CORNER
15.00±0.10
13.00±0.10
7.00
1.00
Ø0.50 (165X)
Ø0.25MCAB
Ø0.05 M C
B
A
0.15(4X)
0.35±0.06
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
PIN1CORNER
TOP VIEW
BOTTOM VIEW
2345678910
10.00
14.00
B
C
D
E
F
G
H
J
K
L
M
N
11
1110986754321
P
R
P
R
K
M
N
L
J
H
G
F
E
D
C
B
A
A
15.00±0.10
13.00±0.10
B
C
1.00
5.00
0.36
-0.06
+0.14
1.40 MAX.
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
NOTES :
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
51-85180-*A
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D
A
1
PIN 1 CORNER
15.00±0.10
13.00±0.10
7.00
1.00
Ø0.50 (165X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.35±0.06
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
PIN 1 CORNER
TOP VIEW
BOTTOM VIEW
2345678910
10.00
14.00
B
C
D
E
F
G
H
J
K
L
M
N
11
1110986754321
P
R
P
R
K
M
N
L
J
H
G
F
E
D
C
B
A
A
15.00±0.10
13.00±0.10
B
C
1.00
5.00
0.36
-0.06
+0.14
1.40 MAX.
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
NOTES :
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
51-85180-*A
165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)
[+] Feedback
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1311BV18
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Document Number: 38-05620 Rev. *C Page 28 of 28
Document History Page
Document Title: CY7C1311BV18/CY7C1911BV18/CY7C1313BV18/CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word
Burst Architecture
Document Number: 38-05620
REV. ECN No. Issue Date Orig. of
Change Description of Change
** 252474 See ECN SYT New data sheet
*A 325581 See ECN SYT Removed CY7C1911BV18 from the title
Included 300-MHz Speed Bin
Added Industrial Temperature Grade
Replaced TBDs for IDD and ISB1 specs
Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 28.51 °C/W
and ΘJC = 5.91°C/W
Replaced TBDs in the Capacitance Table for the 165 FBGA Package
Changed the package diagram from BB165E (15 x 17 x 1.4 mm) to BB165D
(13 x 15 x 1.4 mm)
Added Lead-Free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
*B 413997 See ECN NXR Converted from Preliminary to Final
Added CY7C1911BV18 to the title
Added 278-MHz speed Bin
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed C/C Description in the features section
Added power-up sequence details and waveforms
Added foot notes# 17, 18, 19 on page# 19
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 20
Modified the IDD and ISB values
Modified test condition in Footnote # 22 on page# 20 from VDDQ < VDD to
VDDQ < VDD
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*C 472384 See ECN NXR Modified the ZQ Definition from Alternately, this pin can be connected directly
to VDD to Alternately, this pin can be connected directly to VDDQ
Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND
Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH,
tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC
Switching Characteristics table
Modified Power-Up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied
from –10°C to +85°C to –55°C to +125°C
Added additional notes in the AC parameter section
Modified AC Switching Waveform
Corrected the typo In the AC Switching Characteristics Table
Updated the Ordering Information Table
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