24LC04B/08B 4K/8K 2.5V CMOS Serial EEPROMs FEATURES * Single supply with operation down to 2.5V * Low power CMOS technology - 1 mA active current typical - 10 A standby current typical at 5.5V - 5 A standby current typical at 3.0V * Organized as two or four blocks of 256 bytes (2 x 256 x 8) and (4 x 256 x 8) * Two wire serial interface bus, I2C compatible * Schmitt trigger, filtered inputs for noise suppression * Output slope control to eliminate ground bounce * 100 kHz (2.5V) and 400 kHz (5V) compatibility * Self-timed write cycle (including auto-erase) * Page-write buffer for up to 16 bytes * 2 ms typical write cycle time for page-write * Hardware write protect for entire memory * Can be operated as a serial ROM * Factory programming (QTP) available * ESD protection > 4,000V * 1,000,000 ERASE/WRITE cycles guaranteed* * Data retention > 200 years * 8-pin DIP, 8-lead or 14-lead SOIC packages * Available for extended temperature ranges - Commercial: 0C to +70C - Industrial: -40C to +85C PACKAGE TYPE DIP 24LC04B/08B 8-lead SOIC 14-lead SOIC 24LC04B/08B DESCRIPTION The Microchip Technology Inc. 24LC04B/08B is a 4Kor 8K-bit Electrically Erasable PROM. The device is organized as two or four blocks of 256 x 8 bit memory with a two wire serial interface. Low voltage design permits operation down to 2.5 volts with standby and active currents of only 5 A and 1 mA respectively. The 24LC04B/08B also has a page-write capability for up to 16 bytes of data. The 24LC04B/08B is available in the standard 8-pin DIP and both 8-lead and 14-lead surface mount SOIC packages. 24LC04B/08B BLOCK DIAGRAM WP I/O CONTROL LOGIC MEMORY CONTROL LOGIC HV GENERATOR XDEC EEPROM ARRAY (2 x 256 x 8) or (4 X 256 X 8) PAGE LATCHES SDA SCL YDEC *Future: 10,000,000 E/W cycles guaranteed VCC V SS SENSE AMP R/W CONTROL I2C is a trademark of Philips Corporation 1995 Microchip Technology Inc. DS21051D-page 1 24LC04B/08B 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* TABLE 1-1: Name VCC ........................................................................7.0V All inputs and outputs w.r.t. VSS .....-0.3V to VCC + 1.0V Storage temperature .......................... -65C to +150C Ambient temp. with power applied...... -65C to +125C Soldering temperature of leads (10 seconds) .. +300C ESD protection on all pins ...................................... 4 kV *Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: PIN FUNCTION TABLE Function VSS Ground SDA Serial Address/Data I/O SCL Serial Clock WP Write Protect Input VCC +2.5V to 5.5V Power Supply A0, A1, A2 No Internal Connection DC CHARACTERISTICS VCC = +2.5V to +5.5V Commercial (C): Tamb = 0C to +70C Industrial (I): Tamb = -40C to +85C Parameter Symbol Min Max Units VIH VIL VHYS VOL .7 VCC -- .05 VCC -- -- .3 VCC -- .40 V V V V Note 1 IOL = 3.0mA, VCC = 2.5V Input leakage current ILI -10 10 A VIN = .1V to VCC Output leakage current ILO -10 10 A VOUT = .1V to VCC Pin capacitance (all inputs/outputs) CIN, COUT -- 10 pF VCC = 5.0V (Note 1) Tamb = 25C, Fclk = 1 MHz Operating current ICC WRITE ICC READ -- -- 3 1 mA mA VCC = 5.5V, SCL = 400 kHz ICCS -- -- 30 100 A A VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC WP, SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Standby current Note 1: This parameter is periodically sampled and not 100% tested. FIGURE 1-1: DS21051D-page 2 BUS TIMING START/STOP 1995 Microchip Technology Inc. 24LC04B/08B TABLE 1-3: AC CHARACTERISTICS Parameter Symbol STANDARD MODE Min Max VCC = 4.5 - 5.5V FAST MODE Min Max Units Clock frequency FCLK -- 100 -- 400 kHz Clock high time THIGH 4000 -- 600 -- ns Clock low time Remarks TLOW 4700 -- 1300 -- ns SDA and SCL rise time TR -- 1000 -- 300 ns Note 2 SDA and SCL fall time TF -- 300 -- 300 ns Note 2 START condition hold time THD:STA 4000 -- 600 -- ns After this period the first clock pulse is generated START condition setup time TSU:STA 4700 -- 600 -- ns Only relevant for repeated START condition Data input hold time THD:DAT 0 -- 0 -- ns Data input setup time TSU:DAT 250 -- 100 -- ns STOP condition setup time ns TSU:STO 4000 -- 600 -- Output valid from clock TAA -- 3500 -- 900 ns Note 1 Bus free time TBUF 4700 -- 1300 -- ns Time the bus must be free before a new transmission can start Output fall time from VIH min to VIL max TOF -- 250 20 +0.1 CB 250 ns Note 2, CB 100 pF Input filter spike suppression (SDA and SCL pins) TSP -- 50 -- 50 ns Note 3 Write cycle time TWR -- 10 -- 10 ms Byte or Page mode Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. Note 2: Not 100% tested. CB = total capacitance of one bus line in pF. Note 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation. FIGURE 1-2: BUS TIMING DATA 1995 Microchip Technology Inc. DS21051D-page 3 24LC04B/08B 2.0 FUNCTIONAL DESCRIPTION The 24LC04B/08B supports a bidirectional two wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24LC04B/08B works as slave. Both, master and slave can operate as transmitter or receiver but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (see Figure 3-1). 3.1 Bus not Busy (A) Both data and clock lines remain HIGH. 3.2 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 3.3 Stop Data Transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. FIGURE 3-1: DS21051D-page 4 3.4 Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. 3.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24LC04B/08B does not generate any acknowledge bits if an internal programming cycle is in progress. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS 1995 Microchip Technology Inc. 24LC04B/08B 4.0 BUS CHARACTERISTICS 5.0 WRITE OPERATION 4.1 Device Addressing and Operation 5.1 Byte Write A control byte is the first byte received following the start condition from the master device. The control byte consists of a four bit control code, for the 24LC04B/08B this is set as 1010 binary for read and write operations. The next three bits of the control byte are the block select bits (B2, B1, B0). B2 is a don't care for both the 24LC04B and 24LC08B; B1 is a don't care for the 24LC04B. They are used by the master device to select which of the two or four 256 word blocks of memory are to be accessed. These bits are in effect the most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected. Following the start condition, the 24LC04B/08B monitors the SDA bus checking the device type identifier being transmitted, upon a 1010 code the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24LC04B/ 08B will select a read or write operation. Operation Control Code Block Select R/W Read 1010 Block Address 1 Write 1010 Block Address 0 FIGURE 4-1: CONTROL BYTE ALLOCATION FIGURE 5-1: BYTE WRITE 1995 Microchip Technology Inc. Following the start condition from the master, the device code (4 bits), the block address (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24LC04B/08B. After receiving another acknowledge signal from the 24LC04B/08B the master device will transmit the data word to be written into the addressed memory location. The 24LC04B/08B acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24LC04B/08B will not generate acknowledge signals (see Figure 51). 5.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24LC04B/08B in the same way as in a byte write. But instead of generating a stop condition the master transmits up to sixteen data bytes to the 24LC04B/08B which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the four lower order address pointer bits are internally incremented by one. The higher order seven bits of the word address remains constant. If the master should transmit more than sixteen words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (see Figure 8-1). DS21051D-page 5 24LC04B/08B 6.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 6-1 for flow diagram. FIGURE 6-1: ACKNOWLEDGE POLLING FLOW 7.0 WRITE PROTECTION The 24LC04B/08B can be used as a serial ROM when the WP pin is connected to V CC. Programming will be inhibited and the entire memory will be write-protected. 8.0 READ OPERATION Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 8.1 Current Address Read The 24LC04B/08B contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W b i t s e t t o o n e , t h e 24LC04B/08B issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC04B/08B discontinues transmission (see Figure 8-2). 8.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC04B/08B as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LC04B/ 08B will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC04B/08B discontinues transmission (see Figure 8-3). FIGURE 8-1: DS21051D-page 6 PAGE WRITE 1995 Microchip Technology Inc. 24LC04B/08B FIGURE 8-2: CURRENT ADDRESS READ FIGURE 8-3: RANDOM READ 1995 Microchip Technology Inc. DS21051D-page 7 24LC04B/08B 8.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24LC04B/08B transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24LC04B/08B to transmit the next sequentially addressed 8 bit word (see Figure 9-1). To provide sequential reads the 24LC04B/08B contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. 8.4 Noise Protection The 24LC04B/08B employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. 9.0 PIN DESCRIPTIONS 9.1 SDA Serial Address/Data Input/Output This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to VCC (typical 10K for 100 kHz, 1K for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. 9.2 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. 9.3 WP This pin must be connected to either VSS or VCC. If tied to VSS, normal memory operation is enabled (read/write the entire memory). If tied to VCC, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected. This feature allows the user to use the 24LC04B/08B as a serial ROM when WP is enabled (tied to VCC). 9.4 A0, A1, A2 These pins are not used by the 24LC04B/08B. They may be left floating or tied to either VSS or VCC. FIGURE 9-1: DS21051D-page 8 SEQUENTIAL READ 1995 Microchip Technology Inc. 24LC04B/08B NOTES: 1995 Microchip Technology Inc. DS21051D-page 9 24LC04B/08B NOTES: DS21051D-page 10 1995 Microchip Technology Inc. 24LC04B/08B NOTES: 1995 Microchip Technology Inc. DS21051D-page 11 24LC04B/08B 24LC04B/08B Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 24LC04B - /P Package: P SL SN SM Temperature Range: Device: = = = = Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (207 mil Body), 8-lead Blank = 0C to +70C I = -40C to +85C 24LC04B 24LC04BT 24LC04B 24LC04BT 4K CMOS Serial EEPROM 4K CMOS Serial EEPROM (Tape and Reel) 8K CMOS Serial EEPROM 8K CMOS Serial EEPROM (Tape and Reel) AMERICAS AMERICAS (continued) EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.mchip.com/biz/mchip Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508 480-9990 Fax: 508 480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 708 285-0071 Fax: 708 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 214 991-7177 Fax: 214 991-8588 Dayton Microchip Technology Inc. 35 Rockridge Road Englewood, OH 45322 Tel: 513 832-2543 Fax: 513 832-2841 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 455 Irvine, CA 92715 Tel: 714 263-1888 Fax: 714 263-1338 New York Microchip Technology Inc. 150 Motor Parkway, Suite 416 Hauppauge, NY 11788 Tel: 516 273-5305 Fax: 516 273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408 436-7950 Fax: 408 436-7955 United Kingdom Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 0 1628 851077 Fax: 44 0 1628 850259 France Arizona Microchip Technology SARL 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Pegaso Ingresso No. 2 Via Paracelso 23, 20041 Agrate Brianza (MI) Italy Tel: 39 039 689 9939 Fax: 39 039 689 9883 ASIA/PACIFIC Hong Kong Microchip Technology Unit No. 3002-3004, Tower 1 Metroplaza 223 Hing Fong Road Kwai Fong, N.T. Hong Kong Tel: 852 2 401 1200 Fax: 852 2 401 3431 Korea Microchip Technology 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku, Seoul, Korea Tel: 82 2 554 7200 Fax: 82 2 558 5934 Singapore Microchip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65 334 8870 Fax: 65 334 8850 Taiwan Microchip Technology 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2 717 7175 Fax: 886 2 545 0139 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122 9/5/95 Printed in the USA, 9/95 1995, Microchip Technology Incorporated "Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights." The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21051D-page 12 1995 Microchip Technology Inc.