24LC08B/SL - Microchip Technology

 1995 Microchip Technology Inc. DS21051D-page 1

FEATURES

• Single supply with operation down to 2.5V

• Low power CMOS technology

- 1 mA active current typical

- 10 µA standby current typical at 5.5V

- 5 µA standby current typical at 3.0V

• Organized as two or four blocks of 256 bytes

(2 x 256 x 8) and (4 x 256 x 8)

• Two wire serial interface bus, I2C compatible

• Schmitt trigger, ﬁltered inputs for noise suppres-

sion

• Output slope control to eliminate ground bounce

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 ERASE/WRITE cycles guaranteed*

• Data retention > 200 years

• 8-pin DIP, 8-lead or 14-lead SOIC packages

• Available for extended temperature ranges

- Commercial: 0˚C to +70˚C

- Industrial: -40˚C to +85˚C

DESCRIPTION

The Microchip Technology Inc. 24LC04B/08B is a 4K-

or 8K-bit Electrically Erasable PROM. The device is

organized as two or four blocks of 256 x 8 bit memory

with a two wire serial interface. Low voltage design

permits operation down to 2.5 volts with standby and

active currents of only 5 µA and 1 mA respectively. The

24LC04B/08B also has a page-write capability for up to

16 bytes of data. The 24LC04B/08B is available in the

standard 8-pin DIP and both 8-lead and 14-lead sur-

face mount SOIC packages.

PACKAGE TYPE

BLOCK DIAGRAM

DIP

8-lead

SOIC

14-lead

SOIC

24LC04B/08B

HV GENERATOR

EEPROM ARRAY

(2 x 256 x 8) or

(4 X 256 X 8)

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA SCL

VCC

VSS

24LC04B/08B

4K/8K 2.5V CMOS Serial EEPROMs

I2C is a trademark of Philips Corporation

*Future: 10,000,000 E/W cycles guaranteed

24LC04B/08B

DS21051D-page 2  1995 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maximum Ratings*

VCC........................................................................7.0V

All inputs and outputs w.r.t. VSS.....-0.3V to VCC + 1.0V

Storage temperature ..........................-65˚C to +150˚C

Ambient temp. with power applied......-65˚C to +125˚C

Soldering temperature of leads (10 seconds) ..+300˚C

ESD protection on all pins......................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

VSS Ground

SDA Serial Address/Data I/O

SCL Serial Clock

WP Write Protect Input

VCC +2.5V to 5.5V Power Supply

A0, A1, A2 No Internal Connection

TABLE 1-2: DC CHARACTERISTICS

FIGURE 1-1: BUS TIMING START/STOP

VCC = +2.5V to +5.5V

Commercial (C): Tamb = 0˚C to +70˚C

Industrial (I): Tamb = -40˚C to +85˚C

Parameter Symbol Min Max Units

WP, SCL and SDA pins:

High level input voltage

Low level input voltage

Hysteresis of Schmitt trigger

inputs

Low level output voltage

VIH

VIL

VHYS

VOL

.7 VCC

—

.05 VCC

—

.3 VCC

—

.40

VNote 1

IOL = 3.0mA, VCC = 2.5V

Input leakage current ILI -10 10 µA VIN = .1V to VCC

Output leakage current ILO -10 10 µA VOUT = .1V to VCC

Pin capacitance

(all inputs/outputs) CIN, COUT — 10 pF VCC = 5.0V (Note 1)

Tamb = 25˚C, Fclk = 1 MHz

Operating current ICC WRITE

ICC READ —

—3

1mA

mA VCC = 5.5V, SCL = 400 kHz

Standby current ICCS —

—30

100 µA

µAVCC = 3.0V, SDA = SCL = VCC

VCC = 5.5V, SDA = SCL = VCC

Note 1: This parameter is periodically sampled and not 100% tested.

 1995 Microchip Technology Inc. DS21051D-page 3

24LC04B/08B

TABLE 1-3: AC CHARACTERISTICS

FIGURE 1-2: BUS TIMING DATA

Parameter Symbol

STANDARD

MODE VCC = 4.5 - 5.5V

FAST MODE Units Remarks

Min Max Min Max

Clock frequency FCLK — 100 — 400 kHz

Clock high time THIGH 4000 — 600 — ns

Clock low time TLOW 4700 — 1300 — ns

SDA and SCL rise time TR— 1000 — 300 ns Note 2

SDA and SCL fall time TF— 300 — 300 ns Note 2

START condition hold time THD:STA 4000 — 600 — ns After this period the ﬁrst clock

pulse is generated

START condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated

START condition

Data input hold time THD:DAT 0 — 0 — ns

Data input setup time TSU:DAT 250 — 100 — ns

STOP condition setup time TSU:STO 4000 — 600 — ns

Output valid from clock TAA — 3500 — 900 ns Note 1

Bus free time TBUF 4700 — 1300 — ns Time the bus must be free

before a new transmission can

start

Output fall time from VIH min

to VIL max TOF — 250 20 +0.1

CB250 ns Note 2, CB ≤ 100 pF

Input ﬁlter spike suppression

(SDA and SCL pins) TSP — 50 — 50 ns Note 3

Write cycle time TWR — 10 — 10 ms Byte or Page mode

Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

Note 2: Not 100% tested. CB = total capacitance of one bus line in pF.

Note 3: The combined TSP and VHYS speciﬁcations are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a Ti speciﬁcation for standard operation.

24LC04B/08B

DS21051D-page 4  1995 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

The 24LC04B/08B supports a bidirectional two wire

bus and data transmission protocol. A device that

sends data onto the bus is deﬁned as transmitter, and

a device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions, while the

24LC04B/08B works as slave. Both, master and slave

can operate as transmitter or receiver but the master

device determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been deﬁned:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

deﬁned (see Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition.

All commands must be preceded by a START condi-

tion.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last six-

teen will be stored when doing a write operation. When

an overwrite does occur it will replace data in a ﬁrst in

ﬁrst out fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

The device that acknowledges, has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable

the master to generate the STOP condition.

Note: The 24LC04B/08B does not generate any

acknowledge bits if an internal program-

ming cycle is in progress.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

 1995 Microchip Technology Inc. DS21051D-page 5

24LC04B/08B

4.0 BUS CHARACTERISTICS

4.1 Device Addressing and Operation

A control byte is the ﬁrst byte received following the

start condition from the master device. The control

byte consists of a four bit control code, for the

24LC04B/08B this is set as 1010 binary for read and

write operations. The next three bits of the control byte

are the block select bits (B2, B1, B0). B2 is a don't care

for both the 24LC04B and 24LC08B; B1 is a don't care

for the 24LC04B. They are used by the master device

to select which of the two or four 256 word blocks of

memory are to be accessed. These bits are in effect

the most signiﬁcant bits of the word address.

The last bit of the control byte deﬁnes the operation to

be performed. When set to one a read operation is

selected, when set to zero a write operation is selected.

Following the start condition, the 24LC04B/08B moni-

tors the SDA bus checking the device type identiﬁer

being transmitted, upon a 1010 code the slave device

outputs an acknowledge signal on the SDA line.

Depending on the state of the R/W bit, the 24LC04B/

08B will select a read or write operation.

FIGURE 4-1: CONTROL BYTE

ALLOCATION

Operation Control

Code Block Select R/W

Read 1010 Block Address 1

Write 1010 Block Address 0

5.0 WRITE OPERATION

5.1 Byte Write

Following the start condition from the master, the

device code (4 bits), the block address (3 bits), and the

R/W bit which is a logic low is placed onto the bus by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will fol-

low after it has generated an acknowledge bit during

the ninth clock cycle. Therefore the next byte transmit-

ted by the master is the word address and will be writ-

ten into the address pointer of the 24LC04B/08B. After

receiving another acknowledge signal from the

24LC04B/08B the master device will transmit the data

word to be written into the addressed memory location.

The 24LC04B/08B acknowledges again and the mas-

ter generates a stop condition. This initiates the inter-

nal write cycle, and during this time the 24LC04B/08B

will not generate acknowledge signals (see Figure 5-

1).

5.2 Page Write

The write control byte, word address and the ﬁrst data

byte are transmitted to the 24LC04B/08B in the same

way as in a byte write. But instead of generating a stop

condition the master transmits up to sixteen data bytes

to the 24LC04B/08B which are temporarily stored in

the on-chip page buffer and will be written into the

memory after the master has transmitted a stop condi-

tion. After the receipt of each word, the four lower order

address pointer bits are internally incremented by one.

The higher order seven bits of the word address

remains constant. If the master should transmit more

than sixteen words prior to generating the stop condi-

tion, the address counter will roll over and the previ-

ously received data will be overwritten. As with the byte

write operation, once the stop condition is received an

internal write cycle will begin (see Figure 8-1).

FIGURE 5-1: BYTE WRITE

24LC04B/08B

DS21051D-page 6  1995 Microchip Technology Inc.

6.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately. This involves the master

sending a start condition followed by the control byte

for a write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If the cycle is complete, then the device will return the

ACK and the master can then proceed with the next

read or write command. See Figure 6-1 for ﬂow dia-

gram.

FIGURE 6-1: ACKNOWLEDGE POLLING

FLOW

7.0 WRITE PROTECTION

The 24LC04B/08B can be used as a serial ROM when

the WP pin is connected to VCC. Programming will be

inhibited and the entire memory will be write-protected.

8.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic

types of read operations: current address read, ran-

dom read, and sequential read.

8.1 Current Address Read

The 24LC04B/08B contains an address counter that

maintains the address of the last word accessed, inter-

nally incremented by one. Therefore, if the previous

access (either a read or write operation) was to

address n, the next current address read operation

would access data from address n + 1. Upon receipt of

the slave address with R/W bit set to one, the

24LC04B/08B issues an acknowledge and transmits

the eight bit data word. The master will not acknowl-

edge the transfer but does generate a stop condition

and the 24LC04B/08B discontinues transmission (see

Figure 8-2).

8.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, ﬁrst the word address must

be set. This is done by sending the word address to the

24LC04B/08B as part of a write operation. After the

word address is sent, the master generates a start con-

dition following the acknowledge. This terminates the

write operation, but not before the internal address

pointer is set. Then the master issues the control byte

again but with the R/W bit set to a one. The 24LC04B/

08B will then issue an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the transfer but does generate a stop condition and the

24LC04B/08B discontinues transmission (see

Figure 8-3).

FIGURE 8-1: PAGE WRITE

 1995 Microchip Technology Inc. DS21051D-page 7

24LC04B/08B

FIGURE 8-2: CURRENT ADDRESS READ

FIGURE 8-3: RANDOM READ

24LC04B/08B

DS21051D-page 8  1995 Microchip Technology Inc.

8.3 Sequential Read

Sequential reads are initiated in the same way as a ran-

dom read except that after the 24LC04B/08B transmits

the ﬁrst data byte, the master issues an acknowledge

as opposed to a stop condition in a random read. This

directs the 24LC04B/08B to transmit the next sequen-

tially addressed 8 bit word (see Figure 9-1).

To provide sequential reads the 24LC04B/08B contains

an internal address pointer which is incremented by

one at the completion of each operation. This address

pointer allows the entire memory contents to be serially

read during one operation.

8.4 Noise Protection

The 24LC04B/08B employs a VCC threshold detector

circuit which disables the internal erase/write logic if

the VCC is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and ﬁlter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

9.0 PIN DESCRIPTIONS

9.1 SDA Serial Address/Data Input/Output

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pullup

resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400

kHz).

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

9.2 SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

9.3 WP

This pin must be connected to either VSS or VCC.

If tied to VSS, normal memory operation is enabled

(read/write the entire memory).

If tied to VCC, WRITE operations are inhibited. The

entire memory will be write-protected. Read opera-

tions are not affected.

This feature allows the user to use the 24LC04B/08B

as a serial ROM when WP is enabled (tied to VCC).

9.4 A0, A1, A2

These pins are not used by the 24LC04B/08B. They

may be left ﬂoating or tied to either VSS or VCC.

FIGURE 9-1: SEQUENTIAL READ

 1995 Microchip Technology Inc. DS21051D-page 9

24LC04B/08B

NOTES:

24LC04B/08B

DS21051D-page 10  1995 Microchip Technology Inc.

NOTES:

 1995 Microchip Technology Inc. DS21051D-page 11

24LC04B/08B

NOTES:

24LC04B/08B

DS21051D-page 12  1995 Microchip Technology Inc.

24LC04B/08B Product Identiﬁcation System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed

sales ofﬁces.

Package: P = Plastic DIP (300 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead

SN = Plastic SOIC (150 mil Body), 8-lead

SM = Plastic SOIC (207 mil Body), 8-lead

Temperature Blank = 0°C to +70°C

Range: I= -40°C to +85°C

Device: 24LC04B 4K CMOS Serial EEPROM

24LC04BT 4K CMOS Serial EEPROM (Tape and Reel)

24LC04B 8K CMOS Serial EEPROM

24LC04BT 8K CMOS Serial EEPROM (Tape and Reel)

24LC04B - /P

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Printed in the USA, 9/95

 1995, Microchip Technology Incorporated