R10DS0258EJ0101 Rev.1.01 Page 1 of 14
2020.02.20
RMLV1616A Series
16Mb Advanced LPSRAM (1M word × 16bit / 2M word x 8bit)
Description
The RMLV1616A Series is a family of 16-Mbit static RAMs organized 1,048,576-word × 16-bit, fabricated by
Renesas’s high-performance Advanced LPSRAM technologies. The RMLV1616A Series has realized higher density,
higher performance and low power consumption. The RMLV1616A Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It is offered in 48pin TSOP (I), 52pin TSOP (II) or 48-ball fine
pitch ball grid array.
Features
Single 3V supply: 2.7V to 3.6V
Access time: 55ns (max.)
Current consumption:
── Standby: 0.5µA (typ.)
Common data input and output
── Three state output
Directly TTL compatible
── All inputs and outputs
Battery backup operation
Part Name Information
Part Name Access time Temperature
Range Package
RMLV1616AGSA-5S2
55 ns -40 ~ +85°C
12mm x 20mm 48pin plastic TSOP (I)
RMLV1616AGSD-5S2 10.79mm × 10.49mm 52pin plastic µTSOP (II)
RMLV1616AGBG-5S2 48-ball FBGA with 0.75mm ball pitch
R10DS0258EJ0101
Rev.1.01
2020.02.20
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 2 of 14
2020.02.20
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
CS2
NC
UB#
LB#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CS1#
A0
48pin TSOP (I)
LB#
DQ15
DQ13
Vss
Vcc
DQ10
DQ8
A18
A
B
C
D
E
F
G
H
1 2 3 4 5 6
OE#
UB#
DQ14
DQ12
DQ11
DQ9
A19
A8
A0
A3
A5
A17
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CS1#
DQ1
DQ3
DQ4
DQ6
WE#
A11
CS2
DQ0
DQ2
Vcc
Vss
DQ5
DQ7
NC
48-ball FBGA (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
A15
A14
A13
A12
A11
A10
A9
A8
A19
CS1#
WE#
NC
NC
Vcc
CS2
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
UB#
Vss
LB#
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
NC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
NC
A0
52pin TSOP (II)
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 3 of 14
2020.02.20
Pin Description
Pin name Function
VCC Power supply
VSS Ground
A0 to A19 Address input (word mode)
A-1 to A19 Address input (byte mode)
DQ0 to DQ15 Data input/output
CS1# Chip select 1
CS2 Chip select 2
OE# Output enable
WE# Write enable
LB# Lower byte select
UB# Upper byte select
BYTE# Byte control mode enable
NC No connection
Block Diagram
Memory Array
1048576 Words
x 16BITS
OR
2097152 Words
x 8BITS
DECODER
ADDRESS BUFFER
CLOCK
GENERATOR
x8/x16
SWITCHING
CIRCUIT
CS2
CS1#
LB#
UB#
A0
A19
WE#
OE#
BYTE#
SENSE Amp. SENSE Amp.
OUTPUT
BUFFER
DATA INPUT
BUFFER
OUTPUT
BUFFER
DATA INPUT
BUFFER
DQ0
DQ7
DQ8
DQ15
/ A-1
Vcc
Vss
DATA SELECTOR
DATA SELECTOR
Note 1. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 4 of 14
2020.02.20
Operation Table
CS1# CS2 BYTE# UB# LB# WE# OE# DQ0~7 DQ8~14 DQ15 Operation
H X X X X X X High-Z High-Z High-Z Stand-by
X L X X X X X High-Z High-Z High-Z Stand-by
X X H H H X X High-Z High-Z High-Z Stand-by
L H H H L L X Din High-Z High-Z Write in lower byte
L H H H L H L Dout High-Z High-Z Read in lower byte
L H H H L H H High-Z High-Z High-Z Output disable
L H H L H L X High-Z Din Din Write in upper byte
L H H L H H L High-Z Dout Dout Read in upper byte
L H H L H H H High-Z High-Z High-Z Output disable
L H H L L L X Din Din Din Word write
L H H L L H L Dout Dout Dout Word read
L H H L L H H High-Z High-Z High-Z Output disable
L H L X X L X Din High-Z A-1 Byte write
L H L X X H L Dout High-Z A-1 Byte read
L H L X X H H High-Z High-Z A-1 Output disable
Note 2. H: VIH L:V
IL X: V
IH or VIL
3. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
48-ball FBGA type equals BYTE#=H mode.
Absolute Maximum Ratings
Parameter Symbol Value unit
Power supply voltage relative to VSS V
CC -0.5 to +4.6 V
Terminal voltage on any pin relative to VSS V
T -0.5*4 to VCC+0.3*5 V
Power dissipation PT 0.7 W
Operation temperature Topr -40 to +85 °C
Storage temperature range Tstg -65 to +150 °C
Storage temperature range under bias Tbias -40 to +85 °C
Note 4. -2.0V for pulse ≤ 30ns (full width at half maximum)
5. Maximum voltage is +4.6V.
DC Operating Conditions
Parameter Symbol Min. Typ. Max. Unit Note
Supply voltage VCC 2.7 3.0 3.6 V
VSS 0 0 0 V
Input high voltage VIH 2.2 ─ V
CC+0.3 V
Input low voltage VIL -0.3 ─ 0.6 V 6
Ambient temperature range Ta -40 ─ +85 °C
Note 6. -2.0V for pulse ≤ 30ns (full width at half maximum)
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 5 of 14
2020.02.20
DC Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions*7
Input leakage current | ILI | ─ ─ 1
A Vin = VSS to VCC
Output leakage current
| ILO | ─ ─ 1
A
CS1# = VIH or CS2 = VIL or OE# = VIH
or WE# = VIL or LB# = UB# = VIH,
VI/O = VSS to VCC
Average operating current
ICC1 ─ 23*8 30 mA
Cycle = 55ns, duty =100%, II/O = 0mA,
CS1# = VIL, CS2 = VIH, Others = VIH/VIL
ICC2 ─ 1.6*8 4 mA
Cycle = 1s, duty =100%, II/O = 0mA,
CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V,
VIH ≥ VCC-0.2V, VIL ≤ 0.2V
Standby current ISB ─ ─ 0.3 mA CS2 = VIL, Others = VSS to VCC
Standby current
ISB1
─ 0.5*8 3 A ~+25°C Vin = VSS to VCC,
(1) CS2 ≤ 0.2V or
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V
─ 0.8*9 5 A ~+40°C
─ 2.5*10 12 A ~+70°C
─ 5
*11 16
A ~+85°C
Output high voltage VOH 2.4 ─ ─ V IOH = -1mA
VOH2 Vcc - 0.2 ─ ─ V IOH = -0.1mA
Output low voltage VOL ─ ─ 0.4 V IOL = 2mA
VOL2 ─ ─ 0.2 V IOL = 0.1mA
Note 7. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V or BYTE# ≤ 0.2V
8. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
9. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.
10. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=70ºC), and not 100% tested.
11. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=85ºC), and not 100% tested.
Capacitance
(Ta =25°C, f =1MHz)
Parameter Symbol Min. Typ. Max. Unit Test conditions Note
Input capacitance C in ─ ─ 8 pF Vin =0V 12
Input / output capacitance C I/O ─ ─ 10 pF VI/O =0V 12
Note 12. This parameter is sampled and not 100% tested.
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 6 of 14
2020.02.20
AC Characteristics
Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C)
Input pulse levels:
VIL = 0.4V, VIH = 2.4V
Input rise and fall time: 5ns
Input and output timing reference level: 1.4V
Output load: See figures (Including scope and jig)
Read Cycle
Parameter Symbol Min. Max. Unit Note
Read cycle time tRC 55 ns
Address access time tAA ─ 55 ns
Chip select access time tACS1 ─ 45 ns
tACS2 ─ 45 ns
Output enable to output valid tOE ─ 22 ns
Output hold from address change tOH 10 ─ ns
LB#, UB# access time tBA ─ 45 ns
Chip select to output in low-Z tCLZ1 10 ─ ns 13,14
tCLZ2 10 ─ ns 13,14
LB#, UB# enable to low-Z tBLZ 5 ─ ns 13,14
Output enable to output in low-Z tOLZ 5 ─ ns 13,14
Chip deselect to output in high-Z tCHZ1 0 18 ns 13,14,15
tCHZ2 0 18 ns 13,14,15
LB#, UB# disable to high-Z tBHZ 0 18 ns 13,14,15
Output disable to output in high-Z tOHZ 0 18 ns 13,14,15
Note 13. This parameter is sampled and not 100% tested.
14 At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is
less than tCLZ2 min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device.
15. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not
referred to the DQ levels.
DQ
1.4V
RL = 500 ohm
CL = 30 pF
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 7 of 14
2020.02.20
Write Cycle
Parameter Symbol Min. Max. Unit Note
Write cycle time tWC 55 ─ ns
Address valid to write end tAW 35 ─ ns
Chip select to write end tCW 35 ─ ns
Write pulse width tWP 35 ─ ns 16
LB#,UB# valid to write end tBW 35 ─ ns
Address setup time to write start tAS 0 ─ ns
Write recovery time from write end tWR 0 ─ ns
Data to write time overlap tDW 25 ─ ns
Data hold from write end tDH 0 ─ ns
Output enable from write end tOW 5 ─ ns 17
Output disable to output in high-Z tOHZ 0 18 ns 17,18
Write to output in high-Z tWHZ 0 18 ns 17,18
Note 16. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
17. This parameter is sampled and not 100% tested.
18. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to
the DQ levels.
BYTE# Timing Conditions (BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types)
Parameter Symbol Min. Max. Unit Note
Byte setup time tBS 5 - ms
Byte recovery time tBR 5 - ms
BYTE# Timing Waveforms
CS2
BYTE#
tBS t
BR
CS1#
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 8 of 14
2020.02.20
Timing Waveforms
Read Cycle*19
Note 19. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode)
20. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not
referred to the DQ levels.
21. This parameter is sampled and not 100% tested.
22. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is
less than tCLZ2 min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device.
tAA
CS1#
tOH
tCLZ1
tACS1
tOE
tOLZ
tCHZ1
OE#
WE# VIH
tOHZ
WE# = “H” level
tRC
tBLZ tBHZ
LB#,UB#
tBA
CS2 tACS2
tCLZ2 tCHZ2
High impedance Valid Data
*21,22
*21,22
*21,22
*21,22
*20,21,22
*20,21,22
*20,21,22
*20,21,22
Valid address
A0~19
A -1~19
(Word Mode)
(Byte Mode)
DQ0~15
DQ0~7
(Word Mode)
(Byte Mode)
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 9 of 14
2020.02.20
Write Cycle (1)*23 (WE# CLOCK, OE#=”H” while writing)
Note 23. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode)
24. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
25. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to
the DQ levels.
26. This parameter is sampled and not 100% tested.
27. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins.
CS1#
tCW
tWHZ
OE#
WE#
tDH
tWC
LB#,UB#
tBW
CS2 tCW
Valid address
tWR
tAW
tAS
tWP
tDW
*24
*25,26
*25,26
tOHZ
Valid Data
*27
A0~19
A -1~19
(Word Mode)
(Byte Mode)
DQ0~15
DQ0~7
(Word Mode)
(Byte Mode)
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 10 of 14
2020.02.20
Write Cycle (2)*28 (WE# CLOCK, OE# Low Fixed)
Note 28. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode)
29. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
30. tWHZ is defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ
levels.
31. This parameter is sampled and not 100% tested.
32. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins.
CS1#
tCW
tWHZ
OE#
WE#
tDH
tWC
LB#,UB#
tBW
CS2 tCW
Valid address
tWR
tAW
tAS
tWP
tDW
tOW
*29
*30,31
VIL
OE# = “L” level
Valid Data
*32 *32
A0~19
A -1~19
(Word Mode)
(Byte Mode)
DQ0~15
DQ0~7
(Word Mode)
(Byte Mode)
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 11 of 14
2020.02.20
Write Cycle (3)*33 (CS1#, CS2 CLOCK)
Note 33. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode)
34. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
CS1#
tCW
OE#
WE#
tDH
tWC
LB#,UB#
tBW
CS2
Valid address
tWR
tAW
tAS
tWP
tDW
VIH
OE# = “H” level
tCW tAS
*34
Valid Data
Valid Data
A0~19
A -1~19
(Word Mode)
(Byte Mode)
DQ0~15
DQ0~7
(Word Mode)
(Byte Mode)
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 12 of 14
2020.02.20
Write Cycle (4)*35 (LB#, UB# CLOCK, Word Mode)
Note 35. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode)
36. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
CS1#
tCW
OE#
WE#
tDH
tWC
LB#,UB#
tBW
CS2
Valid address
tWR
tAW
tAS
tWP
tDW
VIH
OE# = “H” level
tCW
*36
Valid Data
A0~19
(Word Mode)
DQ0~15
(Word Mode)
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 13 of 14
2020.02.20
Low VCC Data Retention Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions*37,38
VCC for data retention VDR 1.5 ─ 3.6 V
Vin ≥ 0V
(1) CS2 ≤ 0.2V or
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V
Data retention current ICCDR
─ 0.5*39 3 A ~+25°C
VCC = 3.0V, Vin ≥ 0V
(1) CS2 ≤ 0.2V or
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V
─ 0.8*40 5 A ~+40°C
─ 2.5*41 12 A ~+70°C
─ 5
*42 16 A ~+85°C
Chip deselect time to data retention tCDR 0 ─ ─ ns
See retention waveform.
Operation recovery time tR 5 ─ ─ ms
Note 37. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V or BYTE# ≤ 0.2V
38. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB# buffer, UB# buffer and DQ buffer.
If CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, LB#, UB#, DQ) can be in the high
impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC-0.2V or CS2 ≤ 0.2V.
The other inputs levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high-impedance state.
39. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
40. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.
41. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=70ºC), and not 100% tested.
42. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=85ºC), and not 100% tested.
RMLV1616A Series
R10DS0258EJ0101 Rev.1.01 Page 14 of 14
2020.02.20
Low Vcc Data Retention Timing Waveforms (CS1# controlled)*43
Low Vcc Data Retention Timing Waveforms (CS2 controlled)*43
Low Vcc Data Retention Timing Waveforms (LB#,UB# controlled, Word Mode)*44
Note 43. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V or BYTE# ≤ 0.2V
44. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode)
LB#,UB#
VCC
LB#,UB# Controlled
tCDR tR
2.7V 2.7V
2.4V 2.4V
V
DR
LB#
,
UB# ≥
V
CC - 0.2V
CS1#
VCC
CS1# Controlled
tCDR tR
2.7V 2.7V
2.4V 2.4V
V
DR
CS1# ≥
V
CC - 0.2V
CS2
VCC
CS2 Controlled
tCDR tR
2.7V 2.7V
0.4V 0.4V
V
DR
CS2 ≤ 0.2V
All trademarks and registered trademarks are the property of their respective owners.
Revision History RMLV1616A Series Data Sheet
Rev. Date
Description
Page Summary
1.00 2016.01.06 ─ First Edition issued
1.01 2020.02.20 Last page Updated the Notice to the latest version
Corporate Headquarters
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
Contact Information
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
© 2020 Renesas Electronics Corporation. All rights reserved.
