3-Volt Advanced+ Boot Block Flash Memory 28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16) Datasheet Product Features Flexible SmartVoltage Technology -- 2.7 V-3.6 V Read/Program/Erase -- 12 V for Fast Production Programming 1.65 V-2.5 V or 2.7 V-3.6 V I/O Option -- Reduces Overall System Power High Performance -- 2.7 V-3.6 V: 70 ns Max Access Time Optimized Architecture for Code Plus Data Storage -- Eight 4-Kword Blocks, Top or Bottom Locations -- Up to One Hundred-Twenty-Seven 32Kword Blocks -- Fast Program Suspend Capability -- Fast Erase Suspend Capability Flexible Block Locking -- Lock/Unlock Any Block -- Full Protection on Power-Up -- WP# Pin for Hardware Block Protection -- VPP = GND Option -- VCC Lockout Voltage Low Power Consumption -- 9 mA Typical Read Power -- 7 A Typical Standby Power with Automatic Power Savings Feature 12 V Fast Production Program Extended Temperature Operation -- -40 C to +85 C 128-bit Protection Register -- 64-bit Unique Device Identifier -- 64-bit User Programmable OTP Cells Extended Cycling Capability -- Minimum 100,000 Block Erase Cycles Supports Intel(R) Flash Data Integrator Software -- Flash Memory Manager -- System Interrupt Manager -- Supports Parameter Storage, Streaming Data (e.g., voice) Automated Word/Byte Program and Block Erase -- Command User Interface -- Status Registers Cross-Compatible Command Support -- Intel Basic Command Set -- Common Flash Interface Standard Surface Mount Packaging -- 48-Ball CSP Packages -- 64-Ball Easy BGA Packages -- 48-Lead TSOP Package ETOXTM VIII (0.13 m) Flash Technology -- 16-, 32-Mbit ETOXTM VII (0.18 m) Flash Technology -- 16-, 32-, 64-Mbit ETOXTM VI (0.25 m) Flash Technology -- 8-, 16- and 32-Mbit The 3-Volt Advanced+ Book Block Flash memory, manufactured on Intel's latest 0.13 m and 0.18 m technologies, represents a feature-rich solution for low-power applications. 3-Volt Advanced+ Boot Block Flash memory devices incorporate low-voltage capability (2.7 V read, program, and erase) with high-speed, low-power operation. Flexible block locking allows any block to be independently locked or unlocked. Add to this the Intel(R) Flash Data Integrator (IFDI) software and you have a cost-effecive, flexible, monolithic code plus data storage solution. Intel(R) 3-Volt Advanced+ Boot Block products will be available in 48-lead TSOP, 48-ball CSP, and 64ball Easy BGA packages. Additional information on this product family can be obtained by accessing the Intel(R) Flash website: http://www.intel.com/design/flash. Notice: This specification is subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Order Number: 290645-014 April 2002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F800C3, 28F160C3, 28F320C3, 28F640C3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2002 *Third-party brands and names are the property of their respective owners. 2 Datasheet Contents Contents 1.0 Introduction ...............................................................................................................................7 1.1 1.2 1.3 Document Purpose ...............................................................................................................7 Nomenclature .......................................................................................................................7 Conventions..........................................................................................................................7 2.0 Device Description ..................................................................................................................8 2.1 2.2 Product Overview .................................................................................................................8 Product Overview .................................................................................................................9 3.0 Product Description .............................................................................................................10 3.1 3.2 Package Pinouts .................................................................................................................11 Block Organization..............................................................................................................17 3.2.1 Parameter Blocks ..................................................................................................17 3.2.2 Main Blocks ...........................................................................................................17 4.0 Principles of Operation .......................................................................................................17 4.1 4.2 4.3 4.4 4.5 Datasheet Bus Operation .....................................................................................................................17 4.1.1 Read ......................................................................................................................17 4.1.2 Output Disable .......................................................................................................18 4.1.3 Standby..................................................................................................................18 4.1.4 Reset .....................................................................................................................18 4.1.5 Write ......................................................................................................................19 Modes of Operation ............................................................................................................19 4.2.1 Read Array.............................................................................................................19 4.2.2 Read Configuration ................................................................................................20 4.2.3 Read Status Register.............................................................................................20 4.2.3.1 Clearing the Status Register ..................................................................21 4.2.4 Read Query ...........................................................................................................21 4.2.5 Program Mode .......................................................................................................21 4.2.5.1 Suspending and Resuming Program .....................................................21 4.2.6 Erase Mode ...........................................................................................................22 4.2.6.1 Suspending and Resuming Erase .........................................................22 Flexible Block Locking ........................................................................................................25 4.3.1 Locking Operation..................................................................................................26 4.3.1.1 Locked State ..........................................................................................26 4.3.2 Unlocked State ......................................................................................................26 4.3.3 Lock-Down State ...................................................................................................26 4.3.4 Reading Block-Lock Status....................................................................................27 4.3.5 Locking Operations during Erase Suspend ...........................................................27 4.3.6 Status Register Error Checking .............................................................................27 128-Bit Protection Register .................................................................................................28 4.4.1 Reading the Protection Register ............................................................................28 4.4.2 Programming the Protection Register....................................................................29 4.4.3 Locking the Protection Register .............................................................................29 VPP Program and Erase Voltages ......................................................................................29 4.5.1 Improved 12-Volt Production Programming...........................................................29 4.5.2 VPP VPPLK for Complete Protection .................................................................30 3 Contents 4.6 4.7 4.8 Power Consumption ........................................................................................................... 30 4.6.1 Active Power (Program/Erase/Read)..................................................................... 31 4.6.2 Automatic Power Savings (APS) ........................................................................... 31 4.6.3 Standby Power ...................................................................................................... 31 4.6.4 Deep Power-Down Mode....................................................................................... 31 Power and Reset Considerations ....................................................................................... 31 4.7.1 Power-Up/Down Characteristics............................................................................ 31 4.7.2 RP# Connected to System Reset .......................................................................... 32 4.7.3 VCC, VPP and RP# Transitions ............................................................................ 32 Power Supply Decoupling................................................................................................... 32 5.0 Electrical Specifications ..................................................................................................... 33 5.1 5.2 5.3 5.4 4.5 4.6 4.7 4.8 Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix 4 Absolute Maximum Ratings ................................................................................................ 33 Operating Conditions .......................................................................................................... 34 Capacitance........................................................................................................................ 34 DC Characteristics.............................................................................................................. 35 AC Characteristics--Read Operations ............................................................................... 38 AC Characteristics--Write Operations ............................................................................... 43 Erase and Program Timings ............................................................................................... 47 Reset Operations................................................................................................................ 49 A WSM Current/Next States, Sheet 1 of 2 ...................................................50 B Program/Erase Flowcharts .........................................................................52 C Common Flash Interface Query Structure..............................................58 D Architecture Block Diagram .......................................................................65 E Word-Wide Memory Map Diagrams ..........................................................66 F Device ID Table ...............................................................................................70 G Protection Register Addressing................................................................71 H VF Pitch BGA Package Drawing and Dimensions................................72 I Easy BGA Package Drawing & Dimensions ............................................73 J Additional Information ..................................................................................74 K Ordering Information ....................................................................................75 Datasheet Contents Revision History Date of Revision Version 05/12/98 -001 Original version -002 48-Lead TSOP package diagram change BGA package diagrams change 32-Mbit ordering information change (Section 6) CFI Query Structure Output Table Change (Table C2) CFI Primary-Vendor Specific Extended Query Table Change for Optional Features and Command Support change (Table C8) Protection Register Address Change IPPD test conditions clarification (Section 4.3) BGA package top side mark information clarification (Section 6) 10/03/98 -003 Byte-Wide Protection Register Address change VIH Specification change (Section 4.3) VIL Maximum Specification change (Section 4.3) ICCS test conditions clarification (Section 4.3) Added Command Sequence Error Note (Table 7) Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash Memory Family. 12/04/98 -004 Added tBHWH/tBHEH and tQVBL (Section 4.6) Programming the Protection Register clarification (Section 3.4.2) 12/31/98 -005 Removed all references to x8 configurations 02/24/99 -006 Removed reference to 40-Lead TSOP from front page 06/10/99 -007 Added Easy BGA package (Section 1.2) Removed 1.8 V I/O references Locking Operations Flowchart changed (Appendix B) Added tWHGL (Section 4.6) CFI Primary Vendor-Specific Extended Query changed (Appendix C) 03/20/00 -008 04/24/00 -009 07/21/98 Description Max ICCD changed to 25 A Table 10, added note indicating VCCMax = 3.3 V for 32-Mbit device Added specifications for 0.18 micron product offerings throughout document Added 64-Mbit density Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product offering. 10/12/00 -010 Changed VccMax=3.3V reference to indicate that the affected product is the 0.25m 32Mbit device. Minor text edits throughout document. Added 1.8v I/O operation documentation where applicable Added TSOP PCN `Pin-1' indicator information Changed references in 8 x 8 BGA pinout diagrams from `GND' to `Vssq' 7/20/01 -011 Added `Vssq' to Pin Descriptions Information Removed 0.4 m references in DC characteristics table Corrected 64Mb package Ordering Information from 48-uBGA to 48-VFBGA Corrected `bottom' boot block sizes to on 8Mb device to 8 x 4KWords Minor text edits throughout document Datasheet 5 Contents Date of Revision Version 10/02/01 -012 2/05/02 -013 Description Added specifications for 0.13 micron product offerings throughout document Corrected Iccw / Ippw / Icces /Ippes values. Added mechanicals for 16Mb and 64Mb Minor text edits throughout document. Updated 64Mb product offerings. Updated 16Mb product offerings. 4/05/02 -014 Revised and corrected DC Characteristics Table. Added mechanicals for Easy BGA. Minor text edits throughout document. 6 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 1.0 Introduction 1.1 Document Purpose This document contains the specifications for the 3-Volt Advanced+ Boot Block Flash Memory family. These flash memories add features, such as instant block locking and a protection register, that can be used to enhance the security of systems. 1.2 Nomenclature 0x 0b k (noun) M (noun) Nibble Byte Word Dword Kword Mword Kb KB Mb MB APS CUI OTP PR PRD PLR RFU SCSP SR SRD WSM XSR MLC 1.3 Hexadecimal prefix Binary prefix 1 thousand 1 million 4 bits 8 bits 16 bits Double word = 32 bits 1024 words 1,048,576 words 1024 bits 1024 bytes 1,048,576 bits 1,048,576 bytes Automatic Power Savings Command User Interface One Time Programmable Protection Register Protection Register Data Protection Lock Register Reserved for Future Use Stacked Chip Scale Package Status Register Status Register Data Write State Machine eXtended Status Register Multi-Level Cell Conventions Group Membership Brackets: Square brackets will be used to designate group membership or to define a group of signals with similar function (I.E. A[21:1], SR[4,1] ) VPEN vs. VPEN: When the reference is signal or package connection name, the notation will be VPEN (specifically VPEN[2:1] or VPEN2 and VPEN1). When the reference is timing or level, the notation will be VPEN only. Datasheet 7 28F800C3, 28F160C3, 28F320C3, 28F640C3 [opt. - multi-die use]Device: This term is used interchangeably throughout this document to denote either the particular die, or the combination of the two die. [opt. - multi-die use]Status Register: Each die has its own status register (SR), read out on the lower 8 bits of each die's data bus. SR[23:16], the valid status bits for die #2 (upper die) are read on device outputs D[23:16]; bits SR[31:24] are RFU. SR[7:0], the valid status bits for die #1 (lower die) are read on device outputs D[7:0]; bits SR[15:8] are RFU. [opt. - multi-die use]CE#[2:1]: This method of referring to the two chip enable inputs will be used in the document when considering them as a single entity. When considered singly, they will be referenced as CE#1 (die #1 chip enable) and CE#2 (die #2 chip enable). 2.0 Device Description This section provides an overview of the 3-Volt Advanced+ Boot Block Flash Memory features, packaging information , signal names and device architecture 2.1 Product Overview The 3-Volt Advanced+ Boot Block Flash Memory product lineis a high perfomance memory utilizes reliable and proven ETOXTM technology This family of products features 1.65 V - 2.5 V or 2.7 V-3.6 V I/Os and a low VCC/VPP operating range of 2.7 V-3.6 V for Read, Program, and Erase operations. In addition, this family is capable of fast programming at 12 V. The 3-Volt Advanced+ Boot Block flash memory features include the following: * Zero-latency, flexible block locking * 128-bit Protection Register * Simple system implementation for 12-V production programming with 2.7-V, in-field programming * Ultra low-power operation at 2.7 V * VCCQ input of 1.65 V-2.5 V on all I/Os. See Figures 1 through 4 for pinout diagrams and VCCQ location * Minimum 100,000 block erase cycles * Common Flash Interface for software query of device specs and features Table 1. 3-Volt Advanced+ Boot Block Feature Summary (Sheet 1 of 2) 8 Mbit(1), 16 Mbit, 32 Mbit(2) Feature (3) VCC Operating Voltage 2.7 V - 3.6 V VPP Voltage Provides complete write protection with optional 12 V Fast Programming VCCQ I/O Voltage 1.65 V - 2.5 V or 2.7 V - 3.6 V Bus Width 16-bit Reference Table 8 Table 8 Table 2 8 Mbit: 90, 110 @ 2.7 V and 80, 100 @ 3.0 V Speed (ns) 16 Mbit: 70, 80, 90, 110 @ 2.7 V and 70, 80, 100 @ 3.0 V 32 Mbit: 70, 90, 100, 110 @ 2.7 V and 70, 90, 100 @ 3.0 V Section 5.4 64 Mbit: 80, 100 @ 2.7 V and 80, 100 @ 3.0 V 8 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 1. 3-Volt Advanced+ Boot Block Feature Summary (Sheet 2 of 2) 8 Mbit(1), 16 Mbit, 32 Mbit(2) Feature Reference 8 x 4-Kword parameter 8-Mb: 15 x 32-Kword main 16-Mb: 31 x 32-Kword main 32-Mb: 63 x 32-Kword main 64-Mb: 127 x 32-Kword main Appendix 3.2 Appendix E Operating Temperature Extended: -40 C to +85 C Table 8 Program/Erase Cycling 100,000 cycles Table 8 Packages 48-Lead TSOP 48-Ball BGA* CSP (1), 48-Ball VF BGA, Easy BGA Figure 1, 2 and 3 Block Locking Flexible locking of any block with zero latency Section 4.3 Protection Register 64-bit unique device number, 64-bit user programmable Section 4.4 Blocking (top or bottom) NOTES: 1. 8-Mbit density not available in BGA* CSP. 2. See Specification Update for changes to 32-Mbit devices (order 297938). 3. VCCMax = 3.3 V on 0.25m 32-Mbit devices. 2.2 Product Overview Intel provides secure low voltage memory solutions with the Advanced Boot Block family of products. A new block locking feature allows instant locking/unlocking of any block with zero latency. A 128-bit protection register allows unique flash device identification. Discrete supply pins provide single voltage read, program, and erase capability at 2.7 V, while also allowing 12-V VPP for faster production programming. Improved 12 V, a new feature designed to reduce external logic, simplifies board designs when combining 12-V production programming with 2.7-V in-field programming. The 3-Volt Advanced+ Boot Block flash memory products are available in x16 packages in the following densities: (see Section A, "Ordering Information" on page 50) * * * * 8-Mbit (8, 388, 608 bit) flash memories organized as 512 Kwords of 16 bits each 16-Mbit (16, 777, 216 bit) flash memories organized as 1024 Kwords of 16 bits each 32-Mbit (33, 554, 432 bit) flash memories organized as 2048 Kwords of 16 bits each 64-Mbit (67, 108, 864 bit) flash memories organized as 4096 Kwords of 16 bits each. Eight 4-Kword parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The remaining memory is grouped into 64-Kbyte main blocks (see Appendix E). All blocks can be locked or unlocked instantly to provide complete protection for code or data (see Section 4.3, "Flexible Block Locking" on page 25 for details). The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for Program and Erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block-erase or word program completion and status. Datasheet 9 28F800C3, 28F160C3, 28F320C3, 28F640C3 Program and erase automation allows Program and Erase operations to be executed using an industry-standard two-write command sequence to the CUI. Program operations are performed in word increments. Erase operations erase all locations within a block simultaneously. Both Program and Erase operations can be suspended by the system software in order to read from any other block. In addition, data can be programmed to another block during an erase suspend. The 3-Volt Advanced+ Boot Block flash memories offer two low-power savings features: Automatic Power Savings (APS), and standby mode. The device automatically enters APS mode following the completion of a read cycle. Standby mode is initiated when the system deselects the device by driving CE# inactive. Combined, these two power-savings features significantly reduce power consumption. The device can be reset by lowering RP# to GND, which provides CPU memory reset synchronization and additional protection against bus noise that may occur during system reset and power-up/down sequences (see Section 4.5 and Section 4.6). Refer to Section 5.4, "DC Characteristics" on page 35 for complete current and voltage specifications. Refer to Section 4.5 and Section 4.6 for read and write performance specifications. Section 4.7 shows program and erase times. 3.0 Product Description This section provides device pin descriptions and package pinouts for the 3-Volt Advanced+ Boot Block Flash Memory family, which is available in 48-lead TSOP (x16) and 48-ball BGA and Easy BGA packages (Figures 1, 2 and 3, respectively). 10 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 3.1 Package Pinouts Figure 1. 48-Lead TSOP Package 64 M 32 M 16 M A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE# RP# VPP WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Advanced+ Boot Block 48-Lead TSOP 12 mm x 20 mm TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VCCQ GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0 0645_02 Note: Datasheet Lower densities will have NC on the upper address pins. For example, a 16-Mbit device will have NC on Pins 9 and 10. 11 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 2. New Mark for Pin-1 indicator on 48-Lead 8Mb, 16Mb and 32Mb TSOP Current Mark: New Mark: Note: 12 The topside marking on 8 Mb, 16 Mb, and 32 Mb Advanced and Advanced + Boot Block 48L TSOP products will convert to a white ink triangle as a Pin 1 indicator. Products without the white triangle will continue to use a dimple as a Pin 1 indicator. There are no other changes in package Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 size, materials, functionality, customer handling, or manufactuability. Product will continue to meet Intel stringent quality requirements. Products Affected are Intel Ordering Codes: 48-Lead TSOP TE28F320C3TC70 TE28F320C3BC70 Extended 32 Mbit TE28F320C3TC90 TE28F320C3BC90 TE28F320C3TA100 TE28F320C3BA100 TE28F320C3TA110 TE28F320C3BA110 TE28F160C3TC70 TE28F160C3BC70 Extended 16 Mbit TE28F160C3TC80 TE28F160C3BC80 TE28F160C3TA90 TE28F160C3BA90 TE28F160C3TA110 TE28F160C3BA110 Extended 8 Mbit Datasheet TE28F800C3TA90 TE28F800C3BA90 TE28F800C3TA110 TE28F800C3BA110 13 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 3. 48-Ball BGA* and 48-Ball Very Fine Pitch BGA Chip Size Package (Top View, Ball Down) 1 2 3 4 5 6 7 8 16M A A13 A11 A8 VPP WP# A19 A7 A4 B A14 A10 WE# RP# A18 A17 A5 A2 64M 32M C A15 A12 A9 A21 A20 A6 A3 A1 D A16 D14 D5 D11 D2 D8 CE# A0 E VCCQ D15 D6 D12 D3 D9 D0 GND F GND D7 D13 D4 VCC D10 D1 OE# NOTE: Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Routing is not recommended in this area. A19 is the upgrade address for the 16-Mbit device. A20 is the upgrade address for the 32-Mbit device. A21 is the upgrade address for the 64-Mbit device. 4-Mbit density not available in BGA CSP. 14 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 4. 8 x 8 Easy BGA Package 1 2 3 4 5 6 7 8 A 8 7 6 5 4 3 2 1 VPP A18 A A1 A6 A18 VPP VCC GND A10 A15 B A15 A10 GND VCC A6 A1 A14 A11 A20(1) DU RP# A19(1) A17 A2 A13 A12 A21(1) DU WE# WP# A7 A3 A9 A8 A4 B A2 A17 A19(1) RP# DU A20(1) A11 A14 C C A3 A7 WP# WE# DU A21(1) A12 A13 D D A4 A5 DU DU DU A8 A9 DQ8 DQ1 DQ9 DQ3 DQ12 DQ6 DU DU DU E DU DU DU DU A5 E F DU DU DQ6 DQ12 DQ3 DQ9 DQ1 DQ8 DU DU DQ14 DQ5 DQ11 DQ10 DQ0 CE# F CE# DQ0 DQ10 DQ11 DQ5 DQ14 DU DU G G A0 VSSQ DQ2 DQ4 DQ13 DQ15 VSSQ A16 H A16 VSSQ D15 D13 DQ4 DQ2 VSSQ A0 DU VCCQ D7 VSSQ VCC VCCQ OE# A22(2) H A22(2) OE# VCCQ VCC VSSQ DQ7 VCCQ Top View- Ball Side DU Bottom View - Ball Side 16fast NOTES: 1. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit. 2. A22 indicates future density upgrade path to128 Mbit (not yet available). Datasheet 15 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 2. Symbol A0-A21 3-Volt Advanced+ Boot Block Pin Descriptions Type INPUT Name and Function ADDRESS INPUTS: Memory addresses are internally latched during a program or erase cycle. 8-Mbit: A[0-18], 16-Mbit: A[0-19], 32-Mbit: A[0-20], 64-Mbit: A[0-21] DQ0-DQ7 INPUT/ OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. Outputs array, configuration and status register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. DQ8-DQ15 INPUT/ OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. Outputs array and configuration data. The data pins float to tri-state when the chip is de-selected. CE# INPUT CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. OE# INPUT OUTPUT ENABLE: Enables the device's outputs through the data buffers during a Read operation. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the command register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse. INPUT RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep powerdown mode. When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD). When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. RP# WRITE PROTECT: Controls the lock-down function of the flexible locking feature. When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. WP# INPUT VCC SUPPLY When WP# is logic high, the lock-down mechanism is disabled and blocks previously lockeddown are now locked and can be unlocked and locked through software. After WP# goes low, any blocks previously marked lock-down revert to that state. See Section 4.3 for details on block locking. VCCQ INPUT DEVICE POWER SUPPLY: [2.7 V-3.6 V] Supplies power for device operations. I/O POWER SUPPLY: Enables all outputs to be driven to 1.8 V - 2.5 V while the VCC is at 2.7 V- 3.3 V. If the VCC is regulated to 2.7 V-2.85 V, VCCQ can be driven at 1.65 V-2.5 V to achieve lowest power operation (see Section 5.4). This input may be tied directly to VCC (2.7 V-3.6 V). PROGRAM/ERASE POWER SUPPLY: [1.65 V-3.6 V or 11.4 V-12.6 V] Operates as a input at logic levels to control complete device protection. Supplies power for accelerated Program and Erase operations in 12 V 5% range. This pin cannot be left floating. Lower VPP VPPLK, to protect all contents against Program and Erase commands. VPP INPUT/ SUPPLY Set VPP = VCC for in-system Read, Program and Erase operations. In this configuration, VPP can drop as low as 1.65 V to allow for resistor or diode drop from the system supply. Note that if VPP is driven by a logic signal, VIH = 1.65. That is, VPP must remain above 1.65 V to perform insystem flash modifications. Raise VPP to 12 V 5% for faster program and erase in a production environment. Applying 12 V 5% to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 4.4 for details on VPP voltage configurations. VSSQ SUPPLY GROUND: For all internal circuitry. All VSSQ inputs must be connected. Same function as GND. GND SUPPLY GROUND: For all internal circuitry. All ground inputs must be connected. NC 16 NO CONNECT: Pin may be driven or left floating. Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 3.2 Block Organization The 3-Volt Advanced+ Boot Block is an asymmetrically blocked architecture that enables system integration of code and data within a single flash device. Each block can be erased independently of the others up to 100,000 times. For the address locations of each block, see the memory maps in Appendix E. 3.2.1 Parameter Blocks The 3-Volt Advanced+ Boot Block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters (i.e., data that would normally be stored in an EEPROM). Each device contains eight parameter blocks of 4 Kwords (4,096 words). 3.2.2 Main Blocks After the parameter blocks, the remainder of the array is divided into 32-Kword (32,768 words) main blocks for data or code storage. Each 8-Mbit, 16-Mbit, 32-Mbit, or 64-Mbit device contains 15, 31, 63, or 127 main blocks, respectively. 4.0 Principles of Operation The 3-Volt Advanced+ Boot Block flash memory family uses a CUI and automated algorithms to simplify Program and Erase operations. The CUI allows for 100% CMOS-level control inputs and fixed power supplies during erasure and programming. The internal WSM completely automates Program and Erase operations while the CUI signals the start of an operation and the status register reports status. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation. 4.1 Bus Operation The 3-Volt Advanced+ Boot Block flash memory devices read, program, and erase in-system via the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component: CE#, OE#, WE#, and RP#. Table 3 on page 18 summarizes these bus operations. 4.1.1 Read The flash memory has four read modes available: read array, read configuration, read status, and read query. These modes are accessible independent of the VPP voltage. The appropriate Read Mode command must be issued to the CUI to enter the corresponding mode. Upon initial device power-up or after exit from reset, the device automatically defaults to read-array mode. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control; when active it enables the flash memory device. OE# is the data output control, and it drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at VIH. Figure 9, "AC Waveform: Read Operations" on page 42 illustrates a read cycle. Datasheet 17 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.1.2 Output Disable With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins are placed in a high-impedance state. 4.1.3 Standby Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during Program or Erase operation, the device continues to consume active power until the Program or Erase operation is complete. Table 3. Bus Operations Mode Notes RP# CE# OE# WE# DQ0-7 DQ8-15 Read (Array, Status, Configuration, or Query) 1, 2,3 VIH VIL VIL VIH DOUT DOUT Output Disable 1 VIH VIL VIH VIH High Z High Z Standby 1 VIH VIH X X High Z High Z Reset 1,4 VIL X X X High Z High Z Write 1,4,5,6 VIH VIL VIH VIL DIN DIN NOTES: 1. X must be VIL, VIH for control pins and addresses. 2. See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, voltages. 3. Manufacturer and device codes may also be accessed in read-configuration mode (A1-A20 = 0). See Table 4 on page 20. 4. To program or erase the lockable blocks, hold WP# at VIH. 5. Refer to Table 5 on page 23 for valid DIN during a Write operation. 6. RP# must be at GND 0.2 V to meet the maximum deep power-down current specified. 8-bit devices use only DQ [0:7], 16-bit devices use DQ [0:15]. 4.1.4 Reset From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a highimpedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required until the initial read-access outputs are valid. A delay (tPHWL or tPHEL) is required after return from reset before a write can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read-array mode, the status register is set to 80H, and all blocks are locked. Figure 11, "AC Waveform: Reset Operations" on page 49 (section A) illustrates this case. If RP# is taken low for time tPLPH during a Program or Erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence: 1. When RP# goes low, the device shuts down the operation in progress, a process which takes time tPLRH to complete. 2. After this time tPLRH, the part will either reset to read-array mode (if RP# has gone high during tPLRH, Figure 11, section B) or enter reset mode (if RP# is still logic low after tPLRH, Figure 11, section C). 18 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 3. In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/ tPHEL must be observed before a Read or Write operation is initiated, as discussed in the previous paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when RP# goes high. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, the processor expects to read from the flash memory. Automated flash memories provide status information when read during program or Block-Erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel(R) Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 4.1.5 Write A write occurs when both CE# and WE# are low and OE# is high. Commands are written to the Command User Interface (CUI) using standard microprocessor write timings to control Flash operations. The CUI does not occupy an addressable memory location. The address and data buses are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. See Figure 10, "AC Waveform: Program and Erase Operations" on page 48. The available commands are shown in Table 6 on page 24, and Appendix A provides detailed information on moving between the different modes of operation using CUI commands. Two commands modify array data: Program (40H), and Erase (20H). Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internally timed functions that culminate in the completion of the requested task (unless that operation is aborted by either RP# being driven to VIL for tPLRH or an appropriate Suspend command). 4.2 Modes of Operation The flash memory has four read modes (read array, read configuration, read status, and read query), and two write modes (program and erase). Three additional modes (erase suspend to program, erase suspend to read, and program suspend to read) are available only during suspended operations. Tables 5 and 6 summarize the commands used to reach these modes. Appendix A is a comprehensive chart showing the state transitions. 4.2.1 Read Array When RP# transitions from VIL (reset) to VIH, the device defaults to read-array mode and will respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI commands. When the device is in read array mode, four control signals control data output. * * * * Datasheet WE# must be logic high (VIH) CE# must be logic low (VIL) OE# must be logic low (VIL) RP# must be logic high (VIH) 19 28F800C3, 28F160C3, 28F320C3, 28F640C3 In addition, the address of the desired location must be applied to the address pins. If the device is not in read-array mode, as would be the case after a Program or Erase operation, the Read Array command (FFH) must be written to the CUI before array reads can occur. 4.2.2 Read Configuration The read-configuration mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. The device is switched to this mode by writing the Read Configuration command (90H). Once in this mode, read cycles from addresses shown in Table 4 retrieve the specified information. To return to read-array mode, write the Read Array command (FFH). Table 4. Read Configuration Table Item Address Data Manufacturer Code (x16) 00000 0089 Device ID (See Appendix F) 00001 ID (1) Block Lock Configuration XX002 (2) LOCK * Block Is Unlocked DQ0 = 0 * Block Is Locked DQ0 = 1 * Block Is Locked-Down DQ1 = 1 (3) Protection Register Lock 80 PR-LK Protection Register (x16) 81-88 PR NOTES: 1. See Section 4.3.4 for valid lock-status outputs. 2. "XX" specifies the block address of lock configuration being read. 3. See Section 4.4 for protection register information. 4. Other locations within the configuration address space are reserved by Intel for future use. 4.2.3 Read Status Register The status register indicates the status of device operations, and the success/failure of that operation. The Read Status Register (70H) command causes subsequent reads to output data from the status register until another command is issued. To return to reading from the array, issue a Read Array (FFH) command. The status-register bits are output on DQ0-DQ7. The upper byte, DQ8-DQ15, outputs 00H during a Read Status Register command. The contents of the status register are latched on the falling edge of OE# or CE# (whichever occurs last), which prevents possible bus errors that might occur if status register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the status register will not indicate completion of a Program or Erase operation. When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status register indicate whether the WSM was successful in performing the preferred operation (see Table 7, "Status Register Bit Definition" on page 25). 20 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.2.3.1 Clearing the Status Register The WSM sets status bits 1 through 7 to "1," and clears bits 2, 6, and 7 to "0," but cannot clear status bits 1 or 3 through 5 to "0." Because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. Clear the status register before beginning another command or sequence. Note that this is different from a burst device. The Read Array command must be issued before data can be read from the memory array. Resetting the device also clears the status register. 4.2.4 Read Query The read-query mode outputs Common Flash Interface (CFI) data when the device is read, and can be accessed by writing the Read Query Command (98H). The CFI data structure contains information such as block size, density, command set, and electrical specifications. Once in this mode, read cycles from addresses shown in Appendix C retrieve the specified information. To return to read-array mode, write the Read Array command (FFH). 4.2.5 Program Mode Programming is executed using a two-write sequence. The Program Setup command (40H) is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to program preferred bits of the addressed location, then verify the bits are sufficiently programmed. Programming the memory results in specific bits within an address location being changed to a "0." If users attempt to program "1"s, the memory cell contents do not change and no error occurs. The status register indicates programming status: while the program sequence executes, status bit 7 is "0." The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume. When programming is complete, the program-status bits should be checked. If the programming operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If SR.3 is set, then VPP was not within acceptable limits, and the WSM did not execute the program command. If SR.1 is set, a program operation was attempted on a locked block and the operation was aborted. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status-register reads, be sure to reset the CUI to read-array mode. 4.2.5.1 Suspending and Resuming Program The Program Suspend command halts an in-progress program operation so that data can be read from other locations of memory. Once the programming process starts, writing the Program Suspend command to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). The device continues to output status-register data after the Program Suspend command is written. Polling status-register bits SR.7 and SR.2 will determine when the program operation has been suspended (both will be set to "1"). tWHRH1/ tEHRH1 specify the program-suspend latency. Datasheet 21 28F800C3, 28F160C3, 28F320C3, 28F640C3 A Read Array command can now be written to the CUI to read data from blocks other than that which is suspended. The only other valid commands while program is suspended are Read Status Register, Read Configuration, Read Query, and Program Resume. After the Program Resume command is written to the flash memory, the WSM will continue with the programming process and status register bits SR.2 and SR.7 will automatically be cleared. The device automatically outputs status register data when read (see Figure 13, "Program Suspend/Resume Flowchart" on page 53) after the Program Resume command is written. VPP must remain at the same VPP level used for program while in program-suspend mode. RP# must also remain at VIH. 4.2.6 Erase Mode To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to "1." Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to program all bits within the block to "0," erase all bits within the block to "1," then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a "0." When the status register indicates that erasure is complete, check the erase-status bit to verify that the Erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status register will be set to a "1," indicating an erase failure. If VPP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a "1" to identify that VPP supply voltage was not within acceptable limits. After an Erase operation, clear the status register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent statusregister reads, it is advisable to place the flash in read-array mode after the erase is complete. 4.2.6.1 Suspending and Resuming Erase Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from--or program data to-- another block in memory. Once the erase sequence is started, writing the Erase Suspend command to the CUI suspends the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the Erase operation has been suspended. Erase-suspend latency is specified by tWHRH2/tEHRH2. A Read Array/Program command can now be written to the CUI to read/program data from/to blocks other than that which is suspended. This nested Program command can subsequently be suspended to read yet another location. The only valid commands while Erase is suspended are Read Status Register, Read Configuration, Read Query, Program Setup, Program Resume, Erase Resume, Lock Block, Unlock Block, and Lock-Down Block. During erase-suspend mode, the chip can be placed in a pseudo-standby mode by taking CE# to VIH, which reduces active current consumption. Erase Resume continues the erase sequence when CE# = VIL. Similar to the end of a standard Erase operation, the status register must be read and cleared before the next instruction is issued. 22 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 5. Command Bus Operations First Bus Cycle Command Second Bus Cycle Notes Oper Addr Data 1 Write X FFH Read Configuration 1, 2 Write X Read Query 1, 2 Write X Read Array Oper Addr Data 90H Read IA ID 98H Read QA QD Read X SRD Read Status Register 1 Write X 70H Clear Status Register 1 Write X 50H 1, 3 Write X 40H/10H Write PA PD Block Erase/Confirm 1 Write X 20H Write BA D0H Program/Erase Suspend 1 Write X B0H Program/Erase Resume 1 Write X D0H Lock Block 1 Write X 60H Write BA 01H Unlock Block 1 Write X 60H Write BA D0H Program Lock-Down Block 1 Write X 60H Write BA 2FH Protection Program 1 Write X C0H Write PA PD X = "Don't Care" PA = Prog Addr SRD = Status Reg. Data PD = Prog Data BA = Block Addr IA = Identifier Addr. QA = Query Addr. ID = Identifier Data QD = Query Data NOTES: 1. Following the Read Configuration or Read Query commands, Read operations output device configuration or CFI query information, respectively. See Section 4.2.2 and Section 4.2.4. 2. Either 40H or 10H command is valid, but the Intel standard is 40H. 3. When writing commands, the upper data bus [DQ8-DQ15] should be either VIL or VIH, to minimize current draw. Bus operations are defined in Table 3, "Bus Operations" on page 18. Datasheet 23 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 6. Command Codes and Descriptions Code Device Mode FF Read Array 40 20 D0 Description This command places the device in read-array mode, which outputs array data on the data pins. Program Set-Up This is a two-cycle command. The first cycle prepares the CUI for a program operation. The second cycle latches addresses and data information and initiates the WSM to execute the Program algorithm. The flash outputs status-register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 4.2.5. Erase Set-Up Prepares the CUI for the Erase Confirm command. If the next command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a "1," (b) place the device into the read-status-register mode, and (c) wait for another command. See Section 4.2.6. Erase Confirm If the previous command was an Erase Set-Up command, then the CUI will close the address and data latches and begin erasing the block indicated on the address pins. During program/ erase, the device will respond only to the Read Status Register, Program Suspend and Erase Suspend commands, and will output status-register data when CE# or OE# is toggled. Program/Erase Resume Unlock Block If a Program or Erase operation was previously suspended, this command will resume that operation. If the previous command was Configuration Set-Up, the CUI will latch the address and unlock the block indicated on the address pins. If the block had been previously set to Lock-Down, this operation will have no effect. (Section 4.3) Issuing this command will begin to suspend the currently executing Program/Erase operation. The status register will indicate when the operation has been successfully suspended by setting either the program-suspend (SR.2) or erase-suspend (SR.6) and the WSM status bit (SR.7) to a "1" (ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input-control pins except RP#, which will immediately shut down the WSM and the remainder of the chip if RP# is driven to VIL. See Sections 3.2.5.1 and 3.2.6.1. B0 Program Suspend Erase Suspend 70 Read Status Register This command places the device into read-status-register mode. Reading the device will output the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after a Program or Erase operation has been initiated. See Section 4.2.3. 50 Clear Status Register The WSM can set the block-lock status (SR.1), VPP Status (SR.3), program status (SR.4), and erase-status (SR.5) bits in the status register to "1," but it cannot clear them to "0." Issuing this command clears those bits to "0." 90 Read Configuration Puts the device into the read-configuration mode so that reading the device will output the manufacturer/device codes or block-lock status. Section 4.2.2. 60 Configuration Set-Up Prepares the CUI for changes to the device configuration, such as block-locking changes. If the next command is not Block Unlock, Block Lock, or Block Lock-Down, then the CUI will set both the program and erase-status-register bits to indicate a command-sequence error. See Section 4.2. 01 Lock-Block If the previous command was Configuration Set-Up, the CUI will latch the address and lock the block indicated on the address pins. (Section 4.3) 2F Lock-Down If the previous command was a Configuration Set-Up command, the CUI will latch the address and lock-down the block indicated on the address pins. (Section 4.3) 98 Read Query Puts the device into the read-query mode so that reading the device will output Common Flash Interface information. See Section 4.2.4 and Appendix C. C0 Protection Program Setup This is a two-cycle command. The first cycle prepares the CUI for a program operation to the protection register. The second cycle latches addresses and data information and initiates the WSM to execute the Protection Program algorithm to the protection register. The flash outputs status-register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 4.4. 10 Alt. Prog Set-Up 00 Invalid/ Reserved Operates the same as Program Set-up command. (See 40H/Program Set-Up) Unassigned commands that should not be used. Intel reserves the right to redefine these codes for future functions. NOTE: See Appendix A for mode transition information. 24 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 7. Status Register Bit Definition WSMS ESS ES PS VPPS PSS BLS R 7 6 5 4 3 2 1 0 NOTES: SR.7 WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy Check Write State Machine bit first to determine Word Program or Block Erase completion, before checking program or erasestatus bits. SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an Erase Resume command is issued. SR.5 = ERASE STATUS (ES) 1 = Error In Block Erase 0 = Successful Block Erase When this bit is set to "1," WSM has applied the max. number of erase pulses to the block and is still unable to verify successful block erasure. SR.4 = PROGRAM STATUS (PS) 1 = Error in Programming 0 = Successful Programming When this bit is set to "1," WSM has attempted but failed to program a word/byte. SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK The VPP status bit does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Program or Erase command sequences have been entered, and informs the system if VPP has not been switched on. The VPP is also checked before the operation is verified by the WSM. The VPP status bit is not guaranteed to report accurate feedback between VPPLK and VPP1Min. SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to "1." PSS bit remains set to "1" until a Program Resume command is issued. SR.1 = BLOCK LOCK STATUS 1 = Prog/Erase attempted on a locked block; Operation aborted. 0 = No operation to locked blocks If a Program or Erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) This bit is reserved for future use and should be masked out when polling the status register. NOTE: A Command-Sequence Error is indicated when SR.4, SR.5, and SR.7 are set. 4.3 Flexible Block Locking Intel 3-Volt Advanced+ Boot Block products offer an instant, individual block-locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. This locking scheme offers two levels of protection. The first level allows software-only control of block locking (useful for data blocks that change frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). The following sections will discuss the operation of the locking system. The term "state [XYZ]" will be used to specify locking states; e.g., "state [001]," where X = value of WP#, Y = bit DQ1 of the Block Lock status register, and Z = bit DQ0 of the Block Lock status register. Table 9, "Block Locking State Transitions" on page 28 defines all of these possible locking states. Datasheet 25 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.3.1 Locking Operation The following concisely summarizes the locking functionality. * All blocks power-up locked, then can be unlocked or locked with the Unlock and Lock commands. * The Lock-Down command locks a block and prevents it from being unlocked when WP# = 0. -- When WP# = 1, Lock-Down is overridden and commands can unlock/lock locked-down blocks. -- When WP# returns to 0, locked-down blocks return to Lock Down. -- Lock Down is cleared only when the device is reset or powered down. The locking status of each block can be set to Locked, Unlocked, and Lock Down, each of which will be described in the following sections. Table 9 on page 28 is a comprehensive state table for the locking functions; Figure 16 on page 56 is a flowchart for Locking operations. 4.3.1.1 Locked State The default status of all blocks upon power-up or reset is locked (states [001] or [101]). Locked blocks are fully protected from alteration. Any Program or Erase operations attempted on a locked block will return an error on bit SR.1 of the status register. The status of a locked block can be changed to Unlocked or Lock Down using the appropriate software commands. An Unlocked block can be locked by writing the Lock command sequence, 60H followed by 01H. 4.3.2 Unlocked State Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the Locked state when the device is reset or powered down. The status of an unlocked block can be changed to Locked or Locked Down using the appropriate software commands. A Locked block can be unlocked by writing the Unlock command sequence, 60H followed by D0H. 4.3.3 Lock-Down State Blocks that are Locked Down (state [011]) are protected from Program and Erase operations (just like Locked blocks), but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked Down by writing the Lock-Down command sequence, 60H followed by 2FH. Locked-Down blocks revert to the Locked state when the device is reset or powered down. The Lock-Down function depends on the WP# input pin. When WP# = 0, blocks in Lock Down [011] are protected from program, erase, and lock status changes. When WP# = 1, the Lock-Down function is disabled ([111]) and Locked-Down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110] as required while WP# remains high. When WP# goes low, blocks that were previously Locked Down return to the Lock-Down state [011], regardless of any changes made while WP# was high. Device reset or power-down resets all blocks, including those in Lock-Down, to Locked state. 26 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.3.4 Reading Block-Lock Status The Lock status of every block can be read in the configuration-read mode of the device. To enter this mode, write 90H to the device. Subsequent reads at Block Address + 00002 will output the Lock status of that block. The Lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock Down. DQ1 indicates Lock-Down status, and is set by the Lock-Down command. It cannot be cleared by software--only by device reset or power-down. Table 8. Block Lock Status Item Block Lock Configuration 4.3.5 Address Data XX002 LOCK * Block Is Unlocked DQ0 = 0 * Block Is Locked DQ0 = 1 * Block Is Locked-Down DQ1 = 1 Locking Operations during Erase Suspend Changes to block-lock status can be performed during an erase-suspend by using the standard locking command sequences to Unlock, Lock, or Lock Down a block. This is useful in the case when another block needs to be updated while an Erase operation is in progress. To change block locking during an Erase operation, first write the Erase Suspend command (B0H), then check the status register until it indicates that the Erase operation has been suspended. Next, write the preferred Lock command sequence to a block and the Lock status will be changed. After completing any preferred Lock, Read, or Program operations, resume the Erase operation with the Erase Resume command (D0H). If a block is Locked or Locked Down during a Suspended Erase of the same block, the locking status bits will be changed immediately, but when the Erase is resumed, the Erase operation will complete. Locking operations cannot be performed during a Program Suspend. Refer to Appendix A for detailed information on which commands are valid during Erase Suspend. 4.3.6 Status Register Error Checking Using nested-locking or program-command sequences during Erase Suspend can introduce ambiguity into status register results. Since locking changes are performed using a two-cycle command sequence, e.g., 60H followed by 01H to lock a block, following the Configuration Setup command (60H) with an invalid command will produce a Lock-Command error (SR.4 and SR.5 will be set to 1) in the status register. If a Lock-Command error occurs during an Erase Suspend, SR.4 and SR.5 will be set to 1 and will remain at 1 after the Erase is resumed. When Erase is complete, any possible error during the Erase cannot be detected via the status register because of the previous Lock-Command error. A similar situation happens if an error occurs during a Program-Operation error nested within an Erase Suspend. Datasheet 27 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 9. Block Locking State Transitions Current State Lock Command Input Result (Next State) Erase/Prog Allowed? X Y Z WP# DQ1 DQ0 Name 0 0 0 "Unlocked" 0 0 1 "Locked" (Default) Lock Unlock Lock-Down Yes Goes To [001] No Change Goes To [011] No No Change Goes To [000] Goes To [011] 0 1 1 "Locked-Down" No No Change No Change No Change 1 0 0 "Unlocked" Yes Goes To [101] No Change Goes To [111] 1 0 1 "Locked" No No Change Goes To [100] Goes To [111] 1 1 0 Lock-Down Disabled Yes Goes To [111] No Change Goes To [111] 1 1 1 Lock-Down Disabled No No Change Goes To [110] No Change NOTES: 1. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ1, and Z = DQ0. The current locking state of a block is defined by the state of WP# and the two bits of the block-lock status (DQ0, DQ1). DQ0 indicates if a block is locked (1) or unlocked (0). DQ1 indicates if a block has been Locked Down (1) or not (0). 2. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). Holding WP# = 0 is the recommended default. 3. The "Erase/Program Allowed?" column shows whether Erase and Program operations are enabled (Yes) or disabled (No) in that block's current Lock state. 4. The "Lock Command Input Result [Next State]" column shows the result of writing the three Lock commands (Lock, Unlock, Lock-Down) in the current Lock state. For example, "Goes To [001]" would mean that writing the command to a block in the current Lock state would change it to [001]. 4.4 128-Bit Protection Register The 3-Volt Advanced+ Boot Block architecture includes a 128-bit protection register than can be used to increase the security of a system design. For example, the number contained in the protection register can be used to "mate" the flash component with other system components, such as the CPU or ASIC, preventing device substitution. The Intel application note, AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture, contains additional application information. The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is left blank for customer designs to program, as preferred. Once the customer segment is programmed, it can be locked to prevent reprogramming. 4.4.1 Reading the Protection Register The protection register is read in the configuration-read mode. The device is switched to this mode by writing the Read Configuration command (90H). Once in this mode, read cycles from addresses shown in Appendix G retrieve the specified information. To return to read-array mode, write the Read Array command (FFH). 28 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.4.2 Programming the Protection Register The protection register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide parts, and eight bits at a time for byte-wide parts. First, write the Protection Program Setup command, C0H. The next write to the device will latch in address and data, and program the specified location. The allowable addresses are shown in Appendix G. See Figure 17, "Protection Register Programming Flowchart" on page 57. Attempts to address Protection Program commands outside the defined protection register address space should not be attempted. This space is reserved for future use. Attempting to program to a previously locked protection register segment will result in a Status Register error (Program Error bit SR.4 and Lock Error bit SR.1 will be set to 1). 4.4.3 Locking the Protection Register The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set using the Protection Program command to program "FFFD" to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. Protection Program commands to a locked section will result in a Status Register error (Program Error bit SR.4 and Lock Error bit SR.1 will be set to 1). Protection register lockout state is not reversible. Figure 5. Protection Register Memory Map 88H 4 Words User Programmed 85H 84H 4 Words Factory Programmed 81H 80H PR Lock 0645_05 4.5 VPP Program and Erase Voltages Intel 3-Volt Advanced+ Boot Block products provide in-system programming and erase in the 1.65 V-3.6 V range. For fast production programming, it also includes a low-cost, backwardcompatible 12-V programming feature. 4.5.1 Improved 12-Volt Production Programming When VPP is between 1.65 V and 3.6 V, all program and erase current is drawn through the VCC pin. Note that if VPP is driven by a logic signal, VIH min = 1.65 V. That is, VPP must remain above 1.65 V to perform in-system flash modifications. When VPP is connected to a 12 V power supply, Datasheet 29 28F800C3, 28F160C3, 28F320C3, 28F640C3 the device draws program and erase current directly from the VPP pin. This eliminates the need for an external switching transistor to control the voltage VPP. Figure 6 on page 30 shows examples of how the flash power supplies can be configured for various usage models. The 12-V VPP mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 V may be applied to VPP during Program and Erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage. 4.5.2 VPP VPPLK for Complete Protection In addition to the flexible block locking, the VPP programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. When VPP is below VPPLK, any Program or Erase operation will result in a error, prompting the corresponding status-register bit (SR.3) to be set. Figure 6. Example Power Supply Configurations System Supply System Supply 12 V Supply 10 K VCC VCC VPP Prot# (Logic Signal) VPP 12 V Fast Programming Low-Voltage Programming Absolute Write Protection With VPP VPPLK Absolute Write Protection via Logic Signal System Supply (Note 1) System Supply VCC VCC VPP VPP 12 V Supply Low Voltage and 12 V Fast Programming Low-Voltage Programming 0645_06 NOTE: 1. A resistor can be used if the VCC supply can sink adequate current based on resistor value. See AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture for details. 4.6 Power Consumption Intel Flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. The combination of these features can minimize memory power consumption, and therefore, overall system power consumption. 30 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.6.1 Active Power (Program/Erase/Read) With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer to the DC Characteristic tables for ICC current values. Active power is the largest contributor to overall system power consumption. Minimizing the active current could have a profound effect on system power consumption, especially for battery-operated devices. 4.6.2 Automatic Power Savings (APS) Automatic Power Savings provides low-power operation during read mode. After data is read from the memory array and the address lines are quiescent, APS circuitry places the device in a mode where typical current is comparable to ICCS. The flash stays in this static state with outputs valid until a new location is read. 4.6.3 Standby Power When CE# is at a logic-high level (VIH) and the device is in read mode, the flash memory is in standby mode, which disables much of the device's circuitry and substantially reduces power consumption. Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during Erase or Program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. System engineers should analyze the breakdown of standby time versus active time, and quantify the respective power consumption in each mode for their specific application. This approach will provide a more accurate measure of application-specific power and energy requirements. 4.6.4 Deep Power-Down Mode The deep power-down mode is activated when RP# = VIL (GND 0.2 V). During read modes, RP# going low de-selects the memory and places the outputs in a high-impedance state. Recovery from deep power-down requires a minimum time of tPHQV for Read operations, and tPHWL/tPHEL for Write operations. During program or erase modes, RP# transitioning low will abort the in-progress operation. The memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. During deep power-down, all internal circuits are switched to a low-power savings mode (RP# transitioning to VIL or turning off power to the device clears the status register). 4.7 Power and Reset Considerations 4.7.1 Power-Up/Down Characteristics In order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up VCC, VCCQ and S-VCC together. Conversely, VCC and VCCQ must power-down together. It is also recommended to power-up VPP with or slightly after VCC. Conversely, VPP must powerdown with or slightly before VCC. Datasheet 31 28F800C3, 28F160C3, 28F320C3, 28F640C3 If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMin before applying VCCQ and VPP. Device inputs should not be driven before supply voltage = VCCMin. Power supply transitions should only occur when RP# is low. 4.7.2 RP# Connected to System Reset The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when VCC voltages are above VLKO. Because both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 4.7.3 VCC, VPP and RP# Transitions The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after VCC transitions above VLKO (Lockout voltage), is read-array mode. After any program or Block-Erase operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read-array mode via the Read Array command if access to the flash-memory array is desired. 4.8 Power Supply Decoupling Flash memory power-switching characteristics require careful device decoupling. System designers should consider the following three supply current issues: * Standby current levels (ICCS) * Read current levels (ICCR) * Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Twoline control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 F ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 32 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 5.0 Electrical Specifications 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability . NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Parameter Maximum Rating Extended Operating Temperature During Read -40 C to +85 C During Block Erase and Program -40 C to +85 C Temperature under Bias -40 C to +85 C Storage Temperature -65 C to +125 C Voltage On Any Pin (except VCC and VPP) with Respect to GND -0.5 V to +3.7 V(1) VPP Voltage (for Block Erase and Program) with Respect to GND -0.5 V to +13.5 V(1,2,3) VCC and VCCQ Supply Voltage with Respect to GND -0.2 V to +3.6 V Output Short Circuit Current 100 mA(4) NOTES: 1. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns. 3. VPP Program voltage is normally 1.65 V-3.6 V. Connection to a 11.4 V-12.6 V supply can be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 4.5 for details. 4. Output shorted for no more than one second. No more than one output shorted at a time. Datasheet 33 28F800C3, 28F160C3, 28F320C3, 28F640C3 5.2 Operating Conditions Table 10. Temperature and Voltage Operating Conditions Symbol Parameter TA Operating Temperature VCC1 VCC Supply Voltage Notes VCC2 VCCQ1 VCCQ2 VPP2 Cycling Block Erase Cycling Units -40 +85 C Volts 1, 2 2.7 3.6 3.0 3.6 1 2.7 3.6 1.65 2.5 I/O Supply Voltage Supply Voltage Max 1, 2 Volts 1.8 2.5 1 1.65 3.6 Volts 1, 3 11.4 12.6 Volts 3 100,000 VCCQ3 VPP1 Min Cycles NOTES: 1. VCC and VCCQ must share the same supply when they are in the VCC1 range. 2. VCCMax = 3.3 V for 0.25m 32-Mbit devices. 3. Applying VPP = 11.4 V-12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 4.5 for details. 5.3 Capacitance TA = 25 C, f = 1 MHz Sym Parameter Notes Typ Max Units Conditions CIN Input Capacitance 1 6 8 pF VIN = 0 V COUT Output Capacitance 1 10 12 pF VOUT = 0 V NOTE: Sampled, not 100% tested. 34 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 5.4 DC Characteristics Sym Parameter VCC 2.7 V-3.6 V 2.7 V-2.85 V 2.7 V-3.3 V VCCQ 2.7 V-3.6 V 1.65 V-2.5 V 1.8 V-2.5 V Note Typ Typ Typ Max Max Unit Test Conditions Max 1 A VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND 0.2 10 A VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND 50 150 250 A VCC = VCCMax CE# = RP# = VCCQ or during Program/ Erase Suspend 20 50 150 250 A WP# = VCCQ or GND 15 7 20 7 20 A VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND RP# = GND 0.2 V 7 25 7 25 7 25 A 1,2,3 9 18 8 15 9 15 mA VCC Read Current for 0.25 Micron Product 1,2,3 10 18 8 15 9 15 mA IPPD VPP Deep PowerDown Current 1 0.2 5 0.2 5 0.2 5 A RP# = GND 0.2 V VPP VCC 18 55 18 55 18 55 mA VPP =VPP1, Program in Progress ICCW VCC Program Current 8 22 10 30 10 30 mA VPP = VPP2 (12v) Program in Progress 16 45 21 45 21 45 mA VPP = VPP1, Erase in Progress 8 15 16 45 16 45 mA VPP = VPP2 (12v) , Erase in Progress 7 15 50 200 150 250 A CE# = VCC, Erase Suspend in Progress 2 15 2 15 2 15 A VPP VCC 50 200 50 200 50 200 A VPP > VCC 0.05 0.1 0.05 0.1 0.05 0.1 mA VPP =VPP1, Program in Progress 8 22 8 22 8 22 mA VPP = VPP2 (12v) Program in Progress 1 1 ILI Input Load Current 1,2 ILO Output Leakage Current 1,2 0.2 10 0.2 10 VCC Standby Current for 0.13 and 0.18 Micron Product 1 7 15 20 VCC Standby Current for 0.25 Micron Product 1 10 25 VCC Power-Down Current for 0.13 and 0.18 Micron Product 1,2 7 VCC Power-Down Current for 0.25 Product 1,2 VCC Read Current for 0.13 and 0.18 Micron Product ICCS ICCD ICCR ICCE VCC Erase Current 1,4 1,4 ICCES VCC Erase Suspend Current 1,4 IPPR VPP Read Current 1,4 IPPW VPP Program Current Datasheet 1,4 VCC = VCCMax VCCQ = VCCQMax OE# = VIH , CE# =VIL f = 5 MHz, IOUT=0 mA Inputs = VIL or VIH 35 28F800C3, 28F160C3, 28F320C3, 28F640C3 Sym Parameter VCC 2.7 V-3.6 V 2.7 V-2.85 V 2.7 V-3.3 V VCCQ 2.7 V-3.6 V 1.65 V-2.5 V 1.8 V-2.5 V Note Typ Max Typ Max Typ Max 1,4 0.05 0.1 0.05 0.1 0.05 0.1 mA Unit Test Conditions VPP = VPP1, Erase in Progress IPPE VPP Erase Current VIL Input Low Voltage -0.4 VCC * 0.22 V -0.4 0.4 -0.4 0.4 V VIH Input High Voltage 2.0 VCCQ +0.3V VCCQ -0.4V VCCQ +0.3V VCCQ -0.4V VCCQ +0.3V V VOL Output Low Voltage -0.1 0.1 -0.1 0.1 -0.1 0.1 V VCC = VCCMin VCCQ = VCCQMin IOL = 100 A VOH Output High Voltage V VCC = VCCMin VCCQ = VCCQMin IOH = -100 A VPPLK VPP Lock-Out Voltage V Complete Write Protection VPP1 VCCQ -0.1V 6 6 VCCQ -0.1V 1.0 1.65 VCCQ -0.1V 1.0 1.0 3.6 V VPP2 VPP during Program / Erase Operations VLKO VCC Prog/Erase Lock Voltage 1.5 1.5 1.5 V VLKO2 VCCQ Prog/Erase Lock Voltage 1.2 1.2 1.2 V 6, 7 11.4 12.6 V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 C. 2. The test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or VCCQ voltage listed at the top of each column. VCCMax = 3.3 V for 0.25m 32-Mbit devices. 3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs). 4. Sampled, not 100% tested. 5. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR. 6. Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPP1 and VPP2. 7. Applying VPP = 11.4 V-12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 4.4 for details. 36 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 7. Input/Output Reference Waveform VCCQ VCCQ INPUT 2 VCCQ TEST POINTS 2 OUTPUT 0.0 0645_07 Figure 8. Test Configuration VCCQ R1 Device Under Test Out CL R2 0645_08 Test Configuration CL (pF) R1 () R2 () 2.7 V-3.6 V Standard Test 50 25K 25K NOTE: CL includes jig capacitance. Datasheet 37 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.5 AC Characteristics--Read Operations Density 8 Mbit Product # Sym 90 ns 110 ns Parameter Unit VCC Note 3.0 V - 3.6 V 2.7 V - 3.6 V 3.0 V - 3.6 V 2.7 V - 3.6 V Min Min Min Min Max 90 Max 100 Max R1 tAVAV Read Cycle Time R2 tAVQV Address to Output Delay R3 tELQV CE# to Output Delay R4 tGLQV OE# to Output Delay R5 tPHQV RP# to Output Delay R6 tELQX CE# to Output in Low Z 2 0 0 0 0 ns R7 tGLQX OE# to Output in Low Z 2 0 0 0 0 ns R8 tEHQZ CE# to Output in High Z 2 20 20 20 20 ns R9 tGHQZ OE# to Output in High Z 2 20 20 20 20 ns tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 2 R10 80 Max 110 ns 80 90 100 110 ns 1 80 90 100 110 ns 1 30 30 30 30 ns 150 0 150 0 150 0 150 0 ns ns NOTES: 1. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 2. Sampled, but not 100% tested. 3. See Figure 9, "AC Waveform: Read Operations" on page 42. 4. See Figure 7, "Input/Output Reference Waveform" on page 37 for timing measurements and maximum allowable input slew rate. 38 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 AC Characteristics--Read Operations Density # R1 Sym Parameter 16 Mbit Product 70 ns 80 ns 90 ns 110 ns VCC 2.7 V-3.6 V 2.7 V-3.6 V 3.0 V-3.6 V 2.7 V-3.6 V 3.0 V-3.6 V 2.7 V-3.6 V Min Min Min Min Min Min Unit Max Max Max Max Max Max tAVAV Read Cycle Time R2 tAVQV Address to Output Delay 70 80 80 90 100 110 ns R3 tELQV CE# to Output Delay(1) 70 80 80 90 100 110 ns R4 Output tGLQV OE# to Delay(1) 20 20 30 30 30 30 ns R5 RP# to Output tPHQV Delay 150 150 150 150 150 150 ns R6 tELQX CE# to Output in Low Z(2) 0 0 0 0 0 0 ns R7 OE# to Output in tGLQX Low Z(2) 0 0 0 0 0 0 ns R8 tEHQZ CE# to Output in High Z(2) 20 20 20 20 20 20 ns R9 OE# to Output in tGHQZ High Z(2) 20 20 20 20 20 20 ns R10 tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First(2) 70 0 80 0 80 0 90 0 100 0 110 0 ns ns NOTES: 1. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 2. Sampled, but not 100% tested. 3. See Figure 9, "AC Waveform: Read Operations" on page 42. 4. See Figure 7, "Input/Output Reference Waveform" on page 37 for timing measurements and maximum allowable input slew rate. Datasheet 39 28F800C3, 28F160C3, 28F320C3, 28F640C3 AC Characteristics--Read Operations, continued Density # Sym Parameter 32 Mbit Product 70 ns 90 ns 100 ns 110 ns VCC 2.7 V-3.6 V 2.7 V-3.6 V 3.0 V-3.3 V 2.7 V-3.3 V 3.0 V-3.3 V 2.7 V-3.3 V Min Min Min Min Min Min Unit Read Cycle Time Max 70 Max 90 Max 90 Max 100 Max 100 Max 110 ns R1 tAVAV R2 tAVQV Address to Output Delay 70 90 90 100 100 110 ns R3 tELQV CE# to Output Delay(1) 70 90 90 100 100 110 ns R4 tGLQV OE# to Output Delay(1) 20 20 30 30 30 30 ns R5 tPHQV RP# to Output Delay 150 150 150 150 150 150 ns R6 tELQX CE# to Output in Low Z(2) 0 0 0 0 0 0 ns R7 tGLQX OE# to Output in Low Z(2) 0 0 0 0 0 0 ns R8 tEHQZ CE# to Output in High Z(2) 20 20 20 20 20 20 ns R9 tGHQZ OE# to Output in High Z(2) 20 20 20 20 20 20 ns R10 tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First(2) 0 0 0 0 0 0 ns NOTES: 1. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 2. Sampled, but not 100% tested. 3. See Figure 9, "AC Waveform: Read Operations" on page 42. 4. See Figure 7, "Input/Output Reference Waveform" on page 37 for timing measurements and maximum allowable input slew rate. 40 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 AC Characteristics--Read Operations, continued Density # Sym 64 Mbit Product 70 ns 80 ns VCC 2.7 V-3.6 V 2.7 V-3.6 V Min Min Parameter Unit Note Max R1 tAVAV Read Cycle Time R2 tAVQV Address to Output Delay R3 tELQV CE# to Output Delay 1 R4 tGLQV OE# to Output Delay 1 R5 tPHQV RP# to Output Delay R6 tELQX CE# to Output in Low Z 2 0 0 ns R7 tGLQX OE# to Output in Low Z 2 0 0 ns R8 tEHQZ CE# to Output in High Z 2 20 20 ns R9 tGHQZ OE# to Output in High Z 2 20 20 ns Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 2 R10 tOH 70 Max 0 80 ns 70 80 ns 70 80 ns 20 20 ns 150 150 0 ns ns NOTES: 1. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 2. Sampled, but not 100% tested. 3. See Figure 9, "AC Waveform: Read Operations" on page 42. 4. See Figure 7, "Input/Output Reference Waveform" on page 37 for timing measurements and maximum allowable input slew rate. Datasheet 41 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 9. AC Waveform: Read Operations Device Address Selection Standby Data Valid VIH ADDRESSES (A) Address Stable VIL R1 VIH CE# (E) VIL R8 OE# (G) VIH VIL WE# (W) R9 VIH R4 VIL DATA (D/Q) VOH R7 R3 High Z R6 Valid Output R10 High Z VOL R2 VIH RP# (P) 42 VIL R5 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.6 AC Characteristics--Write Operations Table 11. AC Characteristics, Write Operations (sheet 1 of 2) Density 8 Mbit Product # Sym Parameter 90 ns 3.0 V - 3.6 V 110 ns 80 2.7 V - 3.6 V 100 90 Note Unit 110 Min Min Min Min 150 150 150 150 ns 0 0 0 0 ns W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low W3 tWLWH / tELEH WE# (CE#) Pulse Width 1 50 60 70 70 ns W4 tDVWH / tDVEH Data Setup to WE# (CE#) Going High 2 50 50 60 60 ns W5 tAVWH / tAVEH Address Setup to WE# (CE#) Going High 2 50 60 70 70 ns W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 0 0 0 0 ns W7 tWHDX / tEHDX Data Hold Time from WE# (CE#) High 2 0 0 0 0 ns W8 tWHAX / tEHAX Address Hold Time from WE# (CE#) High 2 0 0 0 0 ns W9 tWHWL / tEHEL WE# (CE#) Pulse Width High 1 30 30 30 30 ns W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3 200 200 200 200 ns W11 tQVVL VPP Hold from Valid SRD 3 0 0 0 0 ns W12 tBHWH / tBHEH WP# Setup to WE# (CE#) Going High 3 0 0 0 0 ns W13 tQVBL WP# Hold from Valid SRD 3 0 0 0 0 ns W14 tWHGL WE# High to OE# Going Low 3 30 30 30 30 ns NOTES: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 2. Refer to Table 5, "Command Bus Operations" on page 23 for valid AIN or DIN. 3. Sampled, but not 100% tested. 4. Write timing characteristics during erase suspend are the same as during Write-only operations. 5. See Figure 7, "Input/Output Reference Waveform" on page 37 for timing measurements and maximum allowable input slew rate. 6. See Figure 9, "AC Waveform: Read Operations" on page 42. 7. VCCMax = 3.3 V for 32-Mbit and 64-Mbit densities. Datasheet 43 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 12. AC Characteristics, Write Operations (sheet 2 of 2) Density 16 Mbit Product # Sym Parameter 70 ns 80 ns 3.0 V - 3.6 V 90 ns 110 ns 80 2.7 V - 3.6 V Note 100 90 Unit 70 80 110 Min Min Min Min Min Min 150 150 150 150 150 150 ns 0 0 0 0 0 0 ns W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low W3 tWLWH / tELEH WE# (CE#) Pulse Width 1 45 50 50 60 70 70 ns W4 tDVWH / tDVEH Data Setup to WE# (CE#) Going High 2 40 40 50 50 60 60 ns W5 tAVWH / tAVEH Address Setup to WE# (CE#) Going High 2 50 50 50 60 70 70 ns W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 0 0 0 0 0 0 ns W7 tWHDX / tEHDX Data Hold Time from WE# (CE#) High 2 0 0 0 0 0 0 ns W8 tWHAX / tEHAX Address Hold Time from WE# (CE#) High 2 0 0 0 0 0 0 ns W9 tWHWL / tEHEL WE# (CE#) Pulse Width High 1 25 30 30 30 30 30 ns W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3 200 200 200 200 200 200 ns W11 tQVVL VPP Hold from Valid SRD 3 0 0 0 0 0 0 ns W12 tBHWH / tBHEH WP# Setup to WE# (CE#) Going High 3 0 0 0 0 0 0 ns W13 tQVBL WP# Hold from Valid SRD 3 0 0 0 0 0 0 ns W14 tWHGL WE# High to OE# Going Low 3 30 30 30 30 30 30 ns NOTES: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 2. Refer to Table 5, "Command Bus Operations" on page 23 for valid AIN or DIN. 3. Sampled, but not 100% tested. 4. Write timing characteristics during erase suspend are the same as during Write-only operations. 5. See Figure 7, "Input/Output Reference Waveform" on page 37 for timing measurements and maximum allowable input slew rate. 6. See Figure 9, "AC Waveform: Read Operations" on page 42. 7. VCCMax = 3.3 V for 32-Mbit and 64-Mbit densities. 44 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 AC Characteristics--Write Operations, continued Density Product # Sym Parameter 32 Mbit 70 ns 90 ns 3.0 V - 3.6 V(4) 2.7 V - 3.6 V(4) Note 100 ns 110 ns 90 100 100 Unit 70 90 110 Min Min Min Min Min Min 150 150 150 150 150 150 ns 0 0 0 0 0 0 ns W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low W3 tWLWH / tELEH WE# (CE#) Pulse Width 1 45 60 60 70 70 70 ns W4 tDVWH / tDVEH Data Setup to WE# (CE#) Going High 2 40 40 50 60 60 60 ns W5 tAVWH / tAVEH Address Setup to WE# (CE#) Going High 2 50 60 60 70 70 70 ns W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 0 0 0 0 0 0 ns W7 tWHDX / tEHDX Data Hold Time from WE# (CE#) High 2 0 0 0 0 0 0 ns W8 tWHAX / tEHAX Address Hold Time from WE# (CE#) High 2 0 0 0 0 0 0 ns W9 tWHWL / tEHEL WE# (CE#) Pulse Width High 1 25 30 30 30 30 30 ns W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3 200 200 200 200 200 200 ns W11 tQVVL VPP Hold from Valid SRD 3 0 0 0 0 0 0 ns W12 tBHWH / tBHEH WP# Setup to WE# (CE#) Going High 3 0 0 0 0 0 0 ns W13 tQVBL WP# Hold from Valid SRD 3 0 0 0 0 0 0 ns W14 tWHGL WE# High to OE# Going Low 3 30 30 30 30 30 30 ns Datasheet 45 28F800C3, 28F160C3, 28F320C3, 28F640C3 AC Characteristics--Write Operations, continued Density 64 Mbit Product # Sym Parameter 70 ns 80 ns 3.0 V - 3.6 V Unit 2.7 V - 3.6 V Note 70 70 Min Min 150 150 ns 0 0 ns W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low W3 tWLWH / tELEH WE# (CE#) Pulse Width 1 45 60 ns W4 tDVWH / tDVEH Data Setup to WE# (CE#) Going High 2 40 40 ns W5 tAVWH / tAVEH Address Setup to WE# (CE#) Going High 2 50 60 ns W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 0 0 ns W7 tWHDX / tEHDX Data Hold Time from WE# (CE#) High 2 0 0 ns W8 tWHAX / tEHAX Address Hold Time from WE# (CE#) High 2 0 0 ns W9 tWHWL / tEHEL WE# (CE#) Pulse Width High 1 25 30 ns W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3 200 200 ns W11 tQVVL VPP Hold from Valid SRD 3 0 0 ns W12 tBHWH / tBHEH WP# Setup to WE# (CE#) Going High 3 0 0 ns W13 tQVBL WP# Hold from Valid SRD 3 0 0 ns W14 tWHGL WE# High to OE# Going Low 3 30 30 ns NOTES: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 2. Refer to Table 5, "Command Bus Operations" on page 23 for valid AIN or DIN. 3. Sampled, but not 100% tested. 4. VCCMax = 3.3 V for 0.25m 32-Mbit devices. 5. Write timing characteristics during erase suspend are the same as during Write-only operations. 6. See Figure 7, "Input/Output Reference Waveform" on page 37 for timing measurements and maximum allowable input slew rate. 7. See Figure 9, "AC Waveform: Read Operations" on page 42. 46 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.7 Erase and Program Timings VPP Symbol 1.65 V-3.6 V 11.4 V-12.6 V Parameter Unit Note Typ(1) Max Typ(1) Max tBWPB 4-KW Parameter Block Word Program Time 2, 3 0.10 0.30 0.03 0.12 s tBWMB 32-KW Main Block Word Program Time 2, 3 0.8 2.4 0.24 1 s Word Program Time for 0.13 and 0.18 Micron Product 2, 3 12 200 8 185 s Word Program Time for 0.25 Micron Product 2, 3 22 200 8 185 s tWHQV2 / tEHQV2 4-KW Parameter Block Erase Time 2, 3 0.5 4 0.4 4 s tWHQV3 / tEHQV3 32-KW Main Block Erase Time 2, 3 1 5 0.6 5 s tWHRH1 / tEHRH1 Program Suspend Latency 3 5 10 5 10 s tWHRH2 / tEHRH2 Erase Suspend Latency 3 5 20 5 20 s tWHQV1 / tEHQV1 NOTES: 1. Typical values measured at TA = +25 C and nominal voltages. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. Datasheet 47 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 10. AC Waveform: Program and Erase Operations A ADDRESSES [A] VIH VIL CE# (WE#) [E(W)] C AIN AIN W5 W2 (Note 1) VIH VIH VIL W3 High Z W1 W7 DIN DIN Valid SRD DIN VIH VIL WP# (Note 1) W14 W9 W4 RP# [P] F W6 VIL DATA [D/Q] W8 E VIH VIL WE# (CE) [W(E)] D VIH VIL OE# [G] B W12 W13 VIH VIL VPPH2 V 1 VPP [V] PPH VPPLK VIL W10 W11 NOTES: 1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register Data. a. b. c. d. e. f. 48 VCC Power-Up and Standby. Write Program or Erase Setup Command. Write Valid Address and Data (for Program) or Erase Confirm Command. Automated Program or Erase Delay. Read Status Register Data (SRD): reflects completed Program/Erase operation. Write Read Array Command. Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.8 Reset Operations Figure 11. AC Waveform: Reset Operations RP# (P) VIH VIL t PLPH (A) Reset during Read Mode t PHQV t PHWL t PHEL Abort Complete t PLRH RP# (P) VIH t PHQV t PHWL t PHEL V IL t PLPH (B) Reset during Program or Block Erase, t PLPH < t PLRH Abort Deep Complete PowerDown RP# (P) VIH VIL t PLRH t PHQV t PHWL t PHEL t PLPH (C) Reset Program or Block Erase, t PLPH > t PLRH Table 13. Reset Specifications VCC 2.7 V - 3.6 V Symbol Parameter Notes Unit Min Max tPLPH RP# Low to Reset during Read (If RP# is tied to VCC, this specification is not applicable) 2,4 tPLRH1 RP# Low to Reset during Block Erase 3,4 22 s tPLRH2 RP# Low to Reset during Program 3,4 12 s 100 ns NOTES: 1. If tPLPH is < 100 ns the device may still reset but this is not guaranteed. 2. If RP# is asserted while a Block Erase or Word Program operation is not executing, the reset will complete within 100 ns. 3. Sampled, but not 100% tested. 4. See Section 4.1.4 for a full description of these conditions. Datasheet 49 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix A WSM Current/Next States, Sheet 1 of 2 Command Input (and Next State) Current State SR. 7 Data When Read Read Array (FFH) Program Setup (10/ 40H) Erase Setup (20H) Read Array "1" Array Read Array Prog. Setup Ers. Setup Read Status "1" Status Read Array Prog. Setup Read Config. "1" Config Read Array Read Query "1" CFI Read Array Lock Setup "1" Status Lock Cmd. Error "1" Status Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array Lock Oper. (Done) "1" Status Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array Prot. Prog. Setup "1" Status Protection Register Program Prot. Prog. (Not Done) "0" Status Protection Register Program (Not Done) Prot. Prog. (Done) "1" Status Read Sts. Read Array Prog. Setup "1" Status Program (Not Done) "0" Status Prog. Susp. Status "1" Status Prog. Sus. Read Array Program Suspend Read Array Prog. (Not Done) Prog. Sus. Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Prog. Susp. Read Array "1" Array Prog. Sus. Read Array Program Suspend Read Array Prog. (Not Done) Prog. Sus. Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Prog. Susp. Read Config "1" Config Prog. Sus. Read Array Program Suspend Read Array Prog. (Not Done) Prog. Sus. Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Prog. Susp. Read Query "1" CFI Prog. Sus. Read Array Program Suspend Read Array Prog. (Not Done) Prog. Sus. Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Program (Done) "1" Status Read Array Read Status Read Array Erase Setup "1" Status Erase Cmd. Error "1" Status Erase (Not Done) "0" Status Ers. Susp. Status "1" Status Erase Sus. Read Array Prog. Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Erase Susp. Array "1" Array Erase Sus. Read Array Prog. Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Ers. Susp. Read Config "1" Config Erase Sus. Read Array Prog. Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Ers. Susp. Read Query "1" CFI Erase Sus. Read Array Prog. Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Erase (Done) "1" Status Read Array Prog. Setup Ers. Setup Read Sts. Read Array 50 Erase Confirm (D0H) Read Status (70H) Clear Status (50H) Read Array Read Sts. Read Array Ers. Setup Read Array Read Sts. Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array Lock (Done) Lock Command Error Read Array Prog. Setup Prog/Ers Suspend (B0H) Prog/Ers Resume (D0) Lock Cmd. Error Lock (Done) Read Array Ers. Setup Lock Cmd. Error Program Prog. Sus. Status Program (Not Done) Prog. Setup Read Array Prog. Setup Read Array Ers. Setup Erase (Not Done) Erase Command Error Program (Not Done) Ers. Setup Erase (Not Done) Erase Cmd. Error Erase (Not Done) Erase Command Error Read Array Read Status Erase Sus. Status Erase (Not Done) Read Array Read Array Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix A: WSM Current/Next States, Sheet 2 of 2 Command Input (and Next State) Current State Read Config (90H) Read Query (98H) Lock Setup (60H) Prot. Prog. Setup (C0H) Read Array Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Read Status Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Read Config. Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Read Query Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Locking Command Error Lock Setup Lock Down Confirm (2FH) Lock Confirm (01H) Lock Operation (Done) Lock Cmd. Error Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Lock Oper. (Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Prot. Prog. Setup Protection Register Program Prot. Prog. (Not Done) Protection Register Program (Not Done) Prot. Prog. (Done) Read Config. Read Query Unlock Confirm (D0H) Lock Setup Prot. Prog. Setup Prog. Setup Program Program (Not Done) Program (Not Done) Read Array Prog. Susp. Status Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Prog. Susp. Read Array Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Prog. Susp. Read Config. Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Prog. Susp. Read Query. Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Program (Done) Read Config. Read Query Erase Setup Erase Cmd. Error Lock Setup Prot. Prog. Setup Read Array Erase (Not Done) Erase Command Error Read Config. Read Query Lock Setup Erase (Not Done) Prot. Prog. Setup Read Array Erase (Not Done) Erase Susp. Status Ers. Susp. Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Erase Suspend Array Ers. Susp. Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Eras Sus. Read Config Erase Suspend Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Eras Sus. Read Query Erase Suspend Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Ers.(Done) Read Config. Read Query Lock Setup Datasheet Prot. Prog. Setup Read Array 51 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix B Program/Erase Flowcharts Figure 12. Automated Word Programming Flowchart Start Write 40H Bus Operation Command Write Program Setup Write Program Program Address/Data Data = 40H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Read Read Status Register Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Repeat for subsequent programming operations. No SR.7 = 1? Comments SR Full Status Check can be done after each program or after a sequence of program operations. Yes Full Status Check if Desired Write FFH after the last program operation to reset device to read array mode. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) Bus Operation 1 SR.3 = 0 VPP Range Error Programming Error 0 1 SR.1 = Comments Standby Check SR.3 1 = VPP Low Detect Standby Check SR.4 1 = VPP Program Error Standby Check SR.1 1 = Attempted Program to Locked Block - Program Aborted 1 SR.4 = Command SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. Attempted Program to Locked Block - Aborted SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked. 0 Program Successful 52 If an error is detected, clear the status register before attempting retry or other error recovery. Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 13. Program Suspend/Resume Flowchart Start Bus Operation Command Write Program Suspend Write Read Status Comments Data = B0H Addr = X Write B0H Data=70H Addr=X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Write 70H Read Read Status Register Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.2 1 = Program Suspended 0 = Program Completed 0 SR.7 = Write 1 0 SR.2 = Program Completed Write Data = FFH Addr = X Read array data from block other than the one being programmed. Read 1 Write FFH Read Array Program Resume Data = D0H Addr = X Read Array Data No Done Reading Yes Datasheet Write D0H Write FFH Program Resumed Read Array Data 53 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 14. Automated Block Erase Flowchart Start Bus Operation Write 20H Write D0H and Block Address Command Write Erase Setup Write Erase Confirm Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle CE# or OE# to Update Status Register Data Read Read Status Register Suspend Erase Loop 0 SR.7 = No Suspend Erase Comments Data = 20H Addr = Within Block to Be Erased Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Yes Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of block erasures. 1 Full Status Check if Desired Write FFH after the last write operation to reset device to read array mode. Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) Bus Operation 1 SR.3 = 0 1 Command Sequence Error 0 1 SR.5 = Block Erase Error Comments Standby Check SR.3 1 = V PP Low Detect Standby Check SR.4,5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error Standby Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted VPP Range Error SR.4,5 = Command SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. 0 1 SR.1 = 0 Attempted Erase of Locked Block - Aborted SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Block Erase Successful 54 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 15. Erase Suspend/Resume Flowchart Start Bus Operation Command Write Erase Suspend Write Read Status Comments Data = B0H Addr = X Write B0H Data=70H Addr=X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Write 70H Read Read Status Register Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.6 1 = Erase Suspended 0 = Erase Completed 0 SR.7 = Write 1 0 SR.6 = Erase Completed Read Array Read array data from block other than the one being erased. Read 1 Write Write FFH Data = FFH Addr = X Erase Resume Data = D0H Addr = X Read Array Data No Done Reading Yes Datasheet Write D0H Write FFH Erase Resumed Read Array Data 55 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 16. Locking Operations Flowchart Start Write 60H (Configuration Setup) Write 01H, D0H, or 2FH Write 90H (Read Configuration) Bus Operation Command Write Config. Setup Data = 60H Addr = X Write Lock, Unlock, or Lockdown Data= 01H (Lock Block) D0H (Unlock Block) 2FH (Lockdown Block) Addr=Within block to lock Write (Optional) Read Configuration Data = 90H Addr = X Read (Optional) Block Lock Status Optional Standby (Optional) Read Block Lock Status Comments Block Lock Status Data Addr = Second addr of block Confirm Locking Change on DQ1, DQ0. (See Block Locking State Table for valid combinations.) Locking Change Confirmed? No Write FFh (Read Array) Locking Change Complete 56 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 17. Protection Register Programming Flowchart Start Bus Operation Command Write C0H (Protection Reg. Program Setup) Write Protection Program Setup Data = C0H Write Protection Program Data = Data to Program Addr = Location to Program Write Protect. Register Address/Data Read Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Read Status Register Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. No SR.7 = 1? Comments Repeat for subsequent programming operations. Yes SR Full Status Check can be done after each program or after a sequence of program operations. Full Status Check if Desired Write FFH after the last program operation to reset device to read array mode. Program Complete FULL STATUS CHECK PROCEDURE Bus Operation Read Status Register Data (See Above) VPP Range Error 0,1 SR.1, SR.4 = Protection Register Programming Error Comments Standby SR.1 SR.3 SR.4 0 1 1 VPP Low Standby 0 0 1 Prot. Reg. Prog. Error 1 0 1 Register Locked: Aborted 1, 1 SR.3, SR.4 = Command Standby SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. 1,1 SR.1, SR.4 = Program Successful Datasheet Attempted Program to Locked Register Aborted SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases of multiple protection register program operations before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. 57 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix C Common Flash Interface Query Structure This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control-interface descriptions called Common Flash Interface, or CFI. C.1 Query Structure Output The Query "database" allows system software to gain information for controlling the flash component. This section describes the device's CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest order data outputs (DQ0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (DQ0-7) and 00h in the high byte (DQ8-15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table 14. Summary of Query Structure Output As a Function of Device and Mode Device Device Addresses 58 Hex Offset Code ASCII Value 10: 51 "Q" 11: 52 "R" 12: 59 "Y" Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 15. Example of Query Structure Output of x16 and x8 Devices Word Addressing Offset Hex Code A15-A0 Byte Addressing Value D15-D0 Offset Hex Code A7-A0 Value D7-D0 0010h 0011h 0012h 0051 0052 0059 "Q" "R" "Y" 10h 11h 12h 51 52 59 "Q" "R" "Y" 0013h 0014h 0015h P_IDLO P_IDHI PLO PrVendor ID # PrVendor 13h 14h 15h P_IDLO P_IDLO P_IDHI PrVendor ID # ID # 0016h 0017h 0018h PHI A_IDLO A_IDHI TblAdr AltVendor ID # 16h 17h 18h ... ... ... ... ... ... C.2 Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below. Table 16. Query Structure(1) Offset Sub-Section Name 00h Description Manufacturer Code 01h Device Code (BA+2)h(2) Block Status Register Block-Specific Information 04-0Fh Reserved Reserved for Vendor-Specific Information 10h CFI Query Identification String Command Set ID and Vendor Data Offset 1Bh System Interface Information Device Timing and Voltage Information 27h Device Geometry Definition Flash Device Layout P(3) Primary Intel-Specific Extended Query Table Vendor-Defined Additional Information Specific to the Primary Vendor Algorithm NOTES: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the block size is 32 Kword). 3. Offset 15 defines "P" which points to the Primary Intel-specific Extended Query Table. Datasheet 59 28F800C3, 28F160C3, 28F320C3, 28F640C3 C.3 Block Lock Status Register The block-status register indicates whether an Erase operation completed successfully or whether a given block is locked or can be accessed for flash Program/Erase operations. Block Erase Status (BSR.1) allows system software to determine the success of the last Block Erase operation. BSR.1 can be used just after power-up to verify that the VCC supply was not accidentally removed during an Erase operation. This bit is reset only by issuing another Erase operation to the block. The block-status register is accessed from word address 02h within each block. Table 17. Block Status Register Offset (1) (BA+2)h Length 1 Description Add. Value Block Lock Status Register BA+2: --00 or --01 BSR.0 Block Lock Status 0 = Unlocked 1 = Locked BA+2: (bit 0): 0 or 1 BSR.1 Block Lock-Down Status 0 = Not locked down 1 = Locked down BA+2: (bit 1): 0 or 1 BSR 2-7: Reserved for future use BA+2: (bit 2-7): 0 NOTE: BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.) C.4 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table 18. CFI Identification Offset Length 10h 3 13h 60 Description Add. Hex Code Value Query-unique ASCII string "QRY" 10 11: 12: --51 --52 --59 "Q" "R" "Y" 2 Primary vendor command set and control interface ID code 16-bit ID code for vendor-specified algorithms 13: 14: --03 --00 15h 2 Extended Query Table primary algorithm address 15: 16: --35 --00 17h 2 Alternate vendor command set and control interface ID code 0000h means no second vendor-specified algorithm exists 17: 18: --00 --00 19h 2 Secondary algorithm Extended Query Table address 0000h means none exists 19: 1A: --00 --00 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 C.5 System Interface Information Table 19. System Interface Information Offset Length 1Bh 1 1Ch Add. Hex Code Value VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1B: --27 2.7 V 1 VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1C: --36 3.6 V 1Dh 1 VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts 1D: --B4 11.4 V 1Eh 1 VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts 1E: --C6 12.6 V 1Fh 1 "n" such that typical single word program time-out =2n s 1F: --05 32 s 20: --00 NA 21: --0A 1s 20h 21h 1 1 Description n "n" such that typical max. buffer write time-out = 2 s n "n" such that typical block erase time-out = 2 ms n 22h 1 "n" such that typical full chip erase time-out = 2 ms 22: --00 NA 23h 1 "n" such that maximum word program time-out = 2n times typical 23: --04 512s 24h 1 "n" such that maximum buffer write time-out = 2n times typical 24: --00 NA 25: --03 8s 26: --00 NA 25h 26h Datasheet 1 1 n "n" such that maximum block erase time-out = 2 times typical n "n" such that maximum chip erase time-out = 2 times typical 61 28F800C3, 28F160C3, 28F320C3, 28F640C3 C.6 Device Geometry Definition Table 20. Device Geometry Definition Code See table below Offset Length 27h 1 "n" such that device size = 2n in number of bytes 27: 28: --01 2 Flash device interface: x8 async x16 async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 29: --00 2 "n" such that maximum number of bytes in write buffer = 2n 2A: 2B: --00 --00 0 2Ch 1 Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) 2C: --02 2 2Dh 4 Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes 2D: 2E: 2F: 30: 31h 4 Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes 31: 32: 33: 34: 28h 2Ah Description x16 Device Geometry Definition 8 Mbit Address 62 16 Mbit 32 Mbit 64 Mbit -B -T -B -T -B -T -B -T 27: --14 --14 --15 --15 --16 --16 --17 --17 28: 29: 2A: --01 --00 --00 --01 --00 --00 --01 --00 --00 --01 --00 --00 --01 --00 --00 --01 --00 --00 --01 --00 --00 --01 --00 --00 2B: 2C: 2D: --00 --02 --07 --00 --02 --0E --00 --02 --07 --00 --02 --1E --00 --02 --07 --00 --02 --3E --00 --02 --07 --00 --02 --7E 2E: 2F: 30: --00 --20 --00 --00 --00 --01 --00 --20 --00 --00 --00 --01 --00 --20 --00 --00 --00 --01 --00 --20 --00 --00 --00 --01 31: 32: 33: --0E --00 --00 --07 --00 --20 --1E --00 --00 --07 --00 --20 --3E --00 --00 --07 --00 --20 --7E --00 --00 --07 --00 --20 34: --01 --00 --01 --00 --01 --00 --01 --00 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 C.7 Intel-Specific Extended Query Table Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information. Table 21. Primary-Vendor Specific Extended Query Offset(1) P = 35h Length (P+0)h (P+1)h (P+2)h 3 (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h (P+9)h Description (Optional Flash Features and Commands) Address Hex Code Value Primary extended query table Unique ASCII string "PRI" 35: 36: 37: --50 --52 --49 "P" "R" "I" 1 Major version number, ASCII 38: --31 "1" 1 Minor version number, ASCII 39: --30 "0" Optional feature and command support (1=yes, 0=no) bits 9-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. 3A: 3B: 3C: 3D: --66 --00 --00 --00 4 1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Page mode read supported bit 8 Synchronous read supported Supported functions after suspend: Read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" 3E: bit 0 Program supported after erase suspend (P+A)h (P+B)h 2 Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status Register active bit 1 Block Lock-Down Bit Status active No Yes Yes No No Yes Yes No No =0 =1 =1 =0 =0 =1 =1 =0 =0 --01 bit 0 = 1 Yes 3F: --03 40: --00 bit 0 = 1 Yes bit 1 = 1 Yes (P+C)h 1 VCC logic supply highest performance program/ erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts 41: --33 3.3 V (P+D)h 1 VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts 42: --C0 12.0 V Datasheet 63 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 22. Protection Register Information Offset(1) P = 35h Length (P+E)h 1 Description (Optional Flash Features and Commands) Address Hex Code Value 43: --01 01 44: 45: 46: --80 --00 --03 80h 00h 8 byte (P+12)h This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with deviceunique serial numbers. Others are user programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and userprogrammable. bits 0-7 = Lock/bytes JEDEC-plane physical low address bits 8-15 = Lock/bytes JEDEC -plane physical high address bits 16-23 = "n" such that 2n = factory pre-programmed bytes bits 24-31 = "n" such that 2n = user programmable bytes 47: --03 8 byte (P+13)h Reserved for future use 48: (P+F)h (P+10)h (P+11)h Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Protection Field 1: Protection Description 4 NOTE: The variable P is a pointer which is defined at CFI offset 15h. 64 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix D Architecture Block Diagram DQ0-DQ15 VCCQ Power Reduction Control Input Buffer Identifier Register Status Register Data Register Output Multiplexer Output Buffer I/O Logic CE# WE# OE# RP# Command User Interface Data Comparator WP# A0-A19 Y-Decoder Y-Gating/Sensing Write State Machine Address Counter Datasheet 32-KWord Main Block X-Decoder 4-KWord Parameter Block 32-KWord Main Block Address Latch 4-KWord Parameter Block Input Buffer Program/Erase Voltage Switch VPP VCC GND 65 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix E Word-Wide Memory Map Diagrams 8-Mbit Word-Wide Memory Addressing Top Boot Size (KW) 66 Bottom Boot 8 Mbit Size (KW) 8 Mbit 4 7F000-7FFFF 32 78000-7FFFF 4 7E000-7EFFF 32 70000-77FFF 4 7D000-7DFFF 32 68000-6FFFF 4 7C000-7CFFF 32 60000-67FFF 4 7B000-7BFFF 32 58000-5FFFF 4 7A000-7AFFF 32 50000-57FFF 4 79000-79FFF 32 48000-4FFFF 4 78000-78FFF 32 40000-47FFF 32 70000-77FFF 32 38000-3FFFF 32 68000-6FFFF 32 30000-37FFF 32 60000-67FFF 32 28000-2FFFF 32 58000-5FFFF 32 20000-27FFF 32 50000-57FFF 32 18000-1FFFF 32 48000-4FFFF 32 10000-17FFF 32 40000-47FFF 32 08000-0FFFF 32 38000-3FFFF 4 07000-07FFF 32 30000-37FFF 4 06000-06FFF 32 28000-2FFFF 4 05000-05FFF 32 20000-27FFF 4 04000-04FFF 32 18000-1FFFF 4 03000-03FFF 32 10000-17FFF 4 02000-02FFF 32 08000-0FFFF 4 01000-01FFF 32 00000-07FFF 4 00000-00FFF Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Size (KW) 16 Mbit 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF Datasheet 32 Mbit Bottom Boot 64 Mbit 1FF000-1FFFFF 3FF000-3FFFFF 1FE000-1FEFFF 3FE000-3FEFFF 1FD000-1FDFFF 3FD000-3FDFFF 1FC000-1FCFFF 3FC000-3FCFFF 1FB000-1FBFFF 3FB000-3FBFFF 1FA000-1FAFFF 3FA000-3FAFFF 1F9000-1F9FFF 3F9000-3F9FFF 1F8000-1F8FFF 3F8000-3F8FFF 1F0000-1F7FFF 3F0000-3F7FFF 1E8000-1EFFFF 3E8000-3EFFFF 1E0000-1E7FFF 3E0000-3E7FFF 1D8000-1DFFFF 3D8000-3DFFFF 1D0000-1D7FFF 3D0000-3D7FFF 1C8000-1CFFFF 3C8000-3CFFFF 1C0000-1C7FFF 3C0000-3C7FFF 1B8000-1BFFFF 3B8000-3BFFFF 1B0000-1B7FFF 3B0000-3B7FFF 1A8000-1AFFFF 3A8000-3AFFFF 1A0000-1A7FFF 3A0000-3A7FFF 198000-19FFFF 398000-39FFFF 190000-197FFF 390000-397FFF 188000-18FFFF 388000-38FFFF 180000-187FFF 380000-387FFF 178000-17FFFF 378000-37FFFF 170000-177FFF 370000-377FFF 168000-16FFFF 368000-36FFFF 160000-167FFF 360000-367FFF 158000-15FFFF 358000-35FFFF 150000-157FFF 350000-357FFF 148000-14FFFF 348000-34FFFF 140000-147FFF 340000-347FFF 138000-13FFFF 338000-33FFFF 130000-137FFF 330000-337FFF 128000-12FFFF 328000-32FFFF 120000-127FFF 320000-327FFF 118000-11FFFF 318000-31FFFF 110000-117FFF 310000-317FFF 108000-10FFFF 308000-30FFFF 100000-107FFF 300000-307FFF 0F8000-0FFFFF 2F8000-2FFFFF 0F0000-0F7FFF 2F0000-2F7FFF 0E8000-0EFFFF 2E8000-2EFFFF 0E0000-0E7FFF 2E0000-2E7FFF 0D8000-0DFFFF 2D8000-2DFFFF 0D0000-0D7FFF 2D0000-2D7FFF 0C8000-0CFFFF 2C8000-2CFFFF 0C0000-0C7FFF 2C0000-2C7FFF 0B8000-0BFFFF 2B8000-2BFFFF 0B0000-0B7FFF 2B0000-2B7FFF 0A8000-0AFFFF 2A8000-2AFFFF This column continues on next page Size (KW) 16 Mbit 32 Mbit 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 64 Mbit 3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF This column continues on next page 67 28F800C3, 28F160C3, 28F320C3, 28F640C3 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 68 16 Mbit 32 Mbit 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF Bottom Boot 64 Mbit 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-21FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF This column continues on next page Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 Mbit 32 Mbit 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF F8000-FFFFF F8000-FFFFF F0000-F7FFF F0000-F7FFF E8000-EFFFF E8000-EFFFF E0000-E7FFF E0000-E7FFF D8000-DFFFF D8000-DFFFF D0000-D7FFF D0000-D7FFF C8000-CFFFF C8000-CFFFF C0000-C7FFF C0000-C7FFF This column continues on next page 64 Mbit 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Size (KW) 16 Mbit 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Datasheet 32 Mbit Bottom Boot 64 Mbit Size (KW) 16 Mbit 32 Mbit 64 Mbit 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 69 Appendix F Device ID Table Read Configuration Addresses and Data Item Address Data x16 00000 0089 8-Mbit x 16-T x16 00001 88C0 8-Mbit x 16-B x16 00001 88C1 16-Mbit x 16-T x16 00001 88C2 16-Mbit x 16-B x16 00001 88C3 32-Mbit x 16-T x16 00001 88C4 32-Mbit x 16-B x16 00001 88C5 64-Mbit x 16-T x16 00001 88CC 64-Mbit x 16-B x16 00001 88CD Manufacturer Code Device Code NOTE: Other locations within the configuration address space are reserved by Intel for future use. 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix G Protection Register Addressing Word-Wide Protection Register Addressing Word Use A7 A6 A5 A4 A3 A2 A1 A0 LOCK Both 1 0 0 0 0 0 0 0 0 Factory 1 0 0 0 0 0 0 1 1 Factory 1 0 0 0 0 0 1 0 2 Factory 1 0 0 0 0 0 1 1 3 Factory 1 0 0 0 0 1 0 0 4 User 1 0 0 0 0 1 0 1 5 User 1 0 0 0 0 1 1 0 6 User 1 0 0 0 0 1 1 1 7 User 1 0 0 0 1 0 0 0 NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A21-A8 = 0. Datasheet 71 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix H VF Pitch BGA Package Drawing and Dimensions Figure 18. VF BGA Drawing and Dimensions Ball A1 Corner D 1 E 2 3 4 Ball A1 C orner S1 5 6 7 8 8 A A B B C C D D E E F F 7 6 5 4 3 2 S2 1 e b Bottom View -Bump s ide up Top View - Bump Side down A1 A2 A Seating Y Plan Side View Note : Drawin g not to scale Dimensions Pac kage Height Ball He ight Pac kage Body Thickne ss Ball (Lead) W idth Pac kage Body Width ( 16Mb/ 32Mb) Pac kage Body Width (64Mb) Pac kage Body Length (16Mb/ 32Mb) Pac kage Body Length (64Mb) Pitch Ball (Lead) Count (16Mg) Ball (Lead) Count (32Mg) Ball (Lead) Count (64Mg) Sea ting Plane Coplanarity Corner t o Ball A1 Distance Along D ( 16Mb 32Mb) Corner t o Ball A1 Distance Along D (64M b) Corner t o Ball A1 Distance Along E (16Mb/32Mb) Corner t o Ball A1 Distance Along E (64Mb) Note: 72 Symbol A A1 A2 b D D E E [e ] N N N Y S1 S1 S2 S2 M illimet ers Min Nom M ax 1.000 Notes 0.150 0.325 7.186 7.600 6.864 8.900 0.918 1.125 1.507 2.525 Inches Min Nom Max 0.0394 0.0059 0.665 0.375 7.286 7.700 6.964 9.000 0.750 46 47 48 1.018 1.225 1.607 2.625 0.425 7.386 7.800 7.064 9.100 1 1 1 1 0.0128 0.2829 0.2994 0.2702 0.3506 2 2 2 0.100 1.118 1.325 1.707 2.725 1 1 1 1 0.0361 0.0443 0.0593 0.0994 0.0262 0.0148 0.2869 0.3033 0.2742 0.3546 0.0295 46 47 48 0.0401 0.0482 0.0633 0.1034 0.0167 0.2908 0.3073 0.2781 0.3585 0.0039 0.0440 0.0522 0.0672 0.1073 1.) P ackage dimensions are for reference only. These dimensions are estimates based on die s ize, and are subject to change. 2.) For 16 Mbit devi ces A20 and A21 are not populated. Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix I Easy BGA Package Drawing & Dimensions Ball A1 Corner D 1 E 2 3 4 Ball A1 Corner S1 5 6 7 8 8 A A B B C C D D E E F F G G H H 7 6 5 4 3 2 1 S2 b e Top View - Ball side down Bottom View - Ball Side Up A1 A2 A Seating Y Plane Side View Note: Drawing not to scale Dimensions Table Package Height BallHeight Package Body Thickness Ball(Lead) Width Package Body Width Package Body Length Pitch Ball(Lead) Count Seating Plane Coplanarity Corner to BallA1Distance Along D Corner to BallA1Distance Along E Symbol A A1 A2 b D E [e] N Y S1 S2 Millimeters Min Nom Max Notes 1.200 0.250 0.330 9.900 12.900 1.400 2.900 Inches Min Nom Max 0.0472 0.0098 0.780 0.430 10.000 13.000 1.000 64 1.500 3.000 0.530 10.100 13.100 1 1 0.0130 0.3898 0.5079 0.100 1.600 3.100 1 1 0.0551 0.1142 0.0307 0.0169 0.3937 0.5118 0.0394 64 0.0591 0.1181 0.0209 0.3976 0.5157 0.0039 0.0630 0.1220 Note: (1) Package dimensions are for reference only. These dimensions are estimates based on die size, and are subject to change. Datasheet 73 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix J Additional Information Order Number Document/Tool 297938 3 Volt Advanced+ Boot Block Flash Memory Specification Update 292216 AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory 292215 AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture Contact your Intel Representative 297874 Intel(R) Flash Data Integrator (IFDI) Software Developer's Kit IFDI Interactive: Play with Intel(R) Flash Data Integrator on Your PC NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at `http://www.intel.com/design/flash' for technical documentation and tools. 74 Datasheet 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix K Ordering Information T E 2 8 F 3 2 0 C3 T C7 0 Access Speed (ns) (70, 80, 90, 100, 110) Package TE = 48-Lead TSOP GT = 48-Ball BGA* CSP GE = VF BGA CSP RC = Easy BGA Lithography A = 0.25 m C = 0.18 m D = 0.13 m Product line designator for all Intel(R) Flash products T = Top Blocking B = Bottom Blocking Device Density 640 = x16 (64 Mbit) 320 = x16 (32 Mbit) 160 = x16 (16 Mbit) 800 = x16 (8 Mbit) Product Family C3 = 3 Volt Advanced+ Boot Block VCC = 2.7 V-3.6 V VPP = 2.7 V-3.6 V or 11.4 V-12.6 V VALID COMBINATIONS (All Extended Temperature) 48-Lead TSOP 48-Ball BGA* CSP 48-Ball VF BGA Easy BGA Extended 64 Mbit TE28F640C3TC80 TE28F640C3BC80 GE28F640C3TC80 GE28F640C3BC80 RC28F640C3TC80 RC28F640C3BC80 Extended 32 Mbit TE28F320C3TC70 TE28F320C3BC70 TE28F320C3TC90 TE28F320C3BC90 TE28F320C3TA100 TE28F320C3BA100 TE28F320C3TA110 TE28F320C3BA110 GE28F320C3TD70 GE28F320C3BD70 GE28F320C3TC70 GE28F320C3BC70 GE28F320C3TC90 GE28F320C3BC90 RC28F320C3TD70 RC28F320C3BD70 RC28F320C3TC90 RC28F320C3BC90 RC28F320C3TA100 RC28F320C3BA100 RC28F320C3TA110 RC28F320C3BA110 Extended 16 Mbit TE28F160C3TC70 TE28F160C3BC70 TE28F160C3TC80 TE28F160C3BC80 TE28F160C3TC90 TE28F160C3BC90 TE28F160C3TA90 TE28F160C3BA90 TE28F160C3TA110 TE28F160C3BA110 GE28F160C3TC70 GE28F160C3BC70 GE28F160C3TC80 GE28F160C3BC80 GE28F160C3TC90 GE28F160C3BC90 RC28F160C3TC70 RC28F160C3BC70 RC28F160C3TC80 RC28F160C3BC80 RC28F160C3TC90 RC28F160C3BC90 RC28F160C3TA90 RC28F160C3BA90 RC28F160C3TA110 RC28F160C3BA110 Extended 8 Mbit TE28F800C3TA90 TE28F800C3BA90 TE28F800C3TA110 TE28F800C3BA110 GE28F800C3TA70 GE28F800C3BA70 GE28F800C3TA90 GE28F800C3BA90 RC28F800C3TA90 RC28F800C3BA90 RC28F800C3TA110 RC28F800C3BA110 GT28F320C3TA100 GT28F320C3BA100 GT28F320C3TA110 GT28F320C3BA110 GT28F160C3TA90 GT28F160C3BA90 GT28F160C3TA110 GT28F160C3BA110 NOTE: The second line of the 48-ball BGA package top side mark specifies assembly codes. For samples only, the first character signifies either "E" for engineering samples or "S" for silicon daisy chain samples. All other assembly codes without an "E" or "S" as the first character are production units. Datasheet 75