CY7C955
PRELIMINARY
10
Transmi t SONET Line Overhead Processor (TLOP)
The Transmit SONET line overhead processor (TLOP) pro-
vi d es BIP−8/24 generation and line l evel alarms.
The BIP−8/24 code is calculated as if the STS−3c frame was
composed of three STS−1s. The first B2 byte is calculated over
the first STS−1 frame, the second B2 byte over the second
STS−1 frame a nd the third B2 byte o ver t he third STS−1 frame.
Each B2 bi t is ca lcula ted ov e r the l ine and SPE portions of the
pre vious fra me bef ore scr ambling usi ng even pari ty and i nsert-
ed int o the curren t frame bef ore scr ambling . For STS−1 RATE,
a BIP−8 is calculated over the entire SPE and line overhead
and placed in B2.
The Li ne Alarm Indi cation Signal (LAIS), is as serted by ch ang-
ing al l bits of the SONET fra me into 1 bef ore scram bli ng. LAI S
generation is co ntr olled by a re gister sett ing (Reg−14H, bit 0).
The Line Far End Receive Failure (LFERF), also called Line
RDI, is indicated by placi ng a 110 pattern in bits 6,7, and 8 of
the first K2 byte. LFERF can be asserted under register
(Reg−20H, bit 0) control.
The Line F ar End Bloc k Errors (LFEBE) are located in the thir d
Z2 byte and indicate the num ber of B2 errors in the previous
fr ame i nterval. Legal v al ues f or th is by te a re 00h thr ough 18h.
All bytes of the line data communication channel (D4−D12)
and all other unused byte s are encoded to 00h.
Transmi t SONET Secti on Ov erhead Pr ocessor (TSOP)
The Transmit SO NET Line Overhead Processor (TSO P) pro-
vides A1,A2 framing pattern generation, section BIP−8 (B1)
insertion, section lev el alarm insertion, and frame scrambling.
The A1 and A2 b ytes provide a f raming pattern f or fra me align-
ment. All A1 bytes are coded to F6h and all A2 bytes are coded
to 28h. These b ytes are not scrambl ed upon transm ission.
The STS−1 identification bytes, C1, are used for frami ng and
de-interleaving purposes and are coded the order in their ap-
pearance in the STS−3c frame. The first C1 byt e is coded to
01h, the second to 02h, and the third to 03h.
The section BIP−8 (B1) is the byte-interleaved parity-8 calcu-
lat ed ov er all byt es of the pre vious fr ame after scramb li ng and
insert ed into the current frame before scrambling.
The by tes of the section dat a commun icati on cha nnel, D1−D3
and the remaining unused byte s are set to 00h.
The fr a me is scr amb led pri or t o tran smis sion wi th the genera t-
ing pol ynomial x7 + x6 + 1. The A1, A2, and C1 bytes are not
scrambled. The scrambler runs continuously through the
frame and resets at the beginning of the next transmission
frame. The scram bler ma y be optionally disabled.
Transmi t Clock Generator (TCG)
The TCG accepts a byte-rate transmit clock from TRCLK that
operates at either 19.44 MHz for STS−3c/STM−1 RATE or at
6.48 MHz for STS−1 RATE. The Transmit PLL multiplies this
byte-rate reference by eight to produce the bit-rate clock used
by the parallel-to-serial converter. Optionally a bit-rate sour ce
can be taken from an exter nal source (TBYP = 1) or from the
Receive Clock Recovery block when in loop-time mode
(LOOPT = 1). In loop-time mode the recovered clock is used
to provide timing to t he transmitte r.
Parallel to Serial Converter (PSC)
The PSC converts the parallel data from the TSOP to serial
data. The bit rate clock is derived from the Transmit Clock Gen-
erator. The serialized data and aligned output clock are pre-
sented to the Transmit Output Mult iplexer.
Transmit Output Multiplexer (TOM)
The TOM selects between the serialized output data stream
and associated clock provided by the PSC and the recovered
data and clock from the Receive Clock Recovery block for
transmission based on the state of t he local loop back enab le
(LLE) register (Reg−05H, bit 2). When LLE = 1 the recovered
data and rec ov ere d cloc k is sel ected f or ou tput on th e tra nsmi t
data lines (TXD±) and the transmit clock lines (TXC±). The
output signal is 100K compatible differential Positive-refer-
enced ECL (PECL) signal capable of driving any copper or
fiber based m edia with imped ances as LOW as 50Ω.
Re ceiv e Section
Receive Cl ock Recovery (RCR)
The RCR provides clock and data r ecover y from an incoming
differential PECL data stream. Clock and data ar e recovered
from the incoming differential PECL data stream without the
need for external buffer ing and AC-coupling. The built- in line
receiver inputs have a wide common-mode range (2.5−5V)
and the abi lit y to re ceiv e signal s wit h as lit tle as 200 mV di ff er-
ential voltage. They are compatible with all PECL signals. They
are compat ible with all PECL signals d riven b y opt ical modules
or twisted-pair equalize rs. The Receive PLL uses the RRCLK
as a byte-rate reference. This input is multiplied by 8 and is
used to improve PL L lock time and to prov ide a cent er frequen -
cy for operation in the absence of input data stream transitions.
The receiver can recover clock and data in two different fre-
quency ranges depending on the state of the RATE0 pin. To
insure accurate data and clock recovery, the received data
stream must be within 1000 ppm of RRCLK * 8 (The PLL will
declare Out Of Lock if the dat a rate is different from REFCLK
x 8 by more than 2000 ppm. The PLL will remain Out Of Lock
until the data rate pulls back to within 700 ppm of REFCLK x
8 frequency). The standards, however, specify that the
RRCLK*8 frequency accuracy be within 20−100 ppm. The wid-
er fr equency to leran ce ra nge o f the CY7C955 is a n adv ant age
that allo ws f or highe r fr equenc y tol eranc e i n bench tes ting set-
ups.
A Loss of Signal ( ROOLV = 1) i s declared when no transiti ons
have been detected on the incoming data stream for more than
512 bit-times. LO S is cleared whe n two valid framing p atterns
(A1, A2) have been found and the intervening data does not
contain a period that violates t he minimum tran sit ions limit.
Serial to Parallel Conversion (SPC)
The SPC con verts bi t seri al da ta to b yte s erial data f rom ei the r
the re co ver ed recei v ed dat a o r the trans mit dat a from t he PSC
depending on the stat e of the DLE register (Reg−05H, bit 1).
When DLE =1 transmit data is used for serial to parallel con-
version. The SPC also provides SONET framing by scanning
the incoming data for the SONET framing pat tern A1,A2. For
STS−1 RATE the framer looks for the pattern F628h and for
STS−3 RATE the framer looks for the pattern
F6F6F6282828h. Out of Frame (OOF) is declared when four
consecutive frames contain a framing error. OOF clea rs when
two frames contain valid framing characters. Loss of Frame