PRELIMINARY
AX™ ATM-SONET/SDH Transceiver
CY7C955
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Nov ember 29, 1999
Features
•WAN and LAN ATM physical layer device
•Provides complete physical layer transport of A TM cells
at:
—STS−3c/ STM −1 rate of 155.52 M H z
—STS−1 rate of 51.84 MHz
•Complia nt with ATM Forum User Netw or k Inter face 3. 1
specification
•UTOP IA ATM interfa c e
•ATM cell processing incl uding:
—HEC generati on/verification
—C e ll s cr a mb ling / d esc rambl in g
—Rate adaption/idle cell filtering
—Local Fl ow Control
—C e ll a lig n men t
•SONET frame processing including:
—Compliant with Bellcore GR−253, I.432,
T1.105, and G.709 for Jitter Tolerance and Jitter
Generation
—Frame generation/recovery
—SONET scr ambling/descrambling
—Frequency justification/point er processing
•Complete li ne interface including:
—Clock and data reco very
—Transmit timing derived from receiver or byte-rate
source
—SONET compl iant PLL
—100K PECL compatible I/O
•Alarm indicati ons including:
—Loss Of Signal
—Out Of Frame, Loss Of Frame
— Line Far E n d Re ceiv e Fa ilur e
—Line Alarm I ndication Signal
— B 1 Par it y Erro r
—Loss Of Cell Alignment
—Loss Of Receive Data
•Controller interfa ce for internal int errupt and
configur ation registers i ncluding:
—Error monitoring
—Status in dication
—Device configuration
•0.65µ Low Power CMOS
• 128-pin PQFP
Functional Descri pti on
The Cypress Semiconductor CY7C955 is a Transceiver chip
designed to carry ATM cell s across SONET/SDH systems.
On the transmit side, ATM cells coming from the Utopia inter-
fa ce ar e being mappe d into SONET/ SDH frames and t hen se-
rialized for transmission over fiber or twisted pair (through an
optical module or an equalizer chip).
On the receive side, ser ial SONET/SDH datastreams coming
from an optical module or an equalizer chip are bei ng r ecov-
ered by the intergrated clock and dat a recovery phase-locked
loop, framed, processed, and presented as parallel ATM cells
on the Receive Utopia I nterface.
The CY7C955 can be used in a Network Interface Card (NIC)
design to connect the segmentation and Reassembly (SAR)
chip to t he opti cal modules or equalizer chip.
The CY7C955 can also be used in work group or enterprise
switches to connect the I/O FIFOs of the switch fabric to the
optical module or equali zer in the interface boards.
The applications of the CY7C955 include adapters, switches,
router s, hubs, and proprietary syst em s.
TABLE OF CONTENTS
Features 1
Functional Description 1
Pin Descripti ons 2
Pin Configuration 7
Description 8
Transmit Section 8
Receive Section 10
Control ler Interface (CI) 12
Loopback Operation 16
SONET Overhead Description 17
CY7C955 Regist er Map 18
Electrical Characterist ics 60
Capacitance 61
AC Test Loads and Waveforms 61
Switching Characteristics 61
CY7C955
PRELIMINARY
2
Pin Descriptions
CY7C955 ATM-SONET/SDH Transceive r
Switchi ng Wa vef orm s 63
Functional Timing Diagram 69
Inter face Terminati on and Biasing Schemes 73
Filter Pi n Confi guration 75
Ordering I nformation 76
P ackage Diagr am 77
TABLE OF CONTENTS (c onti nued)
INTB
RALM
RFP
RATE1
ALE
A[7:0]
D[7:0]
TDAT[7:0]
TSOC
TFCLK
RBYP
RRDENB
RFCLK
RSOC
RXPRTY
RRCLK±
TXD±
TXPRTY
Rate
Selection
Error Monitoring
Configuration and S tatus
Interface
Controller
SONET/SDH
Recovery
ProcessorProcessorProcessor Buffer
Transmit
Multiplier &
Clock
Transmit
Processor
ATM Cell
Transmit Transmit Transmit TransmitTransmit
UTOPIA I/F
Tra nsm it FIF O
4 Cell by 8 bit
4 Cell by 8 bit
UTOPIA I/F
Path
Overhead Overhead Overhead
Line Section
SectionLine OverheadOverheadOverhead
PathATM Cell
Processor Processor Processor Processor
Receive Receive Receive ReceiveReceive
Receive FIFO
Register File
TBYP
TRCLK±
TXC±
Clock
RATE0
RXD±
RXDO±
RCA
RCLK
TCA
TFPO
RDAT[7:0]
TWRENB
RDB
WRB
CSB
TSEN
TCLK
RCP
RGFC XOFF
TGFC
TCP
RSTB ALOS±
7C955−1
Transmi t Utopia Int erface
Name Pin I/O Description
TDAT[7:0] 87−94 Input Transmit Utopia data: Byte-wid e data driven from the ATM to PHY la yer . TD AT[7] is the
MSB.
TPRTY 95 Input Transmit Utopia Data Parity: Data parity calculated over TDAT[7:0]. Odd parity is as-
sumed unless the TXPTYP bit (Reg–63, bit 7) is set to ev en parity
TSOC 96 Input Transm it Utopia Start of Cell: Assert TSOC HIGH when TD AT[7:0] contains the first
byt e of an ATM ce ll. If TSOC is as serted so oner than 53 writes a fter the previou s SOC,
an error condition will be generated. This input i s opti onal after the fir st TSOC pulse .
TFCLK 84 Input Transm it Utopi a Clock: Data transfer clock. Data is transferred to the AX on the risi ng
edge of TFCLK when TWRENB is asserted (LOW).
TWRENB 85 Input Transmit Utopia Data Enable: Enables the TFCLK input for data transfer to the AX. This
signal is active LOW.
CY7C955
PRELIMINARY
3
TCA 86 Output Transmi t Utopi a Cell Availab le: An a ctive state on this si gnal in dicate s that t he Trans mit
FIFO can acce pt at lea st N more cell s (53 oc tets) of dat a wh ere N and the acti ve st ate
of the si gnal (HIGH or LOW) are programmab le through the configur ation registers
(Reg−63H an d Reg−01H) . I n a s peci al case , i f Reg –63H bi t2−3 is set to 00 , Reg−01H,
bit 3 is set to 0, and TCALEVEL0 ( Reg –63H, bit 1) set to 0. TCA will beha ve as an
acti ve HIGH FULL indicator.
Transmi t Utopia Int erface (continued)
Name Pin I/O Description
Transmit ATM Interface
Name Pin I/O Description
XOFF 50 Input Transmit Idle Cel l: A HIGH stat e on thi s pin will force the ATM Cell Processor to send
an IDLE cel l e v en if there ar e cell s to send i n the Transm it FIFO . XOFF i s an async hro-
nous input and has an integr ated pull down re sistor.
TGFC 52 Input Transmit Gen eric Fl ow Cont rol: This bi t serial input pr ovide s the ab ili ty to ov erwrite the
four bits of the ATM cell header G FC field. These bits may be optionally written during
the four TCLK cloc k periods following the assertion of the TCP out put.
TCP 51 Output Transmi t Start Of GFC: This indi cates th at the firs t bit of the GFC f or the ne x t cell read
from the Transmit FIFO is expected on the TGFC pi n during the next risin g edge of
TCLK.
Transmi t Cloc k G enerator
Name Pin I/O Description
TRCLK±9−10 Dif ferenti al In Transmit Input Cloc k: Accepts either a diff erenti al PECL, or a TTL or a CMOS byte rate
reference connected to TRCLK− with TRCLK+ gr ounded fo r the Transmi t f requency
mult iplier PLL. Opti onall y, this input can ac cept also t he bit rat e ref eren ce whe n TBYP
is true (hel d HIGH). In this mode the Transm it frequenc y multipl ier is bypas sed and the
bit rate cl ock is used directly for transmit side clocking.
TXC±13−14 Differential Out Transmi t Output Clock: Provides clock output for the transmit data. TXD± i s updated
on the fall ing edge of this signal. In the default set ti ng, TXC is disabled if RATE0 is
HIGH and a 51.84-MHz clock if RATE0 is LOW. XORTXC (Reg−04H, bit 6) can be used
to in vert the def ault setting suc h that TXC is a 155.52-MHz cloc k if RATE0 is HIGH and
is disabled whe n R ATE 0 is LOW.
TXD±15−16 Differential Out Transmi t Data Output: Accepts NRZ encoded output data. This signal is updated on
the falling edge of TXC±.
TBYP 2Input Transm it Clock Byp ass: When t his i nput i s hel d HIG H the trans mit freq uency m ult iplier
is disabled and TRCLK± input is used directly f or transmit side clocking. When this input
is hel d LO W the tr ansmit f requenc y mul tipl ier mul tip lies the TRCLK ± input b y 8, 24, or
8/3 (depending on the TREFSEL (Reg−0 6H, bi t 0) setting to provide the internal bit
rate clock .
RATE0
RATE1 97−98 Input RATE: When the RATE0 input i s HIGH the Transmit frequency gene rator and the Re-
ceive clock recovery are selected to operate at the STS−3c/STM−1 rate of 155.52 MHz.
When the RATE0 pi n is LO W, the Transm it frequen cy generat or and th e Recei v e cloc k
reco v ery ar e s electe d to op er ate at the STS −1 rat e o f 51.8 4 MHz. RATE1 is f or f act ory
testing use only and should be tied HIGH. Both RATE0 and RATE1 hav e integrated
pull-up resistors.
TCLK 54 Output Transmi t Byte Reference: Byte rate ref erence clock derived fr om the tra nsm it line bit
rate.
TFPO 53 Output Transmit Frame Reference. This signal is an 8-kHz frame rate reference that goes
HIGH during the t ransmission of the fi rst A1 byte of the SONET/SDH frame. TFPO is
updated by the rising edge of TCLK.
Re cei ve C lock R eco very
Name Pin I/O Description
RXD±25−26 Differential In Receive Input Data: These line receiver inputs are connected to an internal Recei ve
PLL that r ecover s the embedded clock and data informati on. The incom ing data rate
can be within one of two frequency ranges depending on the stat e of the RATE0 pin.
CY7C955
PRELIMINARY
4
RXDO±22−23 Differential Out Receive Output Data: These different ial output s represent the retimed version of the
input data stream (RXD±) in normal mode and the buf fe red ver sion of the input datas -
tream (RXD±) i n bypass mode. Thi s output pair can be used as inputs to decision
feedback equalizers to correct for baseline wander. RXDO can be turned off to save
power by setting R XDOD (Reg−04H, bit 7) to 1.
RRCLK±33−34 Differential In Receive Clock : These inpu ts are u sed to cloc k in the diff erenti al data (RXD±) when the
Receiv e cloc k recov e ry bl ock is by passe d (RBYP=HIGH). If RBYP is LO W , RRCLK is
mult ipli ed by 8, 24, or 8/3 d ependi ng on t he setting of RREFSEL (Reg−07H, bit 0) and
use as a ref erence for th e Receiver PLL. Refer to the s ection on “I nterface Termination
and Bias of Schemes” for connection examples to these pins.
RBYP 41 Input Receive Cloc k Bypass: When this input is HIGH the Receiver clock recovery block is
bypassed. In this mode th e device do es not reco ver clock and data from the Receive
input data stream (RXD±) bu t ins tea d uses t he RRCLK± inputs to c lock t he dif f erenti al
data into the device. When this input is LOW the Receiver clock recovery block recovers
the clock and data from the input data stream. In this mode a byte-rate clock is expected
on the RRCLK± inputs.
RCLK 57 Output Receive Byte Reference: Provides a byte-r ate reference derived from the reco vered
bit- rate Receive clock. RALM, RCP, and RGFC are al igned with th is clock.
RFP 58 Output Receive F rame Ref erence: This output pro vides a frame-rate reference clock aligned
to the SONET/SDH frame alignment bytes. RFP wil l pulse HIGH f or one RCLK cycle
every 125 seconds even at OOF and LOF sit uations.
LF+ 42 Input NC. This pin is for factor y testing only.
LF–, LFO 43, 44 Input These are the PLL fil ter pins. Connect a 0.47-µF cap acito r across LF– and LFO.
Re cei ve C lock R eco very (contin ued)
Name Pin I/O Description
Receive ATM Interface
Name Pin I/O Description
RGFC 59 Output Receive Gene ric Flow Control: This outp ut pr ovides the four bits of the current ATM
cell header GFC l ocati ons a t each suc cess iv e RCLK pulse . The RCP output indi cates
the f irst GFC bit locat ion. This out put i s f or ced LOW if t he ATM Cell Processo r has l ost
cell delineat ion.
RALM 63 Output Receive Interrupt: This active HIGH signal is aligned with the RCLK byte-rate clock and
signals the presence of LAIS, PAIS, LOS, LOF, LOP, or LCD.
RCP 60 Output Receive Start Of GFC: This output indicates the first bit of the GFC presented on the
RGFC output. This out put goes HIGH for 1 RCLK cycle 6 byte times after the corre-
sponding cell is written int o the Receive FIFO.
Receive Utopia Interface
Name Pin No I/O Description
RDAT[7:0] 70−71
74−79 Output Receive Utopia Data: Byt e-wide data driv en from th e PHY to ATM la yer . RDAT[7] is t he
MSB
RPRTY 82 Output Receive Utopi a Data Parity: Data parity calculated over RD AT[7:0]. Odd parity is as-
sumed unless the TXPRTY bit is set to even parit y by Reg−50H, bit 6.
RSOC 83 Output Receive Utopi a Start of Cell: Asserted HIGH when RD AT[7:0] co nta ins t he fi rst byte of
an AT M cell.
RFCLK 67 Input Rece ive Utopia Cl ock: Data transf er cl ock. Data i s tran sferred from t he AX o n the rising
edge of RFCLK when RRDENB is asserted ( LOW).
RRDENB 68 Input Receiv e Utopia Enable: Enabl es the RFCLK input f or data trans fers from the AX.
RCA 69 Output Receive Utopia Cell Availab le: An activ e signal indi cates that the Receive FIFO con-
tains at least 1 or 4 more bytes of data. RCA is controlled by RCAINV (Reg−01H, bit
2) and RCALEVEL0 (Reg−59H, bit 2).
CY7C955
PRELIMINARY
5
TSEN 66 Input Rece ive Output Enab le: This output operates in conjun ction wi th the RRDENB output.
When TSEN is HIGH and RRDENB is HIGH the Receive UTOPIA data bus (RDA T[7:0],
RPR TY, and RSOC) is three-stated. When TSEN is HIGH and RRDENB is LOW the
data bus is driv en with the re quested data. When TSEN is LOW the data bus will not
three-state.
Receive Utopia Interface (contin ued)
Name Pin No I/O Description
Controller Interface
Name Pin No I/O Description
D[7:0] 110−112
115−118 I/O Data[7:0]: Bidirecti onal data bus used to transfer data to and fr om the internal config-
uration, st atus, and error monitoring regi sters.
A[7:0] 119−126 Input Address[7:0]: Address bus used to sele ct the inte rnal reg ister for reading or writ ing.
ALE 127 Input Address Lat ch Enabl e: Whe n this input is LO W the address is latc hed from the A[7:0]
inputs. W hen this input is HI G H, t he input is transparent. ALE has an i ntegrated pull-
up resis tor.
RDB 105 Input Read: This activ e LOW signal is used to read the internal register. The AX drives D[7:0]
when RDB and CSB are both LOW.
WRB 104 Input Write: Thi s active LOW signal is used to write the int ernal registers. Data is latched
into the specified address register on the rising edge of WRB when CSB is LOW.
CSB 100 Input Select : Thi s active LOW device select has to be enabled during register accesses.
INTB 108 Output Inter rupt: This act ive LOW open drai n output tr ansitions LOW when an unmasked
inter rupt source is acti ve. This output trans it ions HIGH when the appropriate r egister
has been rea d. Th is inter rupt sig nals the most crit ical error s tates of the de vi ce inc lud-
ing Loss of P oi nter, Li ne Alarm Indicat ion Si gnal (LAI S), Li ne F ar End Receive F ai lure
(LFERF), Loss of F rame (LOF) , Out of Fr ame (OOF), Loss of Signal (LOS), and many
others.
ALOS±27−28 Differen tia l In Carrier Det ect: This differential i nput contr ols the reco very functio n of the Receive PLL
and can be driven b y the carrier detect output from opti cal module s or fr om external
transition detecti on circuitry. When this input is at a Logic Low, the input data stream
(RXD±) is recovered normal ly b y t he Recei v e Cloc k Recov ery PLL. When this input is
at a L ogic Hi gh, the Receiv e PLL n o longe r ali gns t o RXD±, b ut inste ad aligns with the
RRCLK * 8 freq uency and the LOS alarm register (RDOOLV) will be set . Besi des
differential PECL, t he ALO S− in put can be set to accept single ended PECL input if
ALOS+ is tied to GND. ALOS− has to be decoupled.
RSTB 101 Input Reset: This active LOW signal provides a device reset. This line can be pul led LOW
to put the CY7C95 5 i nto th e power -down mode . RSTB has an int egra ted pul l-up resis -
tor.
VCLK 99 Input Factory test pin. Must be LOW f or normal operation. VCLK has an integrated pull-down
resistor.
Transmi t Po wer
Name Pin No I/O Description
TXVDD 12 Power The Transmit Pad Power supplies the TXD± outputs. TXVDD is phy sically isol ated from
the ot her dev ice power pins and should be well regulat ed +5V DC and noise-f ree f or good
performance when drivi ng category 5 unshielded twist pair cabling.
TAVD1 4Power The pow er pin for the transmit clock synthesizer reference cir cuitry. TAVD1 should be
connected to analog +5V.
TAVD2 6Power The pow er pin for the transmit clock synthesizer oscil lator. TAVD2 should be connected
to analog +5V.
TAVD3 8Power The pow er pi n for the tr ansm it PECL inputs . TAVD3 should be connected to analog +5V.
TVDDO 18 Power Power for TXC± and RXDO±.
CY7C955
PRELIMINARY
6
Receive Power
Name Pin No I/O Description
RAVD1 30 Power The power pin for receive clock and data recovery block ref erence circuitry . RA VD1 should
be connected to analog +5V.
RAVD2 36 Power The power pin for receive clock and data recovery block acti ve loop fil ter and oscillator .
RAVD2 should be connected to analog +5V.
RAVD3 24 Power The power pin for the RXD± and ALOS± PECL inputs. RAVD3 should be connected to
analog +5V.
RAVD4 32 Power The po wer pin f or the RRCLK ± PECL inp uts. RAVD4 should be co nnect ed to an alog +5V.
Core Pow er
Name Pin No I/O Description
VDDI 20, 61,
107 Power The core power pins shoul d be connected to a well decoupled +5V DC in common with
VDDO.
VDDO 55, 73,
81, 114 Power The pad ring po wer pins should be conn ected to a well decoupled +5V DC in common
with VDDI.
Ground
Name Pin No I/O Description
TAVS1 5Ground Th e g round pin for the tr ansmit clock synthesizer reference circuitry. TAVS1 sho uld be
connected to analog GND.
TAVS2 7Ground Th e ground pin for the transmit c lock syn thesizer oscillator. TAVS2 should be connected
to analog GND.
TAVS3 11 Ground Th e gro und pin f or the tr ansmit PECL inputs. TA VS3 should be connect ed to anal og GND .
TXVSS 17 Ground The transmit pad ground is the return path for the TXC± and TXD± outputs. TXVSS is
physically isolated from the othe r device ground pins and should be noise-fr ee for good
performance when drivi ng category 5 unshielded twist ed pair cabling.
RAVS1 31 Ground The ground pin for receive clock and data recovery block reference circuitry . RAVS1 should
be connected to analog GND.
RAVS2 37 Ground Th e ground pin for receive clock and data recovery block activ e loop filter and oscillator.
RAVS2 should be connected to analog GND.
RAVS3 29 Ground The ground pin for the RRCLK± PECL inputs. RAVS3 should be connected to analog GND .
RAVS4 35 Ground The ground pin for the RSD± and ALOS± PECL inputs. RAVS4 should be connected to
analog GND.
RVSSO 21 Ground This pin is grounded for TXC± and RXDO±.
VSSI 19, 62,
106,48 Ground The core ground (VSSI) pins should be connected to GND in common with VSSO.
VSSO 56, 72,
80, 113,
49
Ground The pad ring ground (VSSO) pins should be connected to GND in common with VSSI.
VSS 1, 38,
39, 46,
47, 64,
65, 102,
103,
128
Ground These pins must be connected to GND for correct operation.
ATP1,
ATP2,
ATP3
40, 3,
46 I/O These Analog Test Point s (ATPx) are for factory testing use only. These pins hav e to be
tied to GND for correct chip operation.
CY7C955
PRELIMINARY
7
Pin Configuration
128-pin PQFP
Top View
TBYP
ATP2
TAVD1
TAVS1
TAVD2
CY7C955
TAVS2
ATM
TAVD3
TRCLK–
SON ET / SD H
TRCLK+
TRANSCEIVER
TXVDD
AX
TXC+
RVSS
TXC–
TXD+
TXD–
TXVSS
TVDDO
VSSI
RAVD3
RXD–
RXD+
ALOS–
ALOS+
RAVS3
RAVD1
RAVS1
RRCLK–
RRCLK+
RAVS4
RAVD2
RAVS2
VSS
TAVS3
VDDI
RXDO+
RXDO–
RAVD4
ATP1
VSSI
RGFC
RBYP
LF+
LF−
LFO
ATP3
VSS
VSS
VSSO
XOFF
TCP
TGFC
TFPO
TCLK
VDDO
VSSO
RCLK
RFP
RCP
VDDI
VSSI
RALM
VSS
VSS
TSEN
RFCLK
RRDENB
RDAT[0]
RDAT[1]
VSSO
VDDO
RDAT[2]
RDAT[3]
RDAT[4]
RDAT[5]
RDAT[6]
RDAT[7]
VSSO
VDDO
RPRTY
TDAT[0]
TDAT[1]
TDAT[2]
TDAT[3]
TDAT[4]
TDAT[5]
TDAT[6]
TDAT[7]
TPRTY
TWRENB
RSOC
TCA
TSOC
RATE[1]
RATE[0]
VSS
CSB
RSTB
VSS
A[0]
D[0]
INTB
VDDI
D[1]
VSS
VSS
WRB
RDB
VSSI
D[2]
D[3]
VSSO
VDDO
D[4]
D[5]
D[6]
D[7]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
ALE
TFCLK
VSS
RCA
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
41
42
128
43
127
44
126
45
125
46
124
47
123
48
122
49
121
50
120
51
119
52
118
53
117
54
116
55
115
56
114
102
57
113
101
58
112
100
59
111
99
60
110
98
61
109
97
62
63
96
64
108
107
95
106
105
94
104
103
93
92
91
90
40
89
1
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
65
66
68
67
7C955−2
CY7C955
PRELIMINARY
8
Description
Transmit Section
Transmi t Utopia Inter face (TUI)
The transmit int erface provides a si mple access from the ex-
ternal environment to the ATM Transceiver. The operation of
this interface is compliant with the Utopia interface specifica-
tion. The interface provides a 9-bit b y 4-cell FIFO to decou ple
the system interface from the ATM physical layer timing. 9-bit
w ords ar e cloc k ed i nto t he d e vice through a c loc k ed FIFO s ys-
tem interface. These 9 bits include an 8-bit data word along
with a Start Of Cell (SOC) indication. The interface also pro-
vides full and almost full indications (TCA). Maximum clock
rate for this interface is 33 MHz.
Transmit ATM Cell Processor (TA C P)
The ATM cell processor provides HEC generat ion, idle/unas-
sign ed cell header modifi cation, pa yload scr ambl ing, and GFC
insertion.
HEC Generator
The Header Error Check (HEC) code is contained in the last
byte of the ATM cell header and is capable of si ngle error cor-
rection and m ultipl e error detection. Whe n op ti onally generat-
ed, t he Trans mit ATM Cell Proce ssor ca lc ulates a CRC−8 o ver
the f irst f our byt es o f the ATM ce ll he ader usi ng the pol ynomi al
x8 + x2+ x + 1. The coset x 6 + x4 + x2 + 1 is added (modulo 2)
to the residue of thi s funct ion. The HEC is calc ulated in accor-
dance with ANSI T1.624−1993 and CCITT Recommendation
I.4 32. Thi s HEC sequ ence is plac ed i n the 5th byte of the ATM
cell header .
Idle/Unassigned Cell Header Modification
Idle (Unassigned) cells are sent by the ATM cell processor
whenever a com plete cell is not contained within th e Transmit
FIFO. This transforms the non-continuous cell input stream
into a continuous stream of assigned and unassigned cells.
The ATM cell processor provides the ability to overwrite the
Generic Flow Control (GFC), the Payload Type Indication
(PTI), and the Cell Loss Priority (CLP) fields of Idle (Unas-
signed) cells with the values contained in the corresponding
configuration regi sters . VPI and VCI are set to zero in Idle (Un-
assigned) cell s.
Payload Scram bler
The 48 bytes of the ATM payload are scrambled using a par-
all el implem entation of the polynomial x43 + 1 as descri bed in
CCITT Recomm endation I.4 32. The scram bler can be option-
all y deselected.
GFC Insertion
The transmitted GFC field of an ATM cell can be derived from
different sources. For assigned cells, the default is from pins
TDAT[7:0]. For Idle (Unassigned) cells, the default is from
GFC[3:0] (Reg−61H, bit 7−bit 4). However, if any bit of
TGFCE[3:0] (Reg−67H, bit 7−bit4) is set, the corresponding
transmitted GFC location wi ll instead be taken from the serial
TGFC (pin 52) input following the f unct ional timing speci fica-
tions described in the section on Transmit GFC Serial Link
Interface.
Transmit SONET Path Overhead Processor (TPOP)
The SONET pa th ov e rhead pr ocessor pro vides pa yloa d point -
er alignment (H1, H2), path overhead inser tion, and insertion
of the Synchronous Pa yload En velope (SPE). ATM cells (both
assigne d and una ssigned ) are in serted into the SPE for tr ans-
mission in the SONET fram e
SONET Overhead Inser tion
The SONET/SDH STS−3c/STM−1 f ram e struct ure i s sho wn i n
Figure 1 and the SONET STS−1 frame str ucture is shown in
Figure 2. The SONET frame occurs once every 125 µs and is
transmitted beginning with the A1 bytes, followed by the A2
bytes, C1 bytes, 261 bytes (87 bytes for STS −1) of the Syn-
chronous Payload Envelope (SPE), B1 bytes, etc., until the
entir e fr am e is transmitted.
The TPOP generates the H1 and H2 bytes that indicate the
beginning of the SPE and the H4 byte that indicates the ATM
cell offset within the SPE. The default initial value for H1 and
H2 pointer is 522, meaning that t he first byte of t he SPE (J1)
corresponding to a frame actually starts after the C1 byte of
the next frame.
In the d efaul t case des cribed above , a 6h is p resent in t he New
Data Flag (NDF) portion of the first H1 (bits 0−4), a 2h is
present in bits 5−7 and a 0Ah is present in the first H2 byte.
The remai ning H1 b ytes f or STS−3c/STM−1 are set to 93h and
the remai ning H2 b ytes ar e se t to FF h which i s the c onca tena-
tion indication for the J1 pointer. The Pointer Action byt e, H3,
is set to 00h. During Pa th AIS all of the H1 and H2 bits are set
to 1.
The STS path tra ce J1 is set to all zero s. The path BIP−8 (B3)
byte provides path error monitoring. This function calculates
the bi t-i nterleav ed parity- 8 code us ing e v en parity ove r the pre-
vious SPE before scram bling and is inserted into the current
B3 byte before scrambling. Bit-interleaved parity-8 forces the
number of 1s in the xth bit of every byte in the previ ous SPE
plus th e xth bit of the B3 by te in t he cur rent SPE to be an ev en
number.
The path signal level indicator, C2, defaults to 13h.
The path status, G1, has several functions. Bits 1 through 4
are used to indicate Far End Block Er rors (FEBE) der ived by
counti ng the number of BIP−8 errors oc curred in the last frame
received. Valid codes are 0 through 8. If more than 8 errors
have accumulated since the last, frame the m aximum value is
sent wi th the c urrent frame , the F EBE count er is decrement ed
by 8, and the remaining errors are sent with the next frame.
FEBE may be inser ted through register control for diagnostic
purposes. Bits 1 through 4 can also be used to transmit Far
End Receive Failures by setting these bits to 9 (1001). This
error indicates to t he far end that cel l delineatio n has been lost .
Bit 5 can be used to generate a yellow alar m condition. The
default val ue for this bit is 0 (no alarm).
The m ult i-frame indicator, H4, is used to indicate the fi rst ATM
cell and may take on values of 00 to 34h.
The remaining bytes, F2, Z3, Z4, and Z5, are not used by the
SONET path processing and are set to 00h upon transmission.
When oper ati ng in STS−1 mode , SPE colu mns 30 and 5 9 can
be configure d as fi xed stuff col um ns.
CY7C955
PRELIMINARY
9
.
Figure 1. STS −3c/STM−1 Framing Form at
A1 A1 A1 A2 A2 A2 C1 C1 C1
B1
H1 H1 H1 H2 H2 H2 H3 H3 H3
B2 B2 B2 K2
Z2
J1
B3
C2
G1
H4
Line Section
Path
Payload
Payload
F2
Z3
Z4
Z5
E1 F1
D1 D2 D3
K1
D4 D5 D6
D7 D8 D9
D10 D11 D12
Z1 Z1 Z1 Z2 Z2 E2 HD1 HD2 HD3 HD4 HEC PAYLOAD
9Bytes 261Bytes
9 Bytes
7C955−3
Figure 2. STS−1 Framing Format
A1 A2 C1
B1
H1 H2 H3
B2 K2
J1
B3
C2
G1
H4
Line Section
Path
Payload
Payload
F2
Z3
Z4
Z5
E1 F1
D1 D2 D3
K1
D4 D5 D6
D7 D8 D9
D10D11 D12
Z1 Z2 E2 HD1 HD2 HD3 HD4 HEC PAYLOAD
3Bytes 87 Bytes
9 Bytes
7C955−4
CY7C955
PRELIMINARY
10
Transmi t SONET Line Overhead Processor (TLOP)
The Transmit SONET line overhead processor (TLOP) pro-
vi d es BIP−8/24 generation and line l evel alarms.
The BIP−8/24 code is calculated as if the STS−3c frame was
composed of three STS−1s. The first B2 byte is calculated over
the first STS−1 frame, the second B2 byte over the second
STS−1 frame a nd the third B2 byte o ver t he third STS−1 frame.
Each B2 bi t is ca lcula ted ov e r the l ine and SPE portions of the
pre vious fra me bef ore scr ambling usi ng even pari ty and i nsert-
ed int o the curren t frame bef ore scr ambling . For STS−1 RATE,
a BIP−8 is calculated over the entire SPE and line overhead
and placed in B2.
The Li ne Alarm Indi cation Signal (LAIS), is as serted by ch ang-
ing al l bits of the SONET fra me into 1 bef ore scram bli ng. LAI S
generation is co ntr olled by a re gister sett ing (Reg−14H, bit 0).
The Line Far End Receive Failure (LFERF), also called Line
RDI, is indicated by placi ng a 110 pattern in bits 6,7, and 8 of
the first K2 byte. LFERF can be asserted under register
(Reg−20H, bit 0) control.
The Line F ar End Bloc k Errors (LFEBE) are located in the thir d
Z2 byte and indicate the num ber of B2 errors in the previous
fr ame i nterval. Legal v al ues f or th is by te a re 00h thr ough 18h.
All bytes of the line data communication channel (D4−D12)
and all other unused byte s are encoded to 00h.
Transmi t SONET Secti on Ov erhead Pr ocessor (TSOP)
The Transmit SO NET Line Overhead Processor (TSO P) pro-
vides A1,A2 framing pattern generation, section BIP−8 (B1)
insertion, section lev el alarm insertion, and frame scrambling.
The A1 and A2 b ytes provide a f raming pattern f or fra me align-
ment. All A1 bytes are coded to F6h and all A2 bytes are coded
to 28h. These b ytes are not scrambl ed upon transm ission.
The STS−1 identification bytes, C1, are used for frami ng and
de-interleaving purposes and are coded the order in their ap-
pearance in the STS−3c frame. The first C1 byt e is coded to
01h, the second to 02h, and the third to 03h.
The section BIP−8 (B1) is the byte-interleaved parity-8 calcu-
lat ed ov er all byt es of the pre vious fr ame after scramb li ng and
insert ed into the current frame before scrambling.
The by tes of the section dat a commun icati on cha nnel, D1−D3
and the remaining unused byte s are set to 00h.
The fr a me is scr amb led pri or t o tran smis sion wi th the genera t-
ing pol ynomial x7 + x6 + 1. The A1, A2, and C1 bytes are not
scrambled. The scrambler runs continuously through the
frame and resets at the beginning of the next transmission
frame. The scram bler ma y be optionally disabled.
Transmi t Clock Generator (TCG)
The TCG accepts a byte-rate transmit clock from TRCLK that
operates at either 19.44 MHz for STS−3c/STM−1 RATE or at
6.48 MHz for STS−1 RATE. The Transmit PLL multiplies this
byte-rate reference by eight to produce the bit-rate clock used
by the parallel-to-serial converter. Optionally a bit-rate sour ce
can be taken from an exter nal source (TBYP = 1) or from the
Receive Clock Recovery block when in loop-time mode
(LOOPT = 1). In loop-time mode the recovered clock is used
to provide timing to t he transmitte r.
Parallel to Serial Converter (PSC)
The PSC converts the parallel data from the TSOP to serial
data. The bit rate clock is derived from the Transmit Clock Gen-
erator. The serialized data and aligned output clock are pre-
sented to the Transmit Output Mult iplexer.
Transmit Output Multiplexer (TOM)
The TOM selects between the serialized output data stream
and associated clock provided by the PSC and the recovered
data and clock from the Receive Clock Recovery block for
transmission based on the state of t he local loop back enab le
(LLE) register (Reg−05H, bit 2). When LLE = 1 the recovered
data and rec ov ere d cloc k is sel ected f or ou tput on th e tra nsmi t
data lines (TXD±) and the transmit clock lines (TXC±). The
output signal is 100K compatible differential Positive-refer-
enced ECL (PECL) signal capable of driving any copper or
fiber based m edia with imped ances as LOW as 50Ω.
Re ceiv e Section
Receive Cl ock Recovery (RCR)
The RCR provides clock and data r ecover y from an incoming
differential PECL data stream. Clock and data ar e recovered
from the incoming differential PECL data stream without the
need for external buffer ing and AC-coupling. The built- in line
receiver inputs have a wide common-mode range (2.5−5V)
and the abi lit y to re ceiv e signal s wit h as lit tle as 200 mV di ff er-
ential voltage. They are compatible with all PECL signals. They
are compat ible with all PECL signals d riven b y opt ical modules
or twisted-pair equalize rs. The Receive PLL uses the RRCLK
as a byte-rate reference. This input is multiplied by 8 and is
used to improve PL L lock time and to prov ide a cent er frequen -
cy for operation in the absence of input data stream transitions.
The receiver can recover clock and data in two different fre-
quency ranges depending on the state of the RATE0 pin. To
insure accurate data and clock recovery, the received data
stream must be within 1000 ppm of RRCLK * 8 (The PLL will
declare Out Of Lock if the dat a rate is different from REFCLK
x 8 by more than 2000 ppm. The PLL will remain Out Of Lock
until the data rate pulls back to within 700 ppm of REFCLK x
8 frequency). The standards, however, specify that the
RRCLK*8 frequency accuracy be within 20−100 ppm. The wid-
er fr equency to leran ce ra nge o f the CY7C955 is a n adv ant age
that allo ws f or highe r fr equenc y tol eranc e i n bench tes ting set-
ups.
A Loss of Signal ( ROOLV = 1) i s declared when no transiti ons
have been detected on the incoming data stream for more than
512 bit-times. LO S is cleared whe n two valid framing p atterns
(A1, A2) have been found and the intervening data does not
contain a period that violates t he minimum tran sit ions limit.
Serial to Parallel Conversion (SPC)
The SPC con verts bi t seri al da ta to b yte s erial data f rom ei the r
the re co ver ed recei v ed dat a o r the trans mit dat a from t he PSC
depending on the stat e of the DLE register (Reg−05H, bit 1).
When DLE =1 transmit data is used for serial to parallel con-
version. The SPC also provides SONET framing by scanning
the incoming data for the SONET framing pat tern A1,A2. For
STS−1 RATE the framer looks for the pattern F628h and for
STS−3 RATE the framer looks for the pattern
F6F6F6282828h. Out of Frame (OOF) is declared when four
consecutive frames contain a framing error. OOF clea rs when
two frames contain valid framing characters. Loss of Frame
CY7C955
PRELIMINARY
11
(LOF) is declared when the OOF condition fails t o clear wit hin
3 m s. LOF cl ears after 3 ms of fr am es with valid framing char-
acters.
Receive SONET Section Overhead Processor (RSOP)
The RSOP provides descrambling, SONET sect ion alarm in-
dication, and error monitoring.
The data is descrambled using the generating polynomial 1 +
x6 + x7. The A1, A2, and C1 bytes are not descrambled. The
scrambling process may be disabled under register control.
The BI P−8 value calculated ov er the pre vious scrambled frame
is c ompared with t he B1 byt e of the cur rent f rame section over-
head after descrambling. If the two values do not match, the
B1PAR output is taken HIGH. Up to 64,000 errors can be de-
tected per second (8000 frames/second * 8 bit-errors
(max)/frame). Errors are recorded in a 16-bit saturating
counter that can be read through the con tr oller int erface.
Receive SONET Line Overhead Processor (RLOP)
The RLOP provides SONET line alarm indications and error
monitoring.
A Line Al arm Indi cation Signal (LAIS) is asserted when a 111
pattern is dete cted for five consecutive frames in bits 6,7, and
8 of the first K2 byte of the Automatic Protection Switching
channel . LAIS is remov ed when anyt hing other t han a 111 pat-
tern is received for five consec uti ve fra me s.
A Line Far End Receive Failure (LFERF) or Line RDI is indi-
cated with a 110 pattern is detected for five consecutive frames
in bi ts 6,7, and 8 of the first K2 byte. LFERF is remo ved when
anything other than a 110 pattern is received for five consec-
utiv e frames.
The BI P−24 (BIP−8 for STS−1 RATE) value c alculated o ve r th e
pre vious l ine ov erhead a nd SPE i s compar ed with t he B2 by tes
of current frame. Up to 192,000 errors can be detected per
second (3 channels/frame * 8 errors (max)/channel * 8000
frames/second). Errors are recorded in a 20-bit saturating
counter that can be read through the con tr oller int erface.
Far End Block Errors (FEBE) are detected by examining the
val ue i n t he t h ird Z2 byt e. T hi s val ue (0 −18h) is added to the
count in an 18-bit satur ating counter that can be read through
the controller int erface.
Receive SONET Path Overhead Processor (RPOP)
The RPOP provides pointer interpretation, SPE extraction,
SONET path alarm indications, and err or monitoring .
The payl oad loc ation is d ete rmined b y e xam inin g the v alues in
the H1 a nd H2 by tes of the l ine o v erhea d whi ch i ndicat e the J 1
byte of the SPE. The RPOP can process a J1 byte located
anywh ere in the SPE. Loss of P ointer ( LOP) is set when a val id
pointer value has not been found within eight consecutive
frames. This register bit is cleared when a valid pointer is found
for three consecutive frames. Path Alarm Indication Signal
(PAIS) (Reg30H, bit 3) is set when the H1 and H2 bytes are
set to all ones for 3 consecutive frames. This register bit is
cleared when a valid pointer is found for three consecutive
fr ames . PAIS does not caus e LOP to be s et. The SPE lo catio n
is provided to the Recei ve ATM Cell Processor for cell extrac-
tion.
The BIP−8 value calculated over the previous SPE is com-
pared with the B3 byte of the current path overhead. Up to
65,535 errors can be detected per second. Errors are recorded
in a 16-bit saturating counter that can be read through the
control ler interface.
Path F a r End Bl ock Err ors (PF EBE) are detected b y examining
the value in bits 1 through 4 of G1. This value (0−8h) is added
to the count in a 16-bit saturating counter that can be read
through the controller interface.
Path Far End Receive Failures (PFERF) are detected by ex-
amining the value in bits 1 through 4 of G1. If this value is 9h
for two consecutive f rames, PFERF is set. This register bit is
cleared when anything other than 9h appears for two consec -
utive frames.
Path Remote Defect Indication (Path RDI) is detected by ex-
amining bit 5 of G1. If t his v alue is 1 h for 5 c onsecuti ve f ram es,
PYEL is set. This register bit is cleared when a 0 appears in
bit 5 f or 5 consec uti ve fram es.
Receive ATM Cell Pr ocessor (RACP)
The RA CP block provides cel l del ineation, HEC checking and
correct ing, cell filtering for idle/unassigned cells, cell payload
descrambl ing, status indications, and error mon it oring.
Cell d elineation is per formed by co mparin g the HEC seque nce
calculated over the first four bytes of the SPE to the fi fth byte.
If these values match, cell boundar y has been determined. If
not, the calcula tion adv ances one byte further into the pa yload
(bytes 2−5) and the check is performed again. The HEC se-
quence is a CRC−8 calculated over the first 4 octets of the ATM
cell header using the polynomial x 8 + x2 + x + 1. The coset x6
+ x4 + x2 + 1 is added (modulo 2) to t he residue before com-
parison with the recei ved seque nce . This is t he HUNT st ate of
the cel l del ineat ion pr ocess . W hen a v al id matc h has occurr ed
the process enters the PRESYNC state. When 7 consecutive
matches occur the process enters the SYNC state. If 6 con-
secutive incorrect HEC matches are detected the process
moves back to the HUNT state. The average time for cell de-
linea tion is 93µs for STS−1 and 31µs for S T S −3C.
The HEC sequence is used not only to check for cell align-
ment, but also to insure that integri ty of the ATM header. The
HEC is used t o correct single bit errors and to detect mult iple
bit errors. This feature can be disabl ed. The register file con-
tains two sat urat ing 8- bit coun ters for HEC errors; on e f or cell s
with single bit errors and another for multiple-bit errors. Cells
with multiple bit errors are optionally discarded. Figure 3
show s the state di agram fo r HEC.
The RACP optionally discards Idle/Unassigned cells. These
cells contain a VPI/VCI address of 0h. Also, a Header Mask
and Header Match register are provided to allow cell s with a
particular header characteristic in GFC, PTI and CLP to be
filtered.
The payload of valid cells are descrambled using the polyno-
mial x43 +1. The cell headers are not descrambled since they
CY7C955
PRELIMINARY
12
were not scramb led upon t ransmissi on. The descra mbl ing f ea-
ture can be disabled.
Receive Utopia Interface (RUI)
The RUI provides a simple access from the external environ-
ment to t he ATM Transcei ver. The opera tion of thi s inter fa ce is
compliant wit h the Utopia interface specification that is being
standardized by the ATM Forum. The interface provides a 10
bit by 4 cell FIFO to decouple the system interface from the
ATM physical layer timing. Ten bit words are clocked out from
the device through a clocked FIFO style interface. These 10
bits include an 8-bit data word along with an parity bit
(RXPRTY) and a Start Of Cell (SOC) indic ati on. The interface
also provides a cell available (RCA) indication and a read en-
abl e (RRDENB) control. RCA al lows t he FIFO to indi cate emp-
ty and almost empty conditions and RRDENB allows the
downstream circui t to pause the reading proc ess in case t he
downs tream can not accept an ymore read. If the Rec eive FIFO
overflows, FIFO reset will occur and up to 4 cells m ay be lost
because of the operation.
Controller Interface (CI)
The CI interface provides external access to the internal reg-
ister fi le, device resetting and external input fo r t he carrier de-
tect signal. The ALOS input al lows an exter nal carrier detect
from an optical modul e to cause an interrupt t o the control ler.
The INTB and RALM pins can be configured to interrupt the
ext ernal con tro ller whe ne v er an y of se v e ral diff er ent error con-
ditions occur. RALM signals the most important error condi-
tions such as LOS, LOF, line AIS, path AIS, LCD, and LOP.
INTB may indicate all possi ble errors depending on the state
of the mask regist ers . IN TB pro vides n otif icati on of the indiv id-
ual processing block that generated the error condition. The
error register cont ained in each block will det ermine the exact
c a u se of th e int e rrupt.
Figure 3. HEC Verification St ate Diagram
ATMDELINEATION
SYNC STATE
DELTA
consecutive HECs
(From PRESYNCstate)
ALPHA
consecutive
HECs (From
HUNT state)
DETECTION
MODE
CORRECTION
MODE
Apparent Multi-Bit Error
(Drop Cell)
No Errors
Detected
PassCell Single Bit Error
(Correct Error
and PassCell)
No ErrorsDetected
(PassCell)
Errors
Detected
(Drop
Cell)
7C955−5
Figure 4. SO NET/SDH and ATM Int erface
Fiber or Copper
Media Interface Receive Serial Data
Buffered TransmitData
Fiber or Copper
Media Interface
Carrier Detect
Receive Parallel Data
Receive Start of Cell
Read Strobe
TransmitParallel Data
TransmitStart of Cell
TransmitParity
Packet
Reassembly
or
ATM Switch
Core
Packet
Segmentation
or
ATM Switch
Core
7C955−6
Clock andData
Recovery and
Receive
Equalization
Frequency
Multiplication &
Transmit
Buffering
SONET/SDH
Overhead Processing ATM Cell
Processing
Controller
Interface
Byte Rate
Oscillator
CY7C955ATM−SONET/SDHTransceiver(AX)
WriteStrobe
Receive Parity
CY7C955
PRELIMINARY
13
Note:
1. B1, B2, Z2, G1, H4, and B3 are variables.
Figure 5. Default Values for the Tr ansmitted Section and Line STS−3C/STM−1 Overhead
F6H
A1 F6H
A1 F6H
A1 28H
A2 28H
A2 28H
A2 01H
C1
00H00H00H00H00H00H
00H
00H
00H
00H
00H
00H
00H00H
00H
00H
00H
00H
00H
00H
00H
00H
00H00H
00H
00H
00H
00H
00H00H
00H
00H
00H
00H00H00H
B2
02H
C1 03H
C1
00H
E1 00H
F1
00H
D1
0AH
H2
62H
H1
00H
K1
00H
D4
00H
Z1
00H
D6
00H
K2
00H
H3
00H
D5
FFH
H2 FFH
H2 00H
H3 00H
H3
Z2
93H
H1 93H
H1
00H
D7 00H
D8
00H
D11
00H
D9
00H
D12
00H
E2
00H
D10
00H
Z1 00H
Z1 00H
Z2 00H
Z2
00H
D2 00H
D3
B1
B2 B2
[NOTE 1]
NOTE 1
[NOTE 1] [NOTE 1] [NOTE 1]
7C955−7
CY7C955
PRELIMINARY
14
Figure 6. Default Values for the Transmitted Section and Line STS−1 Overhead
B1
F6H
A1 F6H
A2
00H
D1
62H
H1
00H
D4
00H
Z1
0AH
H2 00H
H3
00H
D7
00H
D10
00H
E2
B2
00H
C1
00H
F1
00H
E1
00H
D2 00H
D3
00H
K1 00H
K2
00H
D5 00H
D6
00H
D8 00H
D9
00H
D11 00H
D12
Z2
NOTE 1
NOTE 1
NOTE 1
7C955−8
CY7C955
PRELIMINARY
15
Figure 7. Default Values for the Transmit ted Path Overh ead
B3
00H
J1
13H
C2
00H
Z5
00
Z3
00H
Z4
G1
H4
H
00H
F2
NOTE 1
NOTE 1
NOTE 1
7C955−9
CY7C955
PRELIMINARY
16
Loopback Ope ratio n
VCLK
INTB
RALM
RFP
RATE1
ALE
A[7:0]
D[7:0]
TDAT[7:0]
TSOC
TFCLK
RBYP
RRDENB
RFCLK
RSOC
RXPRTY
RRCLK±
TXD±
TXPRTY
Rate
Selection
Error Monitoring
Configuration and Status
Interface
Controller
SONET/SDH
Recovery
ProcessorProcessorProcessor Buffer
Transmit
Multiplier &
Clock
Transmit
Processor
ATM Cell
Transmit Transmit Transmit TransmitTransmit
UTOPIA I/F
Transmit FIFO
4 Cell by 8 bit
4 Cell by 8 bit
UTOPIA I/F
Path
Overhead Overhead Overhead
Line Section
SectionLine OverheadOverheadOverhead
PathATM Cell
Processor Processor Processor Processor
Receive Receive Receive ReceiveReceive
Receive FIFO
Register File
TBYP
TRCLK±
TXC±
Clock
RATE0
RXD±
RXDO±
RCA
RCLK
TCA
TFPO
RDAT[7:0]
TWRENB
RDB
WRB
CSB
TSEN
TCLK
RCP
RGFC XOFF
TGFC
TCP
RSTB ALOS±
High Speed Line Loopback 7C955−10
VCLK
INTB
RALM
RFP
RATE1
ALE
A[7:0]
D[7:0]
TDAT[7:0]
TSOC
TFCLK
RBYP
RRDENB
RFCLK
RSOC
RXPRTY
RRCLK±
TXD±
TXPRTY
Rate
Selection
Error Moni toring
Co nf igur a tio n and S ta tus
Interface
Controller
SONET/SDH
Recovery
ProcessorProcessorProcessor Buffer
Transmit
Multiplier &
Clock
Transmit
Processor
AT M Ce ll
Transmit Transmit Transmit TransmitTransmit
UT OP IA I/F
Transm it FIFO
4 Cell by 8 b it
4 Cell by 8 b it
UT OP IA I/F
Path
Overhead Overhead Overhead
Line Section
SectionLine OverheadOverheadOverhead
PathATM Cell
Processor Processor Processor Processor
Receive Receive Receive ReceiveReceive
Receive FIFO
Re gi s t er Fil e
TBYP
TRCLK±
TXC±
Clock
RATE0
RXD±
RXDO±
RCA
RCLK
TCA
TFPO
RDAT[7:0]
TWRENB
RDB
WRB
CSB
TSEN
TCLK
RCP
RGFC XOFF
TGFC
TCP
RSTB ALOS±
Diagnostic Loopback 7C955−11
CY7C955
PRELIMINARY
17
SONET Overhead Description
Signal Values Description
A1, A2 The fr ame al ignment b ytes mark the begi nning of a SONET fr ame. The y are tr ansmitt ed every 125
µs in bo th OC−1 and OC3c speeds. Transmit Side: I n OC−1, A1(F6H) an d A2 (2 8 H) are inserted
into the tra nsm itted stre am at t he beginning of ev ery fr am e. These b ytes are not scrambled by the
frame synchronous SO NET scrambler. Receive Side: The receiver wil l search for and frame onto
the incomi ng A1, A2 bytes.
C1 This is t he ident ifi cati on byt e f or the STS d ata stream. Transmi t Side: I n OC−1 , C1 is tran smit ted as
OH . In OC −3c, the sequence C1, C1, C1 of every frame is transmitted as 01H, 02H, 03 H. These
bytes are not scramb led by the frame-sy nchronous SONET sc rambl er. Recei ve side: The receiver
wil l i gnore C1.
B1 This is the section bit interleav e parity byte. Transmit Side: B1 is calculated using the BIP−8 algorithm
descri bed in I.432. I t is inserted into the SONET data st ream bef ore the fra me syn chronous SONET
scrambler. Receive Side: Receiv ed B1 error events are accumulat ed in the SBE [15:0] (Reg−12H
and Reg−13H).
H1, H2 These are the poi nter v alue b yte. The se byt es are use d t o locat e the begi nning of th e Sync hronous
P ay load Env elope (SPE) in the SONET/SDH frame. Tran smit si de: H1, H2 contains th e normal new
data flag (0110) togeth er with 522 (deci m al) as the fixed pointer value field. The concatenati on
indi cation byte is also i nserted (H1* = 93, H2* = FF). Re ceive Side: H1 and H2 are used to l ocate
the b eginning of the SPE. I f a v alid pointer canno t be fou nd, CY7C955 will indicate a Los s of P ointer
State . Path AIS is detected by an all-ones pattern in H1 and H2 bytes.
H3 This is the pointer acti on byte. Transmit Side: H3 wi ll be all ze roes. Receive Side: Synchronous
Payload Data wi ll be stuf fed in the H3 byte if a negative stuff event occurs. This byte is i gnored
otherwise.
B2 This is the line bit interleaved parit y bytes, it is used to monito r line errors. Transmit Side: B2 is
calculated over all bits of t he line overhe ad and the SPE capacity of the pr evious frame before the
frame is being scrambled. The B2 by te itself is then placed in the current frame before scramble.
K2 This is the identity line lay er maint enance signal . Trans mit Side : Bits 6, 7, and 8 of this b yte are ‘110’
bef ore scrambl ing when Lin e Remote Def ect Indicat ion i s true. The whole of K2 is an al l-one pattern
before scrambl ing if Line AIS is inserted. Receiv e Side: Bits 6, 7, and 8 of the K2 by te are being
examined to determin e the pr esence of AIS , and RDI signal s. Access to APs registers will be
available in future revisions.
Z2 This is the growth byte. It is used to provide f ar end block error function useful f or remote performance
monitoring. Transmit Side: The number of B2 errors detected in the last frame is inserted. Z2 is a
num ber fr om 0−24 indi cati ng 0 −24 error s. Rec eiv e Side: A legal (0−24) Z2 n umber will be add ed t o
the l ine FEBE counter.
B3 This is the interl eaved parit y byte. Transmit Si de: B3 is calculated ove r al l bi ts of the SPE of the
previous frame before scrambling and is placed in the current frame before scrambling. This provides
path error monitoring cap abilit y for the link. Receive Side: The value in B3 is accumulated i n a
register.
C2 This is the pat h signal label byte for indicating the contents of the SONET payload. Transmi t Side:
It’s fixed value is 13H. Thi s indicates the payload is ATM. Receive Side: The receive side e xpects
C2 to be 13H. If the data is not 13H for 3 consecutive fr am es, an interrupt (if enab led) will be
generated.
G1 This is the path stat us byte. Transm it Side: P ath remote def ect Indication (Path RDI) together with
the number of B3 errors in the l ast fram e are i nserted i nto G1 before scrambling for tra nsm ission.
G1 is a number from 0−8, indicating 0−8 errors. Receiv e side: A legal G 1 value (0−8) wi l l be accu-
mulated in the FEBE counter. Path remote defect indicati on is also detected through this byte.
H4 This is the cel l offset b yte. Transmit Side: Thi s byte i ndicates the off set in b ytes bet ween the H4 byte
and the first cell byte after H4. Receive Side: H4 byte is ignored.
CY7C955
PRELIMINARY
18
CY7 C95 5 R egister M ap
Address Register
Reg−00H Mas ter Reset/Type/Identify Register
Reg−01H Mas ter Configuration Register
Reg−02H Mas ter Interrupt Register
Reg−04H Mas ter Clock Monitor Regist er
Reg−05H Master Control Register
Reg−06H Transmit Clock Synthesi s Cont rol Register
Reg−07H Receive Clock Synthesis Control Register
Reg−10H Receive Section Overhead Processor C ontrol Register
Reg−11H Receive Section Ove rhead Proc essor Status Regi ster
Reg−12H LSB of the Recei ve Section Overhead Processor Status BIP-8 Counter
Reg−13H MSB of the Recei ve Section Overhead Process or Sta tus BIP-8 Counter
Reg−14H Trans mit Section Overhead Processor Control Regist er
Reg−15H Trans mit Section Overhead Processor Control Error Insertion Register
Reg−18H Receive Line Overhead Processor Control and Status Regi ster
Reg−19H Receive Line Overhead Processor Inter rupt Enab le and Status Regi ster
Reg−1AH Li n e BIP−8/24 Regist er
Reg−1BH Li n e BIP−8/24 Regist er
Reg−1CH Lin e B IP −8/24 Regist er
Reg−1DH Line Far-End Block Error Register
Reg−1EH Line Far-End Block Error Register
Reg−1FH Line Far-End Block Error Register
Reg−20H Transmit Line Overhead Processor Regi ster
Reg−21H Transmit Line Overhead Processor Error I nsert ion Register
Reg−30H Receive P ath Overhead Processor Interrupt Regis ter
Reg−31H Receive P ath Overhead Processor Regist er
Reg−33H Receive P ath Overhead Processor Interrupt Enable Register
Reg−37H Receive P ath Signal Label Register
Reg−38H Path BIP−8 (B3) Register
Reg−39H Path BIP−8 (B3) Register
Reg−3AH Path Far-End Blo ck Error Regi ster
Reg−3BH Path Far-End Blo ck Error Regi ster
Reg−3CH P ath F ar-End Block Err or Regi ster
Reg−40H Transmit Path Overhead Processor Error Insertion Register
Reg−41H Transmit Path Overhead Processor Poi nter Control Register
Reg−45H Transmit Path Overhead Processor Arbit rar y Payload Poi nter R egister
Reg−46H Transmit Path Overhead Processor Arbit rar y Payload Poi nter R egister
Reg−48H Transmit Path Overhead Processor Path Signal Label Register
Reg−49H Transmit Path Overhead Processor Arbitrar y Path Stat us Register
Reg−50H Receive ATM Cell Pro cessor Control and Status Regis ter
Reg−51H Receive ATM Cell Pro cessor Interrupt Register
Reg−52H Receive ATM Cell Pro cessor Match Header P attern Register
Reg−53H Receive ATM Cell Processor Match Header Mask Register
Reg−54H Receive ATM Cell Processor Correc table HCS Error Count Register
CY7C955
PRELIMINARY
19
RESET
This is the master reset bit. Toggling thi s register has the same effect as toggling the RSTB pin, except that RSTB will reset all
registers to their default values, while writing a 1 to this register will only reset al l other registers (but not itself) to their default
values . Leaving a 1 in th is regist er puts the AX in power-down mode.
0: Normal mode.
1: Reset / Power Down Mode.
TYPE[2:0]
These bits dif ferentiate the AX with other Cypress products.
ID[3:0]
These bits show the revision num ber of the CY7C955.
Reg−55H Receive ATM Cell Pro cessor Uncorrectable HCS Error Coun t Regi ster
Reg−56H Recei ve ATM Cell Processor Receiv e Cell Counter Register
Reg−57H Recei ve ATM Cell Processor Receiv e Cell Counter Register
Reg−58H Recei ve ATM Cell Processor Receiv e Cell Counter Register
Reg−59H Receive ATM Cell Pro cessor Receive Configur ation Regis ter
Reg−60H Transmit ATM Cell Processor Control and Status Register
Reg−61H Transmit ATM Cell Processor Unassigned Cell Header Register
Reg−62H Transmit ATM Cell Processor Unassigned Cell Payload Register
Reg−63H Transmit ATM Cell Processor FIFO Control Register
Reg−64H Transmit ATM Cell Processor Transmit Cell Counter Register
Reg−65H Transmit ATM Cell Processor Transmit Cell Counter Register
Reg−66H Transmit ATM Cell Processor Transmit Cell Counter Register
Reg−67H Transmit ATM Cell Processor Transmit Configuration Register
Reg−80H CY7C955 Test Control Regist er
CY7 C95 5 R egister M ap (continued)
Address Register
REG−00H Master Reset / Type / Identi ty Regi ster
BIT POSITION NAME READ/WRITE DEFAULT
7RESET R/W 0
6TYPE[2] R 0
5TYPE[1] R 1
4TYPE[0] R 1
3ID[3] R 1
2ID[2] R 1
1ID[1] R 1
0ID[0] R 1
CY7C955
PRELIMINARY
20
REG − 01H Master Configurati on Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6AUTOFEBE R/W 1
5AUTOLRDI R/W 1
4AUTOPRDI R/W 1
3TCAINV R/W 0
2RCAINV R/W 0
1RXDINV R/W 0
0Unused
AUTOFEBE
This bi t cont rols whether F ar End Bloc k Error (FEBE) i s tr ansmit ted when l ine or pa th BIP e rror is being de tec ted on t he rec eiv e
data st ream.
0: Do not generate line or path FEBE error in respons e to in com ing line or path BIP er ror.
1: Generat e line or path FEBE error in response to incoming line or path BIP error.
AUTOLRDI
This bi t controls whether Line Remote Defect Indication (LRDI) is transmitted when an incoming alar m is being det ected.
0: Do not ins ert line RDI when line AIS , Loss of Frame (LOF) or Loss of Signal (LOS) i s being detected.
1: Insert line RDI when li ne AIS, Loss of Frame (LOF) or Loss of Signal (L OS) is being detect ed.
AUTOPRDI
This bit cont rols whet her STS Pat h Remote Def ect Indi cati on (PRDI) is tr ansmit ted when an incomi ng alarm is being detect ed.
0: Do not in sert STS path RDI when Loss of Signal ( LOS), Loss of P oi nter (LOP), STS pat h AIS, Los s of F r ame (LOF), l ine
AIS, or Loss of Cel l Del ineation (LCD) is being detected.
1: Insert STS path RDI when Los s of Sign al (LOS) , Loss of P oin ter (LOP) , STS path AIS, Loss of Fram e (LOF), line AIS , or
Loss of Cell Deli neation (LCD) is being det ected.
TCAINV
This bi t contr ols the polarity of TCA.
0: TCA is active HIGH.
1: TCA is active LOW.
RCAINV
This bi t contr ols the polarity of RCA.
0: RCA is activ e HIGH.
1: RCA is active LOW.
RXDINV
Th is bi t co n tr o ls the in te rp r e ta tion of the d iffer e nt ia l p ai r RX D.
0: Logical 1 is represented by RXD+ HIGH and RXD− LOW.
1: Logical 0 is represented by RXD+ HIGH and RXD− LOW.
CY7C955
PRELIMINARY
21
REG − 02H Master Inter rupt Register
BIT POSITION NAME READ/WRITE DEFAULT
7TROOLI R
6LCDI R
5RDOOLI R
4TACPI R
3RACPI R
2RPOPI R
1RLOPI R
0RSOPI R
TROOLI
This is the Trans mit Reference Out Of Lock Interrupt. Thi s bit reset s when Reg−02H is being read.
1: TR OO LV (Reg−06H, bit 3) has changed state since Reg −02H was l ast read.
0: TR OO LV (Reg−06H, bit 3) has not changed state since Reg−02H was last read.
LCDI
This is the Loss of Cell Delineati on Interrupt. It has to be enabled by bit 7 of Reg−05H. Th is bit resets when Reg−02H is be ing
read.
1: Loss of cell delineati on is entered or e xited sinc e Re g−02H was la st read.
0: Th ere i s no change in the loss of cell delineation sta te.
RDOOLI
This is the Receive Data Out Of Lock Interrupt. Thi s bi t resets when Reg−02H is being rea d.
1: RDOOLV (Reg−07H, bit 3) has changed st ate since Reg−02H was last read.
0: RDOOLV (Reg−07H, bit 3) has not chang ed state since Reg−02H was last read.
TACPI
This i s the Transmit ATM Cell Processor Int errupt. Thi s bit reset s when Reg−02H is bei ng read. This r egister is a logical OR of
all the Transmit ATM Cell Processor (TAC P) interrupts Reg−60H and 63H.
1: FOVRI, TSOCI, or TXPRTYI is HIGH.
0: FOVRI, TSOCI, and TXPRTYI are all LO W.
RACPI
This is the Receive ATM Cell Processor Interrupt . Thi s bit reset s when Reg−02H is being read. This register is a lo gical OR of
all the Receiv e ATM Cell Processor (RA CP) inter rupts of Reg−51H.
1: OOCDI, CHCSI, or UHCSI is HIGH.
0: OOCDI, CHCSI, and UHCSI are all LOW.
RPOPI
This is the Recei ve Path Overhead Processor Interrupt. This bit reset s when Reg−02H is being read. This register is a logical
OR of all the Receive Path Overhead Processor (RPOP) interrupts of Reg−31H.
1: PSLI, LOPI, PAISI, PRDII, BIPEI, or FEBEI is HIGH.
0: PSLI, LOPI, PAISI, PRDII, BIPEI , and FEBEI are al l LOW.
RLOPI
This is the Receive Line Overhead Processor Int errupt. This bit resets when Reg−02H is being read. This register is a logical
OR of all the Receive Line Overhead Processor (RLOP) inter rupts of Reg−19H.
1: FE B EI, B IP E I , LA I S I, o r R DII is HI GH .
0: FEBEI, BIPEI, LAISI, and RDII are all LOW.
RSOPI
This is the Recei ve Secti on Overhead Proce ssor Interrupt . This bit resets when Reg −02H is being r ead. This re gister is a l ogical
OR or all the Receive Section Overhead Processor (RSOP) interrupts or Reg−11H.
1: BIPEI, LOSI, LOFI, or OOFI is HIGH.
0: BIPEI, LO SI, LO FI, and OOFI are al l LOW.
CY7C955
PRELIMINARY
22
REG − 04H Master Clock Monitor Register
BIT POSITION NAME READ/WRITE DEFAULT
7RXDOD R/W 0
6XORTXC R/W 0
5Unused
4Unused
3RRCLKA R
2TRCLKA R
1RCLKA R
0TCLKA R
RXDOD
This bi t is used to turn off t he RXDO output in case it is not needed. This helps save power and reduce power supply noise.
1: RXDO output is disabled.
0: RXDO is the reti m ed buffered output of RXDXOR TXC.
XORTXC is used to invert the default-on status of the TXC output.
1: TXC is disabled if RATE0 is LOW, and TXC is a 155.52- MHz clock if RATE0 is HI GH.
0: TXC is a 51.84 -MHz clock if RATE0 is LOW, and TXC is disab led if RATE0 is HIGH.
RRCLKA
This bit can be read to check f or RRCLK transitions; when HIGH, thi s bit stays HIGH until Reg−04H is being read.
1: RRCLK+ has a LO W to HIGH transition since this register was last re ad.
0: RRCLK+ has no LO W to HI GH t ransitions since this register was last read.
TRCLKA
This bit can be read to check f or TRCLK transi ti ons; when HIGH, this bit stays HIGH unti l Reg−04H is being read.
1: TRCLK+ has a LOW to HIGH transit ion since this register was last read.
0: TRCLK+ has no LOW to HIGH transitions since this register was last read.
RCLKA
This bit can be read to check f or RCLK transitions; when HIGH, this bit st ays HIGH until Reg −04H is bei ng read.
1: RCLK has a LO W to HIGH tr ansition since this regi ster was last read.
0: RCLK has no LO W to HIGH tr ansitions since thi s register was l ast read.
TCLKA
This bit can be read to check for TCLK transi ti ons; when HIGH, this bit st ays HIGH until Reg−04H is bei ng read.
1: TRCLK+ has a LOW to HIGH transit ion since this register was last read.
0: TRCLK+ has no LOW to HIGH transitions since this register was last read.
CY7C955
PRELIMINARY
23
REG − 05H Master Control Register
BIT POSITION NAME READ/WRITE DEFAULT
7LCDE R/W 0
6LCDV R
5FIXPTR R/W 1
4Unused
3Unused
2LLE R/W 0
1DLE R/W 0
0LOOPT R/W 0
LCDE
This bi t enables a change in the Loss of Cell Delineati on st ate to generate an interrupt on pin INTB.
0: INTB will not be affected by a transition in LCDV (Reg−05H, bit 6).
1: INTB will go LOW when there is a transition in LCDV (Reg−05H, bi t 6).
LCDV
This bit shows the pr esent loss of cell del ineation state of the Receive ATM Cell overhead Processor (RA C P).
0: RACP is in SYNC sta te for longer than 4 ms.
1: RACP is out of cell delineation for more than 4 ms and there are no detected LO S, LO P, Path AIS, and Line AIS.
FIXPTR
This bi t controls the operation of the transmit payload pointer adjustment function.
0: The sett ing in Reg−41H can con trol the payload point er adjustment operations .
1: The transmit payload pointer i s fixed at 522.
LLE
This bit controls t he li ne loop-back path of the CY7C955; DLE and LLE cannot be both set to 1.
0: Normal operation.
1: RXD+ and RXD− are connected to TXD+ and TXD− internally.
DLE
This bit controls t he diagnostic loo p-back path of the CY7C95 5; DLE and LLE cannot be both set to 1.
0: Normal operation.
1: The transmitted dat a steam is being looped back to the received data stream.
LOOPT
This bi t enables loop timi ng.
0: The transmitted data stream derives its clock from TRCLK. The clock to use depends on the setting of TREFSEL
(Reg−06H, bit 0) and on the level of pi ns TBYP and RATE0.
1: The transmit ted data stream derives its clock from RRCLK if the cloc k and data recovery function of the rec eiver is not
acti ve and from RXD if the cloc k and data recovery functio n is active . Agai n, the clock to use in RRCLK depends on
the setting of RREFSEL (Reg−07H), RBYP, and RATE0.
CY7C955
PRELIMINARY
24
REG − 06H Transmit Clock Synthesis Control Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5Unused
4Unused
3TROOLV R
2Unused
1TROOLE R/W 0
0TREFSEL R/W 0
TROOLV
This bit is t he Trans m it Reference Out Of Lock Status register.
0: The divi ded-down syn thesized transmi t cl ock is within 2930 ppm of TRCLK or RRCLK (in loop ti ming mode).
1: The divi ded-down synthesized transmit clock is not within 293 0 ppm of TR CLK or RRCLK (in loop t iming mode).
TROOLE
This bi t is the Transmit Reference Out Of Lock Interrupt Enable register.
0: INTB, the inter rupt pin, will not be affected by transmit out of lock.
1: INTB, the interrupt pi n, will pull LO W when there is a state change of TROOLV.
TREFSEL
This bi t is the Transmit Reference Select. This bit is ignored in transmit bypass mode (TBYP = 1).
0: TRCLK expects a 19.44-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS−3c/STM−1), the transmit PLL will
multiply the TRCLK frequency by 8 times. If RATE0 is LOW (51.84 Mbps, STS−1), the transmit PLL will multiply the
TRCLK frequency by 8/3 tim es to cl ock the transmitter.
1: TRCLK expects a 6.48-M Hz reference clock. If RATE0 is HIGH (155.52 Mbps, STS−3c/STM−1), the transmit PLL will
multiply the TRCLK frequency by 24 times. If RATE0 is LOW (51.84 Mbps, STS−1), the trans mit PLL w ill m ulti ply t he
TRCLK frequency by 8 ti m es to clock the transmitter.
CY7C955
PRELIMINARY
25
REG − 07H Receive Cloc k Synthesis Control Registe r
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5Unused
4Unused
3RROOLV R
2Unused
1RROOLE R/W 0
0RREFSEL R/W 0
RROOLV
This bit is t he Receive Reference Out Of Lock Status register.
0: The divid ed-down recovered clock is wit hin 2930 ppm of RRCLK, and there is at least one tran sition on RXD during
the last 80 bit- peri ods.
1: The divid ed-down recovered clock is not withi n 2930 ppm of RRCLK, or the re are no transitions on RXD with in t he last
80 bit-periods.
RROOLE
This bit is t he Receive Reference Out Of Lock Interrup t Enable register.
0: INTB, the inter rupt pin, will not be affected by receiver out of lock.
1: INTB, the int errupt pin, wil l go LOW when ther e is a state change of RRO O LV.
RREFSEL
This bi t is the Receiver Reference Select. This bit is ignored in receiver bypass mode (R BYP = 1).
0: RRCLK expects a 19.44-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS−3c/STM−1), the recovered clock
is divided down 8 times before comparing with RRCLK. If RATE0 is LOW (51.84 Mbps, STS−1), the recovered clock is
divided down 3/8 times before comparing with RRCLK.
1: RRCLK expects a 6.480-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS−3c/STM−1), the recovered clock
is divide d down 24 times before comparing with RRCLK. If RATE0 is LOW (51.84 Mbps, STS−1), the recovered c lock is
divided down 8 t imes before compar ing with RRCLK.
CY7C955
PRELIMINARY
26
REG − 10H Receive Section Overhead Processor Control Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6DDS R/W 0
5FOOF W 0
4Unused
3BIPEE R/W 0
2LOSE R/W 0
1LOFE R/W 0
0OOFE R/W 0
DDS
This bi t controls whether SONET descrambling is done on the receive data stream.
0: Descrambling i s performed.
1: Descrambling i s not performed.
FOOF
This bit can be used to manual ly put the Recei ve Section Overhead Processor out of fr am e.
0: No action.
1: The Receive Section Ove rhead Proce ssor will detect an out of fr am e alarm at the next frame boundary.
BIPEE
This bi t controls whether a section BIP−8 error (B1) gener ates an inter rupt.
0: The interrupt pin, INTB, is not affected by section BIP−8 errors .
1: The interrupt pi n, INTB , will go LOW upon receiving a section BIP−8 error.
LOSE
This bi t controls whether a Loss of Signal alarm generates an interrupt.
0: Th e int errupt pin, INTB, is not affected by the loss of signal alarm.
1: The interrupt pi n, INTB , will go LO W upon r eceiving a los s of si gnal alarm.
LOFE
This bi t controls whether a Loss of Frame alar m generates an interrupt.
0: The interrupt pin, INTB, is not af fected by the loss of f rame alarm.
1: The interrupt pi n, INTB , will go LOW upon receiving a loss of frame alarm.
OOFE
This bi t controls whether an Out of Frame alar m generates an i nterrupt.
0: The interrupt pin, INTB, i s not affected by the out of frame alarm.
1: The interrupt pi n, INTB , will go LO W upon r eceiving an out of frame alarm.
CY7C955
PRELIMINARY
27
REG − 11H Receive Section Overhead Processor Status Regi ster
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6BIPEI R
5LOSI R
4LOFI R
3OOFI R
2LOSV R
1LOFV R
0OOFV R
BIPEI
This is the section BIP−8 interrupt bit. This bit reset s when Reg−11H is being read.
0: No secti on BIP−8 error is det ected since Reg−11H was last read.
1: Secti on BIP−8 error is det ected since Reg−11H was last read.
LOSI
This is the Loss of Signal (L OS) int errupt bit. Thi s bit reset s when Reg−11H is being read.
0: No change in the LOS status.
1: There is a change in the LOS status since Reg−11H was last read.
LOFI
This is the Loss of F rame (LOF) interrupt bit . Thi s bit reset s when Reg−11H is being rea d.
0: No change in the LOF status.
1: There is a change in the LOF st atus since Reg−11H was last read.
OOFI
This is the Out of Frame (OO F) i nterrupt bi t. This bit resets when Reg−11H is being read.
0: No change in the OOF status.
1: There is a change in the OOF status sinc e Reg−11H was last re ad.
LOSV
This bi t shows the Loss of Signal (LOS) status of the CY7C955.
0: The Receive Section Overhea d Processor is not in a lo ss of signal state.
1: The Receive Section Overhead Processor is in a loss of signal state.
LOFV
This bi t shows the Loss of Frame (LOF) status of the CY7C955.
0: The Receive Secti on Overhead Processor is not in a Loss of Frame state.
1: The Receive Secti on Overhead Processor is in a Loss of Frame st ate. LOF is declared when OOF has lasted for more
than 3 ms. LOFV sta ys HIGH until t he Receive Secti on Overhead Proc essor is in fram e for more than 3 ms.
OOFV
This bi t shows the Out of Frame (OOF) status of t he CY7C955.
0: The Receive Secti on Overhead Processor is in frame.
1: The Receive Secti on Overhead Processor is in an out of frame state.
CY7C955
PRELIMINARY
28
REG − 12H LSB of the Receive Section Overhead Processor Status BIP−8 counter
BIT POSITION NAME READ/WRITE DEFAULT
7SBE[7] R 0
6SBE[6] R 0
5SBE[5] R 0
4SBE[4] R 0
3SBE[3] R 0
2SBE[2] R 0
1SBE[1] R 0
0SBE[0] R 0
SBE[15:0]
Reg−1 2H an d Re g−13H wi ll load the n umber o f BIP−8 error s from an internal count er approx imately 1 µs afte r a write oper ation
is done to Reg−12H, Reg−13H, or Reg−00H. At that time (1 µs after the write operation) , these two regi sters are updated and
the in terna l B IP−8 err or coun ter is r eset t o zer o t o begin another ro und of er ror a ccum ulati on. Readi ng Reg−1 2H and Reg−13H
after the write yields the number of BIP−8 (B1) errors accumulated since the counter was last wr itten to, if overflow has not
occurred.
REG − 13H MSB of the Receive Sect ion Overhead Processor Status BIP−8 counter
BIT POSITION NAME READ/WRITE DEFAULT
7SBE[15] R 0
6SBE[14] R 0
5SBE[13] R 0
4SBE[12] R 0
3SBE[11] R 0
2SBE[10] R 0
1SBE[9] R 0
0SBE[8] R 0
SBE[15:0]
Reg−1 2H an d Re g−13H wi ll load the n umber o f BIP−8 error s from an internal count er approx imately 1 µs afte r a write oper ation
is done to Reg−12H, Reg−13H, or Reg−00H. At that time (1 µs after the write operation) , these two regi sters are updated and
the in terna l B IP−8 err or coun ter is r eset t o zer o t o begin another ro und of er ror a ccum ulati on. Readi ng Reg−1 2H and Reg−13H
after the write yields the number of BIP−8 (B1) errors accumulated since the counter was last written to if overflow has not
occurred.
CY7C955
PRELIMINARY
29
REG − 14H Transmit Secti on Overhead Processor Control Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6DS R/W 0
5Unused
4Unused
3Unused
2Unused
1Unused
0LAIS R/W 0
DS
This bi t controls whether SONET scram bling is done to the transmit data stream.
0: Scrambl ing is performed.
1: Scrambl ing is not per formed.
LAIS
This bit controls whet her line Ala rm Indica tion Signal (AIS) is being inserted into the transmit data str eam .
1: All bits in the SONET frame (excluding the section overhead) are converted to a 1 prior to SONET scrambling. This
operation begins imm ediately at the next frame boundary.
0: No lin e AIS is transmitted.
REG − 15H Transmit Section Overhead Processor Error Insertion Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5Unused
4Unused
3Unused
2DLOS R/W 0
1DBIP8 R/W 0
0DFP R/W 0
DLOS
This bit generates a continuous loss of signal error in the transmit data st ream.
0: Normal operation.
1: TXD transmits all zeros.
DBIP8
This bit generates a continuous section BIP −8 (B1) error in the transmit data stream.
0: Normal operation.
1: B1 byte is inverted.
DFP
This bit generates a framing byte err or i n the transmit data stream.
0: Normal operation.
1: The most significant bit of the section overhead framing byt e is converted from 1 to 0. In other words, F6H becomes H
in the first A1 byte of the section overhead.
CY7C955
PRELIMINARY
30
REG − 18H Receive LI ne Overhead Processor Control and Status Regist er
BIT POSITION NAME READ/WRITE DEFAULT
7BIPWORD R/W 0
6Unused
5Unused
4Unused
3Unused
2Unused
1LAISV R 0
0RDIV R 0
BIPWORD
This bi t controls how many times a B2 error is r ecorded.
0: The B2 erro r counter increments only once per frame on re ceiving B2 bit -errors.
1: The B2 error counter increments once for every bit error represented in the B2 word. Note that in STS−3c , th ere could
be at most 24 B2 bit-errors per frame, and in STS−1 , there co uld be, at most, 8 B2 bit -errors per fram e.
LAISV
This bit is t he Line Alarm Indi cation Signal (LAIS) status regi ster.
0: No Line AIS detected.
1: Line AIS has been detected. Line AIS is tr iggered by LOS or LOF.
RDIV
This bit is t he Remo te Defect Indi cation statu s regi ster.
0: No remote defect indication (RDI) detected.
1: Remote defect indi cation (RDI) has been detected.
CY7C955
PRELIMINARY
31
REG − 19H Receive Line Overhead Pr ocessor Interrupt Enable and Status Regist er
BIT POSITION NAME READ/WRITE DEFAULT
7FEBEE R/W 0
6BIPEE R/W 0
5LAISE R/W 0
4RDIE R/W 0
3FEBEI R
2BIPEI R
1LAISI R
0RDII R
FEBEE
This bit controls whet her line fa r end block err or generates an interrupt by asserting I NTB LO W.
0: Line far-end block error will not generate an interrupt.
1: Line far-end block error will generate an interrupt.
BIPEE
This bi t contr ols whether BIP−24 (B2) erro r generates an int errup t by asserting INTB LOW.
0: BIP−24 error will not generate an interrupt.
1: BIP−24 error wi ll generate an interrupt.
LAISE
This bit controls whet her line al arm indic ati on signal (LAIS) error generates an int errupt by asserting INTB LOW.
0: LAIS error will not generate an interrupt .
1: LAIS err or will generate an interrupt.
RDIE
This bi t controls whether a remote defect indication alar m detect ion generates an interrupt by asser t ing INTB LOW.
0: A change in t he RDIV state (Reg−18H, bit 0) will not generate an int errupt.
1: A change in t he RDIV state (Reg−18H, bit 0) will generate an inte rrupt.
FEBEI
This is the li ne far-end block err or interrup t bi t. This bit resets when Reg −19H is bei ng read.
0: No line far-end block error has been detected si nce Reg−19H wa s las t rea d.
1: Line far-end block error has been detected since Reg−19H was last read.
BIPEI
This is the section BIP−24 (B2) interrupt bit . This bi t resets when Reg−19H is being read.
0: No lin e BIP−24 (B2) err or has been detect ed since Reg−19H was last read.
1: Line BI P−24 ( B2) error has been detected since Reg−19H was last read.
LAISI
This is the Line Alar m Indication Signal (LAIS) interrupt bit. This bit reset s when Reg−19H is being read.
0: No LAIS has been detected since Reg−19H was last read.
1: LAIS has been detected since Reg−19H was las t read.
RDII
This is the Remo te Defect Indication (RDI) inte rrupt bit . This bit resets when Reg −19H is bei ng read.
0: No line remot e defect indi cation has been detected since Reg−19H was last read.
1: Line remote defect indication has been det ected since Reg−19H was last read.
CY7C955
PRELIMINARY
32
REG − 1AH Line BIP−8/24 Register
BIT POSITION NAME READ/WRITE DEFAULT
7LBE[7] R 0
6LBE[6] R 0
5LBE[5] R 0
4LBE[4] R 0
3LBE[3] R 0
2LBE[2] R 0
1LBE[1] R 0
0LBE[0] R 0
LBE[19:0]
Reg−1AH to Reg−1CH will be loaded with the number of BIP−8/24 (B2) er rors from an i nternal counte r appro xim ately 1 µs after
a write operation i s done to Reg−1AH, Reg−1BH, Reg−1CH, Reg−1DH, Reg−1EH, Reg−1FH, or Reg−00H. At that time (1 µs
after the write operation), these three registers are updated and the internal BIP−8/24 error counter reset to zero to begin
another round of error accumulation. Reading Reg−1AH, Reg−1BH, and Reg−1CH after the write yields the number of BIP−8/24
(B2) errors accumulated since the counter was last reset, if overflow has not occurred.
REG − 1BH Line BIP−8/24 Register
BIT POSITION NAME READ/WRITE DEFAULT
7LBE[15] R 0
6LBE[14] R 0
5LBE[13] R 0
4LBE[12] R 0
3LBE[11] R 0
2LBE[10] R 0
1LBE[9] R 0
0LBE[8] R 0
LBE[19:0]
Reg−1AH to Reg−1CH will be loaded with the number of BIP−8/24 (B2) er rors from an i nternal counte r appro xim ately 1 µs after
a write operation i s done to Reg−1AH, Reg−1BH, Reg−1CH, Reg−1DH, Reg−1EH, Reg−1FH, or Reg−00H. At that time (1 µs
after the write operation), these three registers are updated and the internal BIP−8/24 error counter is reset to zero to begin
another round of error accumulation. Reading Reg−1AH, Reg−1BH, and Reg−1CH after the write yields the number of BIP−8/24
(B2) errors accumulated since the counter was last reset, if overflow has not occurred.
CY7C955
PRELIMINARY
33
REG − 1CH Line BIP−8/24 Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5Unused
4Unused
3LBE[19] R 0
2LBE[18] R 0
1LBE[17] R 0
0LBE[16] R 0
LBE[19:0]
Reg−1AH to Reg−1CH will be loaded with the number of BIP−8/24 (B2) er rors from an i nternal counte r appro xim ately 1 µs after
a write operation i s done to Reg−1AH, Reg−1BH, Reg−1CH, Reg−1DH, Reg−1EH, Reg−1FH, or Reg−00H. At that time (1 µs
after the write operation), these three registers are updated and the internal BIP−8/24 error counter is reset to zero to begin
another round of error accumulation. Reading Reg−1AH, Reg−1BH, and Reg−1CH after the write yields the number of BIP−8/24
(B2) errors accumulated since the counter was last reset, if overflow has not occurred.
REG − 1DH Line Far End Block Error Register
BIT POSITION NAME READ/WRITE DEFAULT
7LFE[7] R 0
6LFE[6] R 0
5LFE[5] R 0
4LFE[4] R 0
3LFE[3] R 0
2LFE[2] R 0
1LFE[1] R 0
0LFE[0] R 0
LFE[19:0]
Reg−1D H, Reg−1EH, and Reg−1FH will be loaded with the num ber of lin e FEBE (Z2) errors from an internal counter approx-
imately 1 µs after a write operati on is done to Reg−1AH, Reg−1BH, Reg−1CH, Reg −1DH, Reg−1EH, Reg−1FH, or Reg−00H.
At that time (1 µs aft er the write operatio n), these three register s are updated and the internal li ne FEBE error counter is r eset
to zero to begin another round of error accumulation. Reading Reg−1DH, Reg −1EH, and Reg−1FH afte r the write yiel ds the
number of l ine FEBE (Z2) errors accumulated since the counter was last res et, if overflow has not occurred.
CY7C955
PRELIMINARY
34
REG − 1EH Line Far End Block Error Register
BIT POSITION NAME READ/WRITE DEFAULT
7LFE[15] R 0
6LFE[14] R 0
5LFE[13] R 0
4LFE[12] R 0
3LFE[11] R 0
2LFE[10] R 0
1LFE[9] R 0
0LFE[8] R 0
LFE[19:0]
Reg−1D H, Reg−1EH, and Reg−1FH will be loaded with the num ber of lin e FEBE (Z2) errors from an internal counter approx-
imately 1 µs after a write operati on is done to Reg−1AH, Reg−1BH, Reg−1CH, Reg −1DH, Reg−1EH, Reg−1FH, or Reg−00H.
At that t ime (1 µs a fter the writ e oper ation ), t hese three r egist ers ar e upd ated and the in ternal l ine FEBE error coun ter are r eset
to zero to begin another round of error accumulation. Reading Reg−1DH, Reg −1EH, and Reg−1FH afte r the write yiel ds the
number of l ine FEBE (Z2) errors accumulated since the counter was last res et, if overflow has not occurred.
REG − 1FH Line Far End Block Error Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused R 0
6Unused R 0
5Unused R 0
4Unused R 0
3LFE[19] R 0
2LFE[18] R 0
1LFE[17] R 0
0LFE[16] R 0
LFE[19:0]
Reg−1D H, Reg−1EH, and Reg−1FH will be loaded with the num ber of lin e FEBE (Z2) errors from an internal counter approx-
imately 1 µs after a write operati on is done to Reg−1AH, Reg−1BH, Reg−1CH, Reg −1DH, Reg−1EH, Reg−1FH, or Reg−00H.
At that t im e (1 µs a ft er th e write opera tion) , the se thr ee r egist ers ar e u pdated and the in ternal li ne F EBE error c ount er ar e reset
to zero to begin another round of error accumulation. Reading Reg−1DH, Reg −1EH, and Reg−1FH afte r the write yiel ds the
number of l ine FEBE (Z2) errors accumulated since the counter was last res et, if overflow has not occurred.
CY7C955
PRELIMINARY
35
REG − 20H Transmit Line Overhead Pr ocessor Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5Unused
4Unused
3Unused
2Unused
1Unused
0RDI R/W 0
RDI
This bit controls whet her line f ar end receive failure (RDI) is being inserted i nto the transmit data stream.
0: Transmi t 000 in bits 6, 7, and 8 of K2.
1: Transmi t 110 in bits 6, 7, and 8 of K2.
REG − 21H Transmit Line Overhead Pr ocessor Error Insertion Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5Unused
4Unused
3Unused
2Unused
1Unused
0DBIP R/W 0
DBIP
This bit generates a continuou s li ne BIP−8/24 (B2) error in the t ransmit data stream .
0: Normal operation.
1: Insert BIP8/24 ( B 2) er ror by invertin g the B2 byte.
CY7C955
PRELIMINARY
36
REG − 30H Receive Path Overhead Processor Interrupt Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5LOP R
4Unused
3PAIS R
2PRDI R
1Unused
0Unused
LOP
This bit is the Loss of Point er (LOP) alarm regi ster .
0: N o lo ss of po int e r ala rm detected.
1: Loss of pointer alarm detected.
PAIS
This bi t is the path Alarm Indication Signal (AIS) register.
0: No path alarm indication signal det ected.
1: Path alarm indication signal detected.
PRDI
This bit is t he path F ar-End Receive Failure (RDI) alarm registe r.
0: No path fa r-end recei ve failure (RDI) alarm detected.
1: Path far-end recei ve fail ure (RDI) alarm detected.
CY7C955
PRELIMINARY
37
REG − 31H Receive Path Overhead Processor Register
BIT POSITION NAME READ/WRITE DEFAULT
7PSLI R
6Unused
5LOPI R
4Unused
3PAISI R
2PRDII R
1BIPEI R
0FEBEI R
PSLI
This is the Path Signal Lab el (PSL) register interrupt bit . Thi s bit reset s when Reg−31H is being rea d.
0: No change in the path signal label since Reg−31H was last read.
1: There is a change in the path signal label since Reg−31H was last read.
LOPI
This is the Loss of P ointer (LOP) i nterrupt bit. This bit resets when Reg−31H is being read.
0: No change in the loss of poi nter state since Reg−31H was last read.
1: Th ere i s a change in the loss of pointer state since Reg−31H was last read.
PAISI
This is the path Alar m Indication Signal (AIS) interrupt bit. This bi t resets when Reg−31H is being read.
0: No change in the path alarm indication signal since Reg−31H was last read.
1: There is a change in the path alarm indication signal since Reg−31H was last rea d.
PRDII
This is the path F ar-End Receive Failure (RDI) al arm inte rrupt bit . This bit resets when Reg−31H is bei ng read.
0: No change in the path far-end receive failure alarm since Reg−31H was last read.
1: There is a change in the path far-end receive f ailure alarm since Reg−31H was last read.
BIPEI
This is the BIP−8 (B3) error interrupt bit. This bit resets when Reg −31H is being read.
0: No BIP−8 (B3) error detected since Reg−31H was las t read.
1: BIP−8 (B3) error h as been detected since Reg−31H was last read.
FEBEI
This is the path Far-End Block Error (FEBE) interrupt bit. This bit res ets when Reg−31H i s being read.
0: No path far-end block error detected since Reg−31H was last read.
1: Path f ar-end block error has been detected si nce Reg−31H was las t rea d.
CY7C955
PRELIMINARY
38
REG − 33H Receive Path Overhead Processor Interrupt Enable Regist er
BIT POSITION NAME READ/WRITE DEFAULT
7PSLE R/W 0
6Unused
5LOPE R/W 0
4Unused
3PAISE R/W 0
2PRDIE R/W 0
1BIPEE R/W 0
0FEBEE R/W 0
PSLE
This bi t controls whether a change in the Pat h Signal Label (PSL) generates an interrupt by asserting INTB LOW.
0: A change in the path signal label (PSL) wil l not generate an inter rupt .
1: An interrupt wi ll be generated if mor e than tw o consecutive non-13H C3 bytes are being det ected in the pat h over head.
LOPE
This bi t controls whether a loss of point er generates an inter rupt by asserting I NTB LOW.
0: A change in the loss of poi nter state will not generate an inter rupt .
1: A change in the loss of poi nter state will gen erate an interrupt.
PAISE
This bi t controls whether Pa th Alarm Indication Signal (PAIS) error generates an interrupt by asserting INTB LOW.
0: PAIS error will not generate an interrupt .
1: PA I S err o r w ill g e nera t e a n inte rr up t .
PRDIE
This bi t controls whether a path Remote Defect Indi cation (RDI) generates an interrupt by asserting INTB LOW.
0: A change in the path remote def ect indicat ion state wi ll not generate an int errup t.
1: A change in the path remote def ect indicat ion state wi ll generate an inter rupt.
BIPEE
This bi t contr ols whether BIP−8 (B3) error gener ates an interrupt by asserting INTB LOW.
0: BIP−8 (B3) error wil l not generate an inter rupt .
1: BIP−8 (B3) error wil l generate an interrupt.
FEBEE
This bit controls whet her line fa r end block err or generates an interrupt by asserting I NTB LO W.
0: Line far-end block error will not generate an interrupt.
1: Line far-end block error will generate an interrupt.
CY7C955
PRELIMINARY
39
REG − 37H Receive Path Signal Label Register
BIT POSITION NAME READ/WRITE DEFAULT
7PSL[7] R
6PSL[6] R
5PSL[5] R
4PSL[4] R
3PSL[3] R
2PSL[2] R
1PSL[1] R
0PSL[0] R
PSL[7:0]
This is the path signal label ( C2) register byte. This regist er is either 13H or the first non-13H value detected in the received
SONET data stream.
REG − 38H Pa t h B IP−8 (B3) Register
BIT POSITION NAME READ/WRITE DEFAULT
7PBE[7] R 0
6PBE[6] R 0
5PBE[5] R 0
4PBE[4] R 0
3PBE[3] R 0
2PBE[2] R 0
1PBE[1] R 0
0PBE[0] R 0
PBE[15:0]
Reg−38H and Reg−3 9H will be loaded with the number of path BIP−8 (B3) errors from an inter nal counter approximately 1 µs
after a write operation is done to Reg−38H, Reg−39H, Reg−3AH, Reg−3BH, or Reg−00H. At that time (1 µs a fter the wr ite
operation), these three regi sters are updated and the internal BIP−8 (B3) error counter is rese t to ze ro t o begin another round
of error accumulation. Reading Reg−38H and Reg−39H after the write yields the number of BIP−8 (B3) errors accumulated
since the counter was last reset, if overflow has not occurred.
CY7C955
PRELIMINARY
40
REG − 39H Pa t h B IP−8 (B3) Register
BIT POSITION NAME READ/WRITE DEFAULT
7PBE[15] R 0
6PBE[14] R 0
5PBE[13] R 0
4PBE[12] R 0
3PBE[11] R 0
2PBE[10] R 0
1PBE[9] R 0
0PBE[8] R 0
PBE[15:0]
Reg−38H and Reg−3 9H will be loaded with the number of path BIP−8 (B3) errors from an inter nal counter approximately 1 µs
after a write operation is done to Reg−38H, Reg−39H, Reg−3AH, Reg−3BH, or Reg−00H. At that time (1 µs a fter the wr ite
operation), these three regi sters are updated and the internal BIP−8 (B3) error counter is rese t to ze ro t o begin another round
of error accumulation. Reading Reg−38H and Reg−39H after the write yields the number of BIP−8 (B3) errors accumulated
since the counter was last reset, if overflow has not occurred.
REG − 3AH Path Far-End Bl ock Error Register
BIT POSITION NAME READ/WRITE DEFAULT
7PFE[7] R 0
6PFE[6] R 0
5PFE[5] R 0
4PFE[4] R 0
3PFE[3] R 0
2PFE[2] R 0
1PFE[1] R 0
0PFE[0] R 0
PFE[15:0]
Reg−3 AH and Reg−3BH will be loaded with the number of path FEBE (G1) errors f rom an internal counter approximatel y 1 µs
after a write operation is done to Reg−38H, Reg−39H, Reg−3AH, Reg−3BH, or Reg−00H. At that time (1 µs a fter the wr ite
operation), these three registers are updated and the int ernal path FEBE error counter is re set to zero to begin anot her round
of error accumulation. Reading Reg−3AH a nd Reg −3BH after the write yields the number of path FEBE (G1) errors accumulated
since the counter was last reset, if overflow has not occurred.
CY7C955
PRELIMINARY
41
REG − 3BH Pat h Fa r E n d Blo ck E rro r R e g is ter
BIT POSITION NAME READ/WRITE DEFAULT
7PFE[15] R 0
6PFE[14] R 0
5PFE[13] R 0
4PFE[12] R 0
3PFE[11] R 0
2PFE[10] R 0
1PFE[9] R 0
0PFE[8] R 0
PFE[15:0]
Reg−3 AH and Reg−3BH will be loaded with the number of path FEBE (G1) errors f rom an internal counter approximatel y 1 µs
after a write operation is done to Reg−38H, Reg−39H, Reg−3AH, Reg−3BH, or Reg−00H. At that time (1 µs a fter the wr ite
operati on), these t hree regist ers are update and the i nternal path FEBE error count er is reset to zero to begin another round
of error accumulation. Reading Reg−3AH a nd Reg−3BH after the write yields the number of path FEBE (G1) errors accumulated
since the counter was last reset, if overflow has not occurred.
REG − 3DH Path Far-End Bl ock Error Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5BLKBIP R/W 0
4Unused
3Unused
2Unused
1Unused
0Unused
BLKBIP
This bi t contr ols how path BIP−8 (B 3) er rors are accum ulated.
0: BIP−8 (B3) error s are accumul ated and reported in a bit basis.
1: BIP−8 ( B3) erro rs are acc umul ated and re ported in a bloc k bas is. Only one BIP−8 err or is r eported to the ups tream pat h
even if mo re th an one path BIP−8 (B3) er rors are detected.
CY7C955
PRELIMINARY
42
REG − 40H Transmit Path Overhead Pr ocessor Error Insertion Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5Unused
4Unused
3Unused
2Unused
1DB3 R/W 0
0PAIS R/W 0
DB3
This bi t generates a path BIP−8 erro r in the transmit data stream.
0: Normal operation.
1: The path BIP−8 (B3) byte is in verted, ei ght BIP−8 (B3) errors are thus generated per fr ame PAIS.
PAIS
This bi t generates a path Alar m Indication Signal (AIS) in the transmit data stream.
0: Normal operation.
1: The whole synchronous payload envelope (SPE) together with the H1, H2, and H3 bytes are converted to 1 before
scrambling.
CY7C955
PRELIMINARY
43
REG − 41H Transmit Path Overhead Pr ocessor Poi n ter Control Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6FTPTR R/W 0
5SOS R/W 0
4PLD R/W 0
3NDF R/W 0
2NSE R/W 0
1PSE R/W 0
0Unused
FTPTR
This bi t enab les the ins ertion of the arbitrary payload p ointer value i nto the last 10 bits of H1, H2. The NDF flag is not automat-
ically changed by this opera ti on.
0: Normal operation.
1: The bits contained in Arbitrary Pointer Register (APTR[ 9:0]) are inserted into H1 an d H2 of the transmitt ed data stream.
This bi t is provi ded for creating pointer byte errors to diagnose the down stream sys tem.
SOS
This is the stuff opportunity spacing bit which cont rols how oft en stuff events can occur.
0: Stuff event can occur in every other fr am e. Insertion o f positiv e pointer movement or negative pointer movement can be
done thr ough writing to NSE and PSE (bit 2 and 1 of Reg−41H)
1: Stuff event can occur only once in every four frames. Insertion of positive pointer movement or negative pointer movement
can be done through wr iting to NSE and PSE ( bit 2 and 1 of Reg−41H)
PLD
This bit ena bles the i nsertion of th e arbitrary pa yload point er v alue into the l ast 10 bi ts of H1 and H2 bytes. The value i n NDF[3:0]
(Reg−46H, bit 7 − bit 4) will also be loaded into the new data fl ag (NDF) position of the H1 byte. PLD should be used i nstead
of FTPTR for non-di agnostic payload pointer adjustme nts.
0: Normal operation.
1: The bit s contained in Arbitr ary Pointer Registe r (APTR[ 9:0]) are inserted i nto H1 and H2 of the transmit data stre am .
This operation will not affect the interpretat ion of the pointer in the r eceived data stream, and will only be performed if
the value store d in APTR[9 :0] is >0 and < 782.
NDF
This is the new data flag (NDF) insertion control bit. This bit is i gnored if PLD is set to 1.
0: The nor mal NDF pattern (0110) is being transmitted in the first four bytes of H1.
1: The value stored in NDF[3:0] (Reg−46H, bit 7−bit 4) are insert ed into the first four bytes of H1.
NSE
This bit can be used to generate a negative pointer movement. This bit has to be f irst enabled by setting FIXPTR (Reg−05H,
bit 5) to 1. Thi s bit resets to zero automatica ll y after every write to it.
0: Default st ate.
1: A singl e negative pointer adj ustment will be made on the outgoing data stream. This bit will be cleared to zero
immediately
PSE
This bi t can be used to g enerate a positiv e pointer movement . This bit has to be fi rst enabled by setti ng FIXPTR (Reg −05H, bit
5) to 1. This bit resets to zero automatical ly after every write to it.
0: Default st ate.
1: A si ngle posit ive p ointer a djustmen t will be made on the outgo ing dat a stream. This bit wil l be c leared t o zero i mmediately.
CY7C955
PRELIMINARY
44
REG − 45H Transmit Path Overhead Pr ocessor Arbitrary Paylo ad Pointe r Register
BIT POSITION NAME READ/WRITE DEFAULT
7APTR[7] R/W 0
6APTR[6] R/W 0
5APTR[5] R/W 0
4APTR[4] R/W 0
3APTR[3] R/W 0
2APTR[2] R/W 0
1APTR[1] R/W 0
0APTR[0] R/W 0
APTR[9:0]
Reg−4 5H an d Re g−46H are the ar bitrary payl oad pointer regist ers. This two regi sters ar e used to stor e the new pa yload pointer
value to be loaded into H1and H2 of the transmitted data stream. The value loaded into these 10 bits has to be greater than or
equal to zero and sm aller than 782. A legal value stored in APTR[9:0] is not loaded into the data st ream until PLD or FTPTR
is toggled HIGH.
REG − 46H Transmit Path Overhead Pr ocessor Arbitrary Paylo ad Pointe r Register
BIT POSITION NAME READ/WRITE DEFAULT
7NDF[3] R/W 1
6NDF[2] R/W 0
5NDF[1] R/W 0
4NDF[0] R/W 1
3S[1] R/W 0
2S[2] R/W 0
1APTR[9] R/W 0
0APTR[8] R/W 0
NDF[3:0]
These bit s are used to sto re the arbit rary new dat a flag to be loaded i nto the tr ansm it data str eam. Thes e bit s are loade d when
NDF is toggled HIGH or when PLD is toggl ed HIGH.
S[1:0]
These 2 bits are in serted into the 2 unused bit s of H1 whenever PLD, NDF, or FTPTR are toggled HIGH.
APTR[9:0]
Reg−4 5H an d Re g−46H are the ar bitrary payl oad pointer regist ers. This two regi sters ar e used to stor e the new pa yload pointer
value t o be loaded into H1 and H2 of the transmitted data stream. The value loaded into these 10 bits has to be greater than
or equal t o zer o and smal ler than 782. A legal v alue st ored in APTR[ 9:0] is not loaded int o the data stre am unti l PLD or FTPTR
is toggled HIGH.
CY7C955
PRELIMINARY
45
REG − 48H Transmit P ath Overhead Processor Signal Label Regis ter
BIT POSITION NAME READ/WRITE DEFAULT
7C2[7] R/W 0
6C2[6] R/W 0
5C2[5] R/W 0
4C2[4] R/W 1
3C2[3] R/W 0
2C2[2] R/W 0
1C2[1] R/W 1
0C2[0] R/W 1
C2[7:0]
These bits are inserted in the C2 byte posit ion in the tr ansmit stream.
REG − 49H Transmit Path Overhead Processor Path Status Regist er
BIT POSITION NAME READ/WRITE DEFAULT
7FEBE[3] R/W 0
6FEBE[2] R/W 0
5FEBE[1] R/W 0
4FEBE[0] R/W 0
3PRDI R/W 0
2G1[2] R/W 0
1G1[1] R/W 0
0G1[0] R/W 0
FEBE[3:0]
These bit s ar e used to hold the FEBE value to be inser ted into the transmitt ed data stream. After inser tion of these bits into
the FEBE l ocation of t he next possible frame, FEBE[3:0] wil l be reset. If the value wri tt en to these register b it s can still be rea d
back, it just me an that the insertion has not taken place yet.
PRDI
Th is bi t is us ed to i nse rt re mo te de fec t ind ic a tio n (R DI) in to the tra n s m itt e d d a ta str e am .
0: Normal operation. With the PRDI bit of G1 only affected by the setting of AUTOPRDI (Reg−01H, Bit 4) and the alarm
conditions.
1: The PR D I bi t of G1 is se t to 1.
G1[2:0]
These bits are inserted into t he unused bit posit ions of G1 of every frame.
CY7C955
PRELIMINARY
46
REG − 50H Receive ATM Cell Processor Control and Status Regi ster
BIT POSITION NAME READ/WRITE DEFAULT
7OOCDV R
6RXPTYP R/W 0
5PASS R/W 0
4DISCOR R/W 0
3HCSPASS R/W 0
2HCSADD R/W 1
1DDSCR R/W 0
0FIFORST R/W 0
OOCDV
This bi t is the cell delineation st atus register.
0: This indicates that the cell delineation state machine is in the ‘SYNC’ state and ATM cells are passing though to the
receiv e FIFO.
1: This i ndicates that t he cell deli neation stat e m achine is in t he ‘PRESYNC’ or ‘HUNT’ state.
RXPTYP
This bi t controls whether odd or even par ity is used for RXPRTY.
0: Odd parit y is generated f or RDAT[7:0] .
1: Even parity is generated for RDAT[7:0].
PASS
This bit controls whether cells wi th VPI = 0 and VCI = 0 are dropped .
0: All cell s with VPI = 0, VCI = 0 and header matchi ng all the unmasked bits of Reg−52 H are dropped.
1: No cell filtering is performed.
DISCOR
This bi t controls whether header error (HCS) correction is perfor m ed.
0: Header error correcti on is performed. Single bit-errors detected in the header are corrected automatically.
1: Header error correcti on is not performed. Any HCS error detec ted is considered uncorrectable .
HCSPASS
This bit controls whether cells wi th HCS error are dropped.
0: All cell s with an uncorrectable HCS error are dropped.
1: No cell s are droppe d if the cel l delineat ion state machine is in SYNC state.
HCSADD
This bit controls whet her the coset polynomial x6+x4+x2+1 is added to t he HCS b yte before HCS comparison is performed.
0: No coset polyn om ial is added.
1: The coset polynomial x6+x4+x2+1 is added to the HCS byte.
DDSCR
This bi t controls whether cell payload descrambling is performed.
0: Cell payload des crambling is performed.
1: Cell payload des crambling is not performed.
FIFORST
This bit is t he receive FIFO reset bi t.
0: Normal receive FIFO operati on.
1: All receiv e FIFO loca ti ons are reset and t he receive FIFO will ignore all writes .
CY7C955
PRELIMINARY
47
REG − 51H Receive ATM Cell Processor I nterrupt Register
BIT POSITION NAME READ/WRITE DEFAULT
7OOCDE R/W 0
6HCSE R/W 0
5FIFOE R/W 0
4OOCDI R
3CHCSI R
2UHCSI R
1FOVRI R
0Unused
OOCDE
This bit controls whet her a change i n cell delineation stat e generates an inte rrupt by asserting INTB LOW.
0: A change in the cell del ineation sta te wi ll not generate an interrupt.
1: A change in the cell del ineation sta te wi ll generate an interrupt.
HCSE
This bi t controls whether an HCS error generates an interrupt by asserting INTB LOW.
0: HCS error s will not generate an interrupt .
1: A correctabl e or uncorrect able HCS error wi ll both generate an interrupt.
FIFOE
This bi t controls whether receive FIFO overfl ow wi ll generate an interr upt by asserting INTB LOW.
0: Receive FIFO overflow will not generate an inter rupt.
1: Receive FIFO overflow will generate an interrupt.
OOCDI
This is the change of cell del ineation interrupt bit. Thi s bit resets as Reg−51H is being read.
0: Th ere i s no change in the loss of cell delineation sta te.
1: There i s a change from the PRESYNC state to SYNC state or from the SYNC state to the HUNT state.
CHCSI
This is the corr ectable HCS erro r detection bit. This bit reset s as Reg−51H is being rea d.
0: No correctable HCS error has been detected since Reg−51H was last read.
1: One or more than one correctable HCS errors have been detect ed si nce Reg−51 H w as last read.
UHCSI
This is the uncorrectable HCS error detection bit. This bit resets as Reg−51H is being r ead.
0: No uncorrectable HCS error has been det ected since Reg−51H was last read.
1: One or more than one uncorrectable HCS errors have been detected since Reg−51H was last read.
FOVRI
This is the receive FIFO overflow interrupt bit . This bit resets as Reg−5 1H is being read.
0: No receive FIFO overflow has occur red since Reg−51H was last read.
1: Receive FIFO overflow has occurred since Reg−51H was last re ad.
CY7C955
PRELIMINARY
48
REG − 52H Receive ATM Cell Pr ocessor Matc h Header Pattern Register
BIT POSITION NAME READ/WRITE DEFAULT
7GFC[3] R/W 0
6GFC[2] R/W 0
5GFC[1] R/W 0
4GFC[0] R/W 0
3PTI[2] R/W 0
2PTI[1] R/W 0
1PTI[0] R/W 0
0CLP R/W 0
GFC[3:0]
These are the Generic Flow Control (GFC) regi ster bits. If the PASS bit (Reg−50H, bit 5) is LOW, ATM cells with VPI = 0, VCI
= 0, and with other parts of their header matching all the unmask e d bit s of th is regi ster will be droppe d. Each bit of this reg ister
can be mask ed by its correspond ing bit in Reg−53H. Masked bits are not com pared.
PTI[2:0]
These are the Payl oad Ty pe Indicator (PTI) register bits. If the PASS bit (Reg−50H, bit 5) is LOW, ATM cells with VPI = 0, VCI
= 0, and with other parts of their header matching all the unmask e d bit s of th is regi ster will be droppe d. Each bit of this reg ister
can be mask ed by its correspond ing bit in Reg−53H. Masked bits are not com pared.
CLP
This is the Cell Loss Priority (CLP) register bit . If the PASS bit (Reg−50H, bit 5) is LOW, ATM cells with VPI = 0, VCI = 0,and
with othe r parts of their header matching all the unmasked bits of this register wil l be dropped. Each bit of this reg ist er can be
masked bits correspondi ng bi t in Reg−53H. Masked bits ar e not compared.
CY7C955
PRELIMINARY
49
REG − 53H Receive ATM Cell Pr ocessor Matc h Header M ask Register
BIT POSITION NAME READ/WRITE DEFAULT
7MGFC[3] R/W 0
6MGFC[2] R/W 0
5MGFC[1] R/W 0
4MGFC[0] R/W 0
3MPTI[2] R/W 0
2MPTI[1] R/W 0
1MPTI[0] R/W 0
0MCLP R/W 0
MGFC[3:0]
This is the mask for the Generic Flow Control register. A HIGH in any bit of this register unmasks the corresponding bit of
Reg−5 2H and al lows it t o be compared with t he curr ent ATM cell. I f PASS (Reg−50H, bit 5) is LOW, ATM cells with VPI = 0, VCI
= 0, and other parts of their header matching all th e unma sked bits of Reg−52H are dropped.
MPTI[2:0]
This is the mask for the Payload Type Indicator regi ster. A HIGH in any bit of this regi st er unmasks the corresponding bit of
Reg−52H and allows it to be compared with the current ATM cell. If PASS (Reg−50H, bi t 5) is LOW, ATM cells with VPI = 0,
VCI = 0, and ot her parts of their header matchi ng all the unmasked bits of Reg−52H are dropped.
MCLP
This is the m ask for the Cell Loss Pr iority (CLP) regist er. A HI GH in any bit of this register unmasks the corresponding bit of
Reg−5 2H and al lows i t to be compar ed with t he curre nt ATM cell. If PASS (Reg−50H, bit 5) is LO W, ATM cells wit h VPI = 0, VCI
= 0, and other parts of their header matching all th e unma sked bits of Reg−52H are dropped.
REG − 54H Receive ATM Cell Processor Correcta ble HCS Error Count Register
BIT POSITION NAME READ/WRITE DEFAULT
7CHCS[7] R
6CHCS[6] R
5CHCS[5] R
4CHCS[4] R
3CHCS[3] R
2CHCS[2] R
1CHCS[1] R
0CHCS[0] R
CHCS[7:0]
Reg−54H and Reg−55 H will load the number of correctable HCS errors fr om an internal counter approximately 200 ns after a
write operation is done to Reg−54H, Reg−55H, or Reg−00H. At that time (200 ns after the write operation), this register is
updated and the internal correctable HCS err or counter is reset to zero to begin another round of error accumulation. Reading
Reg−54H and Reg–55H after the write yields the number of corr ect able HCS errors accumulated since the counter was last
reset, if overflow has not occurred.
CY7C955
PRELIMINARY
50
REG − 55H Receive ATM Cell Pr ocessor Uncorr ectable HCS Error Count Register
BIT POSITION NAME READ/WRITE DEFAULT
7UHCS[7] R
6UHCS[6] R
5UHCS[5] R
4UHCS[4] R
3UHCS[3] R
2UHCS[2] R
1UHCS[1] R
0UHCS[0] R
UHCS[7:0]
Reg−54H and Reg−55H will load the number of uncorrectable HCS errors fr om an internal c ounter approximately 200 ns after
a write operation is done to Reg−54H, Reg−55H, or Reg−00H. At that t ime (200 ns after the write operation), this register is
updated and the inte rnal uncor rect able HCS er ror count er is r eset to zero t o begin another round of error accumulation. Reading
Reg−5 4H and Reg. –55H aft er the write yiel ds the n umber of u ncorrec tabl e HCS erro rs accum ula ted sin ce the cou nte r was l ast
reset, if overflow has not occurred.
REG − 56H Receive ATM Cell Processor Receive Cell Counter Register
BIT POSITION NAME READ/WRITE DEFAULT
7RCELL[7] R
6RCELL[6] R
5RCELL[5] R
4RCELL[4] R
3RCELL[3] R
2RCELL[2] R
1RCELL[1] R
0RCELL[0] R
RCELL[18:0]
Reg−56H, Reg−57H, and Reg−58H will load the number of cells received from an internal counter approximately 200ns after
a write operation is done to Reg−54H, Reg−55H, Reg−56H, Reg−57H, Reg−58H , or R eg −00H. At that ti me (200ns after the
write operati on) , this register is updated and the inter nal receive cell counter i s reset to zero to begin another round of accu-
mulati on. Read ing Reg −5 6H, Reg−57 H, and Reg−58H af ter the wri te yi elds t he n umber of c ells r eceived since the counter wa s
last re set, if overflow has not occu rred.
CY7C955
PRELIMINARY
51
REG − 57H Receive ATM Cell Processor Receive Cell Counter Register
BIT POSITION NAME READ/WRITE DEFAULT
7RCELL[15] R
6RCELL[14] R
5RCELL[13] R
4RCELL[12] R
3RCELL[11] R
2RCELL[10] R
1RCELL[9] R
0RCELL[8] R
RCELL[18:0]
Reg−56H, Reg−57H, and Reg−58H wil l load the number of cell s received fr om an int ernal counter approximately 200 ns after
a write operation is done to Reg−54H, Reg−55H, Reg −56H, Reg−57H, Reg−58H, or Reg−00H. At that time (200 ns after t he
write operati on) , this register is updated and the inter nal receive cell counter i s reset to zero to begin another round of accu-
mulati on. Read ing Reg −5 6H, Reg−57 H, and Reg−58H af ter the wri te yi elds t he n umber of c ells r eceived since the counter wa s
last re set, if overflow has not occu rred.
REG − 58H Receive ATM Cell Processor Receive Cell Counter Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5Unused
4Unused
3Unused
2RCELL[18] R
1RCELL[17] R
0RCELL[16] R
RCELL[18:0]
Reg−56H, Reg−57H, and Reg−58H wil l load the number of cell s received fr om an int ernal counter approximately 200 ns after
a write operation is done to Reg−54H, Reg−55H, Reg −56H, Reg−57H, Reg−58H, or Reg−00H. At that time (200 ns after t he
write operati on) , this register is updated and the inter nal receive cell counter i s reset to zero to begin another round of accu-
mulati on. Read ing Reg −5 6H, Reg−57 H, and Reg−58H af ter the wri te yi elds t he n umber of c ells r eceived since the counter wa s
last re set, if overflow has not occu rred.
CY7C955
PRELIMINARY
52
REG − 59H Receive ATM Cell Pr ocessor Receive Configur ati on Register
BIT POSITION NAME READ/WRITE DEFAULT
7RGFCE[3] R/W 1
6RGFCE[2] R/W 1
5RGFCE[1] R/W 1
4RGFCE[0] R/W 1
3FSEN R/W 1
2RCALEVEL0 R/W 1
1HCSFTR[1] R/W 0
0HCSFTR[0] R/W 0
RGFCE[3:0]
This is the Receive Generic Flow Control Enable register. Each bit is logical ANDed with its corr esponding bit i n the ATM cell
header. RGFCE[3] corresponds t o the most significant bit of the GFC header. If RGFC[x] is set LOW, then bit x of the serial
RGFC output (pin 59) will appe ar LOW.
FSEN
This is the fix stuf f expectation bit. Thi s command only affects STS−1 frames.
0: No fix stuff bytes are expected in the STS−1 payload.
1: Fix stuff byt es are expected in Column 30 and 59 of the rec eived STS−1 frame.
RCALEVEL0
This is the receive cell available (RCA) pin empty definition control register.
0: RCA is an active LOW indication for the receive FIFO being 4 bytes from empty.
1: RCA is an active LOW indication for the receive FIFO being empty.
HCSFTR[1:0]
This i s the HCS c ell a ccep tance t hreshol d regi ster. The se bi ts co ntrol ho w man y consecu tiv e error- free cells are nee ded f or th e
Receive ATM cell processor to convert from detection mode to correction mode.
11: 7 cell s wit h no HCS erro r is needed befor e the 8t h cell is accepted. Correction mode is enter ed immediately after that.
10: 3 cell s wit h no HCS erro r is needed befor e the 4t h cell is accepted. Correction mode is enter ed immediately after that.
01: 1 cell wit h no HCS error is needed before the 2nd cell is accepted. Cor rection mode is entered i mmediatel y after that .
00: All cell with no HCS error is accepted. Correction mode is entered immediately after that.
CY7C955
PRELIMINARY
53
REG − 60H Transmit ATM Cell Processor Control and Status Register
BIT POSITION NAME READ/WRITE DEFAULT
7FIFOE R/W 0
6TSOCI R
5FOVRI R
4DHCS R/W 0
3Unused
2HCSADD R/W 1
1DDSCR R/W 0
0FIFORST R/W 0
FIFOE
This bi t controls whether transmit FIFO overflow or misplaced transmit start of cell (TSOC) will generate an inter rupt.
0: Transmi t FIFO ov erflow and misplaced TSOC wil l not generate an interrupt.
1: Transmit FIFO overflow or misplaced TSOC (TSOC appearing not with the first byte of an ATM cell) will generate an
interrupt.
TSOCI
This is the trans mit start of cell interru pt bi t. This bit resets as Reg−60H is bei ng read.
0: No TSOC error has occurred since Reg−60H w as last read.
1: TSOC has occurred at times other than at the beginning o f an ATM cell. The internal 53-byte cell lengt h counter is reset
to zero immediately if such an error occurs and the incomplete ATM cell is discarded.
FOVRI
This is the tr ansmit FIFO overfl ow interrupt bit . This bit resets as Reg−6 0H is being read.
0: No transmit FIFO overflow has occurred since Reg−60H was last read.
1: Transmit FIFO overflow has occurred since Reg−60H was last read.
HCSADD
This bit controls whether the coset polynomial x6+x4+x2+1 is added to t he HC S byte before the ATM cell is inser ted into t he
Synchronous Pay load Envelope (before SONET scrambling if enab led).
0: No coset polyn om ial is added.
1: The coset polynomial x6+x4+x2+1 is added to the HCS byte. This is equivalent to substi tuting the HCS byte with (HCS
byte XOR 01010101 ).
DDSCR
This bi t controls whether cell payload scrambling is performed.
0: Cell payload scrambling is performed.
1: Cell payload scrambling is not performed.
FIFORST
This bit is t he tr ansmit FIFO reset bit.
0: Normal transmit FIFO operation.
1: All transmit FIFO loca ti ons are reset and t he tr ansmit FIFO will ignor e all writes.
CY7C955
PRELIMINARY
54
REG − 61H Transmit ATM Cell Processor Unassigned Cell Header Register
BIT POSITION NAME READ/WRITE DEFAULT
7GFC[3] R/W 0
6GFC[2] R/W 0
5GFC[1] R/W 0
4GFC[0] R/W 0
3PTI[2] R/W 0
2PTI[1] R/W 0
1PTI[0] R/W 0
0CLP R/W 0
GFC[3:0]
These are the transmit Generic Flow C ontrol (GFC) register bi ts. The bits in this register are appended to VPI = 0, and VCI =
0 before adding to the transmit data stream as idle cells. Idle cel ls are transmitted whenever there are no complete ATM cells
in the transmit FIFO.
PTI[2:0]
These are the transmit Payload Type Indicator (PTI) register bi ts. The bits in this r egister are appended to VPI = 0, and VCI =
0 before adding to the transmit data stream as idle cells. Idle cel ls are transmitted whenever there are no complete ATM cells
in the transmit FIFO.
CLP
This is the transmit Cel l Loss Priority (CLP) register bit. The bi ts in this regi ster are appended to VPI = 0, and VCI = 0 before
adding to the transmit data stream as idle cells. Idle cells are transm itted whenever there are no complete ATM cells in the
transmit FIFO.
REG − 62H Transmit ATM Cell Processor Unassigned Cell Payload Register
BIT POSITION NAME READ/WRITE DEFAULT
7ICP[7] R/W 0
6ICP[6] R/W 1
5ICP[5] R/W 1
4ICP[4] R/W 0
3ICP[3] R/W 1
2ICP[2] R/W 0
1ICP[1] R/W 1
0ICP[0] R/W 0
ICP[7:0]
This r egister contai ns the oct et to be p laced in each b yte of t he transmi tted id le cel ls. When there are no user ATM cell s av ailable
for tra nsmi ssion, the Trans mit ATM Cell Proc esso r gener ates i ts ow n idl e cell s based on s etti ng in Reg −6 1H and 62 H. Idle cel ls
allo w CY7C 955 to per form cell rate decoupling.
CY7C955
PRELIMINARY
55
REG − 63H Transmit ATM Cell Processor FIFO Control Regist er
BIT POSITION NAME READ/WRITE DEFAULT
7TXPTYP R/W 0
6TXPRTYE R/W 0
5Unused
4TXPRTYI R
3FIFODP[1] R/W 0
2FIFODP[0] R/W 0
1TCALEVEL0 R/W 0
0Unused 0
TXPTYP
This is the polarity control bit for the interpretat ion of TXPR TY.
0: TXPRTY is t he odd parity input for TDAT[7:0].
1: TXPR TY is the even parity input for TDAT[7:0].
TXPRTYE
This is the trans mit parity error interrupt enable regis ter.
0: Transmi t pari ty error will not pull INTB (p in 108) LOW but will st il l be indicated on TXPRTYI.
1: Transmi t parity error will pull I N TB (pi n 108) LOW as wel l as set ting TXPRTYI.
TXPRTYI
This is the tr ansmit parity error int errupt register. This bit resets when Reg−63H is being read.
0: No transmit parity erro r has been detected since Reg−63H was last read.
1: Transmit parit y error has been detected since Reg−63H was last read.
FIFODP[1:0]
This bi t control s the transmit cell avai lable (TCA) pin definition. Note that this register only determines when TCA (pin 86) is to
be deasserted. The transmit FIFO is alwa ys 4 cells deep regardless of the setting of this register. This means that i nterrupt for
FIFO overflow, if enabled by FIFOE (Reg−60H, bit 7), wil l only occur if a write is attempted on a FIFO that is already filled up
with all 4 cells .
11: TCA will go LOW when t ransmit FIFO is 1 cell fu ll (if TCALEVEL = 1) or 4 bytes awa y from 1 cell full (if TCALEVEL = 0).
10: TCA will go LO W when tr ansmit FIFO is 2 cells full (if TCALEVEL = 1) or 4 b ytes awa y from 2 cells f ull (if TCALEVEL = 0).
01: TCA will go LO W when tr ansmit FIFO is 3 cells full (if TCALEVEL = 1) or 4 b ytes awa y from 3 cells f ull (if TCALEVEL = 0).
00: TCA will go LO W when tr ansmit FIFO is 4 cells full (if TCALEVEL = 1) or 4 b ytes awa y from 4 cells f ull (if TCALEVEL = 0).
TCALEVEL0
This is the transmit cell available (TCA) pin transition definition control register.
0: TCA will go LOW when tra nsm it FIFO is N cells fu ll. N is determin ed by v alue in FIFODP[1:0] (Reg−63H, bit 2 −3).
1: TCA will stay LOW when transmit FIFO is within 4 bytes from N cells full. N is determined by value in FIFODP[1:0]
(Reg−63H, bit 2 −3).
CY7C955
PRELIMINARY
56
REG − 64H Transmit ATM Cell Processor Transmit Cell Coun ter Register
BIT POSITION NAME READ/WRITE DEFAULT
7TCELL[7] R 0
6TCELL[6] R 0
5TCELL[5] R 0
4TCELL[4] R 0
3TCELL[3] R 0
2TCELL[2] R 0
1TCELL[1] R 0
0TCELL[0] R 0
TCELL[18:0]
Reg−64H, Reg−65H , and Reg−66H will load the number of cells transmitted from an internal counter approximately 200 ns
after a write operati on is done to Reg−64H, Reg−65H, Reg−66H, or Reg −00H. At that time (200 ns after the write operation),
this r egister is u pdated and the int ernal transmit cel l counter is reset to zero or one (depending on whether a cell tr ansmission
has occurr ed while the write occurs) to begin anothe r round of ac cumulatio n. Reading Reg−64H, Reg−65H, and Reg−66H af ter
the write yi elds the nu mber of cell tran smitted si nce the count er was last reset, if ov erflo w has not occurr ed. TCELL[18:0] sh ould
be poll ed once a second to prevent the register from being saturat ed.
REG − 65H Transmit ATM Cell Processor Transmit Cell Coun ter Register
BIT POSITION NAME READ/WRITE DEFAULT
7TCELL[15] R 0
6TCELL[14] R 0
5TCELL[13] R 0
4TCELL[12] R 0
3TCELL[11] R 0
2TCELL[10] R 0
1TCELL[9] R 0
0TCELL[8] R 0
TCELL[18:0]
Reg−64H, Reg−65H , and Reg−66H will load the number of cells transmitted from an internal counter approximately 200 ns
after a write operati on is done to Reg−64H, Reg−65H, Reg−66H, or Reg −00H. At that time (200 ns after the write operation),
this r egister is u pdated and the int ernal transmit cel l counter is reset to zero or one (depending on whether a cell tr ansmission
has occurr ed while the write occurs) to begin anothe r round of ac cumulatio n. Reading Reg−64H, Reg−65H, and Reg−66H af ter
the write yi elds the number of cell tra nsmitted si nce the cou nter was last reset, if ov erfl ow has no t occur red. TCELL[1 8:0] should
be poll ed once a second to prevent the register from being saturat ed.
CY7C955
PRELIMINARY
57
REG − 66H Transmit ATM Cell Processor Transmit Cell Coun ter Register
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5Unused
4Unused
3Unused
2TCELL[18] R 0
1TCELL[17] R 0
0TCELL[16] R 0
TCELL[18:0]
Reg−64H, Reg−65H , and Reg−66H will load the number of cells transmitted from an internal counter approximately 200 ns
after a write operati on is done to Reg−64H, Reg−65H, Reg−66H, or Reg −00H. At that time (200 ns after the write operation),
this r egister is u pdated and the int ernal transmit cel l counter is reset to zero or one (depending on whether a cell tr ansmission
has occurr ed while the write occurs) to begin anothe r round of ac cumulatio n. Reading Reg−64H, Reg−65H, and Reg−66H af ter
the write yields the number of cells transmitted since the counter was last reset, if overflow has not occurred. TCELL[18:0]
should be pol led once a second to prevent the regist er fr om being saturated.
CY7C955
PRELIMINARY
58
REG − 67H Transmit ATM Cell Processor Transmit Confi guration Register
BIT POSITION NAME READ/WRITE DEFAULT
7TGFCE[3] R/W 0
6TGFCE[2] R/W 0
5TGFCE[1] R/W 0
4TGFCE[0] R/W 0
3FSEN R/W 1
2H4INSB R/W 0
1FIXBYTE[1] R/W 0
0FIXBYTE[0] R/W 0
TGFCE[3:0]
This is the Transmit Generic Flow Control Enable register. Each bit of this register cor responds to a bit in the GFC field of the
transmitted ATM cell headers. If TGFCE[x] is set HIGH, bit x of the GFC f iel d in the tran sm it ted ATM cell headers will be using
the bit value collect ed from the TGFC (pin 52) pin ( see descripti on of Drop Side Transmit I nterface). If TGFCE[x] is LOW , bit x
will be derived from eit her TDAT (if transmit FIFO has at least one cell available) or from the Idle/Unassigned header register
(if transmit FIFO has less than 1 cell available).
FSEN
This is the fi x stuff enable bit. This bit will onl y affect the STS−1 frame.
0: No stuffing i s performed.
1: Column 30 and 59 of the STS−1 frame contains fix stuff bytes. The contents for the fix stuff byte is controlled by
FIXBYTE[ 1:0] (Reg−67H, bit 0 −1).
H4INSB
This bit controls t he contents of H4 byte .
0: H4 byte represents the cell indicator offset value.
1: H4 byte is set to 00H.
FIXBYTE[1:0]
This register holds the num ber to be used in the fixed byte columns.
11: FFH is inserted into the fixed byt e columns.
10: AAH is inser ted into the fi xed byte col umns.
01: 55H is inserted into the fixed byte col um ns.
00: 00H is inserted into the fixed byte col um ns.
CY7C955
PRELIMINARY
59
Maximum Ratings
(Above which the useful l ife ma y be impaired. For user guide-
li nes, not tested .)
Storage Temperature........ ............. .. ........ .. .–40°C to +1 2 5°C
Ambient Temperature under Bias ................ −40°C to +85 °C
Supply Voltage to Ground Potential...............–0.5V to +6.0V
DC Input Voltage............................................ –0.5V to +7.0V
DC Input Current ..............................................................±20 m A
Stati c Discharge Voltage................................................± 2000V
(per MIL-STD-883, Method 3015)
Latch-Up Current............................................................±100 mA
Lead Temperature .... ........... ..... ............. ..... ........... ..... ..300°C
Ma x im u m Junction Tem p e ra tu re ............ ......... .......... ...1 5 5 °C
Maximum P o wer Dissipation ........................................ 1.5 W
REG − 80H CY7C955 Test Control Registe r
BIT POSITION NAME READ/WRITE DEFAULT
7Unused
6Unused
5Unused
4Unused
3Unused
2Unused
1HIZDATA W
0HIZIO R/W 0
HIZDATA
This is the data bus three-state control bit.
0: Normal operation.
1: This data bus is held at HIGH impedance. Register reading is disabled but writing is stil l possible.
HIZIO
This is the input output three- state control bit .
0: Normal operation.
1: All I/Os ex cept the data bus are being held at the HIGH impedance state. The CY7C955 read/write is sti ll possib le.
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +7 0 °C 5V ± 10%
Industrial –40°C to +85°C5V ± 10%
CY7C955
PRELIMINARY
60
Electrical Characteristics Ov er th e Ope rating Range
Parameter Description Test Condi tions Min. Max. Unit
PECL compatible Input Pins (RXD±, RRCLK±, ALOS± TRCLK±)
VIHP Input HIGH Voltage VCC[1] V
VILP Input LOW Voltage 2.5 V
VIDIFF Input Differential Voltage 200 2500 mV
IIHP PECL Input HIGH Curren t[3] VIN = V CC[2] 500 µA
IILP PECL Input LO W Curr ent[3] VIN = 2 .5 –200 µA
PECL compatible Ou tput Pins (RXDO±, TXD±, TXC±)
VOHP Output HIGH Voltage Terminat ed by 50Ω to VCC[2] –1.33V VCC[2]
–1.03 VCC[2]
–0.7 V
VOLP Output LOW Vol tage VCC[2]
–1.92 VCC[2]
–1.62 V
VODIFF Output Differential Voltage 0.75VAVG 0.6[6] V
PECL compatibl e Input Pin (ALOS–) When ALOS+ is gr ounded
VSIHP Input HIGH Voltage VCC[2]
–1.03 V
VAILP Input LOW Voltage VCC[2]
–1.62 V
TTL compatible Input Pin s
VIHT Input HIGH Voltage 2.0 VDD
+0.3 V
VILT Input LOW Voltage –0.3 0.8 V
IIHPU Input HI GH Cu rrent for I nternal Pull-Up Pins VIH = V DD –10 10 µA
IILPU Input LOW Current for Internal Pull-Up
Pins[3] VIL = 0V −200 −20 µA
IIHPD Input HIGH Current for Internal Pull- Down
Pins[3] VIH = VDD 20 200 µA
IILPD Input LOW Current for In ternal Pull-Down
Pins[3] VIL = 0V –10 10 µA
IIH Input HIGH Current for Pins Without Pull-Up
or Pull-Down Resistors[3] VIH = V DD –10 10 µA
IIL Input LO W Current f or Pins Without Pull-Up
or Pull-Down Resistors[3] VIL = 0 V –10 10 µA
TTL compatibl e Output Pins
VOLT Output LOW Voltage VDD = 4.75V, IOL = 12 mA for INTB and
TCLK and 8 mA for all others 0.4 V
VOHT Output HIGH Voltage [4] VDD = 4.75V, IOH = 1 2 mA for TCLK and 8
mA for a ll ot h er s 2.4 V
IOZ Three-stat e Leakage DATA[0:7] –10 10 µA
IOST Output Shor t Circuit Current[4] VOUT=0V[5] –15 –90 mA
Operating Current
IDD Operational Current Rate 0 = 0 (51.84 Mbps , STS–1)
Rate 0 = 1 (155.52 Mbps, STS–3c/ STM–1) 210[7] mA
IDDS Standby Current RSTB = 0, or RESET (Reg–00H, bit 7) = 1 75 mA
Notes:
2. RXVDD for RXD±, RRCLK±, and ALOS±, RXDO±; TXVDD for TRCLK±, TXD± and TXC±.
3. Current flowing out of the chip has a positive value, current flowing into the chip has a negative value.
4. Maximum leakage current of INTB output at VOHT = 900 µA.
5. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
6. Typical is 0.75VAVG.
7. Conditions: Outputs unloaded; VDD = 5.5V; TXD ± = RXD ± = OPEN.
CY7C955
PRELIMINARY
61
Capacitance
Parameter Description Max. Unit
CIN Input pi n capacitance 7pF
COUT Outp ut pi n capacitance 7pF
CIO Input / Output pin capacitance 7pF
AC Test Loads and Waveforms
2.0V
1.0V
3.0V
GND
2.0V
1.0V
5V
OUTPUT
(a) TTL AC Test Load (b) PECL ACTest Load
≤1ns ≤1ns
80% 20%
80%
20%
≤1ns ≤1ns
(c)TTL InputTestWaveform (d) PECL Input Test Waveform
R1
R2
CL
CLRL
R1=910Ω
R2=510Ω
CL<30pF
(Includes fixture and
probe capa citance)
RL=50Ω
CL<5pF
(Includes fixture and
probe capa citan ce)
VIHE
3.0V
VCC –1.33
VIHE
VILE VILE
7C955-13 7C955-14
7C955-12
Switching Characteristics Ove r the Operating Range
Parameter Description Min. Max. Unit
Microproce ssor Interface Read Cycle
tSAR Vali d Address to Read Set- Up 25 ns
tHRA Read to Address In valid Hold 5ns
tSAL Vali d Address to Address Latch Enable Set-Up 20 ns
tHLA Address Latch Enable to Addres s Invalid Hold 10 ns
tPL Address Latch Enable Pulse Width 20 ns
tSLR Address Latch Enable to Read Set- Up 0ns
tHRL Read to Address Latch Enable Hold 5ns
tSRD Read to Valid Data Set-Up 80 ns
tHRD Read to Data In valid Hol d 20 ns
tSRI Read to Interrup t In active 50 ns
Microproce ssor Interface Write Cycle
tSAW Valid Address to Write Set-Up 25 ns
tSDW Va lid Data to Write Set-Up 20 ns
tSAL Vali d Address to Address Latch Enable Set-Up 20 ns
tHLA Address Latch Enable to Addres s Invalid Hold 10 ns
tPL Address Latch Enable Pulse Width 20 ns
tSLW Addr ess Latch Enable to Write Set-Up 0ns
CY7C955
PRELIMINARY
62
tHWL Write to Address Latch Enable Hold 5ns
tHWD W r ite to Data Inva lid Hol d 5ns
tHWA Write to Address I nval id Hold 5ns
tPW Write Pulse Width 40 ns
Line Int erface (Receive Side) Timing
tRRRCLK± Duty Cycle 19.44 MHz or 6.48 MHz
(RBYP = 0) 30 70 %
fRRRCLK± F requency Tolerance[8, 9] −250 250 ppm
tSDC RXD± Stable to RRCLK± Rising Edge Setup Time. RBYP = 1 2ns
tHCD RRCLK± State Change to RXD Unstab le Hold Time . RBYP = 1 1ns
Receive Side Alarm Timing
tDCR RCLK HIGH to RALM or RFP Valid Delay 220 ns
Line Int erface (Transmit Side) Ti ming
tTTRCLK± Duty Cycle 19.44 MHz or 6.48 MHz
(TBYP = 0) 30 70 %
fTTRCLK± Frequency Tolerance –250 250 ppm
tDTO TCLK HIGH to TFPO V alid Delay 320 ns
tDTD TXC± LOW to TXD± Valid Delay –2 2 ns
UTOPIA Int erface (Receive Side ) Timing [TSEN = 0]
fRF RFCLK F requency 33 MHz
tRF RFCLK Duty Cycle 40 60 %
tSRC RRDENB Stable to RFCLK HIGH Set-Up 10 ns
tHCR RFCLK HIGH to RRDENB Unstable Hold 1ns
tDCD RFCLK HIGH to RSOC / RCA / RXPRTY / RD AT [7:0] Valid Delay 220 ns
UTOPIA Int erface (Receive Side ) Timing [TSEN = 1]
fRF RFCLK F requency 33 MHz
tRF RFCLK Duty Cycle 40 60 %
tSRC RRDENB Stable to RFCLK HIGH Set-Up 10 ns
tHCR RFCLK HIGH to RRDENB Unstable Hold 1ns
tDCA RFCLK HIGH to RCA Valid Delay 220 ns
tDCD RFCLK HIGH to RSOC / RXPR TY / RDAT [7: 0] Valid Delay 220 ns
tDCT RFCLK HIGH to RSOC / RXPR TY / RDAT [7:0] Three- sta te Del ay 220 ns
GFC (RECEIVE SIDE) TIMING
tDCG RCLK HIGH to RGFC / RCP Valid Dela y −110 ns
UTOPIA INTERFACE (TRANSMIT SIDE) TIMING
fTF TFCLK Frequency 33 MHz
tTF TFCLK Duty Cycle 40 60 %
tSTC TWRENB / TDAT[7: 0] / TXPR TY / TSOC Stab l e to TFCLK HIGH Set- Up 10 ns
Notes:
8. Not Tested.
9. See description on Receive Clock Recovery (RCR) page 10
Switching Characteristics Ove r the Operating Range (contin ued)
Parameter Description Min. Max. Unit
CY7C955
PRELIMINARY
63
tHCT TFCLK HIGH to TWRENB / TDAT[7:0] / TXPRTY / TSOC Unstable Hold 1ns
tDTT TFCLK HIGH to TCA V alid Delay 220 ns
GFC (Transmit Side) Timing
tSGT TGFC Stable to TCLK High Set- Up 10 ns
tHTG TCLK High to TGFC Unstable Hold 1ns
tDTP TC L K Hi gh to TCP Va lid D e lay –110 ns
Switching Characteristics Ove r the Operating Range (contin ued)
Parameter Description Min. Max. Unit
Switching Waveforms
VALID ADDRESS
VALID DATA
A[7:0]
ALE
(RDB + CSB)
D[7:0]
tPL
tHRA
tHLA
tSLR
tHRD
tSRD
tHRL
INTB
tSRI
7C955–15
tSAR
tSAL
Microprocessor Interface Read Cycle
CY7C955
PRELIMINARY
64
Switching Waveforms (conti nued)
VALID ADDRESS
VALID DATA
A[7:0]
ALE
(WRB+ CSB)
D[7:0]
tPL
tHWA
tHLA
tSLW
tHWD
tHWL
7C955–16
tSAW
tSAL
tSDW
tPW
Microprocessor Interface Write Cycle
RRCLK±
RXD±
tSDC tHCD
7C955–17
Receive Side Line Interface Timing
CY7C955
PRELIMINARY
65
Switching Waveforms (conti nued)
RALM / RFP
RCLK
tDCR
7C955–18
Receiver Al arm Interface Timing
TFPO
TCLK
tDCT
TXC±
tDCD
7C955–19
TXD±
Transmit Side Line Interf ace Timing
CY7C955
PRELIMINARY
66
Switching Waveforms (conti nued)
RRDENB
RFCLK
tHCR
RDAT[7:0] / RCA/
RSOC/ RXPRTY
tSRC
tDCD
Utopia Interface (Receive Side) Timing [TSEN = 0]
7C955–20
CY7C955
PRELIMINARY
67
Switching Waveforms (conti nued)
RRDENB
RFCLK
tHCR
RCA
tSRC
tDCA
VALID RDAT[7:0] / RSOC/ RXPRTY
RDAT[7:0] /
RSOC/ RXPRTY
tDCD
tDCT
7C955–21
Utopia Interface (Receive Side) Timing [TSEN=1]
tDCG
7C955–22
GFC Interface (Receive Side) Timing
RGFC / RCP
RCLK
CY7C955
PRELIMINARY
68
Switching Waveforms (conti nued)
RRDENB
tSTC
RCA
tHCT
tDTT
7C955–23
RCLK
Utopia Interface (Transmit Side) Timing
TGFC
tSGT
TCP
tHTG
tDTP
7C955–24
TCLK
GFC Interface (TransmitSide)Timing
CY7C955
PRELIMINARY
69
Functional Timing Diagram
Utopia Interface (Transmi t Side) Functional Timing
Figure 8 shows, in a nutshe ll, all the func ti onal timing requir e-
ments of the Transmit Side Utopi a Interf ace. The Transmi t Sid e
Utopia Interface consists of TDAT[7:0], TXPRTY, TSOC,
TWRENB, TCA, and TFCLK.
TDAT[7:0]
ATM cells are expected to be clocked into the Utopia FIFO
interface through TDAT[7:0] with the 1st header byte first fol-
lowed b y the remaining 52 bytes of headers a nd payl oad. The
fifth header byte (HEC) is required but is being ignored and
repl aced by the HCS oc tet gen erated b y the Transmi t ATM Cell
Processor.
TXPRTY
The TXPTYP (Reg−63, bit 7) and TXPRTYE (Reg−63H, bit 6)
can be set to make the Transmit Side Utopia Interface accept
odd, eve n, or no parity TXPRTY inputs.
TSOC
A HIGH TSOC input is expected along with the first header
byte of an ATM ce ll . If TSOC i s absent, the Transm it ATM Cell
Processor will automati cally generate a TSOC based on pre-
vious TSOC positions, no interrupt will be sent. However, if
TSOC is mispl aced, the pre viousl y stored inco mplete ATM cell
wil l be di scarded and t he transmi t FIFO point er will be set back
to th e beginning of the same cel l. A mispl aced e vent will cause
TSOCI (Reg−60H, bit 6) to go HIGH, and causes an interrupt
also if FIFOE (Reg−60H, bit 7) is enabled.
TWRENB
This transmit FIFO write enable bit (TWRENB) should be
pulled LOW whenever there is an ATM byte to send. It can be
deacti vated at any time t o pause the writing pro cess—not nec -
essaril y at cell boundaries.
TCA
The transmit cell available (TCA) is affected by TCAINV
(Reg−01H, bi t 3) and TCALEVEL0 (Reg−63H, bit 94). TCAINV
determines the active polarity of the TCA signal, and
TCALEVEL0 controls the meaning of TCA going active. If
TCALEVEL0 = 0, TCA will be deasserted when the transmit
FIFO is 4 writes from full. If TCALEVEL0 = 1, TCA will be
deasserted when the FIFO is full and can accept no more
writes.
TFCLK
TFCLK has to be a cloc k of 33 MHz or les s. Al though i t can be
stopped if necessary, it is not recommended because some
regis ters and pi ns synchroniz ed by this clock will not be updat-
ed. If this clock is stopped, the line side interface will still be
able to transmit the cells already stored into the FIFO. After
that, idle cells will be transmitted.
Figure 8. Transmit FIFO
TFCLK
TCA
TXPRTY
TSOC
TWNRENB
TDAT[7:0]
TCA LEVEL 0 =1
H1 H1H2 H3 X
P48P47
P46
P45P44
X
XX
CY7C955
PRELIMINARY
70
Functional Timing Diagram (continued)
Utopia Interface (Receive Side) Funct ional Timing
Figure 9 sho w s, in a nutshell, all the functional ti m ing require-
ments of t he Receiv e Side Ut opia I nterf ace . The Receive Side
Utopia Interface consists of TSEN, RDAT[7:0], RXPRTY,
RSOC, RRDENB, RCA, and RFCLK.
TSEN
This three-state enable pin can be used to implement shared
Utopia bus architecture for Multi-PHY operation. If TSEN is
ti ed HIGH, RDAT[7:0] , RXPRTY, and RSOC will be three-stat-
ed if RRDENB is HIGH. If TSEN is pulled LOW, RDAT[7:0],
RXPRTY, and RSOC will always assume a logic 1 or logic 0.
TSEN has an integrated pull down resistor.
RDAT[7:0]
ATM cells are cloc ked out of the Utopia FIFO interf ace through
RDAT[7:0] with the 1st header byte first followed by the remain-
ing 52 bytes of headers and payload. The cell stream can be
stopped at anytime by pulling RRD ENB HIGH.
RXPRTY
The RXPTYP (Reg–50, bit 6) can be set to make the receive
side Utop ia interf ace produce odd or e ven parity RXPR TY out-
puts.
RSOC
RSOC will g o HIGH when RDAT[7:0] contains the f ir st header
byte of an ATM cel l.
Figure 9. Recei ve FI FO
RFCLK
RCA
P43
RXPRTY
RRDENB
P44 P45 P46 P47
H1
RSOC
H1
RDAT[7:0]
RCALEVEL0= 1
READ IGNORED
H2 P48
CY7C955
PRELIMINARY
71
Functional Timing Diagram (continued)
GFC Interface (Transmit Side) Functional Ti ming
Figure 10 sho w s the functional timing for the TGFC input with
re s pect to TCLK and TCP.
TCP
Transmit Cell Pulse toggles HIGH for one clock cycle 6 TCLK
periods before the first oct et of the next ATM cell is read from
the tr ansmit FIFO.
TGFC
If enabled by TGFCE (Reg-67, bit 4−7), a stable TGFC[3] is
expected on the next risi ng edge of the TCLK after TCP goes
HIGH (see Figure 10). All enabled TG FC bits will replace the
corresponding GFC bit of the next transmitted assigned ATM
cell . Unassig ned/ Idle cells will mainta in its defaul t content and
will not be af fected by t he TG FC input .
GFC Interface (Receive Side) Functional Timing
Figure 11 s hows the funct ional timing for the RGFC input with
respect to RCLK and RCP.
RCP
Receive Cell Pulse toggles HIGH whenever the most signifi-
cant GFC bit (GFC[3]) of an assi gned ATM cell header i s pre-
sented on the RGFC pin. GFC[3] can be present for as long
as 1 to 14 RCLK cycles on the RGFC pin, and so RCP can
also be HIGH for anywhere between 1 to 14 RCLK cycles .
Figure 10. Trans mit GFC Serial Link
GFC[3] GFC[2] GFC[1] GFC[0] X
X
TCLK
TCP
TGFC
Figure 11. Receive GFC Serial Link
RCP
GFC[2]
CELLNGFC[1]
CELLN GFC[0]
CELL N
GFC[3]
CELLN
RCP
RCLK
RGFCE[3:0]=1111B
RGFC
GFC[3]
CELLN
RGFC
RGFCE[3:0]=1001B
GFC[0]
CELL N
CY7C955
PRELIMINARY
72
Functional Timing Diagram (continued)
Timing Modes
Figure 12, 13, and 14 shows how to connect the clock refer-
ence for different app li cations.
In the presence of a 155.52 MHz/51.84 MHz primary reference
source (PRS). The configuration described in Figure 12 should
be used. TBYP is HIGH and RBYP is LOW. The primary
reference clock source provides the accurate bit synchroniza-
tion needed for the transmit data stream.
If the application is a LAN t ermination equipment, the config-
uration described in Figure 13 should be used. LOOPT
(Reg–5H, bit 0) i s HIGH to enable loop timing mode. In loop
timing mode, The clock recovered from the received data
stream is being used to synchronize the transmit datastream.
If that cl ock is lost, RRCLK x 8 will be used as the cloc k refer-
ence. The clocking architecture of the CY7C955 is shown in
Figure 14.
Figure 12. Clock Synthesis
19.44 MH z Stratum or free-run
reference
TRCLK±
RRCLK±
RXD± TCLK
Input Data CY7C955
Figure 13. Loop Timing
19.44 MHz St ra tu m or fre e -r u n
reference
TRCLK±
RRCLK±
RXD± TCLK
Input Data CY7C955
Figure 14. Conceptual Clocking Structure
Clock Synthesizer
/8
Cl o ck R e covery Internal
Rx Clock
Source
Internal
Tx Clock
Source A
B
TCLK
RXD±
TRCLK±
RRCLK±
CY7C955
PRELIMINARY
73
Interf ace Term ination and Biasing Schemes
PECL Input Termination and Biasi ng Recom m endations
Figures 15−19 show how to connect different output types to
the CY7C955 PECL inputs. Dif ferential term ination and bias-
ing (Figure 15) is required for RXD, and is highly recommend-
ed for RRCLK, and TRCLK. Ne v ertheless it is a lso possi b le f or
the input to accept singl e-ended signals. If th e positive end of
a PECL input pair is tied to GND (with or without a pull-down
resistor), the negative input wi ll becom e a single-ended i nput.
This input is self-biased to its threshold at VCC/2 . N otice tha t
because the negative input is used, the signal entering the chip
through the input are in verted.
Figure 15 shows a differential PECL connection. Whenever
possible, this differential PECL connection scheme should be
used. Differential signals are less susceptible to com-
mon-m ode noise.
Figure 16 shows another possible type of a differential PECL
connection. Although this connection is allowed, the method
suggested in Figure 15 will give better switching characteris-
tics.
Figure 17 s hows a CMOS connection; no termination is need-
ed if the trac e is kept short. If the tra ce is long, fol low comm on
transmission line termination practices.
Figure 18 shows a TTL connection. The 0.01µF AC-coupling
capacitor allows the CY7C955 inputs to self-bias itself to
VCC/2. This connecti on schem e is not suita ble for the ALOS
input because the signal is close to static.
Figure 19 shows how to connect a single-ended PECL con-
necti on to the ALOS− input. ALOS is almost a static signal, so
the connection must be DC-coupled. A 330Ω resistor to GND
is needed, as a current si nk is needed for the PECL output to
operate correctly.
Figure 15. Differential PECL Terminat ion (Hi gh Performance)
CY7C955
80Ω
130Ω
TRCLK–/
RRCLK–/RXD–
TRCLK+ /
RRCLK+ / RXD+
–ve–
PECL
Output
Vcc
80Ω
130Ω
+ve–
PECL
Output
VCC
CY7C955
PRELIMINARY
74
Figure 16. Different ial PECL Termination (Low Power)
CY7C955
100Ω
330Ω
ALOS–/ TRCLK–/
RRCLK–/RXD–
ALOS+ / TRCLK+ /
RRCLK+ / RXD+
–ve–
PECL
Output
330Ω
+ve–
PECL
Output
Figure 17. CMOS Connecti on
ALOS–/ TRCLK–/
RRCLK–/RXD–
ALOS+ / TRCLK+ /
RRCLK+ / RXD+
CY7C955
CMOS
Output
CY7C955
PRELIMINARY
75
Filt er Pin Configuratio n
The CY7C955 Phase-locked Loop is designed to meet the
Bellcore specifications on jitt er generation, jitter transfer, and
jitter tolerance. The highly integrated charge pump design
drastically reduces the complexity of external filter compo-
nents. Only a single 0.47- µF non-polar capacitor is needed to
provi de the dampi ng factor n eeded to meet t he jitter cei ling de -
fined in GR-253. Figure 14 describes how to connect the ca-
pacitor across the LF− and LFO pins of the CY7C955. The
LF+ pin is to be left unconnected.
Figure 18. TTL Connection
CY7C955
.01µFTRCLK–/ RRCLK–
TRCLK+ / RRCLK+
TTL
Output
Figure 19. Single-ended PECL Connection for ALOS
CY7C955
ALOS–
ALOS+
Single-
ended–
PECL
Output 330Ω
The 1.0-µF capacitor should have the follow ing characteristics:
Breakdown Voltage: 16V or higher
Tolerance: ±10% or better
Dielectric: X7R or better
P olarit y: Non-polar or Bipolar
Size: 1206 or 1210 (0805 is not available commercial ly yet)
Example Part Number:
Size: 1206 Par t Number : 1206YC474JAT1A
Breakdown: 16V AVX Corpor ati on
Capacitance: 0.47µF Tel: 360 699 8746
CY7C955
PRELIMINARY
76
Dielectric: X7R
Tolerance: ± 5%
Size: 1206 Part Number: EMK316BJ474K
Breakdown: 16V Anderson Electronics Compo nent Distribution
Capacitance: 0.47µF Tel: 408 577 1323
Dielectric: X7R
Tolerance: ±10%
The 1.0-µF capacitor should have the follow ing characteristics:
Breakdown Voltage: 16V or higher
Tolerance: ±10% or better
Dielectric: X7R or better
P olarit y: Non-polar or Bipolar
Size: 1206 or 1210 (0805 is not available commercial ly yet)
Figure 20. Phas e-Locked Loop Capacitor Placement
LF- LFO
0.47 uF
Phase
Detector Charge
Pump VCO
FLIP
FLOP
Data
Clock
CORE
LOGIC
Orde ring Information
Orderi ng Code Package
Name P ackage Type Operating
Range
CY7C955-NC N128 128-Lead Plasti c Quad Flat Package Commercial
CY7C955-NI N128 128-Lead Plasti c Quad Flat Package Industrial
Document #: 38-00417-D
CY7C955
PRELIMINARY
77
Package D i ag r am
128-Lead Plastic Quad Flatpack
CY7C955
PRELIMINARY
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
ADDENDUM - Design Considerations for the
CY7C955
This memo outlines current design considerations for the
CY7C955 - ATM PHY in reference to th e ATM Forum UTOPIA
Level 1 specification.
Receive FIFO Reset
The Receive four-cell FIFO is reset by programming register
0x50(RACP)[0] to a logic '1'.
Under this condition the CY7C955 RCA output is not deassert-
ed immediately and the RDATA[7:0] output is not 0x00. The
CY7C955 RCA output is held asserted until the end of the
current transmission of the cell on the RxUTOPIA bus. The
RDATA i s hold immediately af ter the RxFI FO Reset is recog-
nized, whil e the RCA output i s still asserted (indicati ng a valid
cell).
54-Byte Cell on RxUTOPIA Bus
Received ATM cells i n the RXFIFO can be read out from the
RxUTOPIA bus at various throughput. The th roughput can be
throt tl ed by two ways; one way i s by changing the RFCLK fre-
quency; another way is using the RRDENB input and a fixed
RFCLK (for more information on the Rx UTOPIA bus opera-
tion, refer to the pin descr iption, “Receive UTOPIA Interface”
secti on of the d ata sheet a nd the UT OPIA spec Le ve l 1). When
the throughput writing into the RxFIFO is greater than the
throughput reading out, then, intermittently, the CY7C955 out-
puts a cell wit h 54bytes
Figure 21. CY7C955 Receive FI FO Reset Behavior
FIFO RST
RCA
RDATA
