74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 8 -- 6 January 2014 Product data sheet 1. General description The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The device consists of two sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are transparent, that is, the latch outputs change each time its corresponding D-input changes. The latches store the information that was present at the D-inputs one set-up time (tsu) preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pinout architecture Multiple low inductance supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold (74LVCH16373A only) High-impedance when VCC = 0 V Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 3. Ordering information Table 1. Ordering information Type number Package 74LVC16373ADGG Temperature range Name Description Version 40 C to +125 C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 40 C to +125 C SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 74LVCH16373ADGG 74LVC16373ADL 74LVCH16373ADL 4. Functional diagram 1 1LE 1OE 2OE 2OE 47 1D0 1Q0 2 46 1D1 1Q1 3 44 1D2 1Q2 5 43 1D3 1Q3 6 41 40 38 37 36 1D4 1Q4 1D5 1Q5 1D6 1Q6 1D7 1Q7 2D0 2Q0 2D2 2Q2 16 29 27 26 2Q4 2D5 2Q5 2D6 2Q6 2D7 2Q7 1LE 1D3 1D4 1D5 1D6 13 33 2D4 1D2 12 14 30 1D1 11 2Q1 2Q3 1D0 9 2D1 2D3 2LE 8 35 32 1D7 2D0 2D1 17 2D2 19 2D3 20 2D4 22 2D5 23 2D6 2LE 2D7 48 Fig 1. Logic symbol 74LVC_LVCH16373A Product data sheet 25 1 1OE 24 48 24 25 47 1EN C3 2EN C4 3D 1 2 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4D 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 mgu768 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 mgu770 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 2 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 1D0 1Q0 Q D 2D0 D LATCH 1 LE 2Q0 Q LATCH 9 LE LE 1LE 2LE 1OE 2OE to 7 other channels LE to 7 other channels mgu769 Fig 3. Logic diagram VCC data input to internal circuit mgu771 Fig 4. Bus hold circuit 74LVC_LVCH16373A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 3 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 5. Pinning information 5.1 Pinning 1OE 1 48 1LE 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 16373A 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2LE 001aad112 Fig 5. Pin configuration SSOP48 and TSSOP48 5.2 Pin description Table 2. Pin description Symbol Pin Description 1OE 1 output enable input (active LOW) 2OE 24 output enable input (active LOW) 1LE 48 latch enable input (active HIGH) 2LE 25 latch enable input (active HIGH) GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC 7, 18, 31, 42 supply voltage 1Q[0:7] 2, 3, 5, 6, 8, 9, 11, 12 data output 2Q[0:7] 13, 14, 16, 17, 19, 20, 22, 23 data output 1D[0:7] 47, 46, 44, 43, 41, 40, 38, 37 data input 2D[0:7] 36, 35, 33, 32, 30, 29, 27, 26 data input 74LVC_LVCH16373A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 4 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 6. Functional description Table 3. Function table Per section of eight bits [1]. Operating modes Input Internal latch Output nQ0 to nQ7 nOE nLE nDn Enable and read register (transparent mode) L H L L L L H H H H Latch and read register L L l L L L L h H H H L l L Z H L h H Z Latch register and disable outputs [1] H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH to LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH to LOW LE transition Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 [1] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA output HIGH or LOW state [2] 0.5 VCC + 0.5 V output 3-state [2] 0.5 +6.5 V - 50 mA VO > VCC or VO < 0 IO output current VO = 0 V to VCC ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 500 mW Tamb = 40 C to +125 C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] Above 60 C, the value of Ptot derates linearly with 5.5 mW/K. 74LVC_LVCH16373A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 5 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage functional VI input voltage VO output voltage Min Typ Max Unit 1.65 - 3.6 V 1.2 - 3.6 V 0 - 5.5 V output HIGH or LOW state 0 - VCC V output 3-state 0 - 5.5 V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 1.2 V Product data sheet 40 C to +125 C Max Min Max Unit 1.08 - - 1.08 - V 0.65 VCC - - 0.65 VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V 0.12 V VCC = 1.65 V to 1.95 V VCC = 1.2 V - - 0.12 - VCC = 1.65 V to 1.95 V - - 0.35 VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC 0.2 - - VCC 0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - 0.1 5 - 20 A 0.35 VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 3.6 V VI = VIH or VIL input leakage VCC = 3.6 V; current VI = 5.5 V or GND[2] 74LVC_LVCH16373A Typ[1] All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 6 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Table 6. Static characteristics ...continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions 40 C to +125 C Min Typ[1] Max Min Max Unit IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND[2] - 0.1 5 - 20 A IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - 0.1 10 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 20 - 80 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC 0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF IBHL bus hold LOW current VCC = 1.65; VI = 0.58 V[3][4] 10 - - 10 - A VCC = 2.3; VI = 0.7 V 30 - - 25 - A 75 - - 60 - A 10 - - 10 - A 30 - - 25 - A 75 - - 60 - A 200 - - 200 - A VCC = 2.7 V 300 - - 300 - A VCC = 3.6 V 500 - - 500 - A 200 - - 200 - A VCC = 2.7 V 300 - - 300 - A VCC = 3.6 V 500 - - 500 - A VCC = 3.0; VI = 0.8 V IBHH bus hold VCC = 1.65; VI = 1.07 HIGH current V = 2.3; V = 1.7 V CC I VCC = 3.0; VI = 2.0 V IBHLO IBHHO [1] bus hold LOW overdrive current bus hold HIGH overdrive current VCC = 1.95 VCC = 1.95 V[3][5] V[3][5] V[3][4] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. [2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. [3] Valid for data inputs (74LVCH16373A) only; control inputs do not have a bus hold circuit. [4] The specified sustaining current at the data inputs holds the input below the specified VI level. [5] The specified overdrive current at the data input forces the data input to the opposite logic input state. 74LVC_LVCH16373A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 7 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10. Symbol Parameter tpd propagation delay Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max - 12 - - - ns VCC = 1.65 V to 1.95 V 1.5 5.4 11.4 1.5 13.2 ns VCC = 2.3 V to 2.7 V 1.0 2.9 5.7 1.0 6.6 ns Dn to Qn; see Figure 6 [2] VCC = 1.2 V VCC = 2.7 V 1.5 2.9 4.9 1.5 6.5 ns VCC = 3.0 V to 3.6 V 1.0 2.4 4.4 1.0 5.5 ns - 14 - - - ns VCC = 1.65 V to 1.95 V 2.0 6.4 12.4 2.0 14.4 ns VCC = 2.3 V to 2.7 V 1.5 3.4 6.1 1.5 7.1 ns VCC = 2.7 V 1.5 3.0 5.3 1.5 7.0 ns 1.5 2.9 4.8 1.5 6.0 ns - 18 - - - ns VCC = 1.65 V to 1.95 V 1.5 5.5 12.4 1.5 14.3 ns VCC = 2.3 V to 2.7 V 1.0 3.1 6.6 1.0 7.6 ns LE to Qn; see Figure 7 VCC = 1.2 V VCC = 3.0 V to 3.6 V ten enable time OE to Qn; see Figure 8 [2] VCC = 1.2 V tdis disable time VCC = 2.7 V 1.5 3.3 5.7 1.5 7.5 ns VCC = 3.0 V to 3.6 V 1.0 2.5 4.9 1.0 6.5 ns - 11 - - - ns VCC = 1.65 V to 1.95 V 2.8 4.5 9.1 2.8 10.5 ns VCC = 2.3 V to 2.7 V 1.0 2.5 5.1 1.0 6.0 ns VCC = 2.7 V 1.5 3.3 6.3 1.5 8.0 ns VCC = 3.0 V to 3.6 V 1.5 3.1 5.4 1.5 7.0 ns VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.0 - - 3.0 - ns VCC = 3.0 V to 3.6 V 3.0 2.0 - 3.0 - ns VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns VCC = 2.7 V 2.0 - - 2.0 - ns VCC = 3.0 V to 3.6 V 2.0 1.0 - 2.0 - ns OE to Qn; see Figure 8 VCC = 1.2 V tW tsu pulse width set-up time 74LVC_LVCH16373A Product data sheet [2] LE HIGH; see Figure 7 Dn to LE; see Figure 9 All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 8 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Table 7. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10. Symbol Parameter th Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions hold time Min Typ[1] Max Min Max Dn to LE; see Figure 9 VCC = 1.65 V to 1.95 V 2.5 - - 2.5 - ns VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns VCC = 2.7 V 0.9 - - 0.9 - ns +0.9 1.0 - +0.9 - ns - - 1.0 - 1.5 ns VCC = 1.65 V to 1.95 V - 10.8 - - - pF VCC = 2.3 V to 2.7 V - 13.0 - - - pF VCC = 3.0 V to 3.6 V - 15.0 - - - pF VCC = 3.0 V to 3.6 V tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] CPD power dissipation capacitance per input; VI = GND to VCC [4] [1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] [4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL VCC2 fo) = sum of the outputs 11. Waveforms VI VI Dn input LE input VM VM t PHL t PLH VM tW t PHL t PLH VOH VOH Qn output VM VOL Fig 6. VM GND GND Qn output VM VM VM VOL mgu772 mgu773 Measurement points are given in Table 8. Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. VOL and VOH are typical output voltage levels that occur with the output load. Input (Dn) to output (Qn) propagation delays 74LVC_LVCH16373A Product data sheet Fig 7. Latch enable input (LE) pulse width, and the latch enable input to output (Qn) propagation delays All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 9 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state VI OE input VM VM GND t PLZ t PZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY Qn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled mgu775 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. 3-state enable and disable times VI VM Dn input GND th t su th t su VI VM LE input GND mgu774 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data set-up and hold times for the Dn input to the LE input 74LVC_LVCH16373A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 10 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 1.2 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V 1.65 V to 1.95 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V 2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 10. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC 2 ns 30 pF 1 k open 2 VCC GND 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k open 2 VCC GND 2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND 2.7 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 74LVC_LVCH16373A Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 11 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 12. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 (A3) A1 A pin 1 index Lp L 1 24 detail X w bp e 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit mm max nom min A A1 A2 A3 0.15 1.05 1.2 bp c D(1) E(2) 0.28 0.2 12.6 6.2 HE 0.17 0.1 12.4 L 8.3 0.5 0.25 0.05 0.85 e 6.0 Lp Q 0.8 0.50 1 7.9 v w 0.25 0.08 0.4 0.35 y Z 0.8 8 0.4 0 0.1 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Fig 11. Package outline SOT362-1 (TSSOP-48) 74LVC_LVCH16373A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 12 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3) pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 Fig 12. Package outline SOT370-1 (SSOP48) 74LVC_LVCH16373A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 13 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC_LVCH16373A v.8 20140106 Product data sheet - 74LVC_LVCH16373A v.7 * Modifications: 74LVC_LVCH16373A v.7 20130118 Modifications: 74LVC_LVCH16373A v.6 General description corrected (errata). Product data sheet - 74LVC_LVCH16373A v.6 * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. * * Legal texts have been adapted to the new company name where appropriate. Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges. 20031208 Product specification - 74LVC_LVCH16373A v.5 74LVC_LVCH16373A v.5 20021002 Product specification - 74LVC_H16373A v.4 74LVC_H16373A v.4 19980317 Product specification - 74LVC16373A_74LVCH16373A v.3 74LVC16373A_74LVCH16373A v.3 19980317 Product specification - 74LVC16373A v.2 74LVC16373A v.2 19970822 Product specification - 74LVC16373A v.1 74LVC16373A v.1 - - - - 74LVC_LVCH16373A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 14 of 17 74LVC16373A; 74LVCH16373A NXP Semiconductors 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. 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In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC_LVCH16373A Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 15 of 17 NXP Semiconductors 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC_LVCH16373A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 6 January 2014 (c) NXP B.V. 2014. All rights reserved. 16 of 17 NXP Semiconductors 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 January 2014 Document identifier: 74LVC_LVCH16373A