1. General description
The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring
separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state
outputs for bus-o riented applications. One Latch Enable (L E) input and one Output Enable
(OE) are provided for each octal. In puts can be driven from either 3.3 V or 5 V devices.
When disabled, up to 5.5 V can be applie d to the output s. These fe atures allow the use of
these devices in mixed 3.3 V and 5 V applications.
The device consists of two sections of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inpu ts enter the latches. In this condition, the
latches are transparent, that is, the latch outputs change each time its corresponding
D-input changes. The latches store the information that was present at the D-inputs one
set-up time (tsu) preceding the HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the eight latche s are available at the outputs. When OE is HIGH, the outputs
go to the high impedance OFF-st ate. Operation of the OE input does not affect the state of
the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors
to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16373A only)
High-impedance when VCC =0V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115 -B ex ce eds 20 0 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 8 — 6 January 2014 Product data sheet
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 2 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC16373ADGG 40 Cto+125C TSSOP48 plastic thin shrink small outline package;
48 leads; body width 6.1 mm SOT362-1
74LVCH16373ADGG
74LVC16373ADL 40 Cto+125C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm SOT370-1
74LVCH16373ADL
Fig 1. Logic symbol Fig 2. IEC logic symbol
mgu768
1Q0
1Q1
1LE 2LE
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1OE
47
46
48 25
44
43
41
40
38
37
2
3
1
5
6
8
9
11
12
24
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
2OE
23
mgu770
37 12
11
9
8
6
5
47
46
44
43
41
40
38
1D7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
2
3
1Q7
1Q6
1Q5
1Q4
1Q3
1Q2
1Q0
1Q1
26
22
20
19
17
16
36
35
33
32
30
29
27
2D5
2D0
2D1
2D2
2D3
2D4
13
14
2Q5
2Q4
2Q3
2Q2
2Q1
2Q0
24
25 2EN
1OE 11EN
1LE
2OE
2LE
48 C3
C4
3D 1
4D 2
2D7
2D6
2Q7
2Q6
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 3 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
Fig 3. Logic diagram
mgu769
2LE
D
LATCH
9
Q
2OE
to 7 other channels
LE LE
2Q02D0
1LE
D
LATCH
1
Q
1OE
to 7 other channels
LE LE
1Q01D0
Fig 4. Bus hold circuit
to internal circuit
mgu771
V
CC
data input
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 4 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration SSOP48 and TSSOP48
16373A
001aad112
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1Q0
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
VCC
2Q4
2Q5
GND
2Q6
2Q7
2OE
1D0
1D1
GND
1D2
1D3
VCC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
VCC
2D4
2D5
GND
2D6
2D7
2LE
1OE 1LE
Table 2. Pin de scription
Symbol Pin Description
1OE 1 output enable input (active LOW)
2OE 24 output enable input (active LOW)
1LE 48 latch enable input (active HIGH)
2LE 25 latch enable input (active HIGH)
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)
VCC 7, 18, 31, 42 supply voltage
1Q[0:7] 2, 3, 5, 6, 8, 9, 11, 12 data output
2Q[0:7] 13, 14, 16, 17, 19, 20, 22, 23 data output
1D[0:7] 47, 46, 44, 43, 41, 40, 38, 37 data input
2D[0:7] 36, 35, 33, 32, 30, 29, 27, 26 data input
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 5 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
6. Functional description
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH to LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH to LOW LE transition
Z = high-impedance OFF-state
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] Above 60 C, the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Function table
Per section of eight bits [1].
Operating modes Input Internal latch Output
nQ0 to nQ7
nOE nLE nDn
Enable and read register
(transparent mode) LHLLL
LHHHH
Latch and read register L L l L L
LLhHH
Latch register and disable outputs H L l L Z
HLhHZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI<0 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO>V
CC or VO<0 - 50 mA
VOoutput voltage output HIGH or LOW state [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.5 V
IOoutput current VO=0V toV
CC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[3] - 500 mW
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 6 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Re commended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - 3.6 V
VIinput voltage 0 - 5.5 V
VOoutput voltage output HIGH or LOW state 0 - VCC V
output 3-state 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fa ll rate VCC =1.65V to2.7V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage
VI=V
IH or VIL
IO=100 A;
VCC =1.65Vto3.6V VCC 0.2 - - VCC 0.3 - V
IO=4mA; V
CC = 1.65 V 1.2 - - 1.05 - V
IO=8mA; V
CC = 2.3 V 1.8 - - 1.65 - V
IO=12 mA; VCC = 2.7 V 2.2 - - 2.05 - V
IO=18 mA; VCC = 3.0 V 2.4 - - 2.25 - V
IO=24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage
VI=V
IH or VIL
IO= 100 A;
VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V
IO=4mA; V
CC = 1.65 V - - 0.45 - 0.65 V
IO=8mA; V
CC = 2.3 V - - 0.6 - 0.8 V
IO=12mA; V
CC = 2.7 V - - 0.4 - 0.6 V
IO=24mA; V
CC = 3.0 V - - 0.55 - 0.8 V
IIinput leakage
current VCC = 3.6 V;
VI=5.5VorGND
[2] -0.1 5-20 A
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 7 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25C.
[2] The bus hold circuit is switched off when VI>V
CC allowing 5.5 V on the input pin.
[3] Valid for data inputs (74LVCH16373A) only; control inputs do not have a bus hold circuit.
[4] The specified sustaining current at the data inputs holds the input below the specified VI level.
[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.
IOZ OFF-state
output
current
VI=V
IH or VIL; VCC = 3.6 V;
VO=5.5VorGND
[2] -0.1 5-20 A
IOFF power-off
leakage
current
VCC = 0 V; VIor VO= 5.5 V - 0.1 10 - 20 A
ICC supply
current VCC = 3.6 V; VI=V
CC or GND;
IO=0A -0.120 - 80A
ICC additional
supply
current
per input pin;
VCC = 2.7 V to 3.6 V;
VI=V
CC 0.6 V; IO=0A
- 5 500 - 5000 A
CIinput
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
-5.0- - -pF
IBHL bus hold
LOW current VCC = 1.65; VI = 0.58 V[3][4] 10 - - 10 - A
VCC = 2.3; VI = 0.7 V 30 - - 25 - A
VCC = 3.0; VI = 0.8 V 75 - - 60 - A
IBHH bus hold
HIGH current VCC = 1.65; VI = 1.07 V[3][4] 10 - - 10 - A
VCC = 2.3; VI = 1.7 V 30 - - 25 - A
VCC = 3.0; VI = 2.0 V 75 - - 60 - A
IBHLO bus hold
LOW
overdrive
current
VCC = 1.95 V[3][5] 200 - - 200 - A
VCC = 2.7 V 3 00 - - 3 00 - A
VCC = 3.6 V 5 00 - - 500 - A
IBHHO bus hold
HIGH
overdrive
current
VCC = 1.95 V[3][5] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
Table 6. Static characteristics …continued
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 8 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Vo ltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions Tamb =40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation
delay Dn to Qn; see Figure 6 [2]
VCC = 1.2 V - 12 - - - ns
VCC = 1.65 V to 1.95 V 1.5 5.4 11.4 1.5 13.2 ns
VCC = 2.3 V to 2.7 V 1.0 2.9 5.7 1.0 6.6 ns
VCC = 2.7 V 1.5 2.9 4.9 1.5 6.5 ns
VCC = 3.0 V to 3.6 V 1 .0 2.4 4.4 1.0 5.5 ns
LE to Qn; see Figure 7
VCC = 1.2 V - 14 - - - ns
VCC = 1.65 V to 1.95 V 2.0 6.4 12.4 2.0 14.4 ns
VCC = 2.3 V to 2.7 V 1.5 3.4 6.1 1.5 7.1 ns
VCC = 2.7 V 1.5 3.0 5.3 1.5 7.0 ns
VCC = 3.0 V to 3.6 V 1.5 2.9 4.8 1.5 6.0 ns
ten enable time OE to Qn; see Figure 8 [2]
VCC = 1.2 V - 18 - - - ns
VCC = 1.65 V to 1.95 V 1.5 5.5 12.4 1.5 14.3 ns
VCC = 2.3 V to 2.7 V 1.0 3.1 6.6 1.0 7.6 ns
VCC = 2.7 V 1.5 3.3 5.7 1.5 7.5 ns
VCC = 3.0 V to 3.6 V 1 .0 2.5 4.9 1.0 6.5 ns
tdis disable time OE to Qn; see Figure 8 [2]
VCC = 1.2 V - 11 - - - ns
VCC = 1.65 V to 1.95 V 2.8 4.5 9.1 2.8 10.5 ns
VCC = 2.3 V to 2.7 V 1.0 2.5 5.1 1.0 6.0 ns
VCC = 2.7 V 1.5 3.3 6.3 1.5 8.0 ns
VCC = 3.0 V to 3.6 V 1 .5 3.1 5.4 1.5 7.0 ns
tWpulse width LE HIGH; see Figure 7
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.0 - - 3.0 - ns
VCC = 3.0 V to 3.6 V 3.0 2.0 - 3.0 - ns
tsu set-up time Dn to LE; see Figure 9
VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns
VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns
VCC = 2.7 V 2.0 - - 2.0 - ns
VCC = 3.0 V to 3.6 V 2.0 1.0 - 2.0 - ns
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 9 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
[1] Typical values are measured at Tamb =25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs
11. Waveforms
thhold time Dn to LE; see Figure 9
VCC = 1.65 V to 1.95 V 2.5 - - 2.5 - ns
VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns
VCC = 2.7 V 0.9 - - 0.9 - ns
VCC = 3.0 V to 3.6 V +0.9 1.0 - +0.9 - ns
tsk(o) output skew
time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns
CPD power
dissipation
capacitance
per input; VI=GNDtoV
CC [4]
VCC = 1.65 V to 1.95 V - 10.8 - - - pF
VCC = 2.3 V to 2.7 V - 13.0 - - - pF
VCC = 3.0 V to 3.6 V - 15.0 - - - pF
Table 7. Dynamic characteristics …continued
Vo ltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions Tamb =40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur
with the output load.
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur
with the output load.
Fig 6. Input (Dn) to output (Qn) propagation delays Fig 7. Latch enable input (LE) pulse width, and the
latch enable input to output (Qn) propagation
delays
mgu772
Dn input
Qn output
t
PHL
t
PLH
GND
V
I
V
M
V
M
V
M
V
OH
V
OL
mgu773
LE input
Qn output
t
PHL
t
PLH
t
W
V
M
V
M
V
OH
V
I
GND
V
OL
V
M
V
M
V
M
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 10 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. 3-state enable and disa ble times
mgu775
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
Qn output
LOW-to-OFF
OFF-to-LOW
Qn output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VOL
VOH
VCC
VMVM
GND
GND
tPZL
tPZH
VM
VM
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Data set-up and hold times for the Dn input to the LE input
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 11 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
Table 8. Measurement points
Supply voltage Input Output
VCC VIVMVMVXVY
1.2 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
1.65 V to 1.95 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
CL
RT
RL
RL
G
Table 9. Test data
Supply voltage Input Load VEXT
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.2 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
1.65 V to 1.95 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND
2.7V 2.7V 2.5 ns 50 p F 500 open 2 VCC GND
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 12 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
12. Package outline
Fig 11. Package outline SOT362-1 (TSSOP-48)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT362-1 MO-153
sot362-1_po
03-02-19
13-08-05
Unit
mm
max
nom
min
0.15 0.28 0.2 12.6
0.5
0.8
A
Dimensions (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A1A2
1.05
A3bpcD
(1)
8°
θE(2) eH
EL
1
LpQvw
1.2 0.25 0.10.25 0.08
yZ
7.9 0.46.0 0.350.05 0.17 0.1 12.4 0.4 0°
0.85
8.3 0.86.2 0.50
pin 1 index
vA
θ
A
D
Lp
Q
E
Z
c
L
124
48 25
e
w
y
X
A
HE
bp
A1
A2
detail X
(A3)
0 5 mm
scale
2.5
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 13 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
Fig 12. Package outline SOT370-1 (SSOP48)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
48 25
MO-118
24
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 14 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Mo del
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release
date Data sheet status Change
notice Supersedes
74LVC_ LVCH16373A v.8 20140106 Product data sheet - 74LVC _LVCH16373A v.7
Modifications: •General description corrected (errata).
74LVC_ LVCH16373A v.7 20130118 Product data sheet - 74LVC_LVCH16373A v.6
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage
ranges.
74LVC_ LVCH16373A v.6 20031208 Product specification - 74LVC_LVCH16373A v.5
74LVC_ LVCH16373A v.5 20021002 Product specification - 74LVC_H16373A v.4
74LVC_ H16373A v.4 19980317 Product specification - 74LVC16373A_74LVCH16373A v.3
74LVC1 6373A_74LVCH16373A v.3 19980317 Product specification - 74LVC16373A v.2
74LVC16373A v.2 19970822 Product specification - 74LVC16373A v.1
74LVC16373A v.1 - - - -
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 15 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyon d those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors product s are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the pre liminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 6 January 2014 16 of 17
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors prod uct is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs ; 3-state
© NXP B.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 January 2014
Document identifier: 74LVC_LVCH16373A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16 Contact information. . . . . . . . . . . . . . . . . . . . . 16
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17