1
®
FN9098.0
PRELIMINARY
ISL6561
Multi-Phase PWM Controller with
Precision Rds, On or DCR Current
Sensing
The ISL6561 controls microprocessor core voltage
regulation by driving up to 4 synchronous-rectified buck
channe ls in par allel. Multi -pha se bu ck c onverte r archi tectur e
uses interleaved timing to multiply channel ripple frequency
and reduce input and output ripple currents. Lower ripple
results in fewer compon ents, lower component cost ,
reduced power dissipation, and smaller implementation
area.
Microprocessor loads can generate load transients with
extremely fast edge rates. The ISL6561 features a high
bandwidth control loop and ripple frequencies of >4MHz to
provide optimal response to the transients.
Today’s microprocessors require a tightly regulated output
voltage position versus load current (droop). The ISL6561
senses current by utilizing patented techniques to measure
the voltage across the on resistance, rDS(on), of the lower
MOSFETs or DCR of output ind uctor during their cond uction
intervals. Current sensing provides the needed signals for
precisi on droop, channel-current balan cing, and over-curr ent
protection.
The accuracy of the rDS(on) current-sensing method is
enhanced by the ISL6561’s temperature compensation
function. Droop accuracy can be affected by increasing
rDS(on) or DCR with elevated temperature. The ISL6561
uses an internal temperature-sensing element to provide
programmable temperature compensation. Correctly
applied, temperature compensation can completely nullify
the effect of rDS(on) temperature sensitivity.
A unity gain, differe ntial ampli fier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds can be completely eliminated using the
remote-sense amplifier. Eliminating ground differences
improves regulation and protection accuracy. The threshold-
sensitive enable input is available to accurately coordinate
the start up of the ISL6561 with any other voltage rail.
Dynamic-VID™ technology allows seamless on-the -fly VID
changes. The offset pin allows accurate voltage offset
settings that are independent of VID setting. The ISL6561
uses a 5V bias and has a built-in shunt regulator to allow
12V bias using only a small external limiting resistor.
Applications
• Computer D C/D C conve rter VR M/VRD 1 0.0 .
• Computer DC/DC Converter VRM/VRD9.X with 5-bit VID
code up to 1.6V.
• Telecom DC/DC converter.
Features
• Precision Multi-Phase Core Voltage Regulation
- Differential Remote Voltage Sensing
-±0.5% System Accuracy Over Life, Load, Line and
Temperature
- Adjustable Refere nc e-Vo ltag e Offset
• Precision RDS(on) or DCR Current Sensing
- Integrated Programmable Temperature Compensation
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Differential Current Sense
- Low-Cost, Lossless Current Sensing
• Internal Shunt Re gulat or for 5V or 12V Biasin g
• Microprocessor Voltage Identification Input
- Dynamic VID™ technology
- 6-Bit VID Input
- .8375V to 1.600V in 12.5mV Steps
• Threshol d-Sensitive Enab le Func ti on for syn chr oni zing
with driver POR
• Over Current Protection
• Over-Voltage Prot ection
- No Additional External Components Needed
- OVP Pin to drive Crowbar Device
• 2, 3, or 4 Phase Operation
• Greater Than 1MHz Operation (> 4MHz Ripple)
ISL6561 (40-PIN MLFP)
TOP VIE W
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. NO.
ISL6561 0 to 70 40 Ld QFN L40.6X6
VID4
VID3
VID2
VID1
GND
ISEN1-
VID12.5 PWM1
RGND
VID0 26
27
28
25
24
23
1
2
3
4
5
7
6
8
GND
COMP
FB
VDIFF
VSEN
9
10
11
12
13
14
15
16
17
18
19
20
22
21
PWM2
PWM3
ISEN1+
TCOMP
DAC
OFS
29
30
EN
FS
ENLL
GND
VCC
PWM4
PGOOD
OVP
31
32
33
34
35
37
36
38
39
40
GND
IDROOP
ISEN3+
ISEN3-
ISEN2-
ISEN2+
ISEN4+
ISEN4-
REF
GND
GND
Data Sheet November 2002
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Block Diagram
I_TRIP
∑
∑
∑
∑
∑
CHANNEL
POWER-ON
RESET (POR)
+
-E/A
+
-
PWM
PWM
+
-
PWM1
PWM2
PWM3
PWM4
GND
VCC
FB
FS
+
-
+
+
-
+
-PWM
+
-PWM
CLOCK AND
VID4
VID3
VID2
VID1
COMP
VSEN
GENERATOR
SAWTOOTH
ISEN3+
ISEN4+
VID0
RGND
EN
1.23V
+
-
+
+
+
+
-
+
-
+
-
I_TOT
TCOMP
DYNAMIC
VID
D/A
2.5V
SAMPLE
HOLD
&
∑
CURRENT
BALANCE
CHANNEL
DETECT
OFS
DAC
TRI-STATE
OC
ISEN1+
ISEN2+
CHANNEL
CURRENT
SENSE
1.23V
T
VID12.5
IDROOP
REF
ISEN1-
ISEN2-
ISEN3-
ISEN4-
OFFSET
ENLL
OV
LATCH
S
VDIFF PGOOD
OVP
+
x1
+
-
OVP
-CONTROL, SOFT-
START AND FAULT
LOGIC
+200mV
-
ISL6561
3
Typical Application - 4-Phase Buck Converter with Rds, On Sensing and External NTC
VID3
+5V
PWM
VCC BOOT
UGATE
PHASE
LGATE
GND
+12V
VIN
PWM
VCC BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601A
DRIVER
VIN
VID4
PGOOD
VID2
VID1
VID0
VSEN
VDIFF
FB COMP
VCC
GND
RGND
EN
ISEN1+
PWM1
PWM2
ISEN2+
PWM3
ISEN3+
PWM4
ISEN4+
ISL6561
µP
LOAD
VID12.5
ISEN1-
ISEN2-
ISEN3-
ISEN4-
TCOMP
REF
DAC
OVP
NTC
NETWORK
FS
OFS
DRIVER
HIP6601B
PVCC
ENLL
VTTPWRGD
IDROOP
HIP6601B
DRIVER
ISL6561
4
Typical Application - 4-Phase Buck Converter with Rdes, On Sensing and Internal PTC
VID3
+5V
PWM
VCC BOOT
UGATE
PHASE
LGATE
GND
+12V
DRIVER
VIN
PWM
VCC BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
VID4
PGOOD
VID2
VID1
VID0
VSEN
VDIFF
FB
COMP
VCC
GND
RGND
EN
ISEN1+
PWM1
PWM2
ISEN2+
PWM3
ISEN3+
PWM4
ISEN4+
ISL6561
µP
LOAD
VID12.5
ISEN1-
ISEN2-
ISEN3-
ISEN4-
TCOMP
REF
DAC
OVP
FS
OFS
DRIVER
HIP6601B
PVCC
ENLL
VTTPWRGD
IDROOP
HIP6601B
ISL6561
5
Typical Application - 4-Phase Buck Converter with DCR Sensing and Internal P TC
VID3
+5V
PWM
VCC BOOT
UGATE
PHASE
LGATE
GND
+12V
DRIVER
VIN
PWM
VCC BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
VID4
PGOOD
VID2
VID1
VID0
VSEN
VDIFF
FB
COMP
VCC
GND
RGND
EN
ISEN1+
PWM1
PWM2
ISEN2+
PWM3
ISEN3+
PWM4
ISEN4+
ISL6561
µP
LOAD
VID12.5
ISEN1-
ISEN2-
ISEN3-
ISEN4-
TCOMP
REF
DAC
OVP
FS
OFS
DRIVER
HIP6601B
PVCC
ENLL
VTTPWRGD
IDROOP
HIP6601B
ISL6561
Typical Application - 4-Phase Buck Converter with DCR Sensing and Ext ernal NTC
VID3
+5V
PWM
VCC BOOT
UGATE
PHASE
LGATE
GND
+12V
VIN
PWM
VCC BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601A
DRIVER
VIN
VID4
PGOOD
VID2
VID1
VID0
VSEN
VDIFF
FB COMP
VCC
GND
RGND
EN
ISEN1+
PWM1
PWM2
ISEN2+
PWM3
ISEN3+
PWM4
ISEN4+
ISL6561
µP
LOAD
VID12.5
ISEN1-
ISEN2-
ISEN3-
ISEN4-
TCOMP
REF
DAC
OVP
NTC
NETWORK
FS
OFS
DRIVER
HIP6601B
PVCC
ENLL
VTTPWRGD
IDROOP
HIP6601B
DRIVER
ISL6561
7
ISL6561
OFS
The OFS pin provides a progra mmable means to introduce a
DC offset voltage to the DAC reference. The offset is gener-
ated via an external resistor and precision internal voltage
references. The polarity of the offset is selected by connect-
ing the resistor to GND or VCC. For no offset, the OFS pin
should be left un terminate d. The curr ent which f lows th rough
the resistor is output on the FB pin. The magnitude of the off-
set is determined by the reference voltage and the ratio of the
OFS prog ramming resisto r to the DC imp edance from V DIFF
to FB . OF S is intend ed fo r intro ducin g offs ets in a range with-
in ±50mV of the DAC setting.
OVP
A latched ov er-v olt age ind ic ato r. O nce trip ped OVP remain s
set until power is cycl ed.
TABLE 1. VOLTAGE IDENTIFICATION CODES
VID4 VID3 VID2 VID1 VID0 VID12.5 VDAC
0 1 0 1 0 0 0.8375V
0 1 0 0 1 1 0.8500V
0 1 0 0 1 0 0.8625V
0 1 0 0 0 1 0.8750V
0 1 0 0 0 0 0.8875V
0 0 1 1 1 1 0.9000V
0 0 1 1 1 0 0.9125V
0 0 1 1 0 1 0.9250V
0 0 1 1 0 0 0.9375V
0 0 1 0 1 1 0.9500V
0 0 1 0 1 0 0.9625V
0 0 1 0 0 1 0.975V0
0 0 1 0 0 0 0.9875V
0 0 0 1 1 1 1.0000V
0 0 0 1 1 0 1.0125V
0 0 0 1 0 1 1.0250v
0 0 0 1 0 0 1.0375V
0 0 0 0 1 1 1.0500V
0 0 0 0 1 0 1.0625V
0 0 0 0 0 1 1.0750V
0 0 0 0 0 0 1.0875V
1111 1 1 OFF
1111 1 0 OFF
1 1 1 1 0 1 1.1000V
1 1 1 1 0 0 1.1125V
1 1 1 0 1 1 1.1250V
1 1 1 0 1 0 1.1375V
1 1 1 0 0 1 1.1500V
1 1 1 0 0 0 1.1625V
1 1 0 1 1 1 1.1750V
1 1 0 1 1 0 1.1875V
1 1 0 1 0 1 1.2000V
1 1 0 1 0 0 1.2125V
1 1 0 0 1 1 1.2250V
1 1 0 0 1 0 1.2375V
1 1 0 0 0 1 1.2500V
1 1 0 0 0 0 1.2625V
1 0 1 1 1 1 1.2750V
1 0 1 1 1 0 1.2875V
1 0 1 1 0 1 1.3000V
1 0 1 1 0 0 1.3125V
1 0 1 0 1 1 1.3250V
1 0 1 0 1 0 1.3375V
1 0 1 0 0 1 1.3500V
1 0 1 0 0 0 1.3625V
1 0 0 1 1 1 1.3750V
1 0 0 1 1 0 1.3875V
1 0 0 1 0 1 1.4000V
1 0 0 1 0 0 1.4125V
1 0 0 0 1 1 1.4250V
1 0 0 0 1 0 1.4375V
1 0 0 0 0 1 1.4500V
1 0 0 0 0 0 1.4625V
0 1 1 1 1 1 1.4750V
0 1 1 1 1 0 1.4875V
0 1 1 1 0 1 1.5000V
0 1 1 1 0 0 1.5125V
0 1 1 0 1 1 1.5250V
0 1 1 0 1 0 1.5375V
0 1 1 0 0 0 1.5625V
0 1 0 1 1 1 1.5750V
0 1 0 1 1 0 1.5875V
0 1 0 1 0 1 1.600V
TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued)
VID4 VID3 VID2 VID1 VID0 VID12.5 VDAC
8
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiari es.
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ISL6561
Quad Flat No-Le ad Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP) L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDE C MO-220V JJD-2 ISSUE C)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.18 0.23 0.30 5, 8
D 6.00 BSC -
D1 5.75 BSC 9
D2 3.95 4.10 4.25 7, 8
E 6.00 BSC -
E1 5.75 BSC 9
E2 3.95 4. 10 4.25 7, 8
e 0.50 BSC -
k0.25 - - -
L 0.30 0.40 0.50 8
L1 - - 0.15 10
N402
Nd 10 3
Ne 10 3
P- -0.609
θ--129
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to t he metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is opti onal, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
