Single-Lead, Heart Rate Monitor Front End
Data Sheet
AD8232
Rev. C Document Feedback
Information
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FEATURES
Fully integrated single-lead ECG front end
Low supply current: 170 µA (typical)
Common-mode rejection ratio: 80 dB (dc to 60 Hz)
Two or three electrode configurations
High signal gain (G = 100) with dc blocking capabilities
2-pole adjustable high-pass filter
Accepts up to ±300 mV of half cell potential
Fast restore feature improves filter settling
Uncommitted op amp
3-pole adjustable low-pass filter with adjustable gain
Leads off detection: ac or dc options
Integrated right leg drive (RLD) amplifier
Single-supply operation: 2.0 V to 3.5 V
Integrated reference buffer generates virtual ground
Rail-to-rail output
Internal RFI filter
8 kV HBM ESD rating
Shutdown pin
20-lead 4 mm × 4 mm LFCSP package
APPLICATIONS
Fitness and activity heart rate monitors
Portable ECG
Remote health monitors
Gaming peripherals
Biopotential signal acquisition
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD8232 is an integrated signal conditioning block for ECG
and other biopotential measurement applications. It is designed
to extract, amplify, and filter small biopotential signals in the
presence of noisy conditions, such as those created by motion or
remote electrode placement. This design allows for an ultralow
power analog-to-digital converter (ADC) or an embedded
microcontroller to acquire the output signal easily.
The AD8232 can implement a two-pole high-pass filter for
eliminating motion artifacts and the electrode half-cell potential.
This filter is tightly coupled with the instrumentation architec-
ture of the amplifier to allow both large gain and high-pass
filtering in a single stage, thereby saving space and cost.
An uncommitted operational amplifier enables the AD8232 to
create a three-pole low-pass filter to remove additional noise.
The user can select the frequency cutoff of all filters to suit
different types of applications.
To improve common-mode rejection of the line frequencies in
the system and other undesired interferences, the AD8232
includes an amplifier for driven lead applications, such as right
leg drive (RLD).
The AD8232 includes a fast restore function that reduces the
duration of otherwise long settling tails of the high-pass filters.
After an abrupt signal change that rails the amplifier (such as a
leads off condition), the AD8232 automatically adjusts to a
higher filter cutoff. This feature allows the AD8232 to recover
quickly, and therefore, to take valid measurements soon after
connecting the electrodes to the subject.
The AD8232 is available in a 4 mm × 4 mm, 20-lead LFCSP
package. Performance is specified from 0°C to 70°C and is
operational from −40°C to +85°C.
LOD–
LOD+
AD8232
+V
S
GND
OUT
OPAMP–REFOUT
OPAMP+
SW
REFINIAOUT
HPSENSE
HPDRIVE
+IN
–IN
RLD
RLDFB
FR
SDN
AC/DC
LEADS-OFF
DETECTION
10kΩ
10kΩ
150kΩ
S1
S2
20
2
1
3
4
19 18 17 16
15
IA
A3
5
6 7 8 9
A1
10
A2
14
13
12
11
10866-001
C2
C1
AD8232 Data Sheet
Rev. C | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Instrumentation Amplifier Performance Curves ..................... 7
Operational Amplifier Performance Curves .......................... 10
Right Leg Drive (RLD) Amplifier Performance Curves ....... 13
Reference Buffer Performance Curves .................................... 14
System Performance Curves ..................................................... 15
Theory of Operation ...................................................................... 16
Architecture Overview .............................................................. 16
Instrumentation Amplifier ........................................................ 16
Operational Amplifier ............................................................... 16
Right Leg Drive Amplifier ......................................................... 17
Reference Buffer ......................................................................... 17
Fast Restore Circuit .................................................................... 17
Leads Off Detection ................................................................... 18
Standby Operation ..................................................................... 19
Input Protection ......................................................................... 19
Radio Frequency Interference (RFI) ........................................ 20
Power Supply Regulation and Bypassing ................................ 20
Input Referred Offsets ............................................................... 20
Layout Recommendations ........................................................ 20
Applications Information .............................................................. 21
Eliminating Electrode Offsets .................................................. 21
High-Pass Filtering .................................................................... 21
Low-Pass Filtering and Gain ..................................................... 23
Driving Analog-to-Digital Converters .................................... 23
Driven Electrode ........................................................................ 23
Application Circuits ....................................................................... 24
Heart Rate Measurement Next to the Heart ........................... 24
Exercise Application: Heart Rate Measured at the Hands .... 24
Cardiac Monitor Configuration ............................................... 25
Portable Cardiac Monitor with Elimination of Motion
Artifacts ....................................................................................... 25
Packaging and Ordering Information ......................................... 27
Outline Dimensions ................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
6/2018—Rev. B to Rev. C
Changes to Figure 24 ...................................................................... 10
Changes to Radio Frequency Interference (RFI) Section ......... 20
Updated Outline Dimensions ....................................................... 27
3/2017—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
2/2013—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 6
Change to Figure 17 ......................................................................... 9
Changes to Figure 22 and Figure 25............................................. 11
Changes to Figure 34 and Figure 36............................................. 14
Changes to Figure 45, Architecture Overview Section, and
Instrumentation Amplifier Section .............................................. 17
Changes to Right Leg Drive Amplifier Section, Reference Buffer
Section, Fast Restore Circuit Section, and Figure 48; Added
Figure 46, Renumbered Sequentially ........................................... 18
Changes to Figure 49...................................................................... 19
Changes to AC Leads Off Detection Section and Standby
Operation Section........................................................................... 20
Changes to Input Referred Offsets Section ................................. 21
Changes to Figure 53 and High-Pass Filtering Section ............. 22
Changes to Additional High-Pass Filtering Options Section;
Added Table 4 ................................................................................. 23
Changes to Low-Pass Filtering and Gain Section; Added Driving
Analog-to-Digital Converters Section and Figure 61................ 24
Changes to Figure 62, Figure 64, and Heart Rate Measurement
Next to the Heart Section .............................................................. 25
Changes to Exercise Application: Heart Rate Measured at the
Hands and Figure 66 ...................................................................... 26
Changes to Figure 68...................................................................... 27
8/2012—Revision 0: Initial Version
Data Sheet AD8232
Rev. C | Page 3 of 28
SPECIFICATIONS
VS = 3 V, V REF = 1.5 V, VCM = 1.5 V, TA = 25°C, FR=low, SDN=high, AC/DC = low, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INSTRUMENTATION AMPLIFIER
Common-Mode Rejection Ratio,
DC to 60 Hz
CMRR VCM = 0.35 V to 2.85 V, VDIFF = 0 V 80 86 dB
VCM = 0.35 V to 2.85 V, VDIFF = ±0.3 V 80 dB
Power Supply Rejection Ratio PSRR VS = 2.0 V to 3.5 V 76 90 dB
Offset Voltage (RTI) VOS
Instrumentation Amplifier Inputs
3
8
mV
DC Blocking Input1 5 50 µV
Average Offset Drift
Instrumentation Amplifier Inputs 10 µV/°C
DC Blocking Input1 0.05 µV/°C
Input Bias Current IB 50 200 pA
TA = 0°C to 70°C 1 nA
Input Offset Current IOS 25 100 pA
TA = 0°C to 70°C 1 nA
Input Impedance
Differential 10||7.5 GΩ||pF
Common Mode 5||15 GΩ||pF
Input Voltage Noise (RTI)
Spectral Noise Density f = 1 kHz 100 nV/√Hz
Peak-to-Peak Voltage Noise f = 0.1 Hz to 10 Hz 12 µV p-p
f = 0.5 Hz to 40 Hz 14 µV p-p
Input Voltage Range TA = 0°C to 70°C 0.2 +VS V
DC Differential Input Range
V
DIFF
−300
+300
mV
Output
Output Swing RL = 50 kΩ 0.1 +VS − 0.1 V
Short-Circuit Current IOUT 6.3 mA
Gain AV 100 V/V
Gain Error VDIFF = 0 V 0.4 %
VDIFF = −300 mV to +300 mV 1 3.5 %
Average Gain Drift TA = 0°C to 70°C 12 ppm/°C
Bandwidth BW 2 kHz
RFI Filter Cutoff (Each Input) 1 MHz
OPERATIONAL AMPLIFIER (A1)
Offset Voltage VOS 1 5 mV
Average TC TA = 0°C to 70°C 5 µV/°C
Input Bias Current IB 100 pA
TA = 0°C to 70°C 1 nA
Input Offset Current IOS 100 pA
TA = 0°C to 70°C 1 nA
Input Voltage Range 0.1 +VS − 0.1 V
Common-Mode Rejection Ratio CMRR VCM = 0.5 V to 2.5 V 100 dB
Power Supply Rejection Ratio PSRR 100 dB
Large Signal Voltage Gain AVO 110 dB
Output Voltage Range RL = 50 kΩ 0.1 +VS − 0.1 V
Short-Circuit Current Limit
I
OUT
12
mA
Gain Bandwidth Product GBP 100 kHz
Slew Rate SR 0.02 V/µs
Voltage Noise Density (RTI) en f = 1 kHz 60 nV/√Hz
Peak-to-Peak Voltage Noise (RTI) en p-p f = 0.1 Hz to 10 Hz 6 µV p-p
f = 0.5 Hz to 40 Hz 8 µV p-p
AD8232 Data Sheet
Rev. C | Page 4 of 28
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
RIGHT LEG DRIVE AMPLIFIER (A2)
Output Swing RL = 50 kΩ 0.1 +VS − 0.1 V
Short-Circuit Current IOUT 11 mA
Integrator Input Resistor 120 150 180 kΩ
Gain Bandwidth Product GDP 100 kHz
REFERENCE BUFFER (A3)
Offset Error VOS RL > 50 kΩ 1 mV
Input Bias Current IB 100 pA
Short-Circuit Current Limit IOUT 12 mA
Voltage Range RL = 50 kΩ 0.1 +VS − 0.7 V
DC LEADS OFF COMPARATORS
Threshold Voltage +VS − 0.5 V
Hysteresis
60
mV
Propagation Delay 0.5 µs
AC LEADS OFF DETECTOR
Square Wave Frequency FAC 50 100 175 kHz
Square Wave Amplitude
I
AC
200
nA p-p
Impedance Threshold Between +IN and −IN 10 20 MΩ
Detection Delay 110 μs
FAST RESTORE CIRCUIT
Switches S1 and S2
On Resistance RON 8 10 12 kΩ
Off Leakage 100 pA
Window Comparator
Threshold Voltage From either rail 50 mV
Propagation Delay
2
µs
Switch Timing Characteristics
Feedback Recovery Switch On Time tSW1 110 ms
Filter Recovery Switch On Time tSW2 55 ms
Fast Restore Reset tRST 2 µs
LOGIC INTERFACE
Input Characteristics
Input Voltage (AC/DC and FR)
Low VIL 1.24 V
High
V
IH
1.35
V
Input Voltage (SDN)
Low VIL 2.1 V
High VIH 0.5 V
Output Characteristics LOD+ and LOD− terminals
Output Voltage
Low VOL 0.05 V
High VOH 2.95 V
SYSTEM SPECIFICATIONS
Quiescent Supply Current
170
230
µA
TA = 0°C to 70°C 210 µA
Shutdown Current 40 500 nA
TA = 0°C to 70°C 100 nA
Supply Range 2.0 3.5 V
Specified Temperature Range 0 70 °C
Operational Temperature Range −40 +85 °C
1 Offset referred to the input of the instrumentation amplifier inputs. See the Input Referred Offsets section for additional information.
Data Sheet AD8232
Rev. C | Page 5 of 28
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage 3.6 V
Output Short-Circuit Current Duration
Indefinite
Maximum Voltage, Any Terminal1 +VS + 0.3 V
Minimum Voltage, Any Terminal1 −0.3 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Maximum Junction Temperature 140°C
θJA Thermal Impedance2 48°C/W
θJC Thermal Impedance 4.4°C/W
ESD Rating
Human Body Model (HBM) 8 kV
Charged Device Model (FICDM) 1.25 kV
Machine Model (MM) 200 V
1 This level or the maximum specified supply voltage, whichever is the lesser,
indicates the superior voltage limit for any terminal. If input voltages beyond
the specified minimum or maximum voltages are expected, place resistors in
series with the inputs to limit the current to less than 5 mA.
2 θJA is specified for a device in free air on a 4-layer JEDEC board.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD8232 Data Sheet
Rev. C | Page 6 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 HPDRIVE High-Pass Driver Output. Connect HPDRIVE to the capacitor in the first high-pass filter. The AD8232 drives this pin
to keep HPSENSE at the same level as the reference voltage.
2 +IN Instrumentation Amplifier Positive Input. +IN is typically connected to the left arm (LA) electrode.
3 −IN Instrumentation Amplifier Negative Input. −IN is typically connected to the right arm (RA) electrode.
4 RLDFB Right Leg Drive Feedback Input. RLDFB is the feedback terminal for the right leg drive circuit.
5 RLD Right Leg Drive Output. Connect the driven electrode (typically, right leg) to the RLD pin.
6
SW
Fast Restore Switch Terminal. Connect this terminal to the output of the second high-pass filter.
7 OPAMP+ Operational Amplifier Noninverting Input.
8 REFOUT Reference Buffer Output. The instrumentation amplifier output is referenced to this potential. Use REFOUT as a
virtual ground for any point in the circuit that needs a signal reference.
9 OPAMP− Operational Amplifier Inverting Input.
10 OUT Operational Amplifier Output. The fully conditioned heart rate signal is present at this output. OUT can be
connected to the input of an ADC.
11 LOD− Leads Off Comparator Output. In dc leads off detection mode, LOD− is high when the electrode to −IN is
disconnected, and it is low when connected. In ac leads off detection mode, LOD− is always low.
12 LOD+ Leads Off Comparator Output. In dc leads off detection mode, LOD+ is high when the +IN electrode is
disconnected, and it is low when connected. In ac leads off detection mode, LOD+ is high when either the −IN
or +IN electrode is disconnected, and it is low when both electrodes are connected.
13 SDN Shutdown Control Input. Drive SDN low to enter the low power shutdown mode.
14 AC/DC Leads Off Mode Control Input. Drive the AC/DC pin low for dc leads off mode. Drive the AC/DC pin high for ac leads
off mode.
15 FR Fast Restore Control Input. Drive FR high to enable fast recovery mode; otherwise, drive it low.
16 GND Power Supply Ground.
17 +VS Power Supply Terminal.
18
REFIN
Reference Buffer Input. Use REFIN, a high impedance input terminal, to set the level of the reference buffer.
19 IAOUT Instrumentation Amplifier Output Terminal.
20 HPSENSE High-Pass Sense Input for Instrumentation Amplifier. Connect HPSENSE to the junction of R and C that sets the
corner frequency of the dc blocking circuit.
EP Exposed Pad. Connect the exposed pad to GND or leave it unconnected.
14
13
12
1
3
4
AC/DC
15 FR
SDN
LOD+
11 LOD–
HPDRIVE
–IN 2
+IN
RLDFB 5RLD
7
OPAMP+ 6SW
8REFOUT 9OPAMP– 10OUT
19 IAOUT
20 HPSENSE
18 REFIN
17 +V
S
16 GND
AD8232
TOP VIEW
(No t t o Scal e)
NOTES
1. CO NNE CT T HE E X P OSED P AD TO GND OR
LE AVE UNCONNECTED.
10866-002
Data Sheet AD8232
Rev. C | Page 7 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 3 V, VREF = 1.5 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.
INSTRUMENTATION AMPLIFIER PERFORMANCE CURVES
Figure 3. Instrumentation Amplifier CMRR Distribution
Figure 4. Instrumentation Amplifier Gain Error Distribution
Figure 5. Instrumentation Amplifier
Input Common-Mode Range vs. Output Voltage
Figure 6. Instrumentation Amplifier Input Bias Current vs. CMV
Figure 7. Instrumentation Amplifier Gain vs. Frequency
Figure 8. Instrumentation Amplifier CMRR vs. Frequency, RTI
1200
1000
200
400
600
800
0
–120 –90 9060300–60 –30 120
UNITS
CMRR ( µV/V)
10866-003
1400
1200
1000
200
400
600
800
0
–2.0 –1.5 1.51.00.50–1.0 –0.5 2.0
UNITS
GAIN ERROR (%)
10866-004
3.5
3.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
00.51.0 3.53.02.52.01.5
INPUT COMMON-M ODE VO LTAGE (V)
OUTPUT VOLTAGE (V)
10866-005
50
–50 00.51.0 3.53.02.52.01.5
INP UT BI AS CURRE N T ( pA)
INPUT COMMON-MODE VOLT AGE (V)
–40
–30
–20
–10
0
10
20
30
40
10866-006
50
40
30
20
10
0
–10 1100k10k1k10010
GAIN (dB)
FREQUENCY (Hz)
NO DC O FF S E T
300mV O F FSET
10866-007
120
100
40
60
80
2010 100k10k1k100
CMRR (dB)
FREQUENCY (Hz)
NO DC O FF S E T
+300mV O FFSET
–300mV OF FSET
10866-008
AD8232 Data Sheet
Rev. C | Page 8 of 28
Figure 9. Instrumentation Amplifier PSRR vs. Frequency
Figure 10. Instrumentation Amplifier Voltage Noise Spectral Density (RTI)
Figure 11. Instrumentation Amplifier 0.1 Hz to 10 Hz Noise
Figure 12. Instrumentation Amplifier 0.5 Hz to 40 Hz Noise
Figure 13. Instrumentation Amplifier Gain Error vs. DC Offset
Figure 14. Instrumentation Amplifier Small Signal Pulse Response
120
20
0.1 1 10 100k10k1k100
PSRR (dB)
FREQUENCY (Hz)
30
40
50
60
70
80
90
100
110
10866-009
10k
1k
100
1
0.1 1 10 100k10k1k100
NOISE (nV/√Hz)
FREQUENCY (Hz)
10866-010
10µV/DIV
1s/DIV
10866-011
10µV/DIV
200ms/DIV
10866-012
1.0
0
050 300250200150100
GAIN ERROR (%)
DC OFFSET (mV)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
10866-013
50mV/DIV100µs/DIV
22pF
470pF
1nF
10866-014
Data Sheet AD8232
Rev. C | Page 9 of 28
Figure 15. Instrumentation Amplifier Large Signal Pulse Response
Figure 16. Instrumentation Amplifier Output Swing vs. Load
Figure 17. Instrumentation Amplifier DC Blocking Input Offset Drift
Figure 18. Instrumentation Amplifier
Input Bias Current and Input Offset Current vs. Temperature
Figure 19. Instrumentation Amplifier Gain Error vs. Temperature
Figure 20. Instrumentation Amplifier CMRR vs. Temperature
100µs/DIV0.5V/DIV
10866-015
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
100 1M100k10k1k
OUTPUT SWING (V)
LOAD (Ω)
–40-°C
+25°C
+85°C
10866-016
0.4
–0.4
–40–20 0 204060 10080
DC BLOCKING INPUT OFFSET (mV)
TEMPERATURE (°C)
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
10866-017
4.0
–1.0
–40 –20 –0 20 40 60 80 100
INPUT BIAS CURRENT (nA)
INPUT OFFSET CURRENT (nA)
TEMPERATURE (°C)
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
I
B
I
OS
10866-018
0.5
–0.5
–40 –20 0 10080604020
GAIN ERROR (%)
TEMPERATURE (°C)
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
10866-019
50
–50
–40 –20 0 10080604020
CMRR (µV/V)
TEMPERATURE (°C)
–40
–30
–20
–10
0
10
20
30
40
10866-020
AD8232 Data Sheet
Rev. C | Page 10 of 28
OPERATIONAL AMPLIFIER PERFORMANCE CURVES
Figure 21. Operational Amplifier Offset Distribution
Figure 22. Operational Amplifier Open-Loop Gain and Phase vs.
Frequency
Figure 23. Operational Amplifier Small Signal Response for
Various Capacitive Loads
Figure 24. Operational Amplifier Large Signal Transient Response
Figure 25. Operational Amplifier Voltage Spectral Noise Density vs. Frequency
Figure 26. Operational Amplifier 0.1 Hz to 10 Hz Noise
1000
200
400
600
800
0
–4 –2 0 42
UNITS
OFFSET VOLTAGE (mV)
10866-021
140
–40
180
0
0.1 1M100k10k1k100101
GAIN (dB)
PHASE MARGIN (Degrees)
FREQUENCY (Hz)
20
40
60
80
100
120
140
160
–20
0
20
40
60
80
100
120
GAIN
PHASE MARGIN
10866-022
50mV/DIV10µS/DIV
22pF
470pF
1nF
10866-023
100µs/DIV 0.5V/DIV
10866-024
10k
1k
100
10
0.1 1 10 100k10k1k100
NOISE (nV/√Hz)
FREQUENCY (Hz)
10866-025
5µV/DIV
1s/DIV
10866-026
Data Sheet AD8232
Rev. C | Page 11 of 28
Figure 27. Operational Amplifier 0.5 Hz to 40 Hz Noise
Figure 28. Operational Amplifier Bias Current vs. Input
Common-Mode Voltage
Figure 29. Operational Amplifier Output Voltage Swing vs.
Output Current
Figure 30. Operational Amplifier Power Supply Rejection Ratio
Figure 31. Operational Amplifier Load Transient Response
(100 μA Load Change)
Figure 32. Operational Amplifier Offset vs. Temperature
5µV/DIV
200ms/DIV
10866-027
100
–100
03.5
INPUT BIAS CURRENT (pA)
INPUT COMMON-MODE VOLTAGE (V)
–80
–60
–40
–20
0
20
40
60
80
0.5 1.0 1.5 2.0 2.5 3.0
10866-028
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
100 1M100k10k1k
OUTPUT SWING (V)
LOAD (Ω)
–40-°C
+25°C
+85°C
10866-029
120
0
10
20
0.1 1 10 100k10k1k100
PSRR (dB)
FREQUENCY (Hz)
30
40
50
60
70
80
90
100
110
10866-030
20V/DIV
10µV/DIV
10866-031
0.8
–0.8
–40–20 0 204060 10080
OFFSET (mV)
TEMPERATURE (°C)
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
10866-032
AD8232 Data Sheet
Rev. C | Page 12 of 28
Figure 33. Operational Amplifier Bias Current vs. Temperature
10,000
1,000
100
10
1
–40 100
INPUT BI AS CURRE NT (p A)
TEMPERATURE (°C)
–20 020 40 60 80
10866-033
Data Sheet AD8232
Rev. C | Page 13 of 28
RIGHT LEG DRIVE (RLD) AMPLIFIER PERFORMANCE CURVES
Figure 34. RLD Amplifier Open-Loop Gain and Phase vs.
Frequency
Figure 35. RLD Amplifier Output Voltage Swing vs.
Output Current
Figure 36. RLD Amplifier Voltage Spectral Noise Density vs. Frequency
Figure 37. RLD Amplifier 0.1 Hz to 10 Hz Noise
Figure 38. RLD Amplifier 0.5 Hz to 40 Hz Noise
140
–40
180
0
0.01 1M100k10k1k1001010.1
OPEN-LOOP GAIN (dB)
PHASE (Degrees)
FREQUENCY (Hz)
20
40
60
80
100
120
140
160
–20
0
20
40
60
80
100
120
10866-034
GAIN
PHASE
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
100 1M100k10k1k
OUTPUT SWING (V)
LOAD (Ω)
–40-°C
+25°C
+85°C
10866-035
10k
1k
100
10
0.1 1 10 100k10k1k100
NOISE (nV/√Hz)
FREQUENCY (Hz)
10866-036
5µV/DIV
1s/DIV
10866-037
5µV/DIV
200ms/DIV
10866-038
AD8232 Data Sheet
Rev. C | Page 14 of 28
REFERENCE BUFFER PERFORMANCE CURVES
Figure 39. Reference Buffer Load Regulation
Figure 40. Reference Buffer
Load Transient Response (100 μA Load Change)
Figure 41. Reference Buffer Output Impedance vs.
Frequency
Figure 42. Reference Buffer Bias Current vs. Temperature
20
–20
0.01 1010.10
OUTPUT ERROR (mV)
LOAD CURRENT (mA)
10866-039
–15
–10
–5
0
5
10
15
SOURCE
SINK
20mV/DIV
10µs/DIV
10866-040
10,000.0
1,000.0
1.0
10.0
100.0
0.1
0.1 1 10 100k10k1k100
OUTPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
10866-041
1000
100
10
1
–40 100
INPUT BIAS CURRENT (pA)
TEMPERATURE (°C)
10866-042
–20 200 406080
Data Sheet AD8232
Rev. C | Page 15 of 28
SYSTEM PERFORMANCE CURVES
Figure 43. Supply Current vs. Temperature
Figure 44. Shutdown Current vs. Temperature
240
100
–40 100
SUPPLY CURRE NT (µ A)
TEMPERATURE (°C)
10866-043
–20 20040 60 80
120
140
160
180
200
220
V
S
= 2V
V
S
= 3V
V
S
= 3.5V
200
0
–40 100
SHUT DO WN CURRENT (nA)
TEMPERATURE (°C)
10866-044
–20 20040 60 80
V
S
= 2V
V
S
= 3V
V
S
= 3.5V
20
40
60
80
100
120
140
160
180
AD8232 Data Sheet
Rev. C | Page 16 of 28
THEORY OF OPERATION
Figure 45. Simplified Schematic Diagram
ARCHITECTURE OVERVIEW
The AD8232 is an integrated front end for signal conditioning
of cardiac biopotentials for heart rate monitoring. It consists of
a specialized instrumentation amplifier (IA), an operational
amplifier (A1), a right leg drive amplifier (A2), and a midsupply
reference buffer (A3). In addition, the AD8232 includes leads
off detection circuitry and an automatic fast restore circuit that
brings back the signal shortly after leads are reconnected.
The AD8232 contains a specialized instrumentation amplifier
that amplifies the ECG signal while rejecting the electrode half-cell
potential on the same stage. This is possible with an indirect
current feedback architecture, which reduces size and power
compared with traditional implementations
INSTRUMENTATION AMPLIFIER
The instrumentation amplifier is shown in Figure 45 as
comprised by two well-matched transconductance amplifiers
(GM1 and GM2), the dc blocking amplifier (HPA), and an
integrator formed by C1 and an op amp. The transconductance
amplifier, GM1, generates a current that is proportional to the
voltage present at its inputs. When the feedback is satisfied, an
equal voltage appears across the inputs of the transconductance
amplifier, GM2, thereby matching the current generated by
GM1. The difference generates an error current that is
integrated across Capacitor C1. The resulting voltage appears at
the output of the instrumentation amplifier.
The feedback of the amplifier is applied via GM2 through two
separate paths: the two resistors divide the output signal to set
an overall gain of 100, whereas the dc blocking amplifier integrates
any deviation from the reference level. Consequently, dc offsets
as large as ±300 mV across the GM1 inputs appear inverted and
with the same magnitude across the inputs of GM2, all without
saturating the signal of interest.
To increase the common-mode voltage range of the instrumen-
tation amplifier, a charge pump boosts the supply voltage for the
two transconductance amplifiers. This further prevents saturation
of the amplifier in the presence of large common-mode signals,
such as line interference. The charge pump runs from an internal
oscillator, the frequency of which is set around 500 kHz.
OPERATIONAL AMPLIFIER
This general-purpose operational amplifier (A1) is a rail-to-rail
device that can be used for low-pass filtering and to add additional
gain. The following sections provide details and example circuits
that use this amplifier.
10kΩ
IAOUTHPSENSEHPDRIVE
S1
GM1 GM2
99R
R
+V
S
0.7V
INSTRUMENTATION AMPLIFIER (IA)
+V – 0.05V
S
0.05V
REFOUTREFIN
–IN
+IN FR
V
CM
C1
LOD+
LOD–
+V – 0.5V
S
SW OP
A
MP+ OPAMP–
OUT
RLD
RLDFB
GND
150kΩ
10kΩ
HPA
+V
S
= REFOUT
CHARGE
PUMP
SYNCH
RECTIFIER
SWITCH
TIMING
A3
A2
A1
AC/DC
AC/DC
AC/DC
AC/DC
SDN
S1
S2
S2
19
2
3
4
5
18
6 7 9
10
120
15
14
13
11
12
17
16
8
*ALL SWITCHES SHOWN IN DC LEADS-OFF DETECTION POSITION AND FAST RESTORE DISABLED
10866-045
RFI
FILTER
Data Sheet AD8232
Rev. C | Page 17 of 28
RIGHT LEG DRIVE AMPLIFIER
The right leg drive (RLD) amplifier inverts the common-mode
signal that is present at the instrumentation amplifier inputs.
When the right leg drive output current is injected into the
subject, it counteracts common-mode voltage variations, thus
improving the common-mode rejection of the system.
The common-mode signal that is present across the inputs of
the instrumentation amplifier is derived from the transconduct-
ance amplifier, GM1. It is then connected to the inverting input
of A2 through a 150 kΩ resistor.
An integrator can be built by connecting a capacitor between the
RLD FB and RLD terminals. A good starting point is a 1 nF
capacitor, which places the crossover frequency at about 1 kHz
(the frequency at which the amplifier has an inverting unity
gain). This configuration results in about 26 dB of loop gain
available at a frequency range from 50 Hz to 60 Hz for
common-mode line rejection. Higher capacitor values reduce
the crossover frequency, thereby reducing the gain that is
available for rejection and, consequently, increasing the line
noise. Lower capacitor values move the crossover frequency to
higher frequencies, allowing increased gain. The tradeoff is that
with higher gain, the system can become unstable and saturate
the output of the right leg amplifier.
Note that when using this amplifier to drive an electrode, there
should be a resistor in series with the output to limit the current
to be always less than 10 μA even in fault conditions. For
example, if the supply used is 3.0 V, this resistor should be
greater than 330 kΩ to account for component and supply
variations.
Figure 46. Typical Configuration of Right-Leg Drive Circuit
In two-electrode configurations, RLD can be used to bias the
inputs through 10 MΩ resistors as described in the Leads Off
Detection section. If left unused, it is recommended to configure
A2 as a follower by connecting RLDFB directly to RLD.
REFERENCE BUFFER
The AD8232 operates from a single supply. To simplify the
design of single-supply applications, the AD8232 includes a
reference buffer to create a virtual ground between the supply
voltage and the system ground. The signals present at the out-
put of the instrumentation amplifier are referenced around this
voltage. For example, if there is zero differential input voltage,
the voltage at the output of the instrumentation amplifier is this
reference voltage.
The reference voltage level is set at the REFIN pin. It can be set
with a voltage divider or by driving the REFIN pin from some
other point in the circuit (for example, from the ADC reference).
The voltage is available at the REFOUT pin for the filtering
circuits or for an ADC input.
Figure 47. Setting the Internal Reference
To limit the power consumption of the voltage divider, the use
of large resistors is recommended, such as 10 MΩ. The designer
must keep in mind that high resistor values make it easier for
interfering signals to appear at the input of the reference buffer.
To minimize noise pickup, it is recommended to place the resistors
close to each other and as near as possible to the REFIN terminal.
Furthermore, use a capacitor in parallel with the lower resistor
on the divider for additional filtering, as shown in Figure 47.
Keep in mind that a large capacitor results in better noise
filtering but it takes longer to settle the reference after power-up.
The total time it takes the reference to settle within 1% can be
estimated with the formula
R2R1
C1R2R1
tREFERENCESETTLE
5
_
Note that disabling the AD8232 with the shutdown terminal
does not discharge this capacitor.
FAST RESTORE CIRCUIT
Because of the low cutoff frequency used in high-pass filters in
ECG applications, signals may require several seconds to settle.
This settling time can result in a frustrating delay for the user
after a step response: for example, when the electrodes are first
connected.
This fast restore function is implemented internally, as shown in
Figure 48. The output of the instrumentation amplifier is connec-
ted to a window comparator. The window comparator detects a
saturation condition at the output of the instrumentation amplifier
when its voltage approaches 50 mV from either supply rail.
Figure 48. Fast Restore Circuit
RLD
1nF
R*
*LIMIT CURRENT TO LESS THAN 10µA.
RLDFB
A2
REFOUT
TO DRIVEN
ELECTRODE
150kΩV
CM
185
4
10866-146
REFIN A3
18
R
1
R
2
C
1
+V
S
10866-046
SWITCH
TIMING
S1
S2
LOD+
LOD–
FR
15
IAOUT
0.05V
+IN
–IN
IA
2
3
+V
S
– 0.05V
10866-047
AD8232 Data Sheet
Rev. C | Page 18 of 28
Figure 49. Timing Diagram for Fast Restore Switches
(Time Base Not to Scale)
If this saturation condition is present when both input electrodes
are attached to the subject, the comparator triggers a timing
circuit that automatically closes Switch S1 and Switch S2 (see
Figure 49 for a timing diagram).
These two switches (S1 and S2) enable two different 10 kΩ
resistor paths: one between HPSENSE and IAOUT and another
between SW and REFOUT. During the time Switch S1 and
Switch S2 are enabled, these internal resistors appear in parallel
with their corresponding external resistors forming high-pass
filters. The result is that the equivalent lower resistance shifts
the pole to a higher frequency, delivering a quicker settling
time. Note that the fast restore settling time depends on how
quickly the internal 10 kΩ resistors of the AD8232 can drain the
capacitors in the high-pass circuit. Smaller capacitor values
result in a shorter settling time.
If, by the end of the timing, the saturation condition persists,
the cycle repeats. Otherwise, the AD8232 returns to its normal
operation. If either of the leads off comparator outputs is indi-
cating that an electrode has been disconnected, the timing
circuit is prevented from triggering because it is assumed that
no valid signal is present. To disable fast restore, drive the FR
pin low or tie it permanently to GND.
LEADS OFF DETECTION
The AD8232 includes leads off detection. It features ac and dc
detection modes optimized for either two- or three-electrode
configurations, respectively.
DC Leads Off Detection
The dc leads off detection mode is used in three-electrode con-
figurations only. It works by sensing when either instrumentation
amplifier input voltage is within 0.5 V from the positive rail. In
this case, each input must have a pull-up resistor connected to the
positive supply. During normal operation, the subject’s potential
must be inside the common-mode range of the instrumentation
amplifier, which is only possible if a third electrode is connected
to the output of the right leg drive amplifier.
Figure 50. Circuit Configuration for DC Leads Off Detection
Because in dc leads off mode the AD8232 checks each input
individually, it is possible to indicate which electrode is discon-
nected. The AD8232 indicates which electrode is disconnected by
setting the corresponding LOD− or LOD+ pin high. To use this
mode, connect the AC/DC pin to ground.
LEADS OFF L E ADS ON
S1
S2
SAT URATION DET E CTED NO SATURAT ION
t
S1
t
S2
t
RST
10866-048
RLD
10MΩ 10MΩ
TO DRIVEN
ELECTRODE
IA
2
3
5
+VS
10866-049
Data Sheet AD8232
Rev. C | Page 19 of 28
AC Leads Off Detection
The ac leads off detection mode is useful when using two
electrodes only (it does not require the use of a driven electrode).
In this case, a conduction path must exist between the two
electrodes, which is usually formed by two resistors, as shown
in Figure 51.
These resistors also provide a path for bias return on each input.
Connect each resistor to REFOUT or RLD to maintain the inputs
within the common-mode range of the instrumentation
amplifier.
Figure 51. Circuit Configuration for AC Leads Off Detection
The AD8232 detects when an electrode is disconnected by
forcing a small 100 kHz current into the input terminals. This
current flows through the external resistors from IN+ to IN−
and develops a differential voltage across the inputs, which is
then synchronously detected and compared to an internal
threshold. The recommended value for these external resistors
is 10 MΩ. Low resistance values make the differential drop too
low to be detected and lower the input impedance of the
amplifier. When the electrodes are attached to the subject, the
impedance of this path should be less than 3 MΩ to maintain
the drop below the comparator’s threshold.
As opposed to the dc leads off detection mode, the AD8232 is
able to determine only that an electrode has lost its connection,
not which one. During such an event, the LOD+ pin goes high.
In this mode, the LOD− pin is not used and remains in a logic
low state. To use the ac leads off mode, tie the AC/DC pin to the
positive supply rail.
Note that while REFOUT is at a constant voltage value, using
the RLD output as the input bias may be more effective in
rejecting common-mode interference.
STANDBY OPERATION
The AD8232 includes a shutdown pin (SDN) that further
enhances the flexibility and ease of use in portable applications
where power consumption is critical. A logic level signal can be
applied to this pin to switch to shutdown mode, even when the
supply is still on.
Driving the SDN pin low places the AD8232 in shutdown mode
and draws less than 200 nA of supply current, offering
considerable power savings. To enter normal operation,
drive SDN high; when not using this feature, permanently
tie SDN to +VS.
During shutdown operation, the AD8232 is not able to
maintain the REFOUT voltage, but it does not drain the REFIN
voltage, thereby maintaining this additional conduction path
from the supply to ground.
When emerging from a shutdown condition, the charge stored
in the capacitors on the high-pass filters can saturate the instru-
mentation amplifier and subsequent stages. The use of the fast
restore feature helps reduce the recovery time and, therefore,
minimize on time in power sensitive applications.
INPUT PROTECTION
All terminals of the AD8232 are protected against ESD. In
addition, the input structure allows for dc overload conditions
that are a diode drop above the positive supply and a diode drop
below the negative supply. Voltages beyond a diode drop of the
supplies cause the ESD diodes to conduct and enable current to
flow through the diode. Therefore, use an external resistor in
series with each of the inputs to limit current for voltages
beyond the supplies. In either scenario, the AD8232 safely
handles a continuous 5 mA current at room temperature.
For applications where the AD8232 encounters extreme over-
load voltages, such as in cardiac defibrillators, use external series
resistors and gas discharge tubes (GDT). Neon lamps are com-
monly used as an inexpensive alternative to GDTs. These devices
can handle the application of large voltages but do not maintain
the voltage below the absolute maximum ratings for the AD8232.
A complete solution includes further clamping to either supply
using additional resistors and low leakage diode clamps, such as
BAV199 or FJH1100.
As a safety measure, place a resistor between the input pin and
the electrode that is connected to the subject to ensure that the
current flow never exceeds 10 µA. Calculate the value of this
resistor to be equal to the supply voltage across the AD8232
divided by 10 µA.
REFOUT
10MΩ 10MΩ
IA
2
3
17
8
+V
S
10866-050
AD8232 Data Sheet
Rev. C | Page 20 of 28
RADIO FREQUENCY INTERFERENCE (RFI)
Radio frequency (RF) rectification is often a problem in
applications where there are large RF signals. The problem
appears as a dc offset voltage at the output. The AD8232 has a
15 pF gate capacitance and 10 kΩ resistors at each input. This
forms a low-pass filter on each input that reduces rectification
at high frequency (see Figure 52) without the addition of
external elements.
Figure 52. RFI Filter Without External Capacitors
For increased filtering, additional resistors can be added in
series with each input. They must be placed as close as possible
to the instrumentation amplifier inputs. These can be the same
resistors used for overload and patient protection.
POWER SUPPLY REGULATION AND BYPASSING
The AD8232 is designed to be powered directly from a single
3 V battery, such as CR2032 type. It can also operate from
rechargeable lithium-ion batteries, but the designer must take
into account that the voltage during a charge cycle may exceed
the absolute maximum ratings of the AD8232. To avoid damage
to the part, use a power switch or a low power, low dropout
regulator, such as ADP150.
In addition, excessive noise on the supply pins can adversely
affect performance. As in all linear circuits, bypass capacitors
must be used to decouple the chip power supplies. Place a 0.1 μF
capacitor close to the supply pin. A 1 μF capacitor can be used
farther away from the part. In most cases, the capacitor can be
shared by other integrated circuits. Keep in mind that excessive
decoupling capacitance increases power dissipation during
power cycling.
INPUT REFERRED OFFSETS
Because of its internal architecture, the instrumentation amplifier
should be used always with the dc blocking amplifier, shown as
HPA in Figure 45.
As described in the Theory of Operation section, the dc blocking
amplifier attenuates the input referred offsets present at the
inputs of the instrumentation amplifier. However, this is true
only when the dc blocking amplifier is used as an integrator. In
this configuration, the input offsets from the dc blocking
amplifier dominate appear directly at the output of the
instrumentation amplifier.
If the dc blocking amplifier is used as a follower instead of its
intended function as an integrator, the input referred offsets of
the in-amp are amplified by a factor of 100.
LAYOUT RECOMMENDATIONS
It is important to follow good layout practices to optimize
system performance. In low power applications, most resistors
are of a high value to minimize additional supply current. The
challenge of using high value resistors is that high impedance
nodes become even more susceptible to noise pickup and board
parasitics, such as capacitance and surface leakages. Keep all of
the connections between high impedance nodes as short as
possible to avoid introducing additional noise and errors from
corrupting the signal.
To maintain high CMRR over frequency, keep the input traces
symmetrical and length matched. Place safety and input bias
resistors in the same position relative to each input. In addition,
the use of a ground plane significantly improves the noise
rejection of the system.
AD8232
C
G
C
G
IAOUT
+IN
–IN
10kΩ
10kΩ
10866-151
Data Sheet AD8232
Rev. C | Page 21 of 28
APPLICATIONS INFORMATION
ELIMINATING ELECTRODE OFFSETS
The instrumentation amplifier in the AD8232 is designed to
apply gain and to filter out near dc signals simultaneously. This
capability allows it to amplify a small ECG signal by a factor of
100 yet reject electrode offsets as large as ±300 mV.
To achieve offset rejection, connect an RC network between the
output of the instrumentation amplifier, HPSENSE, and
HPDRIVE, as shown in Figure 53.
Figure 53. Eliminating Electrode Offsets
This RC network forms an integrator that feeds any near dc signals
back into the instrumentation amplifier, thus eliminating the offsets
without saturating any node and maintaining high signal gain.
In addition to blocking offsets present across the inputs of the
instrumentation amplifier, this integrator also works as a high-
pass filter that minimizes the effect of slow moving signals, such
as baseline wander. The cutoff frequency of the filter is given by
the equation
RC
fdB
π
2
100
3=
−
where R is in ohms and C is in farads.
Note that the filter cutoff is 100 times higher than is typically
expected from a single-pole filter. Because of the feedback
architecture of the instrumentation amplifier, the typical filter
cutoff equation is modified by the gain of 100 of the
instrumentation amplifier.
Figure 54. Frequency Response of Single-Pole DC Blocking Circuit
Just like with any high-pass filter with low frequency cutoff, any
fast change in dc offset takes a long time to settle. If such change
saturates the instrumentation amplifier output, the S1 switch
briefly enables the 10 kΩ resistor path, thus moving the cutoff
frequency to
)10(2
)10(100
4
4
3RC
R
fdB
π
+
=
−
(1)
For values of R greater than 100 kΩ, the expression in Equation 1
can be approximated by
C
f
dB
π
200
1
3
=
−
This higher cutoff reduces the settling time and enables faster
recovery of the ECG signal. For more information, see the Fast
Restore Circuit section.
HIGH-PASS FILTERING
The AD8232 can implement higher order high-pass filters. A
higher filter order yields better artifact rejection but at a cost of
increased signal distortion and more passive components on the
printed circuit board (PCB).
Two-Pole High-Pass Filter
A two-pole architecture can be implemented by adding a simple
ac coupling RC at the output of the instrumentation amplifier,
as shown in Figure 55.
Figure 55. Schematic for a Two-Pole High-Pass Filter
Note that the right side of C2 connects to the SW terminal. Just
like S1, S2 reduces the recovery time for this ac coupling network
by placing 10 kΩ in parallel with R2. See the Fast Restore
Circuit section for additional details on switch timing and
trigger conditions.
Keep in mind that if this passive network is not buffered, it
exhibits higher output impedance at the input of a subsequent
low-pass filter, such as with Sallen-Key filter topologies. Careful
component selection can yield good results without a buffer. See
the Low-Pass Filtering and Gain section for additional
information on component selection.
10kΩ
IAOUTHPSENSEHPDRIVE
S1
GM1 GM2
99R
R
IN+
IN– V
CM
H
P
A
ELECTRODE
OFFSETS
CR
= REF OUT
19
3
1 20
2
C1
10866-253
50
40
10
20
30
0
0.01 1001010.1
MAG NITUDE ( dB)
FRE Q UE NCY ( Hz )
10866-153
20dB P ER
DECADE
10kΩ
IAOUTHPSENSEHPDRIVE
S1
+IN
–IN
HPA
SW
10kΩ
S2
6
REFOUT
8
TO NEXT
STAGE
= REF OUT
19
3
120
2
C1 C2
R1
R2
10866-053
AD8232 Data Sheet
Rev. C | Page 22 of 28
Additional High-Pass Filtering Options
In addition to the topologies explained in the previous sections,
an additional pole may be added to the dc blocking circuit for
additional rejection of low frequency signals. This configuration
is shown in Figure 56.
Figure 56. Schematic for an Alternative Two-Pole High-Pass Filter
An extra benefit of this circuit topology is that it allows lower
cutoff frequency with lower R and C values and the resistor,
RCOMP, can be used to control the Q of the filter to achieve narrow
band-pass filters (for heart rate detection) or maximum pass-
band flatness (for cardiac monitoring).
With this topology, the filter attenuation reverts to a single pole
roll off at very low frequencies. Because the initial roll off was 40 dB
per decade, this reversion to 20 dB per decade has little impact on
the ability of the filter to reject out-of-band low frequency signals.
The designer may choose different values to achieve the desired
filter performance. To simplify the design process, use the following
recommendations as a starting point for component value selection.
R1 = R2 ≥ 100 kΩ
C1 = C2
RCOMP = 0.14 × R1
The cutoff frequency is located at
C2R2C1R1
fC
π
2
10
=
The selection of RCOMP to be 0.14 times the value of the other two
resistors optimizes the filter for a maximally flat pass band. Reduce
its value to increase the Q and, consequently, the peaking of the
filter. Keep in mind that a very low value of RCOMP can result in
an unstable circuit. The selection of values based on these criteria
result in a transfer function similar to the one shown in Figure 58.
When additional low frequency rejection is desired, a high-order
high-pass filter can be implemented by adding an ac coupling
network at the output of the instrumentation amplifier, as shown in
Figure 57. The SW terminal is connected to the ac coupling network
to obtain the best settling time response when fast restore engages.
Figure 57. Schematic for a Three-Pole High-Pass Filter
Figure 58. Frequency Response of Circuits in Figure 56 and Figure 57
Careful analysis and adjustment of all of the component values
in practice is recommended to optimize the filter characteristics.
A useful hint is to reduce the value of RCOMP to increase the peaking
of the active filter to overcome the additional roll off introduced
by the ac coupling network. Proper adjustment can yield the
best pass-band flatness.
The design of the high-pass filter involves tradeoffs between signal
distortion, component count, low frequency rejection, and
component sizes. For example, a single-pole high-pass filter
results in the least distortion to the signal, but its rejection of
low-frequency artifacts is the lowest Table 4 compares the
recommended filtering options.
Table 4. Comparison of High-Pass Filtering Options
Filter Order Component Count Low Frequency Rejection Capacitor Sizes/Values Signal Distortion1 Output Impedance2
Figure 53 1 2 Good Large Low Low
Figure 55 2 4 Better Large Medium Higher
Figure 56 2 5 Better Smaller Medium Low
Figure 57 3 7 Best Smaller Highest Higher
1 For equivalent corner frequency location.
2 Output impedance refers to the drive capability of the high-pass filter before the low-pass filter. Low output impedance is desirable to allow flexibility in the selection
of values for a low-pass filter, as explained in the Low-Pass Filtering and Gain section.
10kΩ
IAOUT
HPSENSE
HPDRIVE
S1
+IN
–IN
HPA
SW
10kΩ
S2
6
REFOUT 8
TO NEXT
STAGE
= REF OUT
19
3
120
2
C1 R1 R2
RCOMP
C2
10866-155
10kΩ
IAOUTHPSENSE
HPDRIVE
S1
+IN
–IN
HPA
SW
10kΩ
S2
6
REFOUT
8
TO NEXT
STAGE
= REF OUT
19
3
120
2
C1 C3
R1 R2
R
COMP
C2 R3
10866-156
60
40
20
0
–20
–40
–60
0.01 1001010.1
MAGNIT UDE ( dB)
FREQUENCY ( Hz )
10866-157
THREE-POLE FILTER
TWO-POLE FILTER
40dB PE R
DECADE
40dB PE R
DECADE
20dB PE R
DECADE 60dB P E R
DECADE
Data Sheet AD8232
Rev. C | Page 23 of 28
LOW-PASS FILTERING AND GAIN
The AD8232 includes an uncommitted op amp that can be used
for extra gain and filtering. For applications that do not require
a high-order filter, a simple RC low-pass filter should suffice,
and the op amp can buffer or further amplify the signal.
Figure 59. Schematic for a Single-Pole Low-Pass Filter and Additional Gain
Applications that require a steeper roll off or a sharper cut off, a
Sallen-Key filter topology can be implemented, as shown in
Figure 60.
Figure 60. Schematic for a Two-Pole Low-Pass Filter
The following equations describe the low-pass cut off frequency,
gain, and Q:
fC = 1/(2π√(R1 C1 R2 C2))
Gain = 1 + R3/R4
GainC1R1CR2C2R1
C2R2C1R1
Q
12
Note that changing the gain has an effect on Q and vice versa.
Common values for Q are 0.5 to avoid peaking or 0.7 for
maximum flatness and sharp cut off. A high value of Q can be
used in narrow-band applications to increase peaking and the
selectivity of the band-pass filter.
A common design procedure is to set R1 = R2 = R and C1 = C2 =
C, which simplifies the expressions for cutoff frequency and Q to
fC = 1/(2πRC)
Gain
Q
3
1
Note that Q can be controlled by setting the gain with R3 and
R4; however, this limits the gain to be less than 3. For gain
values equal to or greater than 3, the circuit becomes unstable.
A simple modification that allows higher gains is to make the
value of C2 at least four times larger than C1.
It is important to note that these design equations only hold
true in the case that the output impedance of the previous stage
is much lower than the input impedance of the Sallen-Key filter.
This is not the case when using an ac coupling network between
the instrumentation amplifier output and the input of the low-
pass filter without a buffer.
To connect these two filtering stages properly without a buffer,
make the value of R1 at least ten times larger than the resistor of
the ac coupling network (labeled as R2 in Figure 55).
DRIVING ANALOG-TO-DIGITAL CONVERTERS
The ability of AD8232 to drive capacitive loads makes it ideal to
drive an ADC without the need for an additional buffer. However,
depending on the input architecture of the ADC, a simple low-
pass RC network may be required to decouple the transients
from the switched-capacitor input typical of modern ADCs.
This RC network also acts as an additional filter that can help
reduce noise and aliasing. Follow the recommended guidelines
from the ADC data sheet for the selection of proper R and C values.
Figure 61. Driving an ADC
DRIVEN ELECTRODE
A driven lead (or reference electrode) is often used to minimize
the effects of common-mode voltages induced by the power line
and other interfering sources. The AD8232 extracts the common-
mode voltage from the instrumentation amplifier inputs and
makes it available through the RLD amplifier to drive an opposing
signal into the patient. This functionality maintains the voltage
between the patient and the AD8232 at a near constant, greatly
improving the common-mode rejection ratio.
As a safety measure, place a resistor between the RLD pin and
the electrode connected to the subject to ensure that current
flow never exceeds 10 μA. Calculate the value of this resistor to
be equal to the supply voltage across the AD8232 divided by 10 μA.
The AD8232 implements an integrator formed by an internal
150 kΩ resistor and an external capacitor to drive this electrode.
Choice of the integrator capacitor is a tradeoff between line rejec-
tion capability and stability. The capacitor should be small to
maintain as much loop gain as possible, around 50 Hz and 60 Hz,
which are typical line frequencies. For stability, the gain of the
integrator should be less than unity at the frequency of any
other poles in the loop, such as those formed by the patient’s
capacitance and the safety resistors. The suggested application
circuits use a 1 nF capacitor, which results in a loop gain of about
20 at line frequencies, with a crossover frequency of about 1 kHz.
In a two-lead configuration, the RLD amplifier can be used to
drive the bias current resistors on the inputs. Although not as
effective as a true driven electrode, this configuration can
provide some common-mode rejection improvement if the
sense electrode impedance is small and well matched.
REFOUT
FILTERED
SIGNAL
A1
FROM IN-AMP
STAGE
C
R
10866-158
REFOUT
FILTERED
SIGNAL
A1
FROM IN-AMP
STAGE
C2
C1
R2
R3
R4
10866-159
R1
A1 C
RADC
10
AD8232
10866-261
AD8232 Data Sheet
Rev. C | Page 24 of 28
APPLICATION CIRCUITS
HEART RATE MEASUREMENT NEXT TO THE HEART
For wearable exercise devices, the AD8232 is typically placed in
a pod near the heart. The two sense electrodes are placed under-
neath the pectoral muscles; no driven electrode is used. Because
the distance from the heart to the AD8232 is small, the heart
signal is strong and there is less muscle artifact interference.
In this configuration, space is at a premium. By using as few
external components as possible, the circuit in Figure 62 is
optimized for size.
Figure 62. Circuit for Heart Rate Measurement Next to Heart
A shorter distance from the AD8232 to the heart makes this
application less vulnerable to common-mode interference.
However, since RLD is not used to drive an electrode, it can be
used to improve the common-mode rejection by maintaining
the midscale voltage through the 10 MΩ bias resistors.
A single-pole high-pass filter is set at 7 Hz, and there is no low-
pass filter. No gain is used on the output op amp thereby
reducing the number of resistors for a total system gain of 100.
Figure 63. Frequency Response for HRM Next to Heart Circuit
The input terminals in this configuration use two 180 kΩ
resistors, to protect the user from fault conditions. Two 10 MΩ
resistors provide input bias. Use higher values for electrodes
with high output impedance, such as cloth electrodes.
The schematic also shows two 10 MΩ resistors to set the
midscale reference voltage. If there is already a reference voltage
available, it can be driven into the REFIN input to eliminate
these two 10 MΩ resistors.
EXERCISE APPLICATION: HEART RATE MEASURED
AT THE HANDS
In this application, the heart rate signal is measured at the
hands with stainless steel electrodes. The user’s arm and upper
body movement create large motion artifacts and the long lead
length makes the system susceptible to common-mode inter-
ference. A very narrow band-pass characteristic is required to
separate the heart signal from the interferers.
Figure 64. Circuit for Heart Rate Measurement at Hands
The circuit in Figure 64 uses a two-pole high-pass filter set at
7 Hz. A two-pole low-pass filter at 24 Hz follows the high-pass
filters to eliminate any other artifacts and line noise.
Figure 65. Frequency Response for HRM Circuit Taken at the Hands
10866-161
+V
S
+V
S
+IN
–IN
HPDRIVE
+V
S
HPSENSE
IAOUT
REFIN
GND
FR
AC/DC
SDN
LO+
LO–
RLD
RLDFB
OUT
OPAMP+
OPAMP–
REFOUT
SW
AD8232
180kΩ
180kΩ
10MΩ
10MΩ0.1µF
10MΩ
1nF
10MΩ
ELECTRODE
INTERFACE
0.1µF
0.22µF
TO DIGITAL
INTERFACE
SIGNAL
OUTPUT
10MΩ
70
0
0.1 10k
MAGNITUDE (dB)
FREQUENCY (Hz)
10866-057
10
20
30
40
50
60
1101001k
10866-262
RL
RA
LA
+V
S
+V
S
+V
S
+IN
–IN
HPDRIVE
+V
S
HPSENSE
IAOUT
REFIN
GND
FR
AC/DC
SDN
LO+
LO–
RLD
RLDFB
OUT
OPAMP+
OPAMP–
REFOUT
SW
AD8232
22nF
1MΩ
1MΩ
100kΩ
3.3nF
100kΩ
180kΩ
180kΩ
1MΩ
10MΩ
10MΩ0.1µF
10MΩ
1nF
10MΩ
10MΩ
0.1µF
360kΩ
0.22µF
TO DIGITAL
INTERFACE
SIGNAL OUTPUT
0.22µF
70
0
0.1 1k
MAGNITUDE (dB)
FREQUENCY (Hz)
10866-059
10
20
30
40
50
60
110100
Data Sheet AD8232
Rev. C | Page 25 of 28
The overall narrow-band nature of this filter combination
distorts the ECG waveform significantly. Therefore, it is only
suitable to determine the heart rate, and not to analyze the ECG
signal characteristics.
The low-pass filter stage also includes a gain of 11, to bring the
total system gain close to 1100 (note that the filter roll off
prevents the maximum gain from reaching this value). Because
the ECG signal is measured at the hands, it is weaker than when
measured closer to the heart.
The RLD circuit drives to the third electrode, which can also be
located at the hands, to cancel common-mode interference.
CARDIAC MONITOR CONFIGURATION
This configuration is designed for monitoring the shape of the
ECG waveform. It assumes that the patient remains relatively
still during the measurement, and therefore, motion artifacts
are less of an issue.
Figure 66. Circuit for ECG Waveform Monitoring
To obtain an ECG waveform with minimal distortion, the
AD8232 is configured with a 0.5 Hz two-pole high-pass filter
followed by a two-pole, 40 Hz, low-pass filter. A third electrode
is driven for optimum common-mode rejection.
Figure 67. Frequency Response of Cardiac Monitor Circuit
In addition to 40 Hz filtering, the op amp stage is configured for
a gain of 11, resulting in a total system gain of 1100. To
optimize the dynamic range of the system, the gain level is
adjustable, depending on the input signal amplitude (which
may vary with electrode placement) and ADC input range.
PORTABLE CARDIAC MONITOR WITH ELIMINA-
TION OF MOTION ARTIFACTS
The circuit in Figure 68 shows an implementation of a battery-
powered embedded system for monitoring heart rate in
applications where the patient engages in moderate activity,
such as with a Holter monitor. The AD8232 uses a three-
electrode patient interface and implements a two-pole high-
pass filter with a cutoff at 0.3 Hz, and a two-pole low-pass filter
with a cutoff frequency of 37 Hz. The total signal gain in the
pass band is 400. The fully conditioned signal is sampled by the
sigma-delta ADC integrated on the low power microcontroller,
ADuCM360. The wide dynamic range of this ADC provides
flexibility to reduce the signal gain to avoid saturation, depending
on electrode placement.
Because the pass band is relatively wide for ambulatory applica-
tions, the ADXL346 accelerometer signal can be used to further
minimize the noise introduced by the motion of the patient.
Moreover, the microcontroller can use the motion information
to monitor inactivity and to issue a system shutdown to save
battery power.
The low dropout regulator ensures that the maximum of 3 V is
not exceeded, especially during charge cycles of the battery,
which can be a lithium-ion cell.
In this application, the ADuCM360 uses its Port 0 to perform
DMA transfers to the host communication interface or to an
on-board memory, if recording the waveform for later transfer.
However, in any particular application, this port should be used
for the busiest interface to minimize CPU cycles and maintain
low power operation.
Note that this circuit is shown to demonstrate the capabilities of
AD8232 and other system components. It is not a complete
system design and additional effort must be made to ensure
compliance with medical safety guidelines from regulatory
agencies.
RL
RA
LA
+V
S
+V
S
+V
S
+IN
–IN
HPDRIVE
+V
S
HPSENSE
IAOUT
REFIN
GND
FR
AC/DC
SDN
LO+
LO–
RLD
RLDFB
OUT
OPAMP+
OPAMP–
REFOUT
SW
AD8232
10nF
1M
1M
100k
1.5nF
180k
180k
1M
10M
10M0.1µF
1nF
10M
10M
0.1µF
360k
0.33µF
0.33µF
REFOUT
10M1.4M
TO DIGITAL
INTERFACE
SIGNAL OUTPUT
10866-266
10M
70
0
0.01 1k
MAGNITUDE (dB)
FREQUENCY (Hz)
10866-061
10
20
30
40
50
60
0.1 1 10 100
AD8232 Data Sheet
Rev. C | Page 26 of 28
Figure 68. Low Power Portable Cardiac Monitor
10866-163
RA
LA
RL
+V
S
+V
S
+V
S
HPSENSE
IAOUT
REFIN
GND
FR
AC/DC
SDN
LO+
LO–
+IN
–IN
HPDRIVE
RLD
RLDFB
OUT
OPAMP+
OPAMP–
REFOUT
SW
AD8232
6.8nF
1MΩ
1MΩ
332kΩ
2.7nF
100kΩ
180kΩ
180kΩ
1MΩ
10MΩ
10MΩ0.1µF
10MΩ
1nF
10MΩ
10MΩ
0.1µF
360kΩ
4.7µF
4.7µF
+V
S
1µF
1µF
+V
S
4.7µF
0.47µF
0.47µF
1µF V
BATT
+V
S
ADXL346
VS
VDDIO
GND
TO HOST,
MEMORY
OR
DISPLAY
+V
S
= +2.8V
TX
CLK
RX
CS
ELECTRODE
INTERFACE
P1.SCLK0
P1.4/MISO0
P1.6/MOSI0
P0.1/SCLK1
P0.2/MOSI1
P0.0/MISO1
P0.3/CS1
P0.6/IRQ2
P1.7/CS0
REG_DVDD
AVDD_REG
ADuCM360
ADP150x-2.8
GND
VINVOUT
SCL/SCLK
INT2
SDA/SDI/SDIO
SDO/ALT_ADD
CS
AIN0
AIN1
P1.1
P1.0
P1.2
VREF+
VREF–
IOVDD
GND
AVDD
Data Sheet AD8232
Rev. C | Page 27 of 28
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
Figure 69. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8232ACPZ-R7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP] CP-20-8
AD8232ACPZ-RL −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP] CP-20-8
AD8232ACPZ-WP −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP] CP-20-8
AD8232-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.18
COMPLIANT
TO
JEDEC STANDARDS M O-220- WGGD-11.
4.10
4.00 SQ
3.90
0.80
0.75
0.70 0. 05 MAX
0.02 NO M
0.20 REF
0.20 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
2.75
2.60 SQ
2.35
1
20
6
10
11
15
16
5
BOTTOM VIEW
TOP VIEW
SIDE VIEW FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
10-12-2017-C
EXPOSED
PAD
PKG-003502
SEATING
PLANE
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
