084-65958 - BEL POWER SOLUTIONS

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si5347/46

DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT

JITTER ATTENUATORS

Features

Applications

Description

The Si5347 is a high performance jitter attenuating clock multiplier which

integrates four any-frequency DSPLLs for applications that require maximum

integration and independent timing paths. The Si5346 is a dual DSPLL version in

a smaller package. Each DSPLL has access to any of the four inputs and can

provides low jitter clocks on any of the device outputs. Based on 4th generation

DSPLL technology, these devices provide any-frequency conversion with typical

jitter performance of 100 fs. Each DSPLL supports independent free-run,

holdover modes of operation, and offers automatic and hitless input clock

switching. The Si5347/46 is programmable via a serial interface with in-circuit

programmable non-volatile memory so that it always powers up with a known

configuration. Programming the Si5347/46 is made easy with Silicon Labs’

ClockBuilderPro software. Factory pre-programmed devices are also available.

Four or two independent DSPLLs in

a single monol i th ic IC

Each DSPLL generates any output

frequency from any input frequency

Input frequency range:

Differential: 8 kHz to 750 MHz

LVCMOS: 8 kHz to 250 MHz

Output frequency range:

Differential: up to 800 MHz

LVCMOS: up to 250 MHz

Jitter performance:

<100 fs typ (12 kHz–20 MHz)

Flexible crosspoints route any input

to any output clock

Programmable jitter attenuation

bandwidth per DSPLL: 0.1 Hz to

4kHz

Highly configurable outputs

compatible with LVDS, LVPECL,

LVCMOS, programmable signal

swings

Status monitoring (LOS, OOF, LOL)

Hitless input clock switching:

automatic or manu a l

Locks to gapped clock inputs

Automatic free-run and holdover

modes

Fastlock: <200 ms lock time

Glitchless on-the-fly DSPLL

frequency changes

DCO mode: as low as 0. 01 ppb

steps per DSPLL

Core voltage:

VDD: 1.8 V ±5%

VDDA: 3.3 V ±5%

Independent output supply pins:

3.3V, 2.5V, or 1.8V

Output-output skew:

<100 ps per DSPLL

Serial interface: I2C or SPI

In-circuit programmable with non-

volatile OTP memory

ClockBuilder Pro software tool

simplifies device configuration

Si5347: Quad DSPLL, 4 input,

8 output, 64 QFN

Si5346: Dual DSPLL, 4 input,

4 output, 44 QFN

Temperature range: –40 to +85 °C

Pb-free, RoHS-6 compliant

OTN Muxponders and

Transponders

10/40/100G network line cards

GbE/10GbE/100GbE Synchronous

Ethernet

Carrier Ethernet switches

Broadcast video

Ordering Information:

See section 7

Pin Assignmen ts

GND

Pad

IN1

OE0

INTR

VDDA

IN2

A0/CS

SDA/SDIO

A1/SDO

OUT0

VDDO0

SCLK

I2C_SEL

OUT1

VDDO1

VDDO3

OUT3

IN3

IN0

Si5346 44QFN

Top View

VDD

OUT2

VDDO2

VDDS

LOL_B

LOS_XAXB

VDD

OE1

IN2 11 23

NC 22

VDD

RST

LOL_A

GND

Pad

IN1

INTR

LOL_A

LOL_B

I2C_SEL

OE0

VDDA

IN2

SDA/SDIO

A1/SDO

VDD

RSVD

VDDO0

OUT0

LOS_XAXB

DSPLL_SEL0

A0/CS

VDDO1

OUT1

FINC

LOL_D

VDD

OUT4

VDDO4

FDEC

OE1

VDDS

OUT3

VDDO3

OUT2

VDDO2

VDDO5

OUT5

VDDO6

OUT6

RSVD

VDDO7

OUT7

VDD

IN3

IN0

Si5347 64QFN

Top View

LOL_C

RST

SCLK

DSPLL_SEL1

Si5347/46

2 Preliminary Rev. 0.9

Functional Block Diagram

Si5347/46

DSPLL

IN1

IN2

IN3

IN0

OUT7

OUT6

OUT5

OUT1

OUT4

OUT3

OUT2

OUT0

÷INT

÷FRAC

Si5346

NVM

I2C/SPI

Control/

Status

XTAL/

REFCLK

XBXA

OSC

Si5347

Si5347/46

Preliminary Rev. 0.9 3

TABLE OF CONTENTS

1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.4. Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.5. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

4.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

5.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

8. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

8.1. Si5347 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

8.2. Si5346 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

11. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Appendix—Advance Product Information Revision History . . . . . . . . . . . . . . . . . . . . . . .51

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Si5347/46

4 Preliminary Rev. 0.9

1. Typical Application Schematic

Figure 1. Using The Si5347 to Clean Gapped Clocks in an OTN Application

DSPLL A

LPF

÷Mn_A

Md_A

PHY

DSPLL B

LPFPD

÷Mn_B

Md_B

PHY

DSPLL C

LPFPD

÷Mn_C

Md_C

PHY

DSPLL D

LPFPD

÷Mn_D

Md_D

PHY

Si5347

Data

Clock

Client #4

Data

Clock

Client #3

Data

Clock

Client #2

Data

Clock

Client #1

OTN

De-Mapper

40G OTN

10GbE

OTN Muxponder

Gapped Clock Non-gapped

Jitter Attenuated Cloc k

Gapped Clock Non-gapped

Jitter Attenuated Cloc k

Gapped Clock Non-gapped

Jitter Attenuated Cloc k

Gapped Clock Non-gapped

Jitter Attenuated Cloc k

10GbE

Si5347/46

Preliminary Rev. 0.9 5

2. Electrical Specifications

Table 1. Recommended Operating Conditions

(VDD =1.8V ±5%, V

DDA =3.3V ±5%,T

A= –40 to 85 °C)

Parameter Symbol Min Typ Max Units

Ambient Temperature TA–40 25 85 °C

Junction Temperature TJMAX ——125°C

Core Supply Voltage VDD 1.71 1.80 1.89 V

VDDA 3.14 3.30 3.47 V

Output Driver Supply Voltage VDDO 3.14 3.30 3.47 V

2.38 2.50 2.62 V

1.71 1.80 1.89 V

Status Pin Supply Voltage VDDS 3.14 3.30 3.47 V

1.71 1.80 1.89 V

Note: All minimum and maximu m spec ifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 2. DC Characteristics

(VDD =1.8V ±5%, V

DDA =3.3V ±5%, V

DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Core Supply Current IDD Si5347 Notes 1, 2— 270 365 mA

Si5346 — — 173 mA

IDDA Si5347 — 125 137 mA

Note:

1. Si5347 test configuration: 7 x 2.5 V LVDS outputs enable d @156.25 MHz. Excludes power in termination resistors.

2. Si5346 test configuration: 4 x 2.5 V LVDS outputs enable d @ 156.25 MHz. Excludes power in termination resistors.

3. Differential outputs terminated into an AC coupl ed 100  load.

4. LVCMOS outputs measured into a 6 inch 50  PCB trace with 5 pF load.

5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board

(EVB) is not available. All EVBs support detailed current measurements for any configuration.

100

OUT

IDDO

Differential Output Test Configuration

OUTa

IDDO

5 pF

LVCMOS Output Test Configuration

6 inch

OUTb

Si5347/46

6 Preliminary Rev. 0.9

Output Buffer Supply Current IDDOx LVPECL Output3

@ 156.25 MHz —2325mA

LVDS Output3

@ 156.25 MHz —1618mA

3.3V LVCMOS4 output

@ 156.25 MHz —1926mA

2.5V LVCMOS4 output

@ 156.25 MHz —1519mA

1.8V LVCMOS4 output

@ 156.25 MHz —1113mA

Total Power Dissipation PdSi5347 Note 1,5— 1180 1380 mW

Si5346 Note 2,5—883—mW

Table 2. DC Characteristics (Continued)

(VDD =1.8V ±5%, V

DDA =3.3V ±5%, V

DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Note:

1. Si5347 test configuration: 7 x 2.5 V LVDS outputs enable d @156.25 MHz. Excludes power in termination resistors.

2. Si5346 test configuration: 4 x 2.5 V LVDS outputs enable d @ 156.25 MHz. Excludes power in termination resistors.

3. Differential outputs terminated into an AC coupl ed 100  load.

4. LVCMOS outputs measured into a 6 inch 50  PCB trace with 5 pF load.

5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board

(EVB) is not available. All EVBs support detailed current measurements for any configuration.

100

OUT

IDDO

Differential Output Test Configuration

OUTa

IDDO

5 pF

LVCMOS Output Test Configuration

6 inch

OUTb

Si5347/46

Preliminary Rev. 0.9 7

Table 3. Input Specifications

(VDD =1.8V ±5%, V

DDA =3.3V ±5%, T

A=–40 to 85°C)

Parameter Symbol Test Condition Min Typ Max Units

Differential or Single-Ended - AC Coupled (IN0/IN0 , IN1/IN1, IN2/IN2, IN3/IN3)

Input Frequency Range fIN_DIFF 0.008 — 750 MHz

Voltage Swing VIN fin< 400 MHz 100 — 1000 mVpp_se

600 MHz < fin< 800 MHz 225 — 1000 mVpp_se

fin > 800 MHz 375 — 1000 mVpp_se

Slew Rate1,2 SR 400 — — V/µs

Duty Cycle DC 40 — 60 %

Capacitance CIN —2—pF

LVCMOS - DC Coupled (IN0, IN1, IN2, IN3)

Input Frequency fIN_CMOS 0.008 — 250 MHz

Input Voltage VIL –0.2 — 0.18 V

VIH 0.7 — — V

Slew Rate1,2 SR 400 — — V/µs

Minimum Pulse Width PW Pulse Input 1.6 — — ns

Input Resistance RIN —8—k

REFCLK (Applied to XA/XB)

REFCLK Frequency fIN_REF Frequency range for best

output jitter performance 48 — 54 MHz

Input Voltage Swing VIN 350 — 1600 mVpp_se

Slew rate1,2 SR Imposed for best jitter per-

formance 400 — — V/µs

Input Duty Cycle DC 40 — 60 %

Note:

1. Imposed for jitter performance

2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) x VIN_Vpp_se) / SR

3. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD.

4. A programmable internal divider (PREF) is available to help support REFCLK frequencies up to 200 MHz.

Si5347/46

8 Preliminary Rev. 0.9

Table 4. Control Input Pin Specifications

(VDD =1.8V ±5%, V

DDA =3.3V ±5%, V

DDS = 3.3 V ±5%, 1.8 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Si5347 Control Input Pins (I2C_SEL, RST, OE0, A1, SCLK, A0/CS, FINC, A0/CS, SDA, SDI, DSPLL_SEL0,

DSPLL_SEL1)

Input Voltage VIL –0.1 — 0.3 x VDDIO*V

VIH 0.7 x VDDIO*— 3.6 V

Input Capacitance CIN —2— pF

Input Resistance IL—20— k

Minimum Pulse Width PW RST 50 — — ns

Si5347 Control Input Pins (FDEC, OE1)

Input Voltage VIL –0.1 — 0.3 x VDDS V

VIH 0.7 x VDDS —3.6 V

Input Capacitance CIN —2— pF

Input Resistance IL—20— k

Minimum Pulse Width PW FDEC 50 — — ns

Si5346 Control Input Pins (I2C_SEL, RST, OE0, OE1, A1, SCLK, A0/CS, SDA, SDI)

Input Voltage VIL –0.1 — 0.3 x VDDIO*V

VIH 0.7 x VDDIO*— 3.6 V

Input Capacitance CIN —2— pF

Input Resistance IL—20— k

Minimum Pulse Width PW RST 50 — — ns

*Note: VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD.

Si5347/46

Preliminary Rev. 0.9 9

Table 5. Differential Clock Output Specifications

(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Output Frequency fOUT 0.0001 — 800 MHz

Duty Cycle DC f < 400 MHz 48 — 52 %

400 MHz < f < 800 MHz 45 — 55 %

Output-Output Skew TSK Differential Output — — 100 ps

OUT-OUT Skew TSK_OUT Measured from the positive to

negative output pins — — 100 ps

Output Voltage Swing1Normal Swing Mode

VOUT VDDO =3.3V,

2.5 V, or 1.8 V LVDS 370 470 570 mVpp_se

LVPECL 650 820 1050

Low Power Mode

VOUT VDDO =3.3V,

2.5 V, or 1.8 V LVDS 310 420 530 mVpp_se

VDDO =3.3V,

2.5 V, or 1.8 V LVPECL 590 830 1063

Common Mode Voltage1,2,3 Normal Swing or Low Power Modes

VCM VDDO = 3.3 V LVDS 1.12 1.23 1.34 V

LVPECL 1.90 2.0 2.13

VDDO = 2.5 V LVPECL,

LVDS 1.17 1.23 1.30

Rise and Fall Times

(20% to 80%) tR/tFNormal Swing Mode — 170 220 ps

Low Power Mode — 250 320

Differential Output Impedance4ZONormal Swing Mode — 100 — 

Low Power Mode — Hi-Z — 

Si5347/46

10 Preliminary Rev. 0.9

Power Supply Noise Rejection5PSRR Normal Swing Mode

10 kHz sinusoidal noise — –93 — dBc

100 kHz sinusoidal noise — –93 —

500 kHz sinusoidal noise — –84 —

1 MHz sinusoidal noise — –79 —

Low Power Mode

10 kHz sinusoidal noise — –98 — dBc

100 kHz sinusoidal noise — –95 —

500 kHz sinusoidal noise — –84 —

1 MHz sinusoidal noise — –76 —

Output-output Crosstalk XTALK Measured spur from adjacent

output —–73— dB

Notes:

1. Normal swing mode, low power mode, Vswing and Cmode settin gs are programmable through register settin gs and

can be stored in NVM. Each output driver can be programmed independently.

2. Not all combinations of voltage swing and common mode voltages settings are possible.

3. Common mode voltage min/max variation = ±4% from typical value.

4. Driver output impedance depends on selected output mode (Normal, High).

5. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/

3.3 V = 100 mVpp) and noise spur amplitude measured.

Table 5. Differential Clock Output Specifications (Continued)

(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

OUTx

OUTx Vpp_se

Vpp_se Vpp_diff = 2*Vpp_se

Vcm

Vcm Vcm

Si5347/46

Preliminary Rev. 0.9 11

Table 6. Output Status Pin Specifications

(VDD =1.8V ±5%, V

DDA =3.3V ±5%, V

DDS = 3.3 V ±5%, 1.8 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Si5347 Status Output Pins (LOL_A, LOL_B, LOL_C, LOL_D, INTR, LOS_XAXB)

Output Voltage VOH IOH =–2mA V

DDIO* x 0.75 — — V

VOL IOL =2mA — — V

DDIO1 x 0.15 V

Si5346 Status Output Pins (LOL_A, LOL_B)

Output Voltage VOH IOH =–2mA V

DDS x 0.85 — — V

VOL IOL =2mA — — V

DDS x 0.15 V

Si5346 Status Output Pins (INTR, LOS_XAXB)

Output Voltage VOH IOH =–2mA V

DDIO* x 0.75 — — V

VOL IOL =2mA — — V

DDIO* x 0.15 V

*Note: VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD.

Si5347/46

12 Preliminary Rev. 0.9

Table 7. LVCMOS Clock Output Specifications

(VDD =1.8V ±5%, V

DDA =3.3V ±5%, V

DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Output Frequency FOUT 0.0001 — 250 MHz

Duty Cycle DC f < 400 MHz 48 — 52 %

400 MHz < f < 800 MHz 45 — 55 %

Output-to-Output Skew TSK — — 100 ps

Output Voltage High1,2,3 VOH VDDO =3.3V

CMOS1 IOH =–10mA V

DDO x 0.85 — — V

CMOS2 IOH =–12mA — —

CMOS3 IOH =–17mA — —

VDDO =2.5V

CMOS2 IOH =–8mA V

DDO x 0.85 — — V

CMOS3 IOH =–11mA — —

VDDO =1.8V

CMOS3 IOH =–5mA V

DDO x 0.85 — — V

Output Voltage Low1,2,3 VOL VDDO =3.3V

CMOS1 IOL =10mA — — V

DDO x 0.15 V

CMOS2 IOL =12mA — —

CMOS3 IOL =17mA — —

VDDO =2.5V

CMOS2 IOL =8mA — — V

DDO x 0.15 V

CMOS3 IOL =11mA — —

VDDO =1.8V

CMOS3 IOL =5mA — — V

DDO x 0.15 V

LVCMOS Rise and Fall

Times3 (20% to 80%) tr/tf VDDO = 3.3 V — 360 — ps

VDDO = 2.5 V — 420 — ps

VDDO = 1.8 V — 280 — ps

Notes:

1. Driver strength is a register programmable setting and stored in NVM. Options are CMOS1, CMOS2, CMOS3.

2. IOL/IOH is measured at VOL/VOH as shown in the DC test configuration

3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 Ohm PCB trace. A 5 pF

capacitive load is assumed.

DC Test Configuration

IOL/IOH

VOL/VOH

5 pF

AC Test Configuration

Zs + Rs = 50 Ohms

Si5347/46

Preliminary Rev. 0.9 13

Table 8. Performance Characteristics

(VDD = 1.8 V ±5%, or 3.3 V ±5%, VDD33 = 3.3V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Initial Start-Up Time tSTART Time from power-up to

when the device gene ra tes

free-running clocks

—30— ms

PLL Lock Time tACQ With Fastlock enabled1—160— ms

POR to Serial Interface Ready tRDY ——10 ms

PLL Loop Bandwidth fBW 0.1 — 4000 Hz

Jitter Peaking JPK ——0.1dB

Jitter Tolerance JTOL Jitter modulation = 10 Hz — 23 — UI pk-pk

Maximum Phase Transient

During a Hitless Switch tSWITCH ——1.5 ns

Pull-in Range P—500— ppm

Input-to-Output Delay tIODELAY Input-to-output delay is con-

sistent at every power-up —2— ns

RMS Phase Jitter2JGEN 12 kHz to 20 MHz — 0. 115 0.160 ps

Notes:

1. Fastlock bandwidth = 1 kHz. Measured from valid input to LOL deassertion.

2. Jitter generation test conditions: fIN = 19.44 MHz, fOUT = 156.25 MHz LVPECL, loop bandwidth = 100 Hz.

Does not include jitter from input clock.

Si5347/46

14 Preliminary Rev. 0.9

Table 9. I2C Timing Specifications (SCL,SDA)

Parameter Symbol Test Condition Standard Mode

100 kbps Fast Mode

400 kbps Units

Min Max Min Max

SCL Clock

Frequency fSCL 0 100 0 400 kHz

SMBus Timeout — When Timeout is

Enabled 25 35 25 35 ms

Hold time (repeated)

START condition tHD:STA 4.0 — 0.6 — µs

Low period of the SCL

clock tLOW 4.7 — 1.3 — µs

HIGH period of the SCL

clock tHIGH 4.0 — 0.6 — µs

Set-up time for a repeated

START condition tSU:STA 4.7 — 0.6 — µs

Data hold time tHD:DAT 5.0 — — — µs

Data set-up time tSU:DAT 250 — 100 — ns

Rise time of both SDA and

SCL signals tr— 1000 20 300 ns

Fall time of both SDA and

SCL signals tf— 300 — 300 ns

Set-up time for STOP con-

dition tSU:STO 4.0 — 0.6 — µs

Bus free time between a

STOP and START condi-

tion

tBUF 4.7 — 1.3 — µs

Data valid time tVD:DAT —3.45— 0.9 µs

Data valid acknowledge

time tVD:ACK —3.45— 0.9 µs

Si5347/46

Preliminary Rev. 0.9 15

Figure 2. I2C Serial Port Timing Standard and Fast Modes

Table 10. SPI Timing Specifications

(VDD = 1.8 V ±5%, or 3.3 V ±5%, VDD33 = 3.3V ±5%, TA= –40 to 85 °C)

Parameter Symbol Min Typ Max Units

SCLK Frequency fSPI ——20MHz

SCLK Duty Cycle TDC 40 — 60 %

SCLK Rise & Fall Time Tr /Tf — — 10 ns

SCLK High & Low Time THL

SCLK Period TC50 — — ns

Delay Time, SCLK Fall to SDO Active TD1 — — 12.5 ns

Delay Time, SCLK Fall to SDO TD2 — — 12.5 ns

Delay Time, CS Rise to SDO Tri-State TD3 — — 12.5 ns

Setup Time, CS to SCLK TSU1 25 — — ns

Hold Time, CS to SCLK Rise TH1 25 — — ns

Setup Time, SDI to SCLK Rise TSU2 12.5 — — ns

Hold Time, SDI to SCLK Rise TH2 12.5 — — ns

Delay Time Between Chip Selects (CS)T

CS 50 — — ns

Si5347/46

16 Preliminary Rev. 0.9

Figure 3. SPI Serial Interface Timing

Table 11. Crystal Specifications

Parameter Symbol Test Condition Min Typ Max Units

Crystal Frequency Range fXTAL Frequency range for

best jitter performance 48 — 54 MHz

Load Capacitance CL—8—pF

Shunt Capacitance CO—— 3pF

Crystal Drive Level dL——200µW

Equivalent Series Resistance rESR Refer to the Si5347/46 Fam ily Reference Manual to deter mine

ESR

Notes:

1. The Si5347/46 is designed to work with crystals that meet the specifications in Table 11.

2. Refer to the Si5347/46 Family Reference Manual for recommended 48 to 54 MHz crystals. Crystal frequencies from

24.97 to 54.06 MHz are supported, but jitter performance is best from 48 to 54 MHz.

SCLK

SDI

SDO

TSU1 TD1

TSU2

TD2

TCS

TD3

TH2

TH1

Si5347/46

Preliminary Rev. 0.9 17

Table 12. Thermal Characteristics

Parameter Symbol Test Condition* Value Units

Si5347–64QFN

Thermal Resistance

Junction to Ambient JA Still Air 22 °C/W

Air Flow 1 m/s 19.4

Air Flow 2 m/s 18.3

Thermal Resistance

Junction to Case JC 9.5

Thermal Resistance

Junction to Board JB 9.4

JB 9.3

Thermal Resistance

Junction to Top Center JT 0.2

Si5346–44QFN

Thermal Resistance

Junction to Ambient JA Still Air 22.3 °C/W

Air Flow 1 m/s 19.4

Air Flow 2 m/s 18.4

Thermal Resistance

Junction to Case JC 10.9

Thermal Resistance

Junction to Board JB 9.3

JB 9.2

Thermal Resistance

Junction to Top Center JT 0.23

*Note: Based on PCB Dimension: 3” x 4.5”, PCB Thickness: 1.6 mm, PCB Land/Via under GNP pad: 36, Number of Cu

Layers: 4

Si5347/46

18 Preliminary Rev. 0.9

Table 13. Absolute Maximum Ratings1,2,3,4

Parameter Symbol Test Condition Value Units

Storage Temperature Range TSTG –55 to +150 °C

DC Supply Voltage VDD –0.5 to 3.8 V

VDDA –0.5 to 3.8 V

VDDO –0.5 to 3.8 V

VDDS –0.5 to 3.8 V

Input Voltage Range VI1 IN0 - IN3 –0.85 to 3.8 V

VI2 RST, OE0, OE1, I2C_SEL,

FINC, FDEC, PLL_SEL[1:0]

SDI, SCLK, A0/CS

–0.5 to 3.8 V

VI3 XA/XB –0.5 to 2.7 V

Latch-up Tolerance LU JESD78 Compliant

ESD Tolerance HBM 100 pF, 1.5 k2.0 kV

Storage Temperature Range TSTG –55 to 150 °C

Junction Temperature TJCT –55 to 150 °C

Soldering Temperature

(Pb-free profile)5TPEAK 260 °C

Soldering Temperature Time at TPEAK

(Pb-free profile)5TP20–40 s

Note:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

2. 64-QFN and 44-QFN packages are RoHS-6 compliant.

3. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.

4. Moisture sensitivity level is MSL2.

5. The device is compliant with JEDEC J-STD-020.

Si5347/46

Preliminary Rev. 0.9 19

3. Detailed Block Diagram

Figure 4. Si5347 Detailed Block Diagram

DSPLL A

LPFPD

DSPLL B

LPFPD

DSPLL C

LPFPD

DSPLL D

LPFPD

Si5347

÷Mn_A

Md_A

÷Mn_B

Md_B

÷Mn_C

Md_C

÷Mn_D

Md_D

DSPLL_SEL[1:0]

SDA/SDIO

A1/SDO

SCLK

A0/CS

I2C_SEL

SPI/

I2C

RST

OE0

OE1

VDD

VDDA

IN2

IN2 ÷P2n

P2d

IN0

IN0 ÷P0n

P0d

IN1

IN1 ÷P1n

P1d

IN3

IN3 ÷P3n

P3d

÷R0

÷R1

OUT0

VDDO0

OUT0

OUT1

VDDO1

OUT1

÷R2

÷R3

OUT2

VDDO2

OUT2

OUT3

VDDO3

OUT3

÷R4

÷R5

OUT4

VDDO4

OUT4

OUT5

VDDO5

OUT5

÷R6

÷R7

OUT6

VDDO6

OUT6

OUT7

VDDO7

OUT7

FDEC

FINC

Status

Monitors

LOS_XAXB

LOL_A

LOL_B

LOL_C

LOL_D

INTR

NVM

48-54MHz XTAL

or REFCLK

OSC

XBXA

÷PREF

VDDS

Si5347/46

20 Preliminary Rev. 0.9

Figure 5. Si5346 Detailed Block Diagram

Si5346

SDA/SDIO

A1/SDO

SCLK

A0/CS

I2C_SEL

SPI/

I2CNVM

RST

OE0

OE1

Status

Monitors

LOS_XAXB

INTR

LOL_A

LOL_B

IN2

IN2 ÷P2n

P2d

IN0

IN0 ÷P0n

P0d

IN1

IN1 ÷P1n

P1d

IN3

IN3 ÷P3n

P3d

÷R0

÷R1

OUT0

VDDO0

OUT0

OUT1

VDDO1

OUT1

÷R2

÷R3

OUT2

VDDO2

OUT2

OUT3

VDDO3

OUT3

DSPLL A

LPFPD

DSPLL B

LPFPD

÷Mn_A

Md_A

÷Mn_B

Md_B

VDD

VDDA

VDDS

48-54MHz XTAL

or REFCLK

OSC

XBXA

÷PREF

Si5347/46

Preliminary Rev. 0.9 21

4. Functional Description

The Si5347 takes advantage of Silicon Labs’ 4th

generation DSPLL technology to offer the industry’s

most integrated and flexible jitter attenuating clock

generator solution. Each of the DSPLLs operate

independently from each other and are controlled

through a common serial interface. Each DSPLL has

access to any of the four inputs ( IN0 to IN3) with manual

or automatic input selection. Any of the output clocks

(OUT0 to OUT7) can be configured to any of the

DSPLLs using a flexible crosspoint connection. The

Si5346 is a smaller form factor dual DSPLL version with

four inputs and four outpu ts.

4.1. Frequency Configuration

The frequency configuration for each of the DSPLLs is

programmable through the serial interface and can also

be stored in non-volatile memory. The combination of

fractional input dividers (Pn/Pd), fractional frequency

multiplication (Mn/Md), and integer output division (Rn)

allows each of the DSPLLs to lock to any input

frequency and generate virtually any output frequency

All divider values for a specific frequency pla n are ea sily

determined using the ClockBuilder Pro utility.

4.2. DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of

input clock jitter attenuation. Register configurable

DSPLL loop bandwid th settings in the range of 0.1 Hz to

4 kHz are available for selection for each of the

DSPLLs. Since the loop bandwidth is controlled digit ally,

each of the DSPLLs will always remain stable with less

than 0.1 dB of peaking regardless of the loop bandwid t h

selection.

4.2.1. Fastlock Feature

Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will

generally lengthen the lock acquisition time. The

fastlock feature allows setting a temporary Fastlock

Loop Bandwidth that is used during the lock acquisition

process. Higher fastlock loop bandwidth settings will

enable the DSPLLs to lock faster. Fastlock Loop

Bandwidth settings in in the range of 100 Hz to 4 kHz

are available for selection. Once lock acquisition has

completed, the DSPLL’s loop bandwidth will

automatically revert to the DSPLL Loop Bandwidth

setting as described in section “4.2. DSPLL Loop

Bandwidth” . The fastlock feature can be enabled or

disabled independently for each of the DSPLLs.

4.3. Modes of Operation

Once initialization is complete, each of the DSPLLs

operates independently in one of thr ee modes: Fre e-run

Mode, Lock Acquisition Mode, Locked Mode, or

Holdover Mode. A state diagram showing the modes of

operation is shown in Figure 6. The following sections

describe each of these modes in greater detail.

4.3.1. Initialization and Reset

Once power is applied, the device begins an

initialization period where it downloads default register

values and configuration data from NVM and performs

other initialization tasks. Communica ting with the d evice

through the serial interface is possible once this

initialization period is complete. No clocks will be

generated until the initialization is complete. There are

two types of resets available. A hard reset is functionally

similar to a device power-up. All registers will be

restored to the values stored in NVM, and all circuits will

be restored to their initial state including the serial

interface. A hard reset is initiated using the RST pin or

by asserting the hard reset bit. A sof t reset byp asses the

NVM download. It is simply used to initiate register

configuration changes. A hard reset affects all DSPLLs,

while a soft reset can affect all or each DSPLL

individually.

Si5347/46

22 Preliminary Rev. 0.9

Figure 6. Modes of Operation

4.3.2. Freerun Mode

Once power is applied to the Si5347 and initialization is

complete, all four DSPLLs will automatically enter

freerun mode. The fre que ncy accu racy o f the g ene ra ted

output clocks in freerun mode is entirely dependent on

the frequency accuracy of the external crystal or

reference clock on the XA/XB pins. For example, if the

crystal frequency is ±100 ppm, then all the output clocks

will be generated at their configured frequency

±100 ppm in freerun mode. Any drift of the crystal

frequency will be tracked at the output clock

frequencies. A TCXO or OCXO is recommended for

applications that need better frequency accuracy and

stability while in freerun or holdover modes.

4.3.3. Lock Acquisition Mode

Each of the DSPLLs independently monitors its

configured inputs for a valid clock. If at least one valid

clock is available for synchronization, a DSPLL will

automatically start the lock acquisition process.

If the fast lock feature is enabled, a DSPLL will acquire

lock using the Fastlock Loop Bandwidth setting and

then transition to the DSPLL Loop Bandwidth setting

when lock acquisition is complete. During lock

acquisition the outputs will generate a clock that follows

the VCO frequency change as it pulls-in to the input

clock frequency.

4.3.4. Locked Mode

Once locked, a DSPLL will generate output clocks that

are both frequency and phase locked to their selected

input clocks. At this point any XTAL frequency drift will

not affect the output frequency. Each DSPLL has its

own LOL pin and status bit to indicate when lock is

achieved. See "4.7.4. LOL Detection" on page 28 for

more details on the operation of the loss of lock circuit.

4.3.5. Holdover Mode

Any of the DSPLLs will automatically enter holdover

mode when the selected input clock becomes invalid

and no other valid input clocks are available for

selection. Each DSPLL uses an averaged input clock

frequency as its fin al holdover frequen cy to minimize the

disturbance of the output clock phase and frequency

No valid

input clocks

selected

Lock Acquisition

(Fast Lock)

Locked

Mode

Holdover

Mode Phase lock on

selected input

clock is achieved

Selected

input clock

fails

An input is qualified

and available for

selection

No valid input

clocks availa b le

for selection

Free-run

Valid input clock

selected

Reset and

Initialization

Power-Up

Si5347/46

Preliminary Rev. 0.9 23

when an input clock suddenly fails. The holdover circuit

for each DSPLL stores up to 120 seconds of historical

frequency data while locked to a valid clock input. The

final averaged holdover frequency value is calculated

from a programmable window within the stored

historical frequency data. Both the window size and

delay are programmable as shown in Figure 7. The

window size determines the amount of holdover

frequency averaging. The delay value allows ignoring

frequency data that may be corrupt just before the input

clock failure.

Figure 7. Programmable Holdover Window

When entering holdover, a DSPLL will pull its output

clock frequency to the calculated averaged holdover

frequency. While in holdover, the output frequency drift

is entirely dependent on the external crystal or external

reference clock connected to the XA/XB pins. If the

clock input becomes valid, a DSPLL will automatically

exit the holdover mode and reacquire lock to the new

input clock. This process involves pulling the output

clock frequencies to achieve frequency and phase lock

with the input clock. This pull-in process is glitchless,

and its rate is controlled by the DSPLL bandwidth, the

Fastlock bandwidth, or an artificial linear ramp rate

selectable from 0.75 ppm/s up to 40 ppm/s. These

options are register programmable.

4.4. Digitally-Controlled Oscillator (DCO)

Mode

The DSPLLs support a DCO mode where their output

frequencies are adjustable in predefined steps defined

by frequency step words (FSW). The frequency

adjustments are controlled through the serial interface

or by pin control using frequency increments (FINC) or

decrements (FDEC). A FINC will add the frequency step

word to the DSPLL output frequency, while a FDEC will

decrement it. The DCO mode is available when the

DSPLL is operating in either free-running or locked

mode. Controlling The DCO Mode Using The Serial

Interface

4.5. External Reference (XA/XB)

An external crystal (XTAL) is used in combination with

the internal oscillator (OSC) to produce an ultra low jitter

reference clock for the DSPLLs and for providing a

stable reference for the free-run and holdover modes. A

simplified diagram is shown in Figure 8. The device

includes internal XTAL loading capacitors which

eliminates the need for external capacitors and also has

the benefit of reduced noise coupling from external

sources. Refer to Table 11 for crystal specifications. A

crystal in the range of 48 to 5 4 MHz is recommended for

best jitter performance. Frequency offsets due to CL

mismatch can be adjusted using the frequency

adjustment fe ature which allo ws frequency ad justments

of ±200 ppm. The Si5347/46 Family Reference Manual

provides additional information on PCB layout

recommendations for the crystal to ensure optimum

jitter performance.

The device can also accommodate an external

reference clock (REFCLK) instead of a crystal.

Selection between the external XTAL or REFCLK is

controlled by register configuration. The internal crystal

loading capacitors (CL) are disabled in this mode. Refer

to Table 3 for REFCLK requirements when using this

mode. The Si5347/46 Family Reference Manual

provides additional information on PCB layout

recommendations for the crystal to ensure optimum

jitter performance. A PREF divider is available to

accommodate external clock frequencies higher than

54 MHz. Although the REFCLK frequency range of

25 MHz to 200 MHz is supported, frequencies in the

range of 48 MHz to 54 MHz will achieve the best output

jitter performance.

Programmable delay

Clock Failure and

Entry into Ho ldover

time

Historical Frequency Data Collected

Programmable historical data window

used to determine the final holdover value

120s 1s,10s, 30s, 60s 30ms, 60ms, 1s,10s, 30s, 60s

Si5347/46

24 Preliminary Rev. 0.9

Figure 8. Crystal Resonator and External Reference Clock Connection Options

4.6. Inputs (IN0, IN1, IN2, IN3)

There are four inputs that can be used to synchronize any of the DSPLLs. The inputs accept both differential and

single-ended clocks. A crosspoint betwe en the inpu t s and the DSPLLs all ows any of the in put s to connect to any of

the DSPLLs as shown in Figure 9.

Figure 9. DSPLL Input Selection Crosspoint

OSC

XBXA

48-54MHz

XTAL

2xCL2xCL

Crystal Resonator Connection

OSC

XBXA

48-54MHz

100

Differential XO Connection

OSC

XBXA

48-54MHz

Single-Ended XO Connection

2xCL2xCL2xCL

Si5347/46 Si5347/46 Si5347/46

2xCL

÷PREF ÷PREF ÷PREF

Input

Crosspoint

DSPLL

Si5347

÷P0n

P0d

÷P1n

P1d

÷P2n

P2d

÷P3n

P3d

IN0

IN1

IN2

IN3

Si5347/46

Preliminary Rev. 0.9 25

4.6.1. Input Selection

Input selection for each of the DSPLLs can be made

manually through register control or automatically using

an internal state machine.

4.6.2. Manual Input Selection

In manual mode the input selection is made by writing to

a register. If there is no clock signal on the selected

input, the DSPLL will automatically enter holdover

mode.

4.6.3. Automatic Input Selection

When configured in this mode, the DSPLLs

automatically selects a valid input that has the highest

configured priority. The priority scheme is in dep end ently

configurable for each DSPLL and supports revertive or

non-revertive selection.

All inputs are continuously monitored for loss of signal

(LOS) and/or invalid frequency range (OOF). Only

inputs that do not assert both the LOS and OOF

monitors can be selected for synchronization by the

automatic state machine. The DSPLL(s) will enter the

holdover mode if there are no valid inputs available.

4.6.4. Input Configuration and Terminations

Each of the inputs can be configured as differential or

single-ended LVCMOS. The recommended input

termination schemes are shown in Figure 10.

Differential signals must be ac coupled, while single-

ended LVCMOS signals can be ac or dc coupled.

Unused inputs can be disabled and left unconnected

when not in use.

Figure 10. Termination of Differential and LVCMOS Input Signals

4.6.5. Hitless Input Switching

Hitless switching is a feature that prevents a phase

transient from propagating to the output when switching

between two clock inputs that have a fixed phase

relationship. A hitless switch can only occur when the

two input frequencies are frequency locked meaning

that they have to be exactly at the same frequ ency, or at

a fractional frequency relationship to each other. When

hitless switching is enabled, the DSPLL simply absorbs

the phase difference between the two input clocks

during a input switch. When disabled, the phase

difference between the two inputs is propagated to the

output at a rate determined by the DSPLL Loop

Bandwidth. The hitless switching feature supports clock

frequencies down to the minimum input frequency of

8 kHz. Hitless switching can be enabled on a per

DSPLL basis.

DC Coupled LVCMOS

AC Coupled Single-ended

100

3.3V , 2.5V, 1 .8V

LVCMOS

AC Coupled Differential

INx

LVCMOS

DIFF

INx

LVCMOS

DIFF

INx

LVCMOS

DIFF

Si5347/46

26 Preliminary Rev. 0.9

4.6.6. Glitchless Input Switching

The DSPLLs have the ability of switching between two

input clock frequencies that are up to ±500 ppm apart.

The DSPLL will pull-in to the new frequency using the

DSPLL Loop Bandwidth or using the Fastlock Loop

Bandwidth if it is enabled. The loss of lock (LOL)

indicator will assert while the DSPLL is pulling-in to the

new clock frequency. There will be n o outpu t runt p ulses

generated at the output during the transition.

4.6.7. Synchronizing to Gapped Input Clocks

Each of the DSPLLs support locking to an input clock

that has missing periods. This is also referred to as a

gapped clock. The purpose of gapped clocking is to

modulate the frequency of a periodic clock by

selectively removing some of its cycles. Gapping a clock

severely increases its jitter so a phase-locked loop with

high jitter tolerance and low loop bandwidth is required

to produce a low-jitter periodic clock. The resulting

output will be a periodic non-gapped clock with an

average frequency of the input with its missing cycles.

For example, an input clock of 100 MHz with one cycle

removed every 10 cycles will result in a 90 MHz periodic

non-gapped output clock. This is shown in Figure 11.

Figure 11. Generating an Averaged Clock Output Frequency from a Gapped Clock Input

A valid gapped clock input must have a minimum

frequency of 10 MHz with a maximum of two missing

cycles out of every 8. Locking to a gapped clock will not

trigger the LOS, OOF, and LOL fault monitors. Clock

switching between gapped clocks may violate the

hitless switching specification in Table 8 when the

switch occurs during a gap in either input clocks.

4.7. Fault Monitoring

All four input clocks (IN0, IN1, IN2, IN3) are monitored

for loss of signal (LOS) and out-of-frequency (OOF) as

shown in Figure 1 2. The reference at the XA/XB pins is

also monitored for LOS since it provides a critical

reference clock for the DSPLLs. Each of the DSPLLs

also has a Loss Of Lock (LOL) indicator, which is

asserted when synchronizati on is lost with their selected

input clock.

DSPLL

100 ns 100 ns

12345678910 123456789

100 MHz clock

1 missing period every 10 90 MHz non-gapped clock

10 ns 11.11111... ns

Gapped Input Clock Periodic Output Clock

Period Removed

Si5347/46

Preliminary Rev. 0.9 27

Figure 12. Si5347/46 Fault Monitors

4.7.1. Input LOS Detection

The loss of sign al monitor measur es the period of each input clock cycle to detect phase irregularities or missing

clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing

edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS

status for each of the monitors is accessible by reading a status register. The live LOS register always displays the

current LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS

monitors is also available.

Figure 13. LOS Status Indicators

Si5347

IN3

OSC

LOS

DSPLL A

PD LPF

÷M

LOL

DSPLL B

PD LPF

÷M

LOL

DSPLL C

PD LPF

÷M

LOL

DSPLL D

PD LPF

÷M

LOL

IN1

IN2

IN0

Precision

Fast

OOF

LOS

Precision

Fast

OOF

LOS

Precision

Fast

OOF

LOS

Precision

Fast

OOF

LOS

÷P0n

P0d

÷P1n

P1d

÷P2n

P2d

÷P3n

P3d

LOS

Monitor

LOS

Sticky

Live

Si5347/46

28 Preliminary Rev. 0.9

4.7.2. XA/XB LOS Detection

A LOS monitor is available to ensure that the external

crystal or reference clock is valid. By default the output

clocks are disabled when XAXB_LOS is detected. This

feature can be disabled such that the device will

continue to produce output clocks when XAXB_LOS is

detected.

4.7.3. OOF Detection

Each input clock is monitored for frequency accuracy

with respect to a OOF reference which it considers as

its “0_ppm” reference.

This OOF reference can be selected as either:

XA/XB pins

Any input clock (IN0, IN1, IN2, IN3)

The final OOF status is determined by the combination

of both a precise OOF monitor and a fast OOF monitor

as shown in Figure 14. An option to disable either

monitor is also available. The live OOF register always

displays the current OOF state and its sticky register bit

stays asserted until cleared.

Figure 14. OOF Status Indicator

4.7.3.1. Precision OOF Monitor

The precision OOF monitor circuit measures the

frequency of all input clocks to within ±1 ppm accuracy

with respect to the selected OOF frequency reference.

A valid input clock frequency is one that remains within

the OOF frequency range which is register configurable

from ±2 ppm to ±500 ppm in steps of 2 ppm. A

configurable amount of hysteresis is also available to

prevent the OOF status from toggling at the failure

boundary. An example is shown in Figure 15. In this

case the OOF monitor is configured with a valid

frequency range of ±6 ppm and with 2 ppm of

hysteresis. An option to use one of the input pins (IN0 –

IN3) as the 0 ppm OOF reference instead of the XA/XB

pins is available. This option is register-configurable.

Figure 15. Example of Precise OOF Monitor Assertion and De-assertion Triggers

4.7.3.2. Fast OOF Monitor

Because the precision OOF monitor needs to provide

1 ppm of frequency measurement accuracy, it must

measure the monitored input clock frequencies over a

relatively long period of time. This may be too slow to

detect an input clock that is quickly ramping in

frequency. An additional lev el of OOF monitoring called

the Fast OOF monitor runs in parallel with the precision

OOF monitors to quickly detect a ramping input

frequency. The Fast OOF monitor asserts OOF on an

input clock frequency that has changed by greater than

±4000 ppm.

4.7.4. LOL Detection

There is a loss of lock (LOL) monitor for each of the

DSPLLs. The LOL monitor asserts a LOL register bit

when a DSPLL has lost synchronization with its

selected input clock. There is also a dedicated loss of

lock pin that reflects the loss of lock condition for each

of the DSPLLs (LOL_A, LOL_B, LOL_C, LOL_D). The

LOL monitor functions by measuring the frequency

difference between the input and feedback clocks at the

phase detector. There are two LOL frequency monitors,

one that sets the LOL indicator (LOL Set) and another

that clears the indicato r (LOL Clear ). An optional timer is

available to delay clearing of the LOL indicator to allow

additional time for the DSPLL to completely lock to the

Precision

Fast

OOF

Monitor

LOS

OOF

Sticky

Live

OOF

Reference

Hysteresis Hysteresis

OOF Declared

OOF Cleared -6 ppm

(Set) -4 ppm

(Clear) 0 pp m +4 ppm

(Clear) +6 ppm

(Set)

fIN

Si5347/46

Preliminary Rev. 0. 9 29

input clock. The timer is also useful to prevent the LOL

indicator from toggling or chattering as the DSPLL

completes lock acquisition. A block diagram of the LOL

monitor is shown in Figure 16. The live LOL register

always displays the current LOL state and a sticky

pin reflects the current state of the LOL monitor.

Figure 16. LOL Status Indicators

Each of the LOL frequency monitors has adjustable

sensitivity which is register configurable from 0.2 ppm to

20000 ppm. Having two separate frequency monitors

allows for hysteresis to help prevent chattering of LOL

status. An example configuration where LOCK is

indicated when there is less than 0.2 ppm frequency

diff erence at the inp uts of the phase dete ctor and LOL is

indicated when there’s more than 2 ppm frequency

difference is shown in Figure 17.

Figure 17. LOL Set and Clear Thresholds

An optional timer is available to delay clearing of the

LOL indicator to allow additional time for the DSPLL to

completely lock to the input clock. The timer is also

useful to prevent the LOL indicator from toggling or

chattering as the DSPLL completes lock acquisition.

The configurable delay value depends on frequency

configuration and loop bandwidth of the DSPLL and is

automatically calculated using the ClockBuilder Pro

utility.

4.7.5. Interrupt Pin (INTR)

An interrupt pin (INTR) indicates a chan ge in state with

any of the status indicators for any of the DSPLLs. All

status indicators are maskable to prevent assertion of

the interrupt pin. The state of the INTR pin is reset by

clearing the sticky status registers.

LOS

LOL Status Registers

Sticky

Live

DSPLL B

PD LPF

÷M

LOL Monitor DSPLL A

DSPLL C

DSPLL D

LOL_A

LOL_B

LOL_C

LOL_D

DSPLL A

LOL

Clear

LOL

Set

fIN

Si5347

Phase Detector Frequency Difference (ppm)

Hysteresis

LOL

LOCKED

Clear LOL

Threshold Set LOL

ThresholdLock Acquisition

Lost Lock

20,0000.2 2

Si5347/46

30 Preliminary Rev. 0.9

4.8. Outputs

The Si5347 support s eight dif fer ential output dr ivers and

the Si5346 support s four. Each driver has a configurable

voltage swing and common mode voltage covering a

wide variety of differential signal formats including

LVPECL, LVDS, and CML. In addition to supporting

diff er entia l signals, any of the output s can be configured

as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V)

providing up to 16 single-ended outputs, or any

combination of differential and single-ended outputs.

4.8.1. Output Crosspoint

A crosspoint allows any of the output drivers to connect

with any of the DSPLLs as shown in Figure 18. The

crosspoint configuration is programmable and can be

stored in NVM so that the desired output configuration is

ready at power up.

Figure 18. DSPLL to Output Driver Crosspoint

Si5347 Output

Crosspoint

DSPLL

OUT0

÷R0

VDDO0

÷R1OUT1

VDDO1

OUT1

OUT2

VDDO2

OUT2

÷R2

÷R3OUT3

VDDO3

OUT3

÷R4OUT4

VDDO4

OUT4

÷R5OUT5

VDDO5

OUT5

÷R6OUT6

VDDO6

OUT6

÷R7OUT7

VDDO7

OUT7

Si5347/46

Preliminary Rev. 0. 9 31

4.8.2. Differential Output Terminations

Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling

standards.

The differential output drivers supp ort both ac coupled and dc coupled terminations as shown in Figure 19.

Figure 19. Supported Differential Output Terminations

4.8.3. LVCMOS Outpu t Termination s

LVCM O S out puts are dc-co u ple d as shown in Figure 20.

Figure 20. LVCMOS Output Terminations

4.8.4. Output Signal Format

The differential output swing and common mode voltage are both fully programmable and compatible with a wide

variety of signal formats, including LVDS and LVPECL. In addition to supporting differential signals, any of the

outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 20 single-ended outputs or

any combination of differential and single-ende d outputs.

4.8.5. Differential Output Swing Modes

There are two selectable differential output swing modes: Normal and high swing. Each output can support a

unique mode.

Differential Normal Swing Mode: When an output driver is configured in normal swing mode, its output

swing is selectable as one of 7 settings ranging from 200 mVpp_se to 800 mVpp_se in increments of

100 mV. The output impedance in the Normal Swing Mode is 100differentialAny of the termination s

shown in Figure 19 is supported in this mode.

100

Internally

self-biased

AC Coupled LVDS/LVPECL

AC Coupled LVPECLVDD – 1.3V

5050

100

DC Coupled LVDS/LVPECL

OUTx

VDDO = 3.3V, 2.5V, 1.8V VDDO = 3.3V, 2.5V

VDDO = 3.3V, 2.5V, 1.8V

Si5347/46

Si5347/46 Si5347/46

3.3V, 2.5V, 1.8V

LVCMOS

VDDO = 3.3V, 2.5V, 1.8V

OUTx

Si5347/46

32 Preliminary Rev. 0.9

Differential Low Powe r Mode: When an output driver is configured in low power mode, its output swing is

configurable as one of 7 settings ranging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV.

The output driver is in high impedance mode and suppor ts standard 50 PCB traces. Any of the

terminations shown in Figure 19 is supported in this mode.

4.8.6. Programmable Common Mode Voltage For Differential Outputs

The common mode voltage (VCM) for the differential Normal and Low Power modes is programmable in 100 mV

increments from 0.7 V to 2.3 V depending on the voltage available at the output’s VDDO pin. Setting the common

mode voltage is useful when DC coupling the output drivers.

4.8.7. LVCMOS Output Impedance Selection

Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive

strengths. A source termination resistor is recommended to help match the selected output impedance to the trace

impedance. There are three programmable output impedance selections (CMOS1, CMOS2, CMOS3) for each

VDDO options as show n in Table 14.

4.8.8. LVCMOS Output Sig n al Swing

The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output

driver has its own VDDO pin allowing a unique output voltage swing for each of the LV CMOS drivers. Each output

driver automatically detects the voltage on the VDDO pin to properly determine the correct output voltage.

4.8.9. LVCMOS Outp u t Po la rity

When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTx). By

default the clock on the OUTx pin is generated with the same polarity (in phase) with the clock on the OUTx pin.

The polarity of these clocks is configurable enabling complimentary clock generation and/or inverted polarity with

respect to othe r outp ut drive rs .

4.8.10. Output Enable/Disable

The Si5347/46 allows enabling/disabling outputs by pin or register control, or a combination of both. Two output

enable pins are available (OE0, OE1). The output enable pins can be mapped to any of the outputs (OUTx)

through register con figur ation. By defa ult OE0 controls all of the output s while OE1 re main s u nmapp ed a nd has no

affect until configured. Figure 21 shows an example of a output enable mapping scheme that is register

configurable and can be stored in NVM as the default at power-up.

Enabling and disabling outputs can also be controlled by register control. This allows disabling one or more output

when the OE pin(s) has them ena bled. By de fault the outpu t enable r egister settings ar e configured to allow the OE

pins to have full control.

Table 14. Typical Output Impedance (ZS)

CMOS_DRIVE_Selection

VDDO CMOS1 CMOS2 CMOS3

3.3 V 38 30 22 

2.5 V 43 35 24 

1.8 V — 46 31 

Si5347/46

Preliminary Rev. 0. 9 33

Figure 21. Example of Configuring Output Enable Pins

4.8.11. Output Disable During LOL

By default a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode.

There is an option to disable the outputs when a DSPLL is out of lock (LOL). This option can be useful to force a

downstream PLL into holdover.

4.8.12. Outp u t Dis a bl e During XAXB_LOS

The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for

the operation of the DSPLLs. In the event of a crystal failure the device will assert an XAXB_LOS alarm. By default

all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the outputs

enabled during an XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault

condition.

4.8.13. Outp u t Driv er State When Disabled

The disabled state of an output driver is register configurable as: disable low, disable high, or disable high-

impedance.

4.8.14. Synchronous/Asynchronous Output Disable

Outputs can be configured to disable synchronously or asynchronously. In synchronous disable mode the output

will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from

occurring when disabling an output. In asynchronous disable mode the output clock will disable immediately

without waiting for the period to comple te.

4.8.15. Output Divider (R) Synchronization

All the output R dividers are reset to a known state during the power-up initialization period. This ensures

consistent and repeatable phase alignment across all output drivers. Resetting the device using the RST pin or

asserting the hard reset bit will have the same result.

Si5346

OUT0

OUT1

OUT2

OUT3

OUT1

OUT2

OUT3

÷R0

÷R1

÷R2

÷R3

Output

Crosspoint

OE0

DSPLL

OE1

In its default state the OE0 pin enables/

disables all outputs. The OE1 pin is not

mapped and has no effect on outputs.

An example of an configurable output enable

scheme. In this case OE0 controls the outputs

associated with DSPLL A, while OE1 controls

the outputs of DSPLL B.

Si5346

OUT0

OUT1

OUT2

OUT3

OUT1

OUT2

OUT3

÷R0

÷R1

÷R2

÷R3

Output

Crosspoint

DSPLL

OE0

OE1

Si5347/46

34 Preliminary Rev. 0.9

4.9. Power Management

Unused inputs, output drivers, and DSPLLs can be

powered down when unused. Consult the Si5347/46

Family Reference Manual and ClockBuilder Pro

configuration utility for details.

4.10. In-Circuit Programming

The Si5347/46 is fully configurable using the serial

interface (I2C or SPI). At power-up the device

downloads its default register values from internal non-

volatile memory (NVM). Application specific default

configurations can be written into NVM allowing the

device to generate specific clock frequencies at power-

up. Writing default values to NVM is in-circuit

programmable with normal operating power supply

voltages applied to its VDD and VDDA pins. The NVM is

two time writable. Once a new configuration has been

written to NVM, the old configuration is no longer

accessible. Refer to the Si5347/46 Family Reference

Manual for a detailed procedure for writing registers to

NVM.

4.11. Serial Interface

Configuration and operation of the Si5347/46 is

controlled by reading and writing registers using the I2C

or SPI interface. The I2C_SEL pin selects I2C or SPI

operation. Communication with both 3.3V an d 1 .8V ho st

is supported. The SPI mode operates in either 4-wire or

3-wire. See the Si5347/46 Family Reference Manual for

details.

4.12. Custom Factory Preprogrammed

Parts

For applications where a serial interface is not available

for programming the device, custom pre-programmed

parts can be ordered with a specific configuration

written into NVM. A factory pre-programmed part will

generate clocks at power-up. Custom, factory-

preprogrammed devices are available. Use the

ClockBuilder Pro custom part number wizard

(www.silabs.com/clockbuilderpro) to quickly and easily

request and generate a custom part number for your

configuration.

In less than three minutes, you will be able to generate

a custom part number with a detailed data sheet

addendum matching your design’s configuration. Once

you receive the confirmation email with the data sheet

addendum, simply place an order with your local Silicon

Labs sales representative. Samples of your pre-

programmed device will ship to you within two weeks.

Si5347/46

Preliminary Rev. 0. 9 35

5. Register Map

The register map is divided into multiple pages where

each page has 256 addressable registers. Page 0

contains frequently accessible register such as alarm

status, resets, device identification, etc. Other pages

contain registers that need less fre quent access such as

frequency configuration, and general device settings. A

high level map of the registers is shown in Table 15.

Refer to the Si5347/46 Family Reference Manual for a

complete list of register descriptions and settings.

5.1. Addressing Scheme

The device registers are accessible using a 16-bit

address which consists of an 8-bit page address +8-bit

0x00. Changing to another page is accomplished by

writing to the “Set Page Address” byte located at

address 0x01 of ea ch page.

Table 15. High-Level Register Map

16-Bit Address Content

8-bit Page

Address 8-bit Register

Address Range

00 00 Revision IDs

01 Set Page Address

02 - 0A Device IDs

0B–15 Alarm Status

17–1B INTR Masks

1C Reset controls

2C–E1 Alarm Configuration

E2–E4 NVM Controls

FE Device Ready Status

01 01 Set Page Address

08–3A Output Driver Controls

41–42 Output Driver Disable Masks

FE Device Ready Status

02 01 Set Page Address

02–05 XTAL Frequency Adjust

08–2F Input Divider (P) Settings

47–6A Outpu t Divider (R) Settings

6B–72 User Scratch Pad Memory

FE Device Ready Status

03 01 Reserved

Si5347/46

36 Preliminary Rev. 0.9

04 01 Set Page Address

08–0D DSPLL_A Bandwidth Setting

0E–13 DSPLL_A Fastlock Bandwidth Setting

15–1F DSPLL_A Feedback Divider Setting (MA)

23–29 DSPLL_A FINC/FDEC Settings

36, 38–39 DSPLL_A Input Switching Controls

FE Device Ready Status

05 01 Set Page Address

08–0D DSPLL_B Bandwidth Setting

0E–13 DSPLL_B Fastlock Bandwidth Setting

15–1F DSPLL_B Feedback Divider Setting (MA)

23–29 DSPLL_B FINC/FDEC Settings

36, 38–39 DSPLL_B Input Switching Controls

FE Device Ready Status

06 01 Set Page Address

08–0D DSPLL_C Bandwidth Setting

0E–13 DSPLL_C Fastlock Bandwidth Setting

15–1F DSPLL_C Feedback Divider Setting (MA)

23–29 DSPLL_C FINC/FDEC Settings

36, 38–39 DSPLL_C Input Switching Controls

FE Device Ready Status

07 01 Set Page Address

09–0E DSPLL_D Bandwidth Setting

0F–14 DSPLL_D Fastlock Bandwidth Setting

16- 20 DSPLL_D Feedback Divider Setting (MA)

24–2A DSPLL_D FINC/FDEC Settings

37, 39–3A DSPLL_D Input Switching Controls

FE Device Ready Status

09 01 Set Page Address

49 Input Settings

0A–FF 00–FF Reserved

Table 15. High-Level Register Map (Continued)

16-Bit Address Content

8-bit Page

Address 8-bit Register

Address Range

Si5347/46

Preliminary Rev. 0. 9 37

6. Pin Descriptions

GND

Pad

IN1

INTR

LOL_A

LOL_B

I2C_SEL

OE0

VDDA

IN2

SDA/SDIO

A1/SDO

VDD

RSVD

VDDO0

OUT0

LOS_XAXB

DSPLL_SEL0

A0/CS

VDDO1

OUT1

FINC

LOL_D

VDD

OUT4

VDDO4

FDEC

OE1

VDDS

OUT3

VDDO3

OUT2

VDDO2

VDDO5

OUT5

VDDO6

OUT6

RSVD

VDDO7

OUT7

VDD

IN3

IN0

Si5347 64QFN

Top View

LOL_C

RST

SCLK

DSPLL_SEL1

GND

Pad

IN1

OE0

INTR

VDDA

IN2

A0/CS

SDA/SDIO

A1/SDO

OUT0

VDDO0

SCLK

I2C_SEL

OUT1

VDDO1

VDDO3

OUT3

IN3

IN0

Si5346 44 QFN

Top View

VDD

OUT2

VDDO2

VDDS

LOL_B

LOS_XAXB

VDD

OE1

IN2 11 23

NC 22

VDD

RST

LOL_A

Si5347/46

38 Preliminary Rev. 0.9

Table 16. Si5347/46 Pin Descriptions

Name Pin Number Pin

Type1Function

Si5347 Si5346

Inputs

XA 8 5 I Crys tal Input. Input pin for external crystal (XTAL). Alternatively

these pins can be drive n with an ex te rn al re fe re nc e clock (REF-

CLK). An internal register bit selects XTAL or REFCLK mode.

Default is XTAL mode.

XB 9 6 I

X1 7 4 I XTAL Ground. Connect these pins directly to the XTAL ground

pins. X1, X2 and the XTAL ground pins should be separated from

the PCB ground plane. Refer to the Si5347/46 Family Reference

Manual for layout guidelines. These pins should be left discon-

nected when connec tin g XA/XB pins to an external reference clock

(REFCLK).

X2 10 7 I

IN0 63 43 I Clock Inputs. Th es e pin s acc ep t an inpu t cloc k for sync hr on izin g

the device. They support both differential and single-ended clock

signals. Refer to “4.6.4. Input Configuration and Terminations” for

input termination option s. These pins are high-impeda nce and must

be terminated externally. The negative side of the differential input

must be grounded when accepting a single-ended clock.

IN0 64 44 I

IN1 1 1 I

IN1 22I

IN2 14 10 I

IN2 15 11 I

IN3 61 41 I

IN3 62 42 I

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.

3. The voltage on the VDDS pin(s) dete rmines 3.3 V or 1.8 V operation.

Si5347/46

Preliminary Rev. 0. 9 39

Outputs

OUT0 24 20 O Output Clocks. These ou tput clocks support a programmable sig-

nal swing and common mode voltage. Desired output signal format

is configurable using register control. Termination reco mmendations

are provided in “4.8.2. Dif f erential Output Terminations” and “4.8.3.

LVCMOS Output Terminations” Unused outputs should be left

unconnected.

OUT0 23 19 O

OUT1 31 25 O

OUT1 30 24 O

OUT2 35 31 O

OUT2 34 30 O

OUT3 38 36 O

OUT3 37 35 O

OUT4 45 —O

OUT4 44 —O

OUT5 51 —O

OUT5 50 —O

OUT6 54 —O

OUT6 53 —O

OUT7 59 —O

OUT7 58 —O

Table 16. Si5347/46 Pin Descriptions (Continued)

Name Pin Number Pin

Type1Function

Si5347 Si5346

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.

3. The voltage on the VDDS pin(s) dete rmines 3.3 V or 1.8 V operation.

Si5347/46

40 Preliminary Rev. 0.9

Serial Interface

I2C_SEL 39 38 I I2C Select. This pin selects the serial interface mode as I2C

(I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally pulled

high. See note 2.

SDA/SDIO 18 13 I/O Serial Data Interface. This is the bidirectional data pin (SDA) for the

I2C mode, or the bidir ectional data pin (SDIO) in the 3-wire SPI

mode, or the input data pin (SDI) in 4-wire SPI mode. When in I2C

mode, this pin must be pulled-up using an external resistor of at

least 1 k. No pull-up resistor is needed when is SPI mode. See

Note 2.

A1/SDO 17 15 I/O Address Select 1/Serial Data Output. In I2C mode this pin functions

as the A1 address input pin. In 4-wire SPI mode this is the serial

data output (SDO) pin. See Note 2.

SCLK 16 14 I Serial Clock Input. This pin functions as the serial clock input for

both I2C and SPI modes. When in I2C mode, this pin must be

pulled-up using an external resistor of at least 1 k. No pull-up

resistor is needed when in SPI mode. See Note 2.

A0/CS 19 16 I Address Select 0/Chip Select. This pin functions as the hardware

controlled address A0 in I2C mode. In SPI mode, this pin functions

as the chip select input (active low). This pin is internally pulled-up.

See Note 2.

Table 16. Si5347/46 Pin Descriptions (Continued)

Name Pin Number Pin

Type1Function

Si5347 Si5346

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.

3. The voltage on the VDDS pin(s) dete rmines 3.3 V or 1.8 V operation.

Si5347/46

Preliminary Rev. 0. 9 41

Control/Status

INTR 12 17 O Interrupt. This pin is asserted low when a change in device status

has occurred. This pin must be pulled-up using an external resistor

of at least 1 k. It should be left unconnecte d wh en no t in use. See

Note 2.

RST 63I

Device Reset. Active low input that performs power-on reset (POR)

of the device. Resets all internal logic to a known state and forces

the device registers to their default values. Clock outputs are

disabled during reset. This pin is internally pulled-up. See Note 2.

OE0 11 12 I Output Enable 0. This pin is used to enable (when held low) and

disable (when held high) the output clocks. By default this pin co n-

trols all outputs. It can also be configured to control a subset of out-

puts. See section 4.8.10 for details. This pin is internally pulled-

down. See Note 2.

OE1 41 —Output Enable 1. (Si5347) This is an additional output enable pin

that can be configured to control a subset of outputs. By default it

has no control on the outputs until configured. See section 4.8.10

for details. There is no internal pull-up/pull-down for this pin. See

Note 3.

—37 Output Enable 1. (Si5346) This is an additional output enable pin

that can be configured to control a subset of outputs. By default it

has no control on the outputs until configured. See section 4.8.10

for details. This pin is internally pulled-down. See Note 2.

LOL_A 328OLoss Of Lock_A/B/C/D. These output pins indicate when DSPLL

A, B, C, D is out-of-lock (low) or locked (high). They can be left

unconnected when not in use. Si5347: See Note 2, Si5346: See

Note 3.

LOL_B 427O

LOL_C 5—O

LOL_D 47 —O

LOS_XAXB 25 33 O Status Pins. This pin indicates a loss of signal alarm on the XA/XB

pins. This either indicates a XTAL failure or a loss of external signal

on the XA/XB pins. This pin can be left unconnected when unused.

Si5347: See note 3, Si5346: See Note 2.

DSPLL_SEL0 26 —IDSPLL Select Pins (Si5347 only). These pins are used in conjunc-

tion with the FINC and FDEC pins. The DSPLL_SEL[1:0] pins deter-

mine which DSPLL is affected by a frequency change using the

FINC and FDEC pins. See section 4.4 for details. These pins are

internally pulled-down. See Note 2.

DSPLL_SEL1 27 —I

Table 16. Si5347/46 Pin Descriptions (Continued)

Name Pin Number Pin

Type1Function

Si5347 Si5346

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.

3. The voltage on the VDDS pin(s) dete rmines 3.3 V or 1.8 V operation.

Si5347/46

42 Preliminary Rev. 0.9

FDEC 42 —IFrequency Decrement Pin (Si5347 only). This pin is used to step-

down the output frequency of a selected DSPLL. The frequency

change step size is register configurable. The DSPLL that is

affected by the frequency change is determined by the DSPLL_-

SEL[1:0] pins. See Note 2.

FINC 48 —IFrequency Increment Pin (Si5347 only). This pin is used to step-

up the output frequency of a selected DSPLL. The frequency

change step size is register configurable. The DSPLL that is

affected by the frequency change is determined by the DSPLL_-

SEL[1:0] pins. See Note 2.

RSVD 20 ——

Reserved. These pins are connected to the die. Leave discon-

nected.

21 ——

55 ——

56 ——

NC 28 22 —No Connect. These pins are not connected to the die. Leave dis-

connected.

Table 16. Si5347/46 Pin Descriptions (Continued)

Name Pin Number Pin

Type1Function

Si5347 Si5346

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.

3. The voltage on the VDDS pin(s) dete rmines 3.3 V or 1.8 V operation.

Si5347/46

Preliminary Rev. 0. 9 43

Power

VDD 32 21 P Core Supply Voltage. The device core operates from a 1.8 V sup-

ply.

46 32

60 39

—40

VDDA 13 8 P Core Supply Voltage 3.3V. This core supply pin requires a 3.3 V

power source.

—9P

VDDS 40 26 P Status Output Voltage. The voltage on this pin determines the

VOL/VOH on some of the output status pins and VIL/VIH for some

control input pins. Connect to 3.3 V or 1.8 V. A 0.1 uF bypass

capacitor should be placed very close to this pin.

VDDO0 22 18 P Output Clock Supply Voltage 0–7. Supply voltage (3.3 V, 2.5 V.

1.8 V) for OUTn, OUTn outputs. A 0.1 uF bypass capacitor should

be placed very close to this p in. Leave VDDO pins of unused output

drivers unconnected. An alternate option is to connect the VDDO

pin to a power supply and disable the output driver to minimize cur-

rent consumption.

VDDO1 29 23 P

VDDO2 33 29 P

VDDO3 36 34 P

VDDO4 43 —P

VDDO5 49 —P

VDDO6 52 —P

VDDO7 57 —P

GND PAD ——PGround Pad. This pad provides connection to ground and must be

connected for proper operation.

Table 16. Si5347/46 Pin Descriptions (Continued)

Name Pin Number Pin

Type1Function

Si5347 Si5346

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.

3. The voltage on the VDDS pin(s) dete rmines 3.3 V or 1.8 V operation.

Si5347/46

44 Preliminary Rev. 0.9

7. Ordering Guide

Ordering Part

Number Number Of

DSPLLs Output Clock

Frequency Range Package RoHS-6,

Pb-Free Temperature

Range

Si5347A-A-GM1,2 40.0001 to 800 MHz 64-Lead 9x9 QFN

Yes –40 to 85 °C

Si5347B-A-GM1,2 0.0001 to 350 MHz

Si5346A-A-GM1,2 20.0001 to 800 MHz 44-Lead 7x7 QFN

Si5346B-A-GM1,2 0.0001 to 350 MHz

Si5347-EVB ——

Evaluation Board ——

Si5346-EVB —— ——

Notes:

1. Add an R at the end of the device part number to denot e tape and reel ordering options.

2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by Sil icon Labs. Part

number format is: Si5347A-Axxxxx-GM or Si5346A-Axxxxx-GM, where “xxxxx” is a unique numerical sequence

representing the pre-programmed configuration.

Si5347/46

Preliminary Rev. 0. 9 45

8. Package Outlines

8.1. Si5347 9x9 mm 64-QFN Package Diagram

Figure 22 illustrates the package details for the Si5347. Table 17 lists the values for the dimensions shown in the

illustration.

Figure 22. 64-Pin Quad Flat No-Lead (QFN)

Table 17. Package Dimensions

Dimension Min Nom Max

A0.800.850.90

A1 0.00 0.02 0.05

b0.180.250.30

D 9.00 BSC

D2 5.10 5.20 5.30

e 0.50 BSC

E 9.00 BSC

E2 5.10 5.20 5.30

L0.300.400.50

aaa — — 0.10

bbb — — 0.10

ccc — — 0.08

ddd — — 0.10

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

Si5347/46

46 Preliminary Rev. 0.9

8.2. Si5346 7x7 mm 44-QFN Package Diagram

Figure 23 illustrates the package details for the Si5346. Table 18 lists the values for the dimensions shown in the

illustration.

Figure 23. 44-Pin Quad Flat No-Lead (QFN)

Table 18. Package Dimensions

Dimension Min Nom Max

A0.800.850.90

A1 0.00 0.02 0.05

b0.180.250.30

D 7.00 BSC

D2 5.10 5.20 5.30

e 0.50 BSC

E 7.00 BSC

E2 5.10 5.20 5.30

L0.300.400.50

aaa — — 0.10

bbb — — 0.10

ccc — — 0.08

ddd — — 0.10

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.



Si5347/46

Preliminary Rev. 0. 9 47

9. PCB Land Pattern

Figure 24 illustrates the PCB land pattern details for the devices. Table 19 lists the values for the dimensions

shown in the illustration.

Figure 24. PCB Land Pattern



Si5347 Si5346

Si5347/46

48 Preliminary Rev. 0.9

Table 19. PCB Land Pattern Dimensions

Dimension Si5347 (Max) Si5346 (Max)

C1 8.90 6.90

C2 8.90 6.90

E 0.50 0.50

X1 0.30 0.30

Y1 0.85 0.85

X2 5.30 5.30

Y2 5.30 5.30

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 gu idelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least

Material Condition is calculated based on a fabrication Allowance of 0.05 mm.

Solder Mask Design

4. All metal pads are to be non-solder mask defined (NSMD). Clearance

between the solder mask an d the metal pad is to be 60 µm minimum, all the

way around the pad.

Stencil Design

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls

should be used to assure good solder paste release.

6. The stencil thickness should be 0.125 mm (5 mils).

7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter

pads.

8. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for

the center ground pad.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

Si5347/46

Preliminary Rev. 0. 9 49

10. Top Marking

Line Characters Description

1 Si5347g-

Si5346g- Base part number and Device Grade.

Si5347: Quad PLL; 64-QFN

Si5346: Dual PLL; 44-QFN

g = Device Grade. See Ordering Guide for more information.

– = Dash character.

2 Axxxxx-GM A = Product revision.

xxxxx = Customer specific NVM sequence number. (Optional NVM

code assigned for custom, factory pre -programme d devices. Charac-

ters are not included for standard, factory default configured

devices). See "7. Ordering Guide" on page 44 for more information.

-GM = Package (QFN) and temperature range (–40 to +85 °C).

3 YYWWTTTTTT YYWW = Characters correspond to the year (YY) and work week

(WW) of package assemb ly.

TTTTTT = Manufacturing trace code.

4 Circle w/ 1.6 mm (64-QFN) or

1.4 mm (44-QFN) diameter Pin 1 indicator; left-justified

TW Pb-free symbol; Center-Justified

TW = Taiwan; Country of Origin (ISO Abbreviation)

YYWWTTTTTT

Axxxxx-GM

Si5347g-

e4 TW

YYWWTTTTTT

Axxxxx-GM

Si5346g-

Si5347/46

50 Preliminary Rev. 0.9

11. Device Errata

Please log in or register at www.silabs.com to access the device errata document.

Si5347/46

Preliminary Rev. 0. 9 51

APPENDIX—ADVANCE PRODUCT INFORMATION REVISION HISTORY

Table 20 lists the advance product information revision history.

Table 20. Advance Product Information Revision History

Revision Change Description Date

0.10 First draft Aug 2012

0.12 Swapped two serial interface pins

SCLK 17 to 19

A1/SDO 19 to 17

Updated the Serial Interface Section (3.5)

Updated Section 2

Updated Table 9, 10

Added Table 11, 12

Added Figure 2, 3

Aug 2012

0.13 Added Pull-in specification

Other minor edits Dec 2012

0.20 Combined Si5347 and Si5346 datasheets

Verified pin-outs

Added package informatio n

June 2013

0.21 Finalized Pinouts

Added application diag r am

Added high level regis te r map information

Added DCO description

Added gapped clock description

Updated the seria l interface section

Aug 2013

Si5347/46

52 Preliminary Rev. 0.9

0.22 Removed OE2 and OE3 pin functions. Updated diagrams.

Added PREF divider to Fi gu re s 2, 3, 6.

Si5347 pin changes:

Renamed pin 13: VDD33 to VDDA

Renamed pins 32, 46, 60: VDD18 to VDD

Changed pin 3 from INTR to LOL_A

Changed pin 4 from LOL_A to LOL_ B

Changed pin 5 from LOL_B to LOL_ C

Changed pin 6 from I2C_SEL to RST

Changed pin 11 from LOL_C to OE0

Changed pin 12 from OE0 to INTR

Changed pin 16 from OE1 to SCLK

Changed pin 19 from SCLK to A0 /CS

Changed pin 20 from FINC to RSVD

Changed pin 21 from FDEC to RSVD

Changed pin 25 from OE2 to LOS_XAXB

Changed pin 26 from OE3 to DSPLL_SEL0

Changed pin 27 from A0/CS to DSPLL_SEL1

Changed pin 39 from RST to I2C_SEL

Changed pin 40 from RSVD to VDDS

Changed pin 41 from RSVD to OE1

Changed pin 42 from RSVD to FDEC

Changed pin 48 from LOS_XAXB to FINC

Changed pin 55 from OUT7 to RSVD

Changed pin 56 from OUT7 to RSVD

Changed pin 58 from DSPLL_SEL0 to OUT7

Changed pin 59 from DSPLL_SEL1 to OUT7

Si5346 pin changes:

Renamed pin 8, 9: VDD33 to VDDA

Renamed pins 21, 32, 39, 40: VDD18 to VDD

Renamed pin 26: VDD18 to VDDS

Oct 2013

0.23 Change the DCO mode granularity on the front page to 0.01 ppb steps

Corrections to the Si53 4 7 pin diagram of section 6-Pin Descriptions:

Renamed pin 28 from RSVD to NC

Corrections to the Si5347 pin list of “6. Pin Descriptions” :

Pin 11 OE0 - changed internal pull-up to interna l pull-down

Pin 41 OE1 - changed internal pull-up to internal pull-down

Pins 26 (DSPLL_SEL0) and 27 (DSPLL_SEL1) - added internal pull-down

Renamed pin 25 from LOS_XAXB to LOS_XAXB

Renamed pin 28 from RSVD to NC

Corrections to the Si5346 pin diagram of “6. Pin Descriptions” :

Renamed pin 22 from RSVD to NC

Corrections to the Si5346 pin list of “6. Pin Descriptions” :

Renamed pin 33 from LOS_XAXB to LOS_XAXB

Renamed pin 22 from RSVD to NC

Pin 12 OE0 - changed internal pull-up to internal pull-down

Pin 37 OE1 - changed internal pull-up to internal pull-down

Nov 2013

Table 20. Advance Product Information Revision History (Continued)

Revision Change Description Date

Si5347/46

Preliminary Rev. 0. 9 53

0.30 Moved the register descriptions to the Si5347/46 Reference Manual.

Moved the majority of the contents of the Serial Interface section to the

Si5347/46 Reference Manual.

Updated LVCMOS output impedance values in Table 14.

Added Control Input and Status Output table specifications.

Apr 2014

0.31 Added serial interface timing diagram s and specifications

Renamed XGND pins to X1, X2 Jun 2014

0.32 Minor edits Jun 2014

Table 20. Advance Product Information Revision History (Continued)

Revision Change Description Date

Si5347/46

54 Preliminary Rev. 0.9

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