March 1997
ML2008*, ML2009**
µP Compatible Logarithmic Gain/Attenuator
FEATURES
■Low noise 0dBrnc max with +24dB gain
■Low harmonic distortion –60dB max
■Gain range –24 to +24dB
■Resolution 0.1dB steps
■Flat frequency response ±0.05dB from 0.3-4kHz
±0.10dB from 0.1-20kHz
■Low supply current 4mA max from ±5V supplies
■TTL/CMOS compatible digital interface
■ML2008 is designed to interface to an 8-bit data bus;
ML2009 to 16-bit data bus
GENERAL DESCRIPTION
The ML2008 and ML2009 are digitally controlled
logarithmic gain/attenuators with a range of –24 to +24dB
in 0.1dB steps.
Easy interface to microprocessors is provided by an input
latch and control signals consisting of chip select and
write.
The interface for gain setting of the ML2008 is by an 8-bit
data word, while the ML2009 is designed to interface to a
16-bit data bus with a single write operation by hard-
wiring the gain/attenuation pin or LSB pin. The ML2008
can be power downed by the microprocessor utilizing a
bit in the second write operation.
Absolute gain accuracy is 0.05dB max over supply
tolerance of ±10% and temperature range.
These CMOS logarithmic gain/attenuators are designed for * This Part Is End Of Life As Of August 1, 2000
a wide variety of applications in telecom, audio, sonar or ** This Part Is Obsolete
general purpose function generation.
BLOCK DIAGRAM
+
–
+
–
+
–
RESISTORS/
SWITCHES
RESISTORS/
SWITCHES
VCC VSS GND AGND
VIN
COARSE
FINE
BUFFER VOUT
16 16
+5 –5
DECODERS
WR
CS
A0
REGISTER 0
REGISTER 1
81
1
PDN
D1–D8
8
+
–
+
–
+
–
RESISTORS/
SWITCHES
RESISTORS/
SWITCHES
VCC VSS GND AGND
VIN
COARSE
FINE
BUFFER VOUT
16 16
+5 –5
DECODERS
REGISTER 0
9
D0–D8
9
WR
CS
ML2008ML2009*
1
ML2008, ML2009
2
PIN CONFIGURATION
NAME FUNCTION
VSS Negative supply. –5Volts ±10%
VCC Positive supply. 5Volts ±10%
GND Digital ground. 0Volts. All digital
inputs are referenced to this ground.
AGND Analog ground. 0Volts. Analog input
and output are referenced to this
ground.
VIN Analog input
VOUT Analog output
D8 Data bit, ATTEN/GAIN
D7 Data bit, C3
D6 Data bit, C2
D5 Data bit, C1
D4 Data bit, C0
NAME FUNCTION
D3 Data bit, F3
D2 Data bit, PDN, F2 ML2008; F2 ML2009
D1 Data bit, F0, F1 ML2008; F1 ML2009
D0 Data bit, F0 ML2009 only
WR Write enable. This input latches the
data bits into the registers on rising
edges of WR.
CS Chip select. This input selects the
device by only allowing the WR signal
to latch in data when CS is low.
A0 Address select. This input determines
(ML2008 only) which data word is being written into
the registers.
PIN DESCRIPTION
D7
D6
D5
D4
WR
D3
D2
D1
GND
D8
VCC
VOUT
VSS
AGND
VIN
NC
CS
A0
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TOP VIEW
D8
VCC
VOUT
VSS
AGND
VIN
NC
CS
D0
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TOP VIEW
VOUT
VSS
AGND
NC
NC
D4
NC
WR
D3
D2
910111213
D5
D6
D7
D8
VCC
D1
GND
A0
CS
VIN
4
5
6
7
8
3212019
18
17
16
15
14
TOP VIEW
VOUT
VSS
AGND
NC
NC
910111213
D5
D6
D7
D8
VCC
D1
GND
D0
CS
VIN
4
5
6
7
8
3212019
18
17
16
15
14
TOP VIEW
D4
NC
WR
D3
D2
D7
D6
D5
D4
WR
D3
D2
D1
GND
ML2008
18-Pin DIP (P18)
ML2009*
18-Pin DIP (P18)
20-Pin PLCC (Q20) 20-Pin PLCC (Q20)
ML2008, ML2009
3
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage
VCC .................................................................... +6.5V
VSS ......................................................................–6.5V
AGND with Respect to GND....................... VCC to VSS
Analog Inputs and Outputs ..... VSS –0.3V to VCC +0.3V
Digital Inputs and Outputs... GND –0.3V to VCC +0.3V
Input Current Per Pin ........................................ ±25mA
Power Dissipation ........................................... 750mW
Storage Temperature Range ............... –65°C to +150°C
Lead Temperature (Soldering 10 sec.) ................. 300°C
OPERATING CONDITIONS
Temperature Range (Note 2)
ML2008CX, ML2009CX .......................... 0°C to +70°C
ML2008IX, ML2009IX ......................... –40°C to +85°C
Supply Voltage
VCC ................................................................ 4V to 6V
VSS ............................................................. –4V to –6V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, TA = TMIN to TMAX, VCC = 5V ±10%, VSS = –5V ±10%, Data Word: D8 (ATTEN/GAIN) = 1,
Other Bits = 0, (0dB Ideal Gain), CL = 100pF, RL = 600Ω, dBm measurements use 600Ω as reference load, digital timing
measured at 1.4V.
SYMBOL PARAMETER NOTES CONDITIONS MIN TYP MAX UNITS
NOTE 3
Analog
AG Absolute Gain Accuracy 4 VIN = 8dBm, 1kHz –0.05 +0.05 dB
RG Relative Gain Accuracy 4 100000001 –0.05 +0.05 dB
000000000 –0.05 +0.05 dB
000000001 –0.05 +0.05 dB
All other gain settings –0.1 +0.1 dB
All values referenced to 100000000
gain when D8 (ATTEN/GAIN) = 1,
VIN = 8dBm when D8 (ATTEN/GAIN) = 0,
VIN = (8dBm – Ideal Gain) in dB
FR Frequency Response 4 300-4000Hz –0.05 +0.05 dB
100-20,000Hz –0.1 +0.1 dB
Relative to 1kHz
VOS Output Offset Voltage 4 VIN = 0, +24dB gain ±100 mV
ICN Idle Channel Noise 4 VIN = 0, +24dB, C msg weighted –6 0 dBrnc
5V
IN = 0, +24dB, 1kHz 450 900 nv/√Hz
HD Harmonic Distortion 4 VIN = 8dBm, 1kHz –60 dB
Measure 2nd, 3rd, harmonic relative
to fundamental
SD Signal to Distortion 4 VIN = 8dBm, 1kHz +60 dB
C msg weighted
PSRR Power Supply Rejection 4 200mVP-P, 1kHz sine, VIN = 0
on VCC –60 –40 dB
on VSS –60 –40 dB
ZIN Input Impedance, VIN 4 1 Meg
VINR Input Voltage Range 4 ±3.0 V
VOSW Output Voltage Swing 4 ±3.0 V
ML2008, ML2009
4
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER NOTES CONDITIONS MIN TYP MAX UNITS
NOTE 3
Digital and DC
VIL Digital Input Low Voltage 4 0.8 V
VIH Digital Input High Voltage 4 2.0 V
IIN Input Current, Low 4 VIH = GND –10 µA
IIN Input Current, High 4 VIH = VCC 10 µA
ICC VCC Supply Current 4 No output load, VIL = GND, 4 mA
VIH = VCC, VIN = 0
ISS VSS Supply Current 4 No output load, VIL = GND, –4 mA
VIH = VCC, VIN = 0
ICCP VCC Supply Current, ML2008 4 No output load, VIL = GND, 0.5 mA
Powerdown Mode Only VIH = VCC
ISSP VSS Supply Current, ML2008 4 No output load, VIL = GND, –0.1 mA
Powerdown Mode Only VIH = VCC
AC Characteristics
tSET VOUT Settling Time 4 VIN = 0.185V. Change gain from –24 20 µs
to +24dB. Measure from WR rising
edge to when VOUT settles to within
0.05dB of final value.
tSTEP VOUT Step Response 4 Gain = +24dB. VIN = –3V to +3V step. 20 µs
Measure from VIN = –3V to when VOUT
settles to within 0.05dB of final value.
tDS Data Setup Time 4 50 ns
tDH Data Hold Time 4 50 ns
tAS A0 Setup Time 4 0 ns
tAH A0 Hold Time 4 0 ns
tCSS CS* Setup Time 4 0 ns
tCSH CS* Hold Time 4 0 ns
tPW WR* Pulse Width 4 50 ns
Note 1: Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with
respect to ground.
Note 2: 0°C to +70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by
correlation with worst-case test conditions.
Note 3: Typicals are parametric norm at 25°C.
Note 4: Parameter guaranteed and 100% production tested.
Note 5: Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
ML2008, ML2009
5
TIMING DIAGRAM
D0-D8
A0
DATA
VALID
tDS tDH
tAHtAS
tCSS tCSH
tPW
CS
WR
TYPICAL PERFORMANCE CURVES
0
–0.5
–.10
–.15
–.20
–.25
–.30
–.35
–.40
–.45
–.50
100 1K 10K 100K
AMPLITUDE (dB)
FREQUENCY (Hz)
ATTEN: VIN = 0.5VRMS
GAIN: VIN = 0.5VRMS/GAIN SETTING
GAIN = +24dB
GAIN = +18dB
GAIN = +12dB
GAIN = +0, –24dB
0
–0.5
–.10
–.15
–.20
–.25
–.30
–.35
–.40
–.45
–.50
100 1K 10K 100K
AMPLITUDE (dB)
FREQUENCY (Hz)
GAIN = +24dB
GAIN = 0dB
GAIN = –24dB
ATTEN: V
IN
= 2V
RMS
GAIN: V
IN
= 2V
RMS
/GAIN SETTING
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
010 100 1K 10K
OUTPUT NOISE VOLTAGE (µV/√Hz)
FREQUENCY (Hz)
GAIN = +24dB
GAIN = –24dB
GAIN = +12dB
Figure 4. Output Noise Voltage vs Frequency Figure 5. CMSG Output Noise vs Gain Setting
–2
–3
–4
–5
–6
–7
–8
–9
–10
–24
CMSG OUTPUT (NOISE) (dBrnc)
GAIN SETTING (dB)
–18 –12 –6 0 6 12 18 24
VIN = 0
Figure 3. Amplitude vs Frequency
(VIN/VOUT = 2VRMS)
Figure 2. Amplitude vs Frequency
(VIN/VOUT = 0.5VRMS)
ML2008, ML2009
6
TYPICAL PERFORMANCE CURVES (Continued)
0.1
.08
.06
.04
.02
0
–.02
–.04
–.06
–.08
–1.0
–24
GAIN ERROR (dB)
GAIN SETTING (dB)
–18 –12 –6 0 6 12 18 24
80
70
60
50
40
30
20
10
–24
S/N + D (dB)
GAIN SETTING (dB)
–18 –12 –6 0 6 12 18 24
VIN = 1kHz
VIN = 20kHz
VIN = 50kHz
ATTEN: VIN = 2VRMS
GAIN: VIN = 2VRMS/GAIN SETTING
80
70
60
50
40
30
20
S/N + D (dB)
GAIN SETTING (dB)
0 6 12 18 24
VIN = 50kHz
VIN = 20kHz
VIN = 1kHz
–24 –18 –12 –6
ATTEN: VIN = 0.5VRMS
GAIN: VIN = 0.5VRMS/GAIN SETTING
Figure 7. Gain Error vs Gain Setting
Figure 8. S/N +D vs Gain Setting (VIN/VOUT = 2VRMS)Figure 9. S/N +D vs Gain Setting (VIN/VOUT = 0.5VRMS)
Figure 6. CMSG S/N vs Gain Setting
CMSG S/N (DB)
GAIN SETTING (dB)
0 6 12 18 24
100
90
80
70
60
50
40
ATTEN: VIN = 8dBm
GAIN: VIN = 8dBm/GAIN SETTING
1kHZ
–6–12–18–24
1.0 FUNCTIONAL DESCRIPTION
The ML2008, ML2009 consists of a coarse gain stage, a
fine gain stage, an output buffer, and a µP compatible
parallel digital interface.
1.1 Gain Stages
The analog input, VIN, goes directly into the op amp input
in the coarse gain stage. The coarse gain stage has a gain
range of 0 to 22.5dB in 1.5dB steps.
The fine gain stage is cascaded onto the coarse section.
The fine gain stage has a gain range of 0 to 1.5dB in 0.1dB
steps.
Both stages can be programmed for either gain or
attenuation, thus doubling the effective gain range.
The logarithmic steps in each gains stage are generated by
placing the input signal across a resistor string of 16 series
resistors. Analog switches allow the voltage to be tapped
from the resistor string at 16 points. The resistors are sized
such that each output voltage is at the proper logarithmic
ratio relative to the input signal at the top of the string.
Attenuation is implemented by using the resistor string as
a simple voltage divider, and gain is implemented by
using the resistor string as a feedback resistor around an
internal op amp.
1.2 Gain Settings
Since the coarse and fine gain stages are cascaded, their
gains can be summed logarithmically. Thus, any gain from
–24dB to +24dB in 0.1dB steps can be obtained by
combining the coarse and fine gain setting to yield the
ML2008, ML2009
7
desired gain setting. The relationship between the register
0 and 1 bits and the corresponding analog gain values is
shown in Tables 1 and 2. Note that C3-C0 select the
coarse gain, F3-F0 select the fine gain, and ATTEN/GAIN
selects either gain or attenuation.
1.3 Output Buffer
The final analog stage is the output buffer. This amplifier
has internal gain of 1 and is designed to drive 600Ω,
100pF loads. Thus, it is suitable for driving a telephone
hybrid circuit directly without any external amplifier.
1.4 Power Supplies
The digital section is powered between VCC and GND,
or 5V. The analog section is powered between VCC and
VSS and uses AGND as the reference point, or ±5V.
GND and AGND are totally isolated inside the device to
minimize coupling from the digital section into the analog
section. Typically this is less than 100µV. However, AGND
and GND should be tied together physically near the
device and ideally close to the common power supply
ground connection.
Typically, the power supply rejection of VCC and VSS
to the analog output is greater than –60dB at 1KHz. If
decoupling of the power supplies is still necessary in a
system, VCC and VSS should be decoupled with respect
to AGND.
Table 1. Fine Gain Settings (C3 – C0 = 0)
Ideal Gain (dB)
F3 F2 F1 F0 ATTEN/GAIN = 1 ATTEN/GAIN = 0
0000 0.0 0.0
0001 –0.1 0.1
0010 –0.2 0.2
0011 –0.3 0.3
0100 –0.4 0.4
0101 –0.5 0.5
0110 –0.6 0.6
0111 –0.7 0.7
1000 –0.8 0.8
1001 –0.9 0.9
1010 –1.0 1.0
1011 –1.1 1.1
1100 –1.2 1.2
1101 –1.3 1.3
1110 –1.4 1.4
1111 –1.5 1.5
Table 2. Coarse Gain Settings (F3 – F0 = 0)
Ideal Gain (dB)
C3 C2 C1 C0 ATTEN/GAIN = 1 ATTEN/GAIN = 0
0000 0.0 0.0
0001 –1.5 1.5
0010 –3.0 3.0
0011 –4.5 4.5
0100 –6.0 6.0
0101 –7.5 7.5
0110 –9.0 9.0
0111 –10.5 10.5
1000 –12.0 12.0
1001 –13.5 13.5
1010 –15.0 15.0
1011 –16.5 16.5
1100 –18.0 18.0
1101 –19.5 19.5
1110 –21.0 21.0
1111 –22.5 22.5
2.0 DIGITAL INTERFACE
The architecture of the digital section is shown in the
preceding black diagram.
The structure of the data registers or latches is shown in
Figures 10 and 11 for the ML2008 and ML2009,
respectively. The registers control the attenuation/gain
setting bits and with the ML2008 the power down bit.
Tables 1 and 2 describe how the data word programs the
gain.
The difference between the ML2008 and ML2009 is in the
register structure. The ML2008 is an 8-bit data bus
version. This device has one 8-bit register and one 2-bit
register to store the 9 gain setting bits and 1 powerdown
bit. Two write operations are necessary to program the full
10 data bits from eight external data pins. The address pin
A0 controls which register is being written into. The
powerdown bit, PDN, causes the device to be placed in
powerdown. When PDN = 1, the device is powered
down. In this state, the power consumption is reduced by
removing power from the analog section and forcing the
analog output, VOUT, to a high impedance state. While the
device is in powerdown, the digital section is still
functional and the current data word remains stored in the
registers. When PDN = 0, device is in normal operation.
The ML2009 is a 9-bit data bus version. This device has
one 9-bit register to store the 9 gain setting bits. The full 9
data bits can be programmed with one write operation
from nine external data pins.
The internal registers or latches are edge triggered. The
data is transferred from the external pins to the register
output on the rising edge of WR. The address pin, A0,
controls which register the data will be written into as
shown in Figures 1 and 2. The CS control signal selects
the device by allowing the WR signal to latch in the data
only when CS is low. When CS is high, WR is inhibited
from latching in new data into the registers.
ML2008, ML2009
8
Figure 10. ML2008 Register Structure
REG 0ATTEN/GAIN C3 C2 C1 C0 F3 F2 F1 F0
D8 D7 D6 D5 D4 D3 D2 D1 BITD0
D8 D7 D6 D5 D4 D3 D2 D1 BIT
A0 = 0 REG 0ATTEN/GAIN C3 C2 C1 C0 F3 F2 F1
A0 = 1 REG 1PDN F0
Figure 11. ML2009 Register Structure
ML2009
CS WR D0-D8
9
µP
Figure 14. Typical 16-Bit µP Interface Figure 15. AGC for DSP or Modem Front End
ML2009
VOUTVIN
D0-D8 WR CS
VIN
ML2233
12-BIT
+ SIGN
A/D
µP
OR
DSP
ML2008
CS WR
V
OUT
V
IN
A0 D1-D8
8
µP
Figure 12. Typical 8-Bit µP Interface, Double Write
ML2009
CS WR
V
OUT
V
IN
D0
D1-D8
8
µP
+5V
Figure 13. Typical 8-Bit µP Interface, Single Write
ML2008, ML2009
9
ML2009
D0-D8
VIN
+5V
–5V
VOUT
2.5V
REF
µP
ML2008
VIN
D1-D8
WR
CS A0
ML2008
A0
D1-D8 CS A0
CS1
CS2
ADDRESS
D
E
C
O
D
E
R
Figure 16. Operation as Logarithmic D/A Converter Figure 17. Controlling Multiple Gain/Attenuators
ML2008, ML2009
10
0.100 - 0.110
(2.54 - 2.79)
PIN 1 ID
SEATING PLANE
0.385 - 0.395
(8.89 - 10.03)
0.350 - 0.356
(8.89 - 9.04)
0.013 - 0.021
(0.33 - 0.53)
0.165 - 0.180
(4.19 - 4.57)
1
0.350 - 0.356
(8.89 - 9.04)
0.385 - 0.395
(8.89 - 10.03)
6
11
16 0.290 - 0.330
(7.36 - 8.38)
0.025 - 0.045
(0.63 - 1.14)
(RADIUS)
0.009 - 0.011
(0.23 - 0.28)
0.026 - 0.032
(0.66 - 0.81)
0.042 - 0.048
(1.07 - 1.22)
0.042 - 0.056
(1.07 - 1.42)
0.200 BSC
(5.08 BSC)
Package: Q20
20-Pin PLCC
0.146 - 0.156
(3.71 - 3.96)
0.050 BSC
(1.27 BSC)
PHYSICAL DIMENSIONS inches (millimeters)
ML2008, ML2009
11
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
DS2008_09-01
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE
ML2008IP–40°C to 85°CMolded PDIP (P18) (EOL)
ML2008IQ–40°C to 85°CMolded PLCC (Q20) (EOL)
ML2008CP0°C to +70°CMolded PDIP (P18) (EOL)
ML2008CQ0°C to +70°CMolded PLCC (Q20) (EOL)
ML2009IP–40°C to 85°CMolded PDIP (P18) (OBS)
ML2009IQ–40°C to 85°CMolded PLCC (Q20) (OBS)
ML2009CP0°C to +70°CMolded PDIP (P18) (OBS)
ML2009CQ0°C to +70°CMolded PLCC (Q20) (OBS)
SEATING PLANE
0.240 - 0.260
(6.09 - 6.61)
PIN 1 ID 0.295 - 0.325
(7.49 - 8.26)
0.890 - 0.910
(22.60 - 23.12)
0.016 - 0.022
(0.40 - 0.56)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.015 MIN
(0.38 MIN)
18
0º - 15º
1
0.050 - 0.065
(1.27 - 1.65)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.045 MIN
(1.14 MIN)
(4 PLACES)
Package: P18
18-Pin PDIP
© Micro Linear 1997 is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending.
PHYSICAL DIMENSIONS inches (millimeters)
