QS59910-7SOX - Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

QS59910

LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

GND/sOE

REF

PLL

VCCQ/PE

MARCH 2000

2000 Integrated Device Technology, Inc. DSC-5812/-c

QS59910

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

LOW SKEW

PLL CLOCK DRIVER

TURBOCLOCK™ JR.

DESCRIPTION:

The QS59910 is a high fanout phase lock loop clock driver intended

for high performance computing and data-communications applications.

The QS59910 has eight zero delay TTL outputs.

The QS59910 maintains Cypress CY7B9910 compatibility while pro-

viding two additional features: Synchronous Output Enable (GND/sOE),

and Positive/Negative Edge Synchronization (VCCQ/PE). When the GND/

sOE pin is held low, all the outputs are synchronously enabled (CY7B9910

compatibility). However, if GND/sOE is held high, all the outputs except

Q2 and Q3 are synchronously disabled.

Furthermore, when the VCCQ/PE is held high, all the outputs are

synchronized with the positive edge of the REF clock input (CY7B9910

compatibility). When VCCQ/PE is held low, all the outputs are synchro-

nized with the negative edge of REF.

The FB signal is compared with the input REF signal at the phase

detector in order to drive the VCO. Phase differences cause the VCO

of the PLL to adjust upwards or downwards accordingly.

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to

provide minimal jitter (or frequency variation) while still providing accu-

rate responses to input frequency changes.

FEATURES:

• Eight zero delay outputs

• Selectable positive or negative edge synchronization

• Synchronous output enable

• Output frequency: 25MHz to 85MHz

• TTL outputs

• 3 skew grades:

QS59910-2: tSKEW0 <250ps

QS59910-5: tSKEW0 <500ps

QS59910-7: tSKEW0 <750ps

• 3-level input for PLL range control

• PLL bypass for DC testing

• External feedback, internal loop filter

• 46mA IOL high drive outputs

• Low Jitter: <200ps peak-to-peak

• Outputs drive 50Ω terminated lines

• Pin compatible with Cypress CY7B9910

• Available in SOIC Package

FUNCTIONAL BLOCK DIAGRAM

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

QS59910

LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

PIN CONFIGURATION

REF

VCCQ/PE

GND

TEST

GND/sOE

GND

VCCN

VCCQ

VCCN

SO24-2

SOIC

TOP VIEW

ABSOLUTE MAXIMUM RATINGS (1)

Symbol

Rating Max. Unit

Supply Voltage to Ground –0.5 to +7 V

VIDC Input Voltage –0.5 to +7 V

Maximum Power Dissipation (TA = 85°C) 530 mW

TSTG Storage Temperature Range –65°C to +150°C °C

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other c onditions abov e those indic ated in the operati onal s ections

of this specification is not implied. Exposure to absolute maximum

rating condit ions for extended periods may affect reliabilit y.

CAPACITANCE (TA = 25° C, f = 1MHz, VIN = 0V)

Parameter Description Typ. Max. Unit

CIN Input Capacitance 5 7 pF

NOTE:

1. Capacit ance applies to al l i nputs except TE ST and FS. It is

charact eri z ed but not production tested.

PIN DESCRIPTION

Pin Name Type Description

REF IN Reference Clock Input

FB IN Feedback Input

TEST (1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.

GND/ sOE (1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as

the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation.

VCCQ/PE IN Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the

reference clock.

FS (2) IN Frequency range select. 3 level input.

FS = GND: 25 to 35MHz.

FS = MID (or open): 35 to 60MHz

FS = VCC: 60 to 85MHz

Q0 - Q7OUT 8 clock output

VCCN PWR Power supply for output buffers

VCCQ PWR Power supply for phase locked loop and other internal circuitry

GND PWR Ground

NOTES:

1. When TEST = MI D and GND/sOE = HIGH, PLL remains active.

2. This input i s wired to Vcc, GND, or unconnected. Default i s MID level. If it is s witched in the real tim e m ode, the outputs may gl i t ch, and the PLL

may require an additional lock ti m e before all data sheet li m i t s are achieved.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

QS59910

LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

RECOMMENDED OPERATING RANGE QS59910-5, -7

(Industrial) QS59910-2

(Commercial)

Symbol Description Min. Max. Min. Max. Unit

Vcc Power Supply Voltage 4.5 5.5 4.75 5.25 V

TAAmbient Operating Temperature -40 +85 0 +70 °C

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Symbol Parameter Conditions Min. Max. Unit

VIH Input HIGH Voltage Guaranteed Logic HIGH (REF, FB Inputs Only) 2 — V

VIL Input LOW Voltage Guaranteed Logic LOW (REF, FB Inputs Only) — 0.8 V

VIHH Input HIGH Voltage (1) 3-Level Inputs Only VCC−1—V

IMM Input MID Voltage (1) 3-Level Inputs Only VCC/2−0.5 VCC/2+0.5 V

VILL Input LOW Voltage (1) 3-Level Inputs Only — 1 V

IIN Input Leakage Current

(REF, FB Inputs Only) VIN = VCC or GND

VCC = Max. —±5µA

IN = VCC HIGH Level — ±200

I33-Level Input DC Current (TEST, FS) VIN = VCC/2 MID Level — ±50 µA

VIN = GND LOW Level — ±200

IPU Input Pull-Up Current (VCCQ/PE) VCC = Max., VIN = GND — ±100 µA

IPD Input Pull-Down Current (GND/sOE)V

CC = Max., VIN = VCC — ±100 µA

VOH Output HIGH Voltage VCC = Min., IOH = −16mA ——V

CC = Min., IOH = −40mA 2.4 — V

VOL Output LOW Voltage VCC = Min., IOL = 46mA — 0.45 V

IOS Output Short Circuit Current (2) VCC = Max., VO = GND — − 250 mA

NOTES:

1. These inputs are normally wired to V CC, GND, or unconnected. Internal termination resistors bias unconnected inputs t o V CC/2. If these i nputs are

switc hed, the function and t i m i ng of the outputs may be gl i tched, and the PLL may requi re an addi tional tLOCK time before all dat asheet limits are

achieved.

2. QS59910 is t o be m easured at 25°C with 10:1 dut y cycle, one output at a time, and one second maximum.

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions Typ. Max. Unit

ICCQ Quiescent Power Supply Current VCC = Max., TEST = MID, REF = LOW,

GND/sOE = LOW, All outputs unloaded 10 40 mA

∆ICC Power Supply Current per Input HIGH VCC = Max., VIN = 3.4V 0.4 1.5 mA

ICCD Dynamic Power Supply Current per Output VCC = Max., CL = 0pF 100 160 µA/MHz

ITOT Total Power Supply Current VCC = 5V, FREF = 25MHz, CL = 240pF (1) 53 — mA

VCC = 5V, FREF = 33MHz, CL = 240pF (1) 63 — mA

VCC = 5V, FREF = 66MHz, CL = 240pF (1) 117 — mA

NOTE:

1. For eight output s, each loaded with 30pF.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

QS59910

LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

NOTES:

1. All timing tolerances apply for FNOM ≥25MHz.

2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.

3. tSKEW is the skew between all outputs. See AC test loads.

4. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)

5. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating

limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.

6. tPD is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.

7. Refer to Input Timing Requirements for more detail.

INPUT TIMING REQUIREMENTS

Symbol Description (1) Min. Max. Unit

tR, tFMaximum input rise and fall times, 0.8V to 2V — 10 ns/V

tPWC Input clock pulse, HIGH or LOW 3 — ns

DHInput duty cycle 10 90 %

REF Reference Clock Input 25 85 MHz

NOTE:

1. Where pulse wi dt h i mplied by DH is less than tPWC limit, tPWC limit applies.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

QS59910-2 QS59910-5 QS59910-7

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

FREF REF Frequency Range FS = LOW 25 — 35 25 — 35 25 — 35 MHz

FS = MID 35 — 60 35 — 60 35 — 60

FS = HIGH 60 — 85 60 — 85 60 — 85

tRPWH REF Pulse Width HIGH (1,7) 3—— 3 ——3 ——ns

RPWL REF Pulse Width LOW (1,7) 3—— 3 ——3 ——ns

SKEW Zero Output Skew (All Outputs) (1,3) — 0.1 0.25 — 0.25 0.5 — 0.3 0.75 ns

tDEV Device-to-Device Skew (1,2,4) — — 0.75 — — 1.25 — — 1.65 ns

tPD REF Input to FB Propagation Delay (1,6) −0.25 00.25

−0.5 00.5

−0.7 00.7ns

ODCV Output Duty Cycle Variation from 50% (1) −1.2 01.2

−1.2 01.2

−1.2 01.2ns

ORISE Output Rise Time (1) 0.15 1 1.5 0.15 1 1.5 0.15 1.5 2.5 ns

tOFALL Output Fall Time (1) 0.15 1 1.5 0.15 1 1.5 0.15 1.5 2.5 ns

tLOCK PLL Lock Time (5) — — 0.5 — — 0.5 — — 0.5 ms

tJR Cycle-to-Cycle Output Jitter RMS — — 25 — — 25 — — 25 ps

Peak-to-Peak — — 200 — — 200 — — 200

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

QS59910

LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

130Ω

91Ω

VCC

Output

CL = 50pF (CL = 30 p F fo r -2 an d -5 d ev ice s )

2.0V

tORISE tOFALL

0.8V

≤1ns ≤1ns

2.0V

0.8V

3.0V

Vth =1.5V

AC TEST LOADS AND WAVEFORMS

TEST LOAD

TTL INPUT TEST WAVEFORM

TTL OUTPUT WAVEFORM

REF

OTHER Q

tREF

tPD

tSKEW tSKEW

tJR

tODCV tODCV

tRPWH

tRPWL

AC TIMING DIAGRAM

NOTES:

Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5)

and terminated with 50Ω to 2.06V.

tSKEW: The skew between all outputs.

tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow,

etc.)

tODCV: The deviation of the output from a 50% duty cycle.

tORISE and tOFALL are measured between 0.8V and 2V.

tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal

operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within

specified limits.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

QS59910

LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

CORPORATE HEADQUARTERS for SALES:

2975 Stender Way 800-345-7015 or 408-727-6116

Santa Clara, CA 95054 fax: 408-492-8674

www.idt.com*

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Turboclock is a registered trademark of Integrated Device Technology, Inc.

ORDERING INFORMATION

QS XXXXX XX X

Package Process

D e vice T yp e

59910-2

59910-5

59910-7

Low Skew P LL C lock Driver Turbo Clock Jr.

Small Outl ine IC ( 3 00-mil) ( SO24-2 )

Comme r cia l (0° C to +70 ° C)

Industrial (-40°C to +85°C)