1/16April 1999
M27C2001
2 Mbit (256Kb x 8) UV EPROM and OTP EPROM
■5V ±10% SUPPLY VOLTAGE in READ
OPERATION
■FAST ACCESS TIME: 55ns
■LOW POWER CONSUMPTION:
– Active Current 30mA at 5MHz
– Standby Current 100µA
■PROGRAMMING VOLTAGE: 12.75V ±0.25V
■PROGRAMMING TIME: 100µs/byte (typical)
■ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 61h
DESCRIPTION
The M27C2001 is a high speed 2 Mbit EPROM of-
fered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large pro-
grams and is organised as 262,144 by 8 bits.
The FDIP32W (window ceramic frit-seal package)
and LCCC32W (leadless chip carrier package)
have a transparent lids which allow the user to ex-
pose thechipto ultraviolet light to erase the bitpat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications wherethe content is programmed
only one time and erasure is not required, the
M27C2001 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
Figure 1. Logic Diagram
AI00716B
18
A0-A17
P
Q0-Q7
VPP
VCC
M27C2001
G
E
VSS
8
Table 1. Signal Names
A0-A17 Address Inputs
Q0-Q7 Data Outputs
E Chip Enable
G Output Enable
P Program
VPP Program Supply
VCC Supply Voltage
VSS Ground
1
32 32
1
FDIP32W (F) PDIP32 (B)
PLCC32 (K) TSOP32 (N)
8 x 20 mm
LCCC32W (L)
M27C2001
2/16
Figure 2B. LCC Pin Connections
AI00718
A17
A8
A10
Q5
17
A1
A0
Q0
Q1
Q2
Q3
Q4
A7
A4
A3
A2
A6
A5
9
P
A9
1
A16
A11
A13
A12
Q7
32
VPP
VCC
M27C2001
A15
A14
Q6
G
E
25
VSS
Figure 2A. DIP Pin Connections
A1
A0
Q0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
Q7
A14
A11
G
E
Q5Q1
Q2 Q3VSS Q4
Q6
A17
PA16
A12
VPP VCC
A15
AI00717
M27C2001
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
The operationg modes of the M27C2001 are listed
in the Operating Modes table. A single power sup-
ply is required in the read mode. All inputs are TTL
levels except for VPP and 12V on A9 for Electronic
Signature.
Read Mode
The M27C2001 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(tAVQV) is equal to the delay from E to output
(tELQV). Data is available atthe output aftera delay
of tGLQV from the falling edge of G, assuming that
E has been low and the addresses havebeen sta-
ble for at least tAVQV-tGLQV.
Standby Mode
The M27C2001 has a standby mode which reduc-
es the supply current from 30mA to 100µA. The
M27C2001 is placed in the standby mode by ap-
plying a CMOS high signal to the E input. When in
the standbymode, the outputsarein a high imped-
ance state, independent of the G input.
Figure 2C. TSOP Pin Connections
A1
A0
Q0
A7
A4 A3
A2
A6
A5
A13
A10
A8
A9
Q7
A14
A11 G
E
Q5
Q1
Q2
Q3
Q4
Q6
A17
P
A16
A12
VPP
VCC
A15
AI01153B
M27C2001
(Normal)
8
1
9
16 17
24
25
32
VSS
3/16
M27C2001
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decoded and used asthe prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. Thisensures that all deselect-
ed memory devices are in their lowpower standby
mode and that the output pins are only active
when data is required from a particular memory
device.
Table 2. Absolute Maximum Ratings (1)
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Referalso to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Note: X = VIH or VIL,V
ID = 12V ±0.5V.
Table 4. Electronic Signature
Symbol Parameter Value Unit
TAAmbient Operating Temperature (3) –40 to 125 °C
TBIAS Temperature Under Bias –50 to 125 °C
TSTG Storage Temperature –65 to 150 °C
VIO (2) Input or Output Voltage (except A9) –2 to 7 V
VCC Supply Voltage –2 to 7 V
VA9 (2) A9 Voltage –2 to 13.5 V
VPP Program Supply Voltage –2 to 14 V
Mode E G P A9 VPP Q0-Q7
Read VIL VIL XX
V
CC or VSS Data Out
Output Disable VIL VIH XXV
CC or VSS Hi-Z
Program VIL VIH VIL Pulse XVPP Data In
Verify VIL VIL VIH XV
PP Data Out
Program Inhibit VIH XXX
V
PP Hi-Z
Standby VIH XXX
V
CC or VSS Hi-Z
Electronic Signature VIL VIL VIH VID VCC Codes
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’sCode VIL 00100000 20h
Device Code VIH 01100001 61h
M27C2001
4/16
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs requirecareful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the fallingand rising edgesof E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purposeof the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times ≤10ns ≤20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 4. AC Testing Load Circuit
AI01823B
1.3V
OUT
CL
CL= 30pF for High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Table 6. Capacitance (1) (TA=25°C, f = 1 MHz)
Note: 1. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN =0V 6pF
C
OUT Output Capacitance VOUT =0V 12 pF
5/16
M27C2001
Table 7. Read Mode DC Characteristics (1)
(TA = 0to 70 °C or –40 to 85 °C; VCC =5V±5% or 5V ±10%; VPP =V
CC)
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1)
(TA = 0to 70 °C or –40 to 85 °C; VCC =5V±5% or 5V ±10%; VPP =V
CC)
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
3. In case of 45ns speed see High Speed AC measurament conditions.
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤VIN ≤VCC ±10 µA
ILO Output Leakage Current 0V ≤VOUT ≤VCC ±10 µA
ICC Supply Current E=V
IL,G=V
IL,
IOUT = 0mA, f = 5MHz 30 mA
ICC1 Supply Current (Standby) TTL E = VIH 1mA
I
CC2 Supply Current (Standby) CMOS E>V
CC – 0.2V 100 µA
IPP Program Current VPP =V
CC 10 µA
VIL Input Low Voltage –0.3 0.8 V
VIH (2) Input High Voltage 2 VCC +1 V
V
OL Output Low Voltage IOL = 2.1mA 0.4 V
VOH Output High Voltage TTL IOH = –400µA 2.4 V
Output High Voltage CMOS IOH = –100µAV
CC – 0.7V V
Symbol Alt Parameter Test Condition
M27V2001
Unit
-55 (3) -70 -80 -90
Min Max Min Max Min Max Min Max
tAVQV tACC Address Valid to
Output Valid E=V
IL,G=V
IL 55 70 80 90 ns
tELQV tCE Chip Enable Low to
Output Valid G=V
IL 55 70 80 90 ns
tGLQV tOE Output Enable Low
to Output Valid E=V
IL 30 35 40 40 ns
tEHQZ (2) tDF Chip Enable High to
Output Hi-Z G=V
IL 0 30 0 30 0 30 0 30 ns
tGHQZ (2) tDF Output Enable High
to Output Hi-Z E=V
IL 0 30 0 30 0 30 0 30 ns
tAXQX tOH Address Transitionto
Output Transition E=V
IL,G=V
IL 0000ns
M27C2001
6/16
Figure 5. Read Mode AC Waveforms
AI00719B
tAXQX
tEHQZ
A0-A17
E
G
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
Table 8B. Read Mode AC Characteristics (1)
(TA = 0to 70 °C or –40 to 85 °C; VCC =5V±5% or 5V ±10%; VPP =V
CC)
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
Symbol Alt Parameter Test Condition
M27V2001
Unit-10 -12 -15/-20/-25
Min Max Min Max Min Max
tAVQV tACC Address Valid to Output
Valid E=V
IL,G=V
IL 100 120 150 ns
tELQV tCE Chip Enable Low to
Output Valid G=V
IL 100 120 150 ns
tGLQV tOE Output Enable Low to
Output Valid E=V
IL 50 50 60 ns
tEHQZ (2) tDF Chip Enable High to
Output Hi-Z G=V
IL 030040050ns
t
GHQZ (2) tDF Output Enable High to
Output Hi-Z E=V
IL 030040050ns
t
AXQX tOH Address Transition to
Output Transition E=V
IL,G=V
IL 000ns
Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M27C2001 are in the ’1’
state. Data is introduced by selectively program-
ming ’0’s into the desired bit locations. Although
only ’0’s will be programmed,both ’1’s and ’0’s can
be present in the data word. The only way to
change a ’0’to a ’1’is by die exposition to ultravio-
let light (UV EPROM). The M27C2001 is in the
programming mode when VPP input is at 12.75V,
EisatV
IL and P is pulsed to VIL. The data to be
programmed is applied to 8 bits in parallel to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. VCC is specified to
be 6.25V ±0.25V.
7/16
M27C2001
Table 9. Programming Mode AC Characteristics (1)
(TA=25°C; VCC = 6.25V ±0.25V; VPP = 12.75V ±0.25V)
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics (1)
(TA=25°C; VCC = 6.25V ±0.25V; VPP = 12.75V ±0.25V)
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0≤VIN ≤VIH ±10 µA
ICC Supply Current 50 mA
IPP Program Current E=V
IL 50 mA
VIL Input Low Voltage –0.3 0.8 V
VIH Input High Voltage 2 VCC + 0.5 V
VOL Output Low Voltage IOL = 2.1mA 0.4 V
VOH Output High Voltage TTL IOH = –400µA2.4 V
VID A9 Voltage 11.5 12.5 V
Symbol Alt Parameter Test Condition Min Max Unit
tAVPL tAS Address Validto Program Low 2 µs
tQVPL tDS Input Valid to Program Low 2 µs
tVPHPL tVPS VPP High to Program Low 2µs
tVCHPL tVCS VCC High to Program Low 2µs
tELPL tCES Chip Enable Low to Program Low 2 µs
tPLPH tPW Program Pulse Width 95 105 µs
tPHQX tDH Program High to Input Transition 2 µs
tQXGL tOES Input Transition to Output Enable Low 2 µs
tGLQV tOE Output Enable Low to Output Valid 100 ns
tGHQZ (2) tDFP Output Enable High to Output Hi-Z 0 130 ns
tGHAX tAH Output Enable High to Address
Transition 0ns
M27C2001
8/16
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Pro-
gramming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activatedin order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides the
necessary margin to each programmed cell.
Program Inhibit
Programming of multiple M27C2001s in parallel
with different data is also easily accomplished. Ex-
cept for E, all likeinputs including G of the parallel
M27C2001 may be common. A TTL low level
pulse applied to a M27C2001’s P input, with E low
and VPP at 12.75V, will program that M27C2001.
A high level E input inhibits the other M27C2001s
from being programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that theywere correct-
ly programmed. The verify is accomplished with E
and G at VIL, P at VIH,V
PP at 12.75V and VCC at
6.25V.
Figure 6. Programming and Verify Modes AC Waveforms
tAVPL
VALID
AI00720
A0-A17
Q0-Q7
VPP
VCC
P
G
DATA IN DATA OUT
E
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM VERIFY
Figure 7. Programming Flowchart
AI00715C
n=0
Last
Addr
VERIFY
P = 100µs Pulse
++n
=25 ++ Addr
VCC = 6.25V, VPP = 12.75V
FAIL
CHECK ALL BYTES
1st: VCC =6V
2nd: VCC = 4.2V
YES
NO
YES
NO
YES
NO
9/16
M27C2001
On-Board Programming
The M27C2001 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically matchthe device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C±5°C am-
bient temperaturerange that is required when pro-
gramming the M27C2001. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
M27C2001 with VPP=VCC=5V. Two identifier
bytes maythen be sequenced fromthe deviceout-
puts bytoggling address lineA0from VIL toVIH. All
other address lines must be held at VIL during
Electronic Signature mode. Byte 0 (A0=VIL) repre-
sents the manufacturer code and byte 1 (A0=VIH)
the device identifier code. For the STMicroelec-
tronics M27C2001, these two identifier bytes are
given in Table 4 and can be read-out on outputs
Q0 to Q7.
ERASURE OPERATION(applies to UV EPROM)
The erasure characteristics of the M27C2001 are
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Data
shows that constant exposure to room level fluo-
rescent lighting could erase atypical M27C2001 in
about 3 years, while it would takeapproximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C2001 is to be exposed to
these types of lighting conditions for extended pe-
riods of time, it is suggested that opaque labels be
put over the M27C2001 window to prevent unin-
tentional erasure. The recommended erasure pro-
cedure for the M27C2001 is exposure to short
wave ultraviolet light which has wavelength of
2537 Å. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of 15 W-sec/cm2. The erasure time with this dos-
age is approximately 15 to 20 minutes using an ul-
traviolet lamp with 12000 µW/cm2power rating.
The M27C2001 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
M27C2001
10/16
Table 11. Ordering Information Scheme
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
Example: M27C2001 -55 X C 1 X
Device Type
M27
Supply Voltage
C=5V
Device Function
2001 = 2Mb, 256Kb x8
Speed
-55 (1) =55ns
-70 = 70 ns
-80 = 80 ns
-90 = 90 ns
-10 = 100 ns
Not for New Design
-12 = 120 ns
-15 = 150 ns
-20 = 200 ns
-25 = 250 ns
VCC Tolerance
X=±5%
blank = ±10%
Package
F = FDIP32W
B = PDIP32
L = LCCC32W
C = PLCC32
N = TSOP32: 8 x 20mm
Temperature Range
1=0to70°C
6=–40to85°C
Options
X = Additional Burn-in
TR = Tape & Reel Packing
11/16
M27C2001
Table 12. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
Symb mm inches
Typ Min Max Typ Min Max
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 41.73 42.04 1.643 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 0.125
S 1.52 2.49 0.060 0.098
∅7.11 – – 0.280 – –
α4°11°4°11°
N32 32
Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline
Drawing is not to scale.
FDIPW-a
A3
A1
A
L
B1 B e
D
S
E1 E
N
1
C
α
eA
D2
∅
eB
A2
M27C2001
12/16
Table 13. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
Symb mm inches
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 41.78 42.04 1.645 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 15.24 – – 0.600 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.03 0.070 0.080
α0°10°0°10°
N32 32
Figure 9. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline
Drawing is not to scale.
PDIP
A2
A1
A
L
B1 B e1
D
S
E1 E
N
1
C
α
eA
eB
D2
13/16
M27C2001
Table 14. LCCC32W -32 lead Leadless Ceramic Chip Carrier, with window, Package Mechanical Data
Symb mm inches
Typ Min Max Typ Min Max
A 2.28 0.090
B 0.51 0.71 0.020 0.028
D 11.23 11.63 0.442 0.458
E 13.72 14.22 0.540 0.560
e 1.27 – – 0.050 – –
e1 0.39 – 0.015 –
e2 7.62 – – 0.300 – –
e3 10.16 – – 0.400 – –
h 1.02 – – 0.040 – –
j 0.51 – – 0.020 – –
L 1.14 1.40 0.045 0.055
L1 1.96 2.36 0.077 0.093
K 10.50 10.80 0.413 0.425
K1 8.03 8.23 0.316 0.324
N32 32
Figure 10. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, with window, Package Outline
Drawing is not to scale.
LCCCW-a
e3
1
N
L1
B
Lhx45
o
jx45
o
e2
e
e1
A
D
EK
K1
M27C2001
14/16
Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data
Symb mm inches
Typ Min Max Typ Min Max
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline
Drawing is not to scale.
PLCC
D
Ne E1 E
1N
D1
Nd
CP
B
D2/E2 e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
15/16
M27C2001
Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline
Drawing is not to scale.
TSOP-a
D1
E
1N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
Table 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
Symb mm inches
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.15 0.002 0.007
A2 0.95 1.05 0.037 0.041
B 0.15 0.27 0.006 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 7.90 8.10 0.311 0.319
e 0.50 - - 0.020 - -
L 0.50 0.70 0.020 0.028
α0°5°0°5°
N32 32
CP 0.10 0.004
M27C2001
16/16
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
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